1 /* 2 3 Copyright (c) 2010-2017, The Regents of the University of California 4 (Regents). All Rights Reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 1. Redistributions of source code must retain the above copyright 9 notice, this list of conditions and the following disclaimer. 10 2. Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in the 12 documentation and/or other materials provided with the distribution. 13 3. Neither the name of the Regents nor the 14 names of its contributors may be used to endorse or promote products 15 derived from this software without specific prior written permission. 16 17 IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, 18 SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING 19 OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS 20 BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 22 REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 23 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED 25 HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE 26 MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. 27 28 */ 29 30 #ifndef RISCV_CSR_ENCODING_H 31 #define RISCV_CSR_ENCODING_H 32 33 #define MSTATUS_UIE 0x00000001 34 #define MSTATUS_SIE 0x00000002 35 #define MSTATUS_HIE 0x00000004 36 #define MSTATUS_MIE 0x00000008 37 #define MSTATUS_UPIE 0x00000010 38 #define MSTATUS_SPIE 0x00000020 39 #define MSTATUS_HPIE 0x00000040 40 #define MSTATUS_MPIE 0x00000080 41 #define MSTATUS_SPP 0x00000100 42 #define MSTATUS_HPP 0x00000600 43 #define MSTATUS_MPP 0x00001800 44 #define MSTATUS_FS 0x00006000 45 #define MSTATUS_XS 0x00018000 46 #define MSTATUS_MPRV 0x00020000 47 #define MSTATUS_SUM 0x00040000 48 #define MSTATUS_MXR 0x00080000 49 #define MSTATUS_TVM 0x00100000 50 #define MSTATUS_TW 0x00200000 51 #define MSTATUS_TSR 0x00400000 52 #define MSTATUS32_SD 0x80000000 53 #define MSTATUS_UXL 0x0000000300000000 54 #define MSTATUS_SXL 0x0000000C00000000 55 #define MSTATUS64_SD 0x8000000000000000 56 57 #define SSTATUS_UIE 0x00000001 58 #define SSTATUS_SIE 0x00000002 59 #define SSTATUS_UPIE 0x00000010 60 #define SSTATUS_SPIE 0x00000020 61 #define SSTATUS_SPP 0x00000100 62 #define SSTATUS_FS 0x00006000 63 #define SSTATUS_XS 0x00018000 64 #define SSTATUS_SUM 0x00040000 65 #define SSTATUS_MXR 0x00080000 66 #define SSTATUS32_SD 0x80000000 67 #define SSTATUS_UXL 0x0000000300000000 68 #define SSTATUS64_SD 0x8000000000000000 69 70 #define DCSR_XDEBUGVER (3U<<30) 71 #define DCSR_NDRESET (1<<29) 72 #define DCSR_FULLRESET (1<<28) 73 #define DCSR_EBREAKM (1<<15) 74 #define DCSR_EBREAKH (1<<14) 75 #define DCSR_EBREAKS (1<<13) 76 #define DCSR_EBREAKU (1<<12) 77 #define DCSR_STOPCYCLE (1<<10) 78 #define DCSR_STOPTIME (1<<9) 79 #define DCSR_CAUSE (7<<6) 80 #define DCSR_DEBUGINT (1<<5) 81 #define DCSR_HALT (1<<3) 82 #define DCSR_STEP (1<<2) 83 #define DCSR_PRV (3<<0) 84 85 #define DCSR_CAUSE_NONE 0 86 #define DCSR_CAUSE_SWBP 1 87 #define DCSR_CAUSE_HWBP 2 88 #define DCSR_CAUSE_DEBUGINT 3 89 #define DCSR_CAUSE_STEP 4 90 #define DCSR_CAUSE_HALT 5 91 92 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) 93 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) 94 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) 95 96 #define MCONTROL_SELECT (1<<19) 97 #define MCONTROL_TIMING (1<<18) 98 #define MCONTROL_ACTION (0x3f<<12) 99 #define MCONTROL_CHAIN (1<<11) 100 #define MCONTROL_MATCH (0xf<<7) 101 #define MCONTROL_M (1<<6) 102 #define MCONTROL_H (1<<5) 103 #define MCONTROL_S (1<<4) 104 #define MCONTROL_U (1<<3) 105 #define MCONTROL_EXECUTE (1<<2) 106 #define MCONTROL_STORE (1<<1) 107 #define MCONTROL_LOAD (1<<0) 108 109 #define MCONTROL_TYPE_NONE 0 110 #define MCONTROL_TYPE_MATCH 2 111 112 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 113 #define MCONTROL_ACTION_DEBUG_MODE 1 114 #define MCONTROL_ACTION_TRACE_START 2 115 #define MCONTROL_ACTION_TRACE_STOP 3 116 #define MCONTROL_ACTION_TRACE_EMIT 4 117 118 #define MCONTROL_MATCH_EQUAL 0 119 #define MCONTROL_MATCH_NAPOT 1 120 #define MCONTROL_MATCH_GE 2 121 #define MCONTROL_MATCH_LT 3 122 #define MCONTROL_MATCH_MASK_LOW 4 123 #define MCONTROL_MATCH_MASK_HIGH 5 124 125 #define MIP_SSIP (1 << IRQ_S_SOFT) 126 #define MIP_HSIP (1 << IRQ_H_SOFT) 127 #define MIP_MSIP (1 << IRQ_M_SOFT) 128 #define MIP_STIP (1 << IRQ_S_TIMER) 129 #define MIP_HTIP (1 << IRQ_H_TIMER) 130 #define MIP_MTIP (1 << IRQ_M_TIMER) 131 #define MIP_SEIP (1 << IRQ_S_EXT) 132 #define MIP_HEIP (1 << IRQ_H_EXT) 133 #define MIP_MEIP (1 << IRQ_M_EXT) 134 135 #define SIP_SSIP MIP_SSIP 136 #define SIP_STIP MIP_STIP 137 138 #define PRV_U 0 139 #define PRV_S 1 140 #define PRV_H 2 141 #define PRV_M 3 142 143 #define SATP32_MODE 0x80000000 144 #define SATP32_ASID 0x7FC00000 145 #define SATP32_PPN 0x003FFFFF 146 #define SATP64_MODE 0xF000000000000000 147 #define SATP64_ASID 0x0FFFF00000000000 148 #define SATP64_PPN 0x00000FFFFFFFFFFF 149 150 #define SATP_MODE_OFF 0 151 #define SATP_MODE_SV32 1 152 #define SATP_MODE_SV39 8 153 #define SATP_MODE_SV48 9 154 #define SATP_MODE_SV57 10 155 #define SATP_MODE_SV64 11 156 157 #define PMP_R 0x01 158 #define PMP_W 0x02 159 #define PMP_X 0x04 160 #define PMP_A 0x18 161 #define PMP_L 0x80 162 #define PMP_SHIFT 2 163 164 #define PMP_TOR 0x08 165 #define PMP_NA4 0x10 166 #define PMP_NAPOT 0x18 167 168 #define IRQ_S_SOFT 1 169 #define IRQ_H_SOFT 2 170 #define IRQ_M_SOFT 3 171 #define IRQ_S_TIMER 5 172 #define IRQ_H_TIMER 6 173 #define IRQ_M_TIMER 7 174 #define IRQ_S_EXT 9 175 #define IRQ_H_EXT 10 176 #define IRQ_M_EXT 11 177 #define IRQ_COP 12 178 #define IRQ_HOST 13 179 180 #define DEFAULT_RSTVEC 0x00001000 181 #define CLINT_BASE 0x02000000 182 #define CLINT_SIZE 0x000c0000 183 #define EXT_IO_BASE 0x40000000 184 #define DRAM_BASE 0x80000000 185 186 // page table entry (PTE) fields 187 #define PTE_V 0x001 // Valid 188 #define PTE_R 0x002 // Read 189 #define PTE_W 0x004 // Write 190 #define PTE_X 0x008 // Execute 191 #define PTE_U 0x010 // User 192 #define PTE_G 0x020 // Global 193 #define PTE_A 0x040 // Accessed 194 #define PTE_D 0x080 // Dirty 195 #define PTE_SOFT 0x300 // Reserved for Software 196 197 #define PTE_PPN_SHIFT 10 198 199 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) 200 201 #ifdef __riscv 202 203 #define __RISCV_ISR __ALIGN(8) __attribute__((interrupt)) 204 #define __VPR_ISR __ALIGN(8) 205 206 #if defined(__riscv_xlen) && (__riscv_xlen == 64) 207 # define MSTATUS_SD MSTATUS64_SD 208 # define SSTATUS_SD SSTATUS64_SD 209 # define RISCV_PGLEVEL_BITS 9 210 # define SATP_MODE SATP64_MODE 211 #else 212 # define MSTATUS_SD MSTATUS32_SD 213 # define SSTATUS_SD SSTATUS32_SD 214 # define RISCV_PGLEVEL_BITS 10 215 # define SATP_MODE SATP32_MODE 216 #endif 217 #define RISCV_PGSHIFT 12 218 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) 219 220 #ifndef __ASSEMBLER__ 221 222 #ifdef __GNUC__ 223 224 #ifdef __ASSEMBLY__ 225 #define __ASM_STR(x) x 226 #else 227 #define __ASM_STR(x) #x 228 #endif 229 230 #ifndef __ASSEMBLY__ 231 232 #define nrf_csr_swap(csr, val) \ 233 ({ \ 234 unsigned long __v = (unsigned long)(val); \ 235 __asm__ __volatile__ ("csrrw %0, %1, %2" \ 236 : "=r" (__v) : "i" (csr), "rK" (__v) \ 237 : "memory"); \ 238 __v; \ 239 }) 240 241 #define nrf_csr_read(csr) \ 242 ({ \ 243 register unsigned long __v; \ 244 __asm__ __volatile__ ("csrr %0, %1" \ 245 : "=r" (__v) : "i" (csr) \ 246 : "memory"); \ 247 __v; \ 248 }) 249 250 #define nrf_csr_write(csr, val) \ 251 ({ \ 252 unsigned long __v = (unsigned long)(val); \ 253 __asm__ __volatile__ ("csrw %0, %1" \ 254 : : "i" (csr), "rK" (__v) \ 255 : "memory"); \ 256 }) 257 258 #define nrf_csr_read_and_set_bits(csr, mask) \ 259 ({ \ 260 unsigned long __v = (unsigned long)(mask); \ 261 __asm__ __volatile__ ("csrrs %0, %1, %2" \ 262 : "=r" (__v) : "i" (csr), "rK" (__v) \ 263 : "memory"); \ 264 __v; \ 265 }) 266 267 #define nrf_csr_set_bits(csr, mask) \ 268 ({ \ 269 unsigned long __v = (unsigned long)(mask); \ 270 __asm__ __volatile__ ("csrs %0, %1" \ 271 : : "i" (csr), "rK" (__v) \ 272 : "memory"); \ 273 }) 274 275 #define nrf_csr_read_and_clear_bits(csr, mask) \ 276 ({ \ 277 unsigned long __v = (unsigned long)(mask); \ 278 __asm__ __volatile__ ("csrrc %0, %1, %2" \ 279 : "=r" (__v) : "i" (csr), "rK" (__v) \ 280 : "memory"); \ 281 __v; \ 282 }) 283 284 #define nrf_csr_clear_bits(csr, mask) \ 285 ({ \ 286 unsigned long __v = (unsigned long)(mask); \ 287 __asm__ __volatile__ ("csrc %0, %1" \ 288 : : "i" (csr), "rK" (__v) \ 289 : "memory"); \ 290 }) 291 292 /* Define NRF_ENABLE_COMPAT_CSR_ACCESSORS to remove old csr accessor names. */ 293 #if !defined(__ZEPHYR__) && !defined(NRF_DISABLE_COMPAT_CSR_ACCESSORS) 294 #define csr_swap nrf_csr_swap 295 #define csr_read nrf_csr_read 296 #define csr_write nrf_csr_write 297 #define csr_read_and_set_bits nrf_csr_read_and_set_bits 298 #define csr_set_bits nrf_csr_set_bits 299 #define csr_read_and_clear_bits nrf_csr_read_and_clear_bits 300 #define csr_clear_bits nrf_csr_clear_bits 301 #endif 302 303 #ifdef __set_SP 304 #undef __set_SP 305 #endif 306 #define __set_SP(val) \ 307 ({ \ 308 unsigned long __v = (unsigned long)(val); \ 309 __asm__ __volatile__ ("add sp, %0, zero" \ 310 :: "rK" (__v) \ 311 : "memory"); \ 312 }) 313 314 #endif /* __ASSEMBLY__ */ 315 316 #endif 317 318 #endif 319 320 #endif 321 322 #endif 323
