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Searched refs:PWM_INTENSET_SEQEND1_Disabled (Results 1 – 10 of 10) sorted by relevance

/hal_nordic-3.6.0/nrfx/mdk/
Dnrf9120_bitfields.h5398 #define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */ macro
Dnrf52810_bitfields.h5453 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ macro
Dnrf52811_bitfields.h5453 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ macro
Dnrf9160_bitfields.h5320 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ macro
Dnrf52_bitfields.h8896 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ macro
Dnrf52833_bitfields.h8856 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ macro
Dnrf52840_bitfields.h8980 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ macro
Dnrf5340_application_bitfields.h9349 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ macro
Dnrf54l15_enga_types.h21924 …#define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled … macro
Dnrf54h20_enga_types.h63628 …#define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled … macro