1 /* 2 3 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_ENGA_RADIOCORE_H 36 #define NRF54H20_ENGA_RADIOCORE_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_RADIOCORE /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 53 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 54 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 55 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No 56 Match*/ 57 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 58 related Fault*/ 59 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 60 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 61 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 62 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 63 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 64 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 65 /* ============================================== Processor Specific Interrupts ============================================== */ 66 SPU000_IRQn = 0, /*!< 0 SPU000 */ 67 MPC_IRQn = 1, /*!< 1 MPC */ 68 MVDMA_IRQn = 3, /*!< 3 MVDMA */ 69 SPU010_IRQn = 16, /*!< 16 SPU010 */ 70 WDT010_IRQn = 19, /*!< 19 WDT010 */ 71 WDT011_IRQn = 20, /*!< 20 WDT011 */ 72 SPU020_IRQn = 32, /*!< 32 SPU020 */ 73 EGU020_IRQn = 37, /*!< 37 EGU020 */ 74 AAR020_CCM020_IRQn = 38, /*!< 38 AAR020_CCM020 */ 75 ECB020_IRQn = 39, /*!< 39 ECB020 */ 76 TIMER020_IRQn = 40, /*!< 40 TIMER020 */ 77 TIMER021_IRQn = 41, /*!< 41 TIMER021 */ 78 TIMER022_IRQn = 42, /*!< 42 TIMER022 */ 79 RTC_IRQn = 43, /*!< 43 RTC */ 80 RADIO_0_IRQn = 44, /*!< 44 RADIO_0 */ 81 RADIO_1_IRQn = 45, /*!< 45 RADIO_1 */ 82 SPU030_IRQn = 48, /*!< 48 SPU030 */ 83 VPR_IRQn = 52, /*!< 52 VPR */ 84 AAR030_CCM030_IRQn = 58, /*!< 58 AAR030_CCM030 */ 85 ECB030_IRQn = 59, /*!< 59 ECB030 */ 86 IPCT_0_IRQn = 64, /*!< 64 IPCT_0 */ 87 IPCT_1_IRQn = 65, /*!< 65 IPCT_1 */ 88 BELLBOARD_0_IRQn = 96, /*!< 96 BELLBOARD_0 */ 89 BELLBOARD_1_IRQn = 97, /*!< 97 BELLBOARD_1 */ 90 BELLBOARD_2_IRQn = 98, /*!< 98 BELLBOARD_2 */ 91 BELLBOARD_3_IRQn = 99, /*!< 99 BELLBOARD_3 */ 92 GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ 93 GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ 94 GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ 95 GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ 96 TBM_IRQn = 127, /*!< 127 TBM */ 97 USBHS_IRQn = 134, /*!< 134 USBHS */ 98 EXMIF_IRQn = 149, /*!< 149 EXMIF */ 99 IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ 100 I3C120_IRQn = 211, /*!< 211 I3C120 */ 101 VPR121_IRQn = 212, /*!< 212 VPR121 */ 102 CAN_IRQn = 216, /*!< 216 CAN */ 103 I3C121_IRQn = 222, /*!< 222 I3C121 */ 104 TIMER120_IRQn = 226, /*!< 226 TIMER120 */ 105 TIMER121_IRQn = 227, /*!< 227 TIMER121 */ 106 PWM120_IRQn = 228, /*!< 228 PWM120 */ 107 SPIS120_UARTE120_IRQn = 229, /*!< 229 SPIS120_UARTE120 */ 108 SPIM120_IRQn = 230, /*!< 230 SPIM120 */ 109 SPIM121_IRQn = 231, /*!< 231 SPIM121 */ 110 VPR130_IRQn = 264, /*!< 264 VPR130 */ 111 IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ 112 RTC130_IRQn = 296, /*!< 296 RTC130 */ 113 RTC131_IRQn = 297, /*!< 297 RTC131 */ 114 WDT131_IRQn = 299, /*!< 299 WDT131 */ 115 WDT132_IRQn = 300, /*!< 300 WDT132 */ 116 SAADC_IRQn = 386, /*!< 386 SAADC */ 117 COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ 118 TEMP_IRQn = 388, /*!< 388 TEMP */ 119 NFCT_IRQn = 389, /*!< 389 NFCT */ 120 I2S130_IRQn = 402, /*!< 402 I2S130 */ 121 PDM_IRQn = 403, /*!< 403 PDM */ 122 QDEC130_IRQn = 404, /*!< 404 QDEC130 */ 123 QDEC131_IRQn = 405, /*!< 405 QDEC131 */ 124 I2S131_IRQn = 407, /*!< 407 I2S131 */ 125 TIMER130_IRQn = 418, /*!< 418 TIMER130 */ 126 TIMER131_IRQn = 419, /*!< 419 TIMER131 */ 127 PWM130_IRQn = 420, /*!< 420 PWM130 */ 128 SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ 129 SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ 130 TIMER132_IRQn = 434, /*!< 434 TIMER132 */ 131 TIMER133_IRQn = 435, /*!< 435 TIMER133 */ 132 PWM131_IRQn = 436, /*!< 436 PWM131 */ 133 SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ 134 SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ 135 TIMER134_IRQn = 450, /*!< 450 TIMER134 */ 136 TIMER135_IRQn = 451, /*!< 451 TIMER135 */ 137 PWM132_IRQn = 452, /*!< 452 PWM132 */ 138 SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ 139 SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ 140 TIMER136_IRQn = 466, /*!< 466 TIMER136 */ 141 TIMER137_IRQn = 467, /*!< 467 TIMER137 */ 142 PWM133_IRQn = 468, /*!< 468 PWM133 */ 143 SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ 144 SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ 145 } IRQn_Type; 146 147 148 /* =========================================================================================================================== */ 149 /* ================ Processor and Core Peripheral Section ================ */ 150 /* =========================================================================================================================== */ 151 152 /* =========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals ============================ */ 153 #define __CM33_REV r0p4 /*!< CM33 Core Revision */ 154 #define __DSP_PRESENT 1 /*!< DSP present or not */ 155 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 156 #define __VTOR_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 157 #define __MPU_PRESENT 1 /*!< MPU present */ 158 #define __FPU_PRESENT 1 /*!< FPU present */ 159 #define __FPU_DP 0 /*!< Double Precision FPU */ 160 #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ 161 #define __Vendor_SysTickConfig 0 /*!< Vendor SysTick Config implementation is used */ 162 #define __SAUREGION_PRESENT 1 /*!< SAU present */ 163 #define __NUM_SAUREGIONS 4 /*!< Number of regions */ 164 165 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 166 #include "system_nrf.h" /*!< nrf54h20_enga_radiocore System Library */ 167 168 #endif /*!< NRF_RADIOCORE */ 169 170 171 /* ========================================= Start of section using anonymous unions ========================================= */ 172 173 #include "compiler_abstraction.h" 174 175 #if defined (__CC_ARM) 176 #pragma push 177 #pragma anon_unions 178 #elif defined (__ICCARM__) 179 #pragma language=extended 180 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 181 #pragma clang diagnostic push 182 #pragma clang diagnostic ignored "-Wc11-extensions" 183 #pragma clang diagnostic ignored "-Wreserved-id-macro" 184 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 185 #pragma clang diagnostic ignored "-Wnested-anon-types" 186 #elif defined (__GNUC__) 187 /* anonymous unions are enabled by default */ 188 #elif defined (__TMS470__) 189 /* anonymous unions are enabled by default */ 190 #elif defined (__TASKING__) 191 #pragma warning 586 192 #elif defined (__CSMC__) 193 /* anonymous unions are enabled by default */ 194 #else 195 #warning Unsupported compiler type 196 #endif 197 198 /* =========================================================================================================================== */ 199 /* ================ Peripheral Address Map ================ */ 200 /* =========================================================================================================================== */ 201 202 #define NRF_RADIOCORE_UICR_NS_BASE 0x0FFFA000UL 203 #define NRF_RADIOCORE_ICACHEDATA_S_BASE 0x13F00000UL 204 #define NRF_RADIOCORE_ICACHEINFO_S_BASE 0x13F10000UL 205 #define NRF_RADIOCORE_DCACHEDATA_S_BASE 0x33F00000UL 206 #define NRF_RADIOCORE_DCACHEINFO_S_BASE 0x33F10000UL 207 #define NRF_RADIOCORE_ETM_NS_BASE 0xE0041000UL 208 #define NRF_RADIOCORE_CTI_S_BASE 0xE0042000UL 209 #define NRF_RADIOCORE_CPUC_S_BASE 0xE0080000UL 210 #define NRF_RADIOCORE_ICACHE_S_BASE 0xE0082000UL 211 #define NRF_RADIOCORE_DCACHE_S_BASE 0xE0083000UL 212 #define NRF_RADIOCORE_SPU000_S_BASE 0x53000000UL 213 #define NRF_RADIOCORE_MPC_S_BASE 0x53001000UL 214 #define NRF_RADIOCORE_MVDMA_NS_BASE 0x43003000UL 215 #define NRF_RADIOCORE_MVDMA_S_BASE 0x53003000UL 216 #define NRF_RADIOCORE_RAMC000_NS_BASE 0x43004000UL 217 #define NRF_RADIOCORE_RAMC000_S_BASE 0x53004000UL 218 #define NRF_RADIOCORE_HSFLL_S_BASE 0x5300D000UL 219 #define NRF_RADIOCORE_LRCCONF000_S_BASE 0x5300E000UL 220 #define NRF_RADIOCORE_SPU010_S_BASE 0x53010000UL 221 #define NRF_RADIOCORE_MEMCONF_NS_BASE 0x43012000UL 222 #define NRF_RADIOCORE_MEMCONF_S_BASE 0x53012000UL 223 #define NRF_RADIOCORE_WDT010_NS_BASE 0x43013000UL 224 #define NRF_RADIOCORE_WDT010_S_BASE 0x53013000UL 225 #define NRF_RADIOCORE_WDT011_NS_BASE 0x43014000UL 226 #define NRF_RADIOCORE_WDT011_S_BASE 0x53014000UL 227 #define NRF_RADIOCORE_LRCCONF010_S_BASE 0x5301E000UL 228 #define NRF_RADIOCORE_RESETINFO_S_BASE 0x5301E000UL 229 #define NRF_RADIOCORE_SPU020_S_BASE 0x53020000UL 230 #define NRF_RADIOCORE_DPPIC020_NS_BASE 0x43022000UL 231 #define NRF_RADIOCORE_DPPIC020_S_BASE 0x53022000UL 232 #define NRF_RADIOCORE_PPIB020_S_BASE 0x53023000UL 233 #define NRF_RADIOCORE_EGU020_NS_BASE 0x43025000UL 234 #define NRF_RADIOCORE_EGU020_S_BASE 0x53025000UL 235 #define NRF_RADIOCORE_AAR020_NS_BASE 0x43026000UL 236 #define NRF_RADIOCORE_CCM020_NS_BASE 0x43026000UL 237 #define NRF_RADIOCORE_AAR020_S_BASE 0x53026000UL 238 #define NRF_RADIOCORE_CCM020_S_BASE 0x53026000UL 239 #define NRF_RADIOCORE_ECB020_NS_BASE 0x43027000UL 240 #define NRF_RADIOCORE_ECB020_S_BASE 0x53027000UL 241 #define NRF_RADIOCORE_TIMER020_NS_BASE 0x43028000UL 242 #define NRF_RADIOCORE_TIMER020_S_BASE 0x53028000UL 243 #define NRF_RADIOCORE_TIMER021_NS_BASE 0x43029000UL 244 #define NRF_RADIOCORE_TIMER021_S_BASE 0x53029000UL 245 #define NRF_RADIOCORE_TIMER022_NS_BASE 0x4302A000UL 246 #define NRF_RADIOCORE_TIMER022_S_BASE 0x5302A000UL 247 #define NRF_RADIOCORE_RTC_NS_BASE 0x4302B000UL 248 #define NRF_RADIOCORE_RTC_S_BASE 0x5302B000UL 249 #define NRF_RADIOCORE_RADIO_NS_BASE 0x4302C000UL 250 #define NRF_RADIOCORE_RADIO_S_BASE 0x5302C000UL 251 #define NRF_RADIOCORE_LRCCONF020_S_BASE 0x5302E000UL 252 #define NRF_RADIOCORE_SPU030_S_BASE 0x53030000UL 253 #define NRF_RADIOCORE_PPIB030_S_BASE 0x53031000UL 254 #define NRF_RADIOCORE_VPR_NS_BASE 0x43034000UL 255 #define NRF_RADIOCORE_VPR_S_BASE 0x53034000UL 256 #define NRF_RADIOCORE_RAMC001_NS_BASE 0x43038000UL 257 #define NRF_RADIOCORE_RAMC001_S_BASE 0x53038000UL 258 #define NRF_RADIOCORE_AAR030_NS_BASE 0x4303A000UL 259 #define NRF_RADIOCORE_CCM030_NS_BASE 0x4303A000UL 260 #define NRF_RADIOCORE_AAR030_S_BASE 0x5303A000UL 261 #define NRF_RADIOCORE_CCM030_S_BASE 0x5303A000UL 262 #define NRF_RADIOCORE_ECB030_NS_BASE 0x4303B000UL 263 #define NRF_RADIOCORE_ECB030_S_BASE 0x5303B000UL 264 #define NRF_RADIOCORE_IPCT_NS_BASE 0x43024000UL 265 #define NRF_RADIOCORE_IPCT_S_BASE 0x53024000UL 266 #define NRF_RADIOCORE_BELLBOARD_NS_BASE 0x4F09B000UL 267 #define NRF_RADIOCORE_BELLBOARD_S_BASE 0x5F09B000UL 268 269 /* =========================================================================================================================== */ 270 /* ================ Peripheral Declaration ================ */ 271 /* =========================================================================================================================== */ 272 273 #define NRF_RADIOCORE_UICR_NS ((NRF_UICR_Type*) NRF_RADIOCORE_UICR_NS_BASE) 274 #define NRF_RADIOCORE_ICACHEDATA_S ((NRF_CACHEDATA_Type*) NRF_RADIOCORE_ICACHEDATA_S_BASE) 275 #define NRF_RADIOCORE_ICACHEINFO_S ((NRF_CACHEINFO_Type*) NRF_RADIOCORE_ICACHEINFO_S_BASE) 276 #define NRF_RADIOCORE_DCACHEDATA_S ((NRF_CACHEDATA_Type*) NRF_RADIOCORE_DCACHEDATA_S_BASE) 277 #define NRF_RADIOCORE_DCACHEINFO_S ((NRF_CACHEINFO_Type*) NRF_RADIOCORE_DCACHEINFO_S_BASE) 278 #define NRF_RADIOCORE_ETM_NS ((NRF_ETM_Type*) NRF_RADIOCORE_ETM_NS_BASE) 279 #define NRF_RADIOCORE_CTI_S ((NRF_CTI_Type*) NRF_RADIOCORE_CTI_S_BASE) 280 #define NRF_RADIOCORE_CPUC_S ((NRF_CM33SS_Type*) NRF_RADIOCORE_CPUC_S_BASE) 281 #define NRF_RADIOCORE_ICACHE_S ((NRF_CACHE_Type*) NRF_RADIOCORE_ICACHE_S_BASE) 282 #define NRF_RADIOCORE_DCACHE_S ((NRF_CACHE_Type*) NRF_RADIOCORE_DCACHE_S_BASE) 283 #define NRF_RADIOCORE_SPU000_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU000_S_BASE) 284 #define NRF_RADIOCORE_MPC_S ((NRF_MPC_Type*) NRF_RADIOCORE_MPC_S_BASE) 285 #define NRF_RADIOCORE_MVDMA_NS ((NRF_MVDMA_Type*) NRF_RADIOCORE_MVDMA_NS_BASE) 286 #define NRF_RADIOCORE_MVDMA_S ((NRF_MVDMA_Type*) NRF_RADIOCORE_MVDMA_S_BASE) 287 #define NRF_RADIOCORE_RAMC000_NS ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC000_NS_BASE) 288 #define NRF_RADIOCORE_RAMC000_S ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC000_S_BASE) 289 #define NRF_RADIOCORE_HSFLL_S ((NRF_HSFLL_Type*) NRF_RADIOCORE_HSFLL_S_BASE) 290 #define NRF_RADIOCORE_LRCCONF000_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF000_S_BASE) 291 #define NRF_RADIOCORE_SPU010_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU010_S_BASE) 292 #define NRF_RADIOCORE_MEMCONF_NS ((NRF_MEMCONF_Type*) NRF_RADIOCORE_MEMCONF_NS_BASE) 293 #define NRF_RADIOCORE_MEMCONF_S ((NRF_MEMCONF_Type*) NRF_RADIOCORE_MEMCONF_S_BASE) 294 #define NRF_RADIOCORE_WDT010_NS ((NRF_WDT_Type*) NRF_RADIOCORE_WDT010_NS_BASE) 295 #define NRF_RADIOCORE_WDT010_S ((NRF_WDT_Type*) NRF_RADIOCORE_WDT010_S_BASE) 296 #define NRF_RADIOCORE_WDT011_NS ((NRF_WDT_Type*) NRF_RADIOCORE_WDT011_NS_BASE) 297 #define NRF_RADIOCORE_WDT011_S ((NRF_WDT_Type*) NRF_RADIOCORE_WDT011_S_BASE) 298 #define NRF_RADIOCORE_LRCCONF010_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF010_S_BASE) 299 #define NRF_RADIOCORE_RESETINFO_S ((NRF_RESETINFO_Type*) NRF_RADIOCORE_RESETINFO_S_BASE) 300 #define NRF_RADIOCORE_SPU020_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU020_S_BASE) 301 #define NRF_RADIOCORE_DPPIC020_NS ((NRF_DPPIC_Type*) NRF_RADIOCORE_DPPIC020_NS_BASE) 302 #define NRF_RADIOCORE_DPPIC020_S ((NRF_DPPIC_Type*) NRF_RADIOCORE_DPPIC020_S_BASE) 303 #define NRF_RADIOCORE_PPIB020_S ((NRF_PPIB_Type*) NRF_RADIOCORE_PPIB020_S_BASE) 304 #define NRF_RADIOCORE_EGU020_NS ((NRF_EGU_Type*) NRF_RADIOCORE_EGU020_NS_BASE) 305 #define NRF_RADIOCORE_EGU020_S ((NRF_EGU_Type*) NRF_RADIOCORE_EGU020_S_BASE) 306 #define NRF_RADIOCORE_AAR020_NS ((NRF_AAR_Type*) NRF_RADIOCORE_AAR020_NS_BASE) 307 #define NRF_RADIOCORE_CCM020_NS ((NRF_CCM_Type*) NRF_RADIOCORE_CCM020_NS_BASE) 308 #define NRF_RADIOCORE_AAR020_S ((NRF_AAR_Type*) NRF_RADIOCORE_AAR020_S_BASE) 309 #define NRF_RADIOCORE_CCM020_S ((NRF_CCM_Type*) NRF_RADIOCORE_CCM020_S_BASE) 310 #define NRF_RADIOCORE_ECB020_NS ((NRF_ECB_Type*) NRF_RADIOCORE_ECB020_NS_BASE) 311 #define NRF_RADIOCORE_ECB020_S ((NRF_ECB_Type*) NRF_RADIOCORE_ECB020_S_BASE) 312 #define NRF_RADIOCORE_TIMER020_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER020_NS_BASE) 313 #define NRF_RADIOCORE_TIMER020_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER020_S_BASE) 314 #define NRF_RADIOCORE_TIMER021_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER021_NS_BASE) 315 #define NRF_RADIOCORE_TIMER021_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER021_S_BASE) 316 #define NRF_RADIOCORE_TIMER022_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER022_NS_BASE) 317 #define NRF_RADIOCORE_TIMER022_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER022_S_BASE) 318 #define NRF_RADIOCORE_RTC_NS ((NRF_RTC_Type*) NRF_RADIOCORE_RTC_NS_BASE) 319 #define NRF_RADIOCORE_RTC_S ((NRF_RTC_Type*) NRF_RADIOCORE_RTC_S_BASE) 320 #define NRF_RADIOCORE_RADIO_NS ((NRF_RADIO_Type*) NRF_RADIOCORE_RADIO_NS_BASE) 321 #define NRF_RADIOCORE_RADIO_S ((NRF_RADIO_Type*) NRF_RADIOCORE_RADIO_S_BASE) 322 #define NRF_RADIOCORE_LRCCONF020_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF020_S_BASE) 323 #define NRF_RADIOCORE_SPU030_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU030_S_BASE) 324 #define NRF_RADIOCORE_PPIB030_S ((NRF_PPIB_Type*) NRF_RADIOCORE_PPIB030_S_BASE) 325 #define NRF_RADIOCORE_VPR_NS ((NRF_VPR_Type*) NRF_RADIOCORE_VPR_NS_BASE) 326 #define NRF_RADIOCORE_VPR_S ((NRF_VPR_Type*) NRF_RADIOCORE_VPR_S_BASE) 327 #define NRF_RADIOCORE_RAMC001_NS ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC001_NS_BASE) 328 #define NRF_RADIOCORE_RAMC001_S ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC001_S_BASE) 329 #define NRF_RADIOCORE_AAR030_NS ((NRF_AAR_Type*) NRF_RADIOCORE_AAR030_NS_BASE) 330 #define NRF_RADIOCORE_CCM030_NS ((NRF_CCM_Type*) NRF_RADIOCORE_CCM030_NS_BASE) 331 #define NRF_RADIOCORE_AAR030_S ((NRF_AAR_Type*) NRF_RADIOCORE_AAR030_S_BASE) 332 #define NRF_RADIOCORE_CCM030_S ((NRF_CCM_Type*) NRF_RADIOCORE_CCM030_S_BASE) 333 #define NRF_RADIOCORE_ECB030_NS ((NRF_ECB_Type*) NRF_RADIOCORE_ECB030_NS_BASE) 334 #define NRF_RADIOCORE_ECB030_S ((NRF_ECB_Type*) NRF_RADIOCORE_ECB030_S_BASE) 335 #define NRF_RADIOCORE_IPCT_NS ((NRF_IPCT_Type*) NRF_RADIOCORE_IPCT_NS_BASE) 336 #define NRF_RADIOCORE_IPCT_S ((NRF_IPCT_Type*) NRF_RADIOCORE_IPCT_S_BASE) 337 #define NRF_RADIOCORE_BELLBOARD_NS ((NRF_BELLBOARD_Type*) NRF_RADIOCORE_BELLBOARD_NS_BASE) 338 #define NRF_RADIOCORE_BELLBOARD_S ((NRF_BELLBOARD_Type*) NRF_RADIOCORE_BELLBOARD_S_BASE) 339 340 /* =========================================================================================================================== */ 341 /* ================ TrustZone Remapping ================ */ 342 /* =========================================================================================================================== */ 343 344 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ 345 #define NRF_RADIOCORE_UICR NRF_RADIOCORE_UICR_NS 346 #define NRF_RADIOCORE_ETM NRF_RADIOCORE_ETM_NS 347 #define NRF_RADIOCORE_MVDMA NRF_RADIOCORE_MVDMA_NS 348 #define NRF_RADIOCORE_RAMC000 NRF_RADIOCORE_RAMC000_NS 349 #define NRF_RADIOCORE_MEMCONF NRF_RADIOCORE_MEMCONF_NS 350 #define NRF_RADIOCORE_WDT010 NRF_RADIOCORE_WDT010_NS 351 #define NRF_RADIOCORE_WDT011 NRF_RADIOCORE_WDT011_NS 352 #define NRF_RADIOCORE_DPPIC020 NRF_RADIOCORE_DPPIC020_NS 353 #define NRF_RADIOCORE_EGU020 NRF_RADIOCORE_EGU020_NS 354 #define NRF_RADIOCORE_AAR020 NRF_RADIOCORE_AAR020_NS 355 #define NRF_RADIOCORE_CCM020 NRF_RADIOCORE_CCM020_NS 356 #define NRF_RADIOCORE_ECB020 NRF_RADIOCORE_ECB020_NS 357 #define NRF_RADIOCORE_TIMER020 NRF_RADIOCORE_TIMER020_NS 358 #define NRF_RADIOCORE_TIMER021 NRF_RADIOCORE_TIMER021_NS 359 #define NRF_RADIOCORE_TIMER022 NRF_RADIOCORE_TIMER022_NS 360 #define NRF_RADIOCORE_RTC NRF_RADIOCORE_RTC_NS 361 #define NRF_RADIOCORE_RADIO NRF_RADIOCORE_RADIO_NS 362 #define NRF_RADIOCORE_VPR NRF_RADIOCORE_VPR_NS 363 #define NRF_RADIOCORE_RAMC001 NRF_RADIOCORE_RAMC001_NS 364 #define NRF_RADIOCORE_AAR030 NRF_RADIOCORE_AAR030_NS 365 #define NRF_RADIOCORE_CCM030 NRF_RADIOCORE_CCM030_NS 366 #define NRF_RADIOCORE_ECB030 NRF_RADIOCORE_ECB030_NS 367 #define NRF_RADIOCORE_IPCT NRF_RADIOCORE_IPCT_NS 368 #define NRF_RADIOCORE_BELLBOARD NRF_RADIOCORE_BELLBOARD_NS 369 #else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ 370 #define NRF_RADIOCORE_UICR NRF_RADIOCORE_UICR_NS 371 #define NRF_RADIOCORE_ICACHEDATA NRF_RADIOCORE_ICACHEDATA_S 372 #define NRF_RADIOCORE_ICACHEINFO NRF_RADIOCORE_ICACHEINFO_S 373 #define NRF_RADIOCORE_DCACHEDATA NRF_RADIOCORE_DCACHEDATA_S 374 #define NRF_RADIOCORE_DCACHEINFO NRF_RADIOCORE_DCACHEINFO_S 375 #define NRF_RADIOCORE_ETM NRF_RADIOCORE_ETM_NS 376 #define NRF_RADIOCORE_CTI NRF_RADIOCORE_CTI_S 377 #define NRF_RADIOCORE_CPUC NRF_RADIOCORE_CPUC_S 378 #define NRF_RADIOCORE_ICACHE NRF_RADIOCORE_ICACHE_S 379 #define NRF_RADIOCORE_DCACHE NRF_RADIOCORE_DCACHE_S 380 #define NRF_RADIOCORE_SPU000 NRF_RADIOCORE_SPU000_S 381 #define NRF_RADIOCORE_MPC NRF_RADIOCORE_MPC_S 382 #define NRF_RADIOCORE_MVDMA NRF_RADIOCORE_MVDMA_S 383 #define NRF_RADIOCORE_RAMC000 NRF_RADIOCORE_RAMC000_S 384 #define NRF_RADIOCORE_HSFLL NRF_RADIOCORE_HSFLL_S 385 #define NRF_RADIOCORE_LRCCONF000 NRF_RADIOCORE_LRCCONF000_S 386 #define NRF_RADIOCORE_SPU010 NRF_RADIOCORE_SPU010_S 387 #define NRF_RADIOCORE_MEMCONF NRF_RADIOCORE_MEMCONF_S 388 #define NRF_RADIOCORE_WDT010 NRF_RADIOCORE_WDT010_S 389 #define NRF_RADIOCORE_WDT011 NRF_RADIOCORE_WDT011_S 390 #define NRF_RADIOCORE_LRCCONF010 NRF_RADIOCORE_LRCCONF010_S 391 #define NRF_RADIOCORE_RESETINFO NRF_RADIOCORE_RESETINFO_S 392 #define NRF_RADIOCORE_SPU020 NRF_RADIOCORE_SPU020_S 393 #define NRF_RADIOCORE_DPPIC020 NRF_RADIOCORE_DPPIC020_S 394 #define NRF_RADIOCORE_PPIB020 NRF_RADIOCORE_PPIB020_S 395 #define NRF_RADIOCORE_EGU020 NRF_RADIOCORE_EGU020_S 396 #define NRF_RADIOCORE_AAR020 NRF_RADIOCORE_AAR020_S 397 #define NRF_RADIOCORE_CCM020 NRF_RADIOCORE_CCM020_S 398 #define NRF_RADIOCORE_ECB020 NRF_RADIOCORE_ECB020_S 399 #define NRF_RADIOCORE_TIMER020 NRF_RADIOCORE_TIMER020_S 400 #define NRF_RADIOCORE_TIMER021 NRF_RADIOCORE_TIMER021_S 401 #define NRF_RADIOCORE_TIMER022 NRF_RADIOCORE_TIMER022_S 402 #define NRF_RADIOCORE_RTC NRF_RADIOCORE_RTC_S 403 #define NRF_RADIOCORE_RADIO NRF_RADIOCORE_RADIO_S 404 #define NRF_RADIOCORE_LRCCONF020 NRF_RADIOCORE_LRCCONF020_S 405 #define NRF_RADIOCORE_SPU030 NRF_RADIOCORE_SPU030_S 406 #define NRF_RADIOCORE_PPIB030 NRF_RADIOCORE_PPIB030_S 407 #define NRF_RADIOCORE_VPR NRF_RADIOCORE_VPR_S 408 #define NRF_RADIOCORE_RAMC001 NRF_RADIOCORE_RAMC001_S 409 #define NRF_RADIOCORE_AAR030 NRF_RADIOCORE_AAR030_S 410 #define NRF_RADIOCORE_CCM030 NRF_RADIOCORE_CCM030_S 411 #define NRF_RADIOCORE_ECB030 NRF_RADIOCORE_ECB030_S 412 #define NRF_RADIOCORE_IPCT NRF_RADIOCORE_IPCT_S 413 #define NRF_RADIOCORE_BELLBOARD NRF_RADIOCORE_BELLBOARD_S 414 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 415 416 /* =========================================================================================================================== */ 417 /* ================ Local Domain Remapping ================ */ 418 /* =========================================================================================================================== */ 419 420 #ifdef NRF_RADIOCORE /*!< Remap NRF_DOMAIN instances to NRF_X symbol for ease of use. */ 421 #define NRF_UICR NRF_RADIOCORE_UICR 422 #define NRF_ICACHEDATA NRF_RADIOCORE_ICACHEDATA 423 #define NRF_ICACHEINFO NRF_RADIOCORE_ICACHEINFO 424 #define NRF_DCACHEDATA NRF_RADIOCORE_DCACHEDATA 425 #define NRF_DCACHEINFO NRF_RADIOCORE_DCACHEINFO 426 #define NRF_ETM NRF_RADIOCORE_ETM 427 #define NRF_CTI NRF_RADIOCORE_CTI 428 #define NRF_CPUC NRF_RADIOCORE_CPUC 429 #define NRF_ICACHE NRF_RADIOCORE_ICACHE 430 #define NRF_DCACHE NRF_RADIOCORE_DCACHE 431 #define NRF_SPU000 NRF_RADIOCORE_SPU000 432 #define NRF_MPC NRF_RADIOCORE_MPC 433 #define NRF_MVDMA NRF_RADIOCORE_MVDMA 434 #define NRF_RAMC000 NRF_RADIOCORE_RAMC000 435 #define NRF_HSFLL NRF_RADIOCORE_HSFLL 436 #define NRF_LRCCONF000 NRF_RADIOCORE_LRCCONF000 437 #define NRF_SPU010 NRF_RADIOCORE_SPU010 438 #define NRF_MEMCONF NRF_RADIOCORE_MEMCONF 439 #define NRF_WDT010 NRF_RADIOCORE_WDT010 440 #define NRF_WDT011 NRF_RADIOCORE_WDT011 441 #define NRF_LRCCONF010 NRF_RADIOCORE_LRCCONF010 442 #define NRF_RESETINFO NRF_RADIOCORE_RESETINFO 443 #define NRF_SPU020 NRF_RADIOCORE_SPU020 444 #define NRF_DPPIC020 NRF_RADIOCORE_DPPIC020 445 #define NRF_PPIB020 NRF_RADIOCORE_PPIB020 446 #define NRF_EGU020 NRF_RADIOCORE_EGU020 447 #define NRF_AAR020 NRF_RADIOCORE_AAR020 448 #define NRF_CCM020 NRF_RADIOCORE_CCM020 449 #define NRF_ECB020 NRF_RADIOCORE_ECB020 450 #define NRF_TIMER020 NRF_RADIOCORE_TIMER020 451 #define NRF_TIMER021 NRF_RADIOCORE_TIMER021 452 #define NRF_TIMER022 NRF_RADIOCORE_TIMER022 453 #define NRF_RTC NRF_RADIOCORE_RTC 454 #define NRF_RADIO NRF_RADIOCORE_RADIO 455 #define NRF_LRCCONF020 NRF_RADIOCORE_LRCCONF020 456 #define NRF_SPU030 NRF_RADIOCORE_SPU030 457 #define NRF_PPIB030 NRF_RADIOCORE_PPIB030 458 #define NRF_VPR NRF_RADIOCORE_VPR 459 #define NRF_RAMC001 NRF_RADIOCORE_RAMC001 460 #define NRF_AAR030 NRF_RADIOCORE_AAR030 461 #define NRF_CCM030 NRF_RADIOCORE_CCM030 462 #define NRF_ECB030 NRF_RADIOCORE_ECB030 463 #define NRF_IPCT NRF_RADIOCORE_IPCT 464 #define NRF_BELLBOARD NRF_RADIOCORE_BELLBOARD 465 #endif /*!< NRF_RADIOCORE */ 466 467 /* ========================================== End of section using anonymous unions ========================================== */ 468 469 #if defined (__CC_ARM) 470 #pragma pop 471 #elif defined (__ICCARM__) 472 /* leave anonymous unions enabled */ 473 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 474 #pragma clang diagnostic pop 475 #elif defined (__GNUC__) 476 /* anonymous unions are enabled by default */ 477 #elif defined (__TMS470__) 478 /* anonymous unions are enabled by default */ 479 #elif defined (__TASKING__) 480 #pragma warning restore 481 #elif defined (__CSMC__) 482 /* anonymous unions are enabled by default */ 483 #endif 484 485 486 #ifdef __cplusplus 487 } 488 #endif 489 #endif /* NRF54H20_ENGA_RADIOCORE_H */ 490 491
