1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_PWM_H__
35 #define NRF_PWM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_pwm_hal PWM HAL
45 * @{
46 * @ingroup nrf_pwm
47 * @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral.
48 */
49
50 #if defined(PWM_DMA_SEQ_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
51 /** @brief Symbol indicating whether dedicated DMA register is present. */
52 #define NRF_PWM_HAS_DMA_REG 1
53 #else
54 #define NRF_PWM_HAS_DMA_REG 0
55 #endif
56
57 #if defined(PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk) || defined(__NRFX_DOXYGEN__)
58 /** @brief Symbol indicating whether shorting SEQSTART task with LOOPSDONE event is available. */
59 #define NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART 1
60 #else
61 #define NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART 0
62 #endif
63
64 #if (defined(PWM_TASKS_DMA_SEQ_START_START_Msk) && defined(PWM_EVENTS_DMA_SEQ_END_END_Msk)) || \
65 defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether PWM DMA tasks and events are present. */
67 #define NRF_PWM_HAS_DMA_TASKS_EVENTS 1
68 #else
69 #define NRF_PWM_HAS_DMA_TASKS_EVENTS 0
70 #endif
71
72 #if defined(PWM_SEQ_CNT_CNT_Msk) || defined(__NRFX_DOXYGEN__)
73 /** @brief Symbol indicating whether setting the number of duty cycle values for a sequence is available. */
74 #define NRF_PWM_HAS_SEQ_CNT 1
75 #else
76 #define NRF_PWM_HAS_SEQ_CNT 0
77 #endif
78
79 /**
80 * @brief Macro getting pointer to the structure of registers of the PWM peripheral.
81 *
82 * @param[in] idx PWM instance index.
83 *
84 * @return Pointer to the structure of registers of the PWM peripheral.
85 */
86 #define NRF_PWM_INST_GET(idx) NRFX_CONCAT(NRF_, PWM, idx)
87
88 /**
89 * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
90 * function call to specify that a given output channel shall not be
91 * connected to a physical pin.
92 */
93 #define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
94
95 /** @brief Number of channels in each PWM instance. */
96 #define NRF_PWM_CHANNEL_COUNT 4
97
98 /**
99 * @brief Helper macro for calculating the number of 16-bit values in the specified
100 * array of duty cycle values.
101 */
102 #define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / 2UL)
103
104
105 /** @brief PWM tasks. */
106 typedef enum
107 {
108 NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
109 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
110 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_DMA.SEQ[0].START), ///< Starts playback of sequence 0.
111 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_DMA.SEQ[1].START), ///< Starts playback of sequence 1.
112 #else
113 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
114 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
115 #endif
116 NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
117 } nrf_pwm_task_t;
118
119 /** @brief PWM events. */
120 typedef enum
121 {
122 NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
123 NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
124 NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
125 NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
126 NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
127 NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
128 NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the specified number of times.
129 } nrf_pwm_event_t;
130
131 /** @brief PWM interrupts. */
132 typedef enum
133 {
134 NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
135 NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event.
136 NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event.
137 NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event.
138 NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event.
139 NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
140 NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
141 } nrf_pwm_int_mask_t;
142
143 /** @brief PWM shortcuts. */
144 typedef enum
145 {
146 NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
147 NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task.
148 #if NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART
149 NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
150 NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
151 #endif
152 NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
153 } nrf_pwm_short_mask_t;
154
155 /** @brief PWM modes of operation. */
156 typedef enum
157 {
158 NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
159 NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
160 } nrf_pwm_mode_t;
161
162 /** @brief PWM base clock frequencies. */
163 typedef enum
164 {
165 NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
166 NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz.
167 NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz.
168 NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz.
169 NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
170 NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
171 NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
172 NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
173 } nrf_pwm_clk_t;
174
175 /**
176 * @brief PWM decoder load modes.
177 *
178 * The selected mode determines how the sequence data is read from RAM and
179 * spread to the compare registers.
180 */
181 typedef enum
182 {
183 NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3).
184 NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
185 NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
186 NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
187 } nrf_pwm_dec_load_t;
188
189 /**
190 * @brief PWM decoder next step modes.
191 *
192 * The selected mode determines when the next value from the active sequence
193 * is loaded.
194 */
195 typedef enum
196 {
197 NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
198 NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
199 } nrf_pwm_dec_step_t;
200
201 /**
202 * @brief Type used for defining duty cycle values for a sequence
203 * loaded in @ref NRF_PWM_LOAD_COMMON mode.
204 */
205 typedef uint16_t nrf_pwm_values_common_t;
206
207 /**
208 * @brief Structure for defining duty cycle values for a sequence
209 * loaded in @ref NRF_PWM_LOAD_GROUPED mode.
210 */
211 typedef struct {
212 uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
213 uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
214 } nrf_pwm_values_grouped_t;
215
216 /**
217 * @brief Structure for defining duty cycle values for a sequence
218 * loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
219 */
220 typedef struct
221 {
222 uint16_t channel_0; ///< Duty cycle value for channel 0.
223 uint16_t channel_1; ///< Duty cycle value for channel 1.
224 uint16_t channel_2; ///< Duty cycle value for channel 2.
225 uint16_t channel_3; ///< Duty cycle value for channel 3.
226 } nrf_pwm_values_individual_t;
227
228 /**
229 * @brief Structure for defining duty cycle values for a sequence
230 * loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
231 */
232 typedef struct {
233 uint16_t channel_0; ///< Duty cycle value for channel 0.
234 uint16_t channel_1; ///< Duty cycle value for channel 1.
235 uint16_t channel_2; ///< Duty cycle value for channel 2.
236 uint16_t counter_top; ///< Top value for the pulse generator counter.
237 } nrf_pwm_values_wave_form_t;
238
239 /**
240 * @brief Union grouping pointers to arrays of duty cycle values applicable to
241 * various loading modes.
242 */
243 typedef union {
244 nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
245 nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
246 nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
247 nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
248 uint16_t const * p_raw; ///< Pointer providing raw access to the values.
249 } nrf_pwm_values_t;
250
251 /**
252 * @brief Structure for defining a sequence of PWM duty cycles.
253 *
254 * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
255 * provided duty cycle values are not copied. The @p values pointer is stored
256 * in the internal register of the peripheral, and the values are loaded from RAM
257 * during the sequence playback. Therefore, you must ensure that the values
258 * do not change before and during the sequence playback (for example,
259 * the values cannot be placed in a local variable that is allocated on stack).
260 * If the sequence is played in a loop and the values are to be updated
261 * before the next iteration, it is safe to modify them when the corresponding
262 * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
263 * or @ref NRF_PWM_EVENT_SEQEND1, respectively).
264 *
265 * @note The @p repeats and @p end_delay values (which are written to the
266 * SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
267 * respectively) are ignored at the end of a complex sequence
268 * playback, indicated by the LOOPSDONE event.
269 * See the Product Specification for more information.
270 */
271 typedef struct
272 {
273 nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
274 /**< This field is defined as an union of pointers
275 * to provide a convenient way to define duty
276 * cycle values in various loading modes
277 * (see @ref nrf_pwm_dec_load_t).
278 * In each value, the most significant bit (15)
279 * determines the polarity of the output and the
280 * others (14-0) compose the 15-bit value to be
281 * compared with the pulse generator counter. */
282 uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
283 uint32_t repeats; ///< Number of times that each duty cycle is to be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
284 uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
285 } nrf_pwm_sequence_t;
286
287
288 /**
289 * @brief Function for activating the specified PWM task.
290 *
291 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
292 * @param[in] task Task to be activated.
293 */
294 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
295 nrf_pwm_task_t task);
296
297 /**
298 * @brief Function for getting the address of the specified PWM task register.
299 *
300 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
301 * @param[in] task PWM task.
302 *
303 * @return Address of the specified task register.
304 */
305 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
306 nrf_pwm_task_t task);
307
308 /**
309 * @brief Function for clearing the specified PWM event.
310 *
311 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
312 * @param[in] event Event to clear.
313 */
314 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
315 nrf_pwm_event_t event);
316
317 /**
318 * @brief Function for retrieving the state of the PWM event.
319 *
320 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
321 * @param[in] event Event to be checked.
322 *
323 * @retval true The event has been generated.
324 * @retval false The event has not been generated.
325 */
326 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
327 nrf_pwm_event_t event);
328
329 /**
330 * @brief Function for getting the address of the specified PWM event register.
331 *
332 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
333 * @param[in] event PWM event.
334 *
335 * @return Address of the specified event register.
336 */
337 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
338 nrf_pwm_event_t event);
339
340 /**
341 * @brief Function for enabling the specified shortcuts.
342 *
343 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
344 * @param[in] mask Mask of shortcuts to be enabled.
345 */
346 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
347 uint32_t mask);
348
349 /**
350 * @brief Function for disabling the specified shortcuts.
351 *
352 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
353 * @param[in] mask Mask of shortcuts to be disabled.
354 */
355 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
356 uint32_t mask);
357
358 /**
359 * @brief Function for setting the configuration of PWM shortcuts.
360 *
361 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
362 * @param[in] mask Shortcuts configuration to be set.
363 */
364 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
365 uint32_t mask);
366
367 /**
368 * @brief Function for enabling specified interrupts.
369 *
370 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
371 * @param[in] mask Mask of interrupts to be enabled.
372 * Use @ref nrf_pwm_int_mask_t values for bit masking.
373 */
374 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
375 uint32_t mask);
376
377 /**
378 * @brief Function for disabling specified interrupts.
379 *
380 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
381 * @param[in] mask Mask of interrupts to be disabled.
382 * Use @ref nrf_pwm_int_mask_t values for bit masking.
383 */
384 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
385 uint32_t mask);
386
387 /**
388 * @brief Function for setting the configuration of PWM interrupts.
389 *
390 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
391 * @param[in] mask Mask of interrupts to be set.
392 * Use @ref nrf_pwm_int_mask_t values for bit masking.
393 */
394 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
395 uint32_t mask);
396
397 /**
398 * @brief Function for checking if the specified interrupts are enabled.
399 *
400 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
401 * @param[in] mask Mask of interrupts to be checked.
402 * Use @ref nrf_pwm_int_mask_t values for bit masking.
403 *
404 * @return Mask of enabled interrupts.
405 */
406 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask);
407
408 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
409 /**
410 * @brief Function for setting the subscribe configuration for a given
411 * PWM task.
412 *
413 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
414 * @param[in] task Task for which to set the configuration.
415 * @param[in] channel Channel through which to subscribe events.
416 */
417 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
418 nrf_pwm_task_t task,
419 uint8_t channel);
420
421 /**
422 * @brief Function for clearing the subscribe configuration for a given
423 * PWM task.
424 *
425 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
426 * @param[in] task Task for which to clear the configuration.
427 */
428 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
429 nrf_pwm_task_t task);
430
431 /**
432 * @brief Function for setting the publish configuration for a given
433 * PWM event.
434 *
435 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
436 * @param[in] event Event for which to set the configuration.
437 * @param[in] channel Channel through which to publish the event.
438 */
439 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
440 nrf_pwm_event_t event,
441 uint8_t channel);
442
443 /**
444 * @brief Function for clearing the publish configuration for a given
445 * PWM event.
446 *
447 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
448 * @param[in] event Event for which to clear the configuration.
449 */
450 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
451 nrf_pwm_event_t event);
452 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
453
454 /**
455 * @brief Function for enabling the PWM peripheral.
456 *
457 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
458 */
459 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
460
461 /**
462 * @brief Function for disabling the PWM peripheral.
463 *
464 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
465 */
466 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
467
468 /**
469 * @brief Function for checking if the PWM peripheral is enabled.
470 *
471 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
472 *
473 * @retval true The PWM is enabled.
474 * @retval false The PWM is not enabled.
475 */
476 NRF_STATIC_INLINE bool nrf_pwm_enable_check(NRF_PWM_Type const * p_reg);
477
478 /**
479 * @brief Function for assigning pins to PWM output channels.
480 *
481 * Usage of all PWM output channels is optional. If a given channel is not
482 * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
483 * number.
484 *
485 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
486 * @param[in] out_pins Array with pin numbers for individual PWM output channels.
487 */
488 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
489 uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT]);
490
491 /**
492 * @brief Function for getting pin selection associated with specified PWM output channel.
493 *
494 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
495 * @param[in] channel PWM output channel.
496 *
497 * @return Pin selection associated with specified PWM output channel.
498 */
499 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel);
500
501 /**
502 * @brief Function for configuring the PWM peripheral.
503 *
504 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
505 * @param[in] base_clock Base clock frequency.
506 * @param[in] mode Operating mode of the pulse generator counter.
507 * @param[in] top_value Value up to which the pulse generator counter counts.
508 */
509 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
510 nrf_pwm_clk_t base_clock,
511 nrf_pwm_mode_t mode,
512 uint16_t top_value);
513
514 /**
515 * @brief Function for defining a sequence of PWM duty cycles.
516 *
517 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
518 * @param[in] seq_id Identifier of the sequence (0 or 1).
519 * @param[in] p_seq Pointer to the sequence definition.
520 */
521 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
522 uint8_t seq_id,
523 nrf_pwm_sequence_t const * p_seq);
524
525 /**
526 * @brief Function for modifying the pointer to the duty cycle values
527 * in the specified sequence.
528 *
529 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
530 * @param[in] seq_id Identifier of the sequence (0 or 1).
531 * @param[in] p_values Pointer to an array with duty cycle values.
532 */
533 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
534 uint8_t seq_id,
535 uint16_t const * p_values);
536
537 #if NRF_PWM_HAS_SEQ_CNT
538 /**
539 * @brief Function for modifying the total number of duty cycle values
540 * in the specified sequence.
541 *
542 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
543 * @param[in] seq_id Identifier of the sequence (0 or 1).
544 * @param[in] length Number of duty cycle values.
545 */
546 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
547 uint8_t seq_id,
548 uint16_t length);
549 #endif
550
551 /**
552 * @brief Function for modifying the additional number of PWM periods spent
553 * on each duty cycle value in the specified sequence.
554 *
555 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
556 * @param[in] seq_id Identifier of the sequence (0 or 1).
557 * @param[in] refresh Number of additional PWM periods for each duty cycle value.
558 */
559 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
560 uint8_t seq_id,
561 uint32_t refresh);
562
563 /**
564 * @brief Function for modifying the additional time added after the sequence
565 * is played.
566 *
567 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
568 * @param[in] seq_id Identifier of the sequence (0 or 1).
569 * @param[in] end_delay Number of PWM periods added at the end of the sequence.
570 */
571 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
572 uint8_t seq_id,
573 uint32_t end_delay);
574
575 /**
576 * @brief Function for setting the mode of loading sequence data from RAM
577 * and advancing the sequence.
578 *
579 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
580 * @param[in] dec_load Mode of loading sequence data from RAM.
581 * @param[in] dec_step Mode of advancing the active sequence.
582 */
583 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
584 nrf_pwm_dec_load_t dec_load,
585 nrf_pwm_dec_step_t dec_step);
586
587 /**
588 * @brief Function for setting the number of times the sequence playback
589 * should be performed.
590 *
591 * This function applies to two-sequence playback (concatenated sequence 0 and 1).
592 * A single sequence can be played back only once.
593 *
594 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
595 * @param[in] loop_count Number of times to perform the sequence playback.
596 */
597 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg, uint16_t loop_count);
598
599 /**
600 * @brief Function for getting the specified PWM SEQSTART task.
601 *
602 * @param[in] seq_id Sequence index.
603 *
604 * @return The specified PWM SEQSTART task.
605 */
606 NRF_STATIC_INLINE nrf_pwm_task_t nrf_pwm_seqstart_task_get(uint8_t seq_id);
607
608 /**
609 * @brief Function for getting the specified PWM SEQEND event.
610 *
611 * @param[in] seq_id Sequence index.
612 *
613 * @return The specified PWM SEQEND event.
614 */
615 NRF_STATIC_INLINE nrf_pwm_event_t nrf_pwm_seqend_event_get(uint8_t seq_id);
616
617
618 #ifndef NRF_DECLARE_ONLY
619
nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)620 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
621 nrf_pwm_task_t task)
622 {
623 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
624 }
625
nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_task_t task)626 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
627 nrf_pwm_task_t task)
628 {
629 return ((uint32_t)p_reg + (uint32_t)task);
630 }
631
nrf_pwm_event_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)632 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
633 nrf_pwm_event_t event)
634 {
635 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
636 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
637 }
638
nrf_pwm_event_check(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)639 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
640 nrf_pwm_event_t event)
641 {
642 return nrf_event_check(p_reg, event);
643 }
644
nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)645 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
646 nrf_pwm_event_t event)
647 {
648 return ((uint32_t)p_reg + (uint32_t)event);
649 }
650
nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,uint32_t mask)651 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg, uint32_t mask)
652 {
653 p_reg->SHORTS |= mask;
654 }
655
nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,uint32_t mask)656 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg, uint32_t mask)
657 {
658 p_reg->SHORTS &= ~(mask);
659 }
660
nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,uint32_t mask)661 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg, uint32_t mask)
662 {
663 p_reg->SHORTS = mask;
664 }
665
nrf_pwm_int_enable(NRF_PWM_Type * p_reg,uint32_t mask)666 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg, uint32_t mask)
667 {
668 p_reg->INTENSET = mask;
669 }
670
nrf_pwm_int_disable(NRF_PWM_Type * p_reg,uint32_t mask)671 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg, uint32_t mask)
672 {
673 p_reg->INTENCLR = mask;
674 }
675
nrf_pwm_int_set(NRF_PWM_Type * p_reg,uint32_t mask)676 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg, uint32_t mask)
677 {
678 p_reg->INTEN = mask;
679 }
680
nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,uint32_t mask)681 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask)
682 {
683 return p_reg->INTENSET & mask;
684 }
685
686 #if defined(DPPI_PRESENT)
nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,nrf_pwm_task_t task,uint8_t channel)687 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
688 nrf_pwm_task_t task,
689 uint8_t channel)
690 {
691 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
692 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
693 }
694
nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)695 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
696 nrf_pwm_task_t task)
697 {
698 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
699 }
700
nrf_pwm_publish_set(NRF_PWM_Type * p_reg,nrf_pwm_event_t event,uint8_t channel)701 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
702 nrf_pwm_event_t event,
703 uint8_t channel)
704 {
705 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
706 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
707 }
708
nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)709 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
710 nrf_pwm_event_t event)
711 {
712 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
713 }
714 #endif // defined(DPPI_PRESENT)
715
nrf_pwm_enable(NRF_PWM_Type * p_reg)716 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
717 {
718 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
719 }
720
nrf_pwm_disable(NRF_PWM_Type * p_reg)721 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
722 {
723 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
724 }
725
nrf_pwm_enable_check(NRF_PWM_Type const * p_reg)726 NRF_STATIC_INLINE bool nrf_pwm_enable_check(NRF_PWM_Type const * p_reg)
727 {
728 return p_reg->ENABLE == PWM_ENABLE_ENABLE_Enabled;
729 }
730
nrf_pwm_pins_set(NRF_PWM_Type * p_reg,uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT])731 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
732 uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT])
733 {
734 uint8_t i;
735 for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
736 {
737 p_reg->PSEL.OUT[i] = out_pins[i];
738 }
739 }
740
nrf_pwm_pin_get(NRF_PWM_Type const * p_reg,uint8_t channel)741 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel)
742 {
743 NRFX_ASSERT(channel < NRF_PWM_CHANNEL_COUNT);
744 return p_reg->PSEL.OUT[channel];
745 }
746
nrf_pwm_configure(NRF_PWM_Type * p_reg,nrf_pwm_clk_t base_clock,nrf_pwm_mode_t mode,uint16_t top_value)747 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
748 nrf_pwm_clk_t base_clock,
749 nrf_pwm_mode_t mode,
750 uint16_t top_value)
751 {
752 NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
753
754 p_reg->PRESCALER = base_clock;
755 p_reg->MODE = mode;
756 p_reg->COUNTERTOP = top_value;
757 }
758
nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,uint8_t seq_id,nrf_pwm_sequence_t const * p_seq)759 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
760 uint8_t seq_id,
761 nrf_pwm_sequence_t const * p_seq)
762 {
763 NRFX_ASSERT(p_seq != NULL);
764
765 nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw);
766 #if NRF_PWM_HAS_SEQ_CNT
767 nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length);
768 #endif
769 nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats);
770 nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
771 }
772
nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t const * p_values)773 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
774 uint8_t seq_id,
775 uint16_t const * p_values)
776 {
777 NRFX_ASSERT(seq_id <= 1);
778 NRFX_ASSERT(p_values != NULL);
779 #if NRF_PWM_HAS_DMA_REG
780 p_reg->DMA.SEQ[seq_id].PTR = (uint32_t)p_values;
781 #else
782 p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
783 #endif
784 }
785
786 #if NRF_PWM_HAS_SEQ_CNT
nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t length)787 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
788 uint8_t seq_id,
789 uint16_t length)
790 {
791 NRFX_ASSERT(seq_id <= 1);
792 NRFX_ASSERT(length != 0);
793 NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
794 p_reg->SEQ[seq_id].CNT = length;
795 }
796 #endif
797
nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t refresh)798 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
799 uint8_t seq_id,
800 uint32_t refresh)
801 {
802 NRFX_ASSERT(seq_id <= 1);
803 NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
804 p_reg->SEQ[seq_id].REFRESH = refresh;
805 }
806
nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t end_delay)807 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
808 uint8_t seq_id,
809 uint32_t end_delay)
810 {
811 NRFX_ASSERT(seq_id <= 1);
812 NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
813 p_reg->SEQ[seq_id].ENDDELAY = end_delay;
814 }
815
nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,nrf_pwm_dec_load_t dec_load,nrf_pwm_dec_step_t dec_step)816 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
817 nrf_pwm_dec_load_t dec_load,
818 nrf_pwm_dec_step_t dec_step)
819 {
820 p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
821 ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
822 }
823
nrf_pwm_loop_set(NRF_PWM_Type * p_reg,uint16_t loop_count)824 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
825 uint16_t loop_count)
826 {
827 p_reg->LOOP = loop_count;
828 }
829
nrf_pwm_seqstart_task_get(uint8_t seq_id)830 NRF_STATIC_INLINE nrf_pwm_task_t nrf_pwm_seqstart_task_get(uint8_t seq_id)
831 {
832 NRFX_ASSERT(seq_id <= 1);
833 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
834 return (nrf_pwm_task_t)NRFX_OFFSETOF(NRF_PWM_Type, TASKS_DMA.SEQ[seq_id].START);
835 #else
836 return (nrf_pwm_task_t)NRFX_OFFSETOF(NRF_PWM_Type, TASKS_SEQSTART[seq_id]);
837 #endif
838 }
839
nrf_pwm_seqend_event_get(uint8_t seq_id)840 NRF_STATIC_INLINE nrf_pwm_event_t nrf_pwm_seqend_event_get(uint8_t seq_id)
841 {
842 NRFX_ASSERT(seq_id <= 1);
843 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
844 return (nrf_pwm_event_t)NRFX_OFFSETOF(NRF_PWM_Type, EVENTS_DMA.SEQ[seq_id].END);
845 #else
846 return (nrf_pwm_event_t)NRFX_OFFSETOF(NRF_PWM_Type, EVENTS_SEQEND[seq_id]);
847 #endif
848 }
849
850 #endif // NRF_DECLARE_ONLY
851
852 /** @} */
853
854 #ifdef __cplusplus
855 }
856 #endif
857
858 #endif // NRF_PWM_H__
859
860
