1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_I2S_H__
35 #define NRF_I2S_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(HALTIUM_XXAA)
44 #define NRF_I2S_CLOCKPIN_SCK_NEEDED
45 #define NRF_I2S_CLOCKPIN_LRCK_NEEDED
46 #define NRF_I2S_CLOCKPIN_MCK_NEEDED
47 #endif
48
49 #if !defined(NRF_I2S0) && defined(NRF_I2S)
50 #define NRF_I2S0 NRF_I2S
51 #endif
52
53 /**
54 * @defgroup nrf_i2s_hal I2S HAL
55 * @{
56 * @ingroup nrf_i2s
57 * @brief Hardware access layer for managing the Inter-IC Sound (I2S) peripheral.
58 */
59
60 #if defined(I2S_CONFIG_CLKCONFIG_CLKSRC_Msk) || defined(__NRFX_DOXYGEN__)
61 /** @brief Symbol indicating whether clock source configuration is available. */
62 #define NRF_I2S_HAS_CLKCONFIG 1
63 #else
64 #define NRF_I2S_HAS_CLKCONFIG 0
65 #endif
66
67 #if defined(I2S_INTENSET_FRAMESTART_Msk) || defined(__NRFX_DOXYGEN__)
68 /** @brief Symbol indicating whether frame start event is available. */
69 #define NRF_I2S_HAS_FRAMESTART 1
70 #else
71 #define NRF_I2S_HAS_FRAMESTART 0
72 #endif
73
74 #if defined(I2S_PSEL_SCK_PORT_Msk) || defined(__NRFX_DOXYGEN__)
75 /** @brief Symbol indicating whether GPIO port selection for pins is available. */
76 #define NRF_I2S_HAS_GPIO_PORT_SELECTION 1
77 #else
78 #define NRF_I2S_HAS_GPIO_PORT_SELECTION 0
79 #endif
80
81 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_32Bit) || defined(__NRFX_DOXYGEN__)
82 /** @brief Symbol indicating whether 32-bit sample width is available. */
83 #define NRF_I2S_HAS_SWIDTH_32BIT 1
84 #else
85 #define NRF_I2S_HAS_SWIDTH_32BIT 0
86 #endif
87
88 /**
89 * @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set
90 * function call to specify that the given I2S signal (SDOUT, SDIN, or MCK)
91 * shall not be connected to a physical pin.
92 */
93 #define NRF_I2S_PIN_NOT_CONNECTED 0xFFFFFFFF
94
95 /** @brief I2S SCK pin selection mask. */
96 #define NRF_I2S_PSEL_SCK_PIN_MASK I2S_PSEL_SCK_PIN_Msk
97
98 /** @brief I2S SCK port selection mask. */
99 #define NRF_I2S_PSEL_SCK_PORT_MASK I2S_PSEL_SCK_PORT_Msk
100
101 /** @brief I2S tasks. */
102 typedef enum
103 {
104 NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled.
105 NRF_I2S_TASK_STOP = offsetof(NRF_I2S_Type, TASKS_STOP) ///< Stops I2S transfer. Also stops the MCK generator.
106 } nrf_i2s_task_t;
107
108 /** @brief I2S events. */
109 typedef enum
110 {
111 NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double buffers.
112 NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double buffers.
113 NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED), ///< I2S transfer stopped.
114 #if NRF_I2S_HAS_FRAMESTART
115 NRF_I2S_EVENT_FRAMESTART = offsetof(NRF_I2S_Type, EVENTS_FRAMESTART) ///< Frame start event, generated on the active edge of LRCK.
116 #endif
117 } nrf_i2s_event_t;
118
119 /** @brief I2S interrupts. */
120 typedef enum
121 {
122 NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
123 NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event.
124 NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
125 #if NRF_I2S_HAS_FRAMESTART
126 NRF_I2S_INT_FRAMESTART_MASK = I2S_INTENCLR_FRAMESTART_Msk ///< Interrupt on FRAMESTART event.
127 #endif
128 } nrf_i2s_int_mask_t;
129
130 /** @brief I2S modes of operation. */
131 typedef enum
132 {
133 NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode.
134 NRF_I2S_MODE_SLAVE = I2S_CONFIG_MODE_MODE_Slave ///< Slave mode.
135 } nrf_i2s_mode_t;
136
137 /** @brief I2S master clock generator settings. */
138 typedef enum
139 {
140 NRF_I2S_MCK_DISABLED = 0, ///< MCK disabled.
141 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2) || defined(__NRFX_DOXYGEN__)
142 // [conversion to 'int' needed to prevent compilers from complaining
143 // that the provided value (0x80000000UL) is out of range of "int"]
144 NRF_I2S_MCK_32MDIV2 = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz.
145 #endif
146 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3) || defined(__NRFX_DOXYGEN__)
147 NRF_I2S_MCK_32MDIV3 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3, ///< 32 MHz / 3 = 10.6666667 MHz.
148 #endif
149 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4) || defined(__NRFX_DOXYGEN__)
150 NRF_I2S_MCK_32MDIV4 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4, ///< 32 MHz / 4 = 8.0 MHz.
151 #endif
152 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5) || defined(__NRFX_DOXYGEN__)
153 NRF_I2S_MCK_32MDIV5 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5, ///< 32 MHz / 5 = 6.4 MHz.
154 #endif
155 #if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6) || defined(__NRFX_DOXYGEN__)
156 NRF_I2S_MCK_32MDIV6 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6, ///< 32 MHz / 6 = 5.3333333 MHz.
157 #endif
158 NRF_I2S_MCK_32MDIV8 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, ///< 32 MHz / 8 = 4.0 MHz.
159 NRF_I2S_MCK_32MDIV10 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, ///< 32 MHz / 10 = 3.2 MHz.
160 NRF_I2S_MCK_32MDIV11 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11, ///< 32 MHz / 11 = 2.9090909 MHz.
161 NRF_I2S_MCK_32MDIV15 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15, ///< 32 MHz / 15 = 2.1333333 MHz.
162 NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz.
163 NRF_I2S_MCK_32MDIV21 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21, ///< 32 MHz / 21 = 1.5238095 MHz.
164 NRF_I2S_MCK_32MDIV23 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23, ///< 32 MHz / 23 = 1.3913043 MHz.
165 NRF_I2S_MCK_32MDIV30 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30, ///< 32 MHz / 30 = 1.0666667 MHz.
166 NRF_I2S_MCK_32MDIV31 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31, ///< 32 MHz / 31 = 1.0322581 MHz.
167 NRF_I2S_MCK_32MDIV32 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32, ///< 32 MHz / 32 = 1.0 MHz.
168 NRF_I2S_MCK_32MDIV42 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42, ///< 32 MHz / 42 = 0.7619048 MHz.
169 NRF_I2S_MCK_32MDIV63 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63, ///< 32 MHz / 63 = 0.5079365 MHz.
170 NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 ///< 32 MHz / 125 = 0.256 MHz.
171 } nrf_i2s_mck_t;
172
173 /** @brief I2S MCK/LRCK ratios. */
174 typedef enum
175 {
176 NRF_I2S_RATIO_32X = I2S_CONFIG_RATIO_RATIO_32X, ///< LRCK = MCK / 32.
177 NRF_I2S_RATIO_48X = I2S_CONFIG_RATIO_RATIO_48X, ///< LRCK = MCK / 48.
178 NRF_I2S_RATIO_64X = I2S_CONFIG_RATIO_RATIO_64X, ///< LRCK = MCK / 64.
179 NRF_I2S_RATIO_96X = I2S_CONFIG_RATIO_RATIO_96X, ///< LRCK = MCK / 96.
180 NRF_I2S_RATIO_128X = I2S_CONFIG_RATIO_RATIO_128X, ///< LRCK = MCK / 128.
181 NRF_I2S_RATIO_192X = I2S_CONFIG_RATIO_RATIO_192X, ///< LRCK = MCK / 192.
182 NRF_I2S_RATIO_256X = I2S_CONFIG_RATIO_RATIO_256X, ///< LRCK = MCK / 256.
183 NRF_I2S_RATIO_384X = I2S_CONFIG_RATIO_RATIO_384X, ///< LRCK = MCK / 384.
184 NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X ///< LRCK = MCK / 512.
185 } nrf_i2s_ratio_t;
186
187 /** @brief I2S sample widths. */
188 typedef enum
189 {
190 NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit.
191 NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
192 NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit, ///< 24 bit.
193 #if NRF_I2S_HAS_SWIDTH_32BIT
194 NRF_I2S_SWIDTH_32BIT = I2S_CONFIG_SWIDTH_SWIDTH_32Bit, ///< 32 bit.
195 #endif
196 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16) || defined(__NRFX_DOXYGEN__)
197 NRF_I2S_SWIDTH_8BIT_IN16BIT = I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16, ///< 8 bit sample in a 16-bit half-frame.
198 #endif
199 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32) || defined(__NRFX_DOXYGEN__)
200 NRF_I2S_SWIDTH_8BIT_IN32BIT = I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32, ///< 8 bit sample in a 32-bit half-frame.
201 #endif
202 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32) || defined(__NRFX_DOXYGEN__)
203 NRF_I2S_SWIDTH_16BIT_IN32BIT = I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32, ///< 16 bit sample in a 32-bit half-frame.
204 #endif
205 #if defined(I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32) || defined(__NRFX_DOXYGEN__)
206 NRF_I2S_SWIDTH_24BIT_IN32BIT = I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32, ///< 24 bit sample in a 32-bit half-frame.
207 #endif
208 } nrf_i2s_swidth_t;
209
210 /** @brief I2S alignments of sample within a frame. */
211 typedef enum
212 {
213 NRF_I2S_ALIGN_LEFT = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned.
214 NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned.
215 } nrf_i2s_align_t;
216
217 /** @brief I2S frame formats. */
218 typedef enum
219 {
220 NRF_I2S_FORMAT_I2S = I2S_CONFIG_FORMAT_FORMAT_I2S, ///< Original I2S format.
221 NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left-aligned or right-aligned) format.
222 } nrf_i2s_format_t;
223
224 /** @brief I2S enabled channels. */
225 typedef enum
226 {
227 NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo.
228 NRF_I2S_CHANNELS_LEFT = I2S_CONFIG_CHANNELS_CHANNELS_Left, ///< Left only.
229 NRF_I2S_CHANNELS_RIGHT = I2S_CONFIG_CHANNELS_CHANNELS_Right ///< Right only.
230 } nrf_i2s_channels_t;
231
232 #if NRF_I2S_HAS_CLKCONFIG
233 /** @brief I2S Clock source selection. */
234 typedef enum
235 {
236 NRF_I2S_CLKSRC_PCLK32M = I2S_CONFIG_CLKCONFIG_CLKSRC_PCLK32M, ///< 32MHz peripheral clock.
237 NRF_I2S_CLKSRC_ACLK = I2S_CONFIG_CLKCONFIG_CLKSRC_ACLK ///< Audio PLL clock.
238 } nrf_i2s_clksrc_t;
239 #endif
240
241 /** @brief I2S configuration. */
242 typedef struct
243 {
244 nrf_i2s_mode_t mode; /**< Mode of operation (master or slave). */
245 nrf_i2s_format_t format; /**< I2S frame format. */
246 nrf_i2s_align_t alignment; /**< Alignment of sample within a frame. */
247 nrf_i2s_swidth_t sample_width; /**< Sample width. */
248 nrf_i2s_channels_t channels; /**< Enabled channels. */
249 nrf_i2s_mck_t mck_setup; /**< Master clock generator setup. */
250 nrf_i2s_ratio_t ratio; /**< MCK/LRCK ratio. */
251 } nrf_i2s_config_t;
252
253 /** @brief I2S pins. */
254 typedef struct
255 {
256 uint32_t sck_pin; ///< SCK pin number.
257 uint32_t lrck_pin; ///< LRCK pin number.
258 uint32_t mck_pin; ///< MCK pin number.
259 /**< Optional. Use @ref NRF_I2S_PIN_NOT_CONNECTED
260 * if this signal is not needed. */
261 uint32_t sdout_pin; ///< SDOUT pin number.
262 /**< Optional. Use @ref NRF_I2S_PIN_NOT_CONNECTED
263 * if this signal is not needed. */
264 uint32_t sdin_pin; ///< SDIN pin number.
265 /**< Optional. Use @ref NRF_I2S_PIN_NOT_CONNECTED
266 * if this signal is not needed. */
267 } nrf_i2s_pins_t;
268
269 /**
270 * @brief Function for activating the specified I2S task.
271 *
272 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
273 * @param[in] task Task to be activated.
274 */
275 NRF_STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_reg,
276 nrf_i2s_task_t task);
277
278 /**
279 * @brief Function for getting the address of the specified I2S task register.
280 *
281 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
282 * @param[in] task Specified task.
283 *
284 * @return Address of the specified task register.
285 */
286 NRF_STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_reg,
287 nrf_i2s_task_t task);
288
289 /**
290 * @brief Function for clearing the specified I2S event.
291 *
292 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
293 * @param[in] event Event to clear.
294 */
295 NRF_STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg,
296 nrf_i2s_event_t event);
297
298 /**
299 * @brief Function for retrieving the state of the I2S event.
300 *
301 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
302 * @param[in] event Event to be checked.
303 *
304 * @retval true The event has been generated.
305 * @retval false The event has not been generated.
306 */
307 NRF_STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_reg,
308 nrf_i2s_event_t event);
309
310 /**
311 * @brief Function for getting the address of the specified I2S event register.
312 *
313 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
314 * @param[in] event Specified event.
315 *
316 * @return Address of the specified event register.
317 */
318 NRF_STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_reg,
319 nrf_i2s_event_t event);
320
321 /**
322 * @brief Function for enabling specified interrupts.
323 *
324 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
325 * @param[in] mask Mask of interrupts to be enabled.
326 * Use @ref nrf_i2s_int_mask_t values for bit masking.
327 */
328 NRF_STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_reg, uint32_t mask);
329
330 /**
331 * @brief Function for disabling specified interrupts.
332 *
333 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
334 * @param[in] mask Mask of interrupts to be disabled.
335 * Use @ref nrf_i2s_int_mask_t values for bit masking.
336 */
337 NRF_STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_reg, uint32_t mask);
338
339 /**
340 * @brief Function for checking if the specified interrupts are enabled.
341 *
342 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
343 * @param[in] mask Mask of interrupts to be checked.
344 * Use @ref nrf_i2s_int_mask_t values for bit masking.
345 *
346 * @return Mask of enabled interrupts.
347 */
348 NRF_STATIC_INLINE uint32_t nrf_i2s_int_enable_check(NRF_I2S_Type const * p_reg, uint32_t mask);
349
350 /**
351 * @brief Function for enabling the I2S peripheral.
352 *
353 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
354 */
355 NRF_STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_reg);
356
357 /**
358 * @brief Function for disabling the I2S peripheral.
359 *
360 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
361 */
362 NRF_STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_reg);
363
364 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
365 /**
366 * @brief Function for setting the subscribe configuration for a given
367 * I2S task.
368 *
369 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
370 * @param[in] task Task for which to set the configuration.
371 * @param[in] channel Channel through which to subscribe events.
372 */
373 NRF_STATIC_INLINE void nrf_i2s_subscribe_set(NRF_I2S_Type * p_reg,
374 nrf_i2s_task_t task,
375 uint8_t channel);
376
377 /**
378 * @brief Function for clearing the subscribe configuration for a given
379 * I2S task.
380 *
381 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
382 * @param[in] task Task for which to clear the configuration.
383 */
384 NRF_STATIC_INLINE void nrf_i2s_subscribe_clear(NRF_I2S_Type * p_reg,
385 nrf_i2s_task_t task);
386
387 /**
388 * @brief Function for setting the publish configuration for a given
389 * I2S event.
390 *
391 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
392 * @param[in] event Event for which to set the configuration.
393 * @param[in] channel Channel through which to publish the event.
394 */
395 NRF_STATIC_INLINE void nrf_i2s_publish_set(NRF_I2S_Type * p_reg,
396 nrf_i2s_event_t event,
397 uint8_t channel);
398
399 /**
400 * @brief Function for clearing the publish configuration for a given
401 * I2S event.
402 *
403 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
404 * @param[in] event Event for which to clear the configuration.
405 */
406 NRF_STATIC_INLINE void nrf_i2s_publish_clear(NRF_I2S_Type * p_reg,
407 nrf_i2s_event_t event);
408 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
409
410 /**
411 * @brief Function for configuring I2S pins.
412 *
413 * Usage of the SDOUT, SDIN, and MCK signals is optional.
414 * If a given signal is not needed, pass the @ref NRF_I2S_PIN_NOT_CONNECTED
415 * value instead of its pin number.
416 *
417 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
418 * @param[in] p_pins Pointer to the structure with pins selection.
419 */
420 NRF_STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_reg, nrf_i2s_pins_t const * p_pins);
421
422 /**
423 * @brief Function for getting the SCK pin selection.
424 *
425 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
426 *
427 * @return SCK pin selection.
428 */
429 NRF_STATIC_INLINE uint32_t nrf_i2s_sck_pin_get(NRF_I2S_Type const * p_reg);
430
431 /**
432 * @brief Function for getting the LRCK pin selection.
433 *
434 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
435 *
436 * @return LRCK pin selection.
437 */
438 NRF_STATIC_INLINE uint32_t nrf_i2s_lrck_pin_get(NRF_I2S_Type const * p_reg);
439
440 /**
441 * @brief Function for getting the MCK pin selection.
442 *
443 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
444 *
445 * @return MCK pin selection.
446 */
447 NRF_STATIC_INLINE uint32_t nrf_i2s_mck_pin_get(NRF_I2S_Type const * p_reg);
448
449 /**
450 * @brief Function for getting the SDOUT pin selection.
451 *
452 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
453 *
454 * @return SDOUT pin selection.
455 */
456 NRF_STATIC_INLINE uint32_t nrf_i2s_sdout_pin_get(NRF_I2S_Type const * p_reg);
457
458 /**
459 * @brief Function for getting the SDIN pin selection.
460 *
461 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
462 *
463 * @return SDIN pin selection.
464 */
465 NRF_STATIC_INLINE uint32_t nrf_i2s_sdin_pin_get(NRF_I2S_Type const * p_reg);
466
467 /**
468 * @brief Function for setting the I2S peripheral configuration.
469 *
470 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
471 * @param[in] p_config Pointer to the structure with configuration.
472 */
473 NRF_STATIC_INLINE void nrf_i2s_configure(NRF_I2S_Type * p_reg, nrf_i2s_config_t const * p_config);
474
475 /**
476 * @brief Function for setting up the I2S transfer.
477 *
478 * This function sets up the RX and TX buffers and enables reception or
479 * transmission (or both) accordingly. If the transfer in a given direction is not
480 * required, pass NULL instead of the pointer to the corresponding buffer.
481 *
482 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
483 * @param[in] size Size of the buffers (in 32-bit words).
484 * @param[in] p_rx_buffer Pointer to the receive buffer.
485 * Pass NULL to disable reception.
486 * @param[in] p_tx_buffer Pointer to the transmit buffer.
487 * Pass NULL to disable transmission.
488 */
489 NRF_STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_reg,
490 uint16_t size,
491 uint32_t * p_rx_buffer,
492 uint32_t const * p_tx_buffer);
493
494 /**
495 * @brief Function for setting the pointer to the receive buffer.
496 *
497 * @note The size of the buffer can be set only by calling
498 * @ref nrf_i2s_transfer_set.
499 *
500 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
501 * @param[in] p_buffer Pointer to the receive buffer.
502 */
503 NRF_STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_reg,
504 uint32_t * p_buffer);
505
506 /**
507 * @brief Function for getting the pointer to the receive buffer.
508 *
509 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
510 *
511 * @return Pointer to the receive buffer.
512 */
513 NRF_STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_reg);
514
515 /**
516 * @brief Function for setting the pointer to the transmit buffer.
517 *
518 * @note The size of the buffer can be set only by calling
519 * @ref nrf_i2s_transfer_set.
520 *
521 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
522 * @param[in] p_buffer Pointer to the transmit buffer.
523 */
524 NRF_STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_reg,
525 uint32_t const * p_buffer);
526
527 /**
528 * @brief Function for getting the pointer to the transmit buffer.
529 *
530 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
531 *
532 * @return Pointer to the transmit buffer.
533 */
534 NRF_STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg);
535
536 #if NRF_I2S_HAS_CLKCONFIG
537 /**
538 * @brief Function for configuring I2S Clock.
539 *
540 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
541 * @param[in] clksrc I2S Clock source selection.
542 * @param[in] enable_bypass Bypass clock generator. MCK will be equal to source input.
543 * If bypass is enabled the MCKFREQ setting has no effect.
544 */
545 NRF_STATIC_INLINE void nrf_i2s_clk_configure(NRF_I2S_Type * p_reg,
546 nrf_i2s_clksrc_t clksrc,
547 bool enable_bypass);
548 #endif
549
550 #ifndef NRF_DECLARE_ONLY
551
nrf_i2s_task_trigger(NRF_I2S_Type * p_reg,nrf_i2s_task_t task)552 NRF_STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_reg,
553 nrf_i2s_task_t task)
554 {
555 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
556 }
557
nrf_i2s_task_address_get(NRF_I2S_Type const * p_reg,nrf_i2s_task_t task)558 NRF_STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_reg,
559 nrf_i2s_task_t task)
560 {
561 return ((uint32_t)p_reg + (uint32_t)task);
562 }
563
nrf_i2s_event_clear(NRF_I2S_Type * p_reg,nrf_i2s_event_t event)564 NRF_STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg,
565 nrf_i2s_event_t event)
566 {
567 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
568 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
569 }
570
nrf_i2s_event_check(NRF_I2S_Type const * p_reg,nrf_i2s_event_t event)571 NRF_STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_reg,
572 nrf_i2s_event_t event)
573 {
574 return nrf_event_check(p_reg, event);
575 }
576
nrf_i2s_event_address_get(NRF_I2S_Type const * p_reg,nrf_i2s_event_t event)577 NRF_STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_reg,
578 nrf_i2s_event_t event)
579 {
580 return ((uint32_t)p_reg + (uint32_t)event);
581 }
582
nrf_i2s_int_enable(NRF_I2S_Type * p_reg,uint32_t mask)583 NRF_STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_reg, uint32_t mask)
584 {
585 p_reg->INTENSET = mask;
586 }
587
nrf_i2s_int_disable(NRF_I2S_Type * p_reg,uint32_t mask)588 NRF_STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_reg, uint32_t mask)
589 {
590 p_reg->INTENCLR = mask;
591 }
592
nrf_i2s_int_enable_check(NRF_I2S_Type const * p_reg,uint32_t mask)593 NRF_STATIC_INLINE uint32_t nrf_i2s_int_enable_check(NRF_I2S_Type const * p_reg, uint32_t mask)
594 {
595 return p_reg->INTENSET & mask;
596 }
597
nrf_i2s_enable(NRF_I2S_Type * p_reg)598 NRF_STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_reg)
599 {
600 p_reg->ENABLE = (I2S_ENABLE_ENABLE_Enabled << I2S_ENABLE_ENABLE_Pos);
601 }
602
nrf_i2s_disable(NRF_I2S_Type * p_reg)603 NRF_STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_reg)
604 {
605 p_reg->ENABLE = (I2S_ENABLE_ENABLE_Disabled << I2S_ENABLE_ENABLE_Pos);
606 }
607
608 #if defined(DPPI_PRESENT)
nrf_i2s_subscribe_set(NRF_I2S_Type * p_reg,nrf_i2s_task_t task,uint8_t channel)609 NRF_STATIC_INLINE void nrf_i2s_subscribe_set(NRF_I2S_Type * p_reg,
610 nrf_i2s_task_t task,
611 uint8_t channel)
612 {
613 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
614 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
615 }
616
nrf_i2s_subscribe_clear(NRF_I2S_Type * p_reg,nrf_i2s_task_t task)617 NRF_STATIC_INLINE void nrf_i2s_subscribe_clear(NRF_I2S_Type * p_reg,
618 nrf_i2s_task_t task)
619 {
620 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
621 }
622
nrf_i2s_publish_set(NRF_I2S_Type * p_reg,nrf_i2s_event_t event,uint8_t channel)623 NRF_STATIC_INLINE void nrf_i2s_publish_set(NRF_I2S_Type * p_reg,
624 nrf_i2s_event_t event,
625 uint8_t channel)
626 {
627 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
628 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
629 }
630
nrf_i2s_publish_clear(NRF_I2S_Type * p_reg,nrf_i2s_event_t event)631 NRF_STATIC_INLINE void nrf_i2s_publish_clear(NRF_I2S_Type * p_reg,
632 nrf_i2s_event_t event)
633 {
634 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
635 }
636 #endif // defined(DPPI_PRESENT)
637
nrf_i2s_pins_set(NRF_I2S_Type * p_reg,nrf_i2s_pins_t const * p_pins)638 NRF_STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_reg, nrf_i2s_pins_t const * p_pins)
639 {
640 p_reg->PSEL.SCK = p_pins->sck_pin;
641 p_reg->PSEL.LRCK = p_pins->lrck_pin;
642 p_reg->PSEL.MCK = p_pins->mck_pin;
643 p_reg->PSEL.SDOUT = p_pins->sdout_pin;
644 p_reg->PSEL.SDIN = p_pins->sdin_pin;
645 }
646
nrf_i2s_sck_pin_get(NRF_I2S_Type const * p_reg)647 NRF_STATIC_INLINE uint32_t nrf_i2s_sck_pin_get(NRF_I2S_Type const * p_reg)
648 {
649 return p_reg->PSEL.SCK;
650 }
651
nrf_i2s_lrck_pin_get(NRF_I2S_Type const * p_reg)652 NRF_STATIC_INLINE uint32_t nrf_i2s_lrck_pin_get(NRF_I2S_Type const * p_reg)
653 {
654 return p_reg->PSEL.LRCK;
655 }
656
nrf_i2s_mck_pin_get(NRF_I2S_Type const * p_reg)657 NRF_STATIC_INLINE uint32_t nrf_i2s_mck_pin_get(NRF_I2S_Type const * p_reg)
658 {
659 return p_reg->PSEL.MCK;
660 }
661
nrf_i2s_sdout_pin_get(NRF_I2S_Type const * p_reg)662 NRF_STATIC_INLINE uint32_t nrf_i2s_sdout_pin_get(NRF_I2S_Type const * p_reg)
663 {
664 return p_reg->PSEL.SDOUT;
665 }
666
nrf_i2s_sdin_pin_get(NRF_I2S_Type const * p_reg)667 NRF_STATIC_INLINE uint32_t nrf_i2s_sdin_pin_get(NRF_I2S_Type const * p_reg)
668 {
669 return p_reg->PSEL.SDIN;
670 }
671
nrf_i2s_configure(NRF_I2S_Type * p_reg,nrf_i2s_config_t const * p_config)672 NRF_STATIC_INLINE void nrf_i2s_configure(NRF_I2S_Type * p_reg, nrf_i2s_config_t const * p_config)
673 {
674 p_reg->CONFIG.MODE = p_config->mode;
675 p_reg->CONFIG.FORMAT = p_config->format;
676 p_reg->CONFIG.ALIGN = p_config->alignment;
677 p_reg->CONFIG.SWIDTH = p_config->sample_width;
678 p_reg->CONFIG.CHANNELS = p_config->channels;
679 p_reg->CONFIG.RATIO = p_config->ratio;
680
681 if (p_config->mck_setup == NRF_I2S_MCK_DISABLED)
682 {
683 p_reg->CONFIG.MCKEN =
684 (I2S_CONFIG_MCKEN_MCKEN_Disabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
685 }
686 else
687 {
688 p_reg->CONFIG.MCKFREQ = p_config->mck_setup;
689 p_reg->CONFIG.MCKEN =
690 (I2S_CONFIG_MCKEN_MCKEN_Enabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
691 }
692 }
693
nrf_i2s_transfer_set(NRF_I2S_Type * p_reg,uint16_t size,uint32_t * p_buffer_rx,uint32_t const * p_buffer_tx)694 NRF_STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_reg,
695 uint16_t size,
696 uint32_t * p_buffer_rx,
697 uint32_t const * p_buffer_tx)
698 {
699 #if defined(DMA_BUFFER_UNIFIED_BYTE_ACCESS)
700 p_reg->RXTXD.MAXCNT = size * sizeof(uint32_t);
701 #else
702 p_reg->RXTXD.MAXCNT = size;
703 #endif
704
705 nrf_i2s_rx_buffer_set(p_reg, p_buffer_rx);
706 p_reg->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0;
707
708 nrf_i2s_tx_buffer_set(p_reg, p_buffer_tx);
709 p_reg->CONFIG.TXEN = (p_buffer_tx != NULL) ? 1 : 0;
710 }
711
nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_reg,uint32_t * p_buffer)712 NRF_STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_reg,
713 uint32_t * p_buffer)
714 {
715 p_reg->RXD.PTR = (uint32_t)p_buffer;
716 }
717
nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_reg)718 NRF_STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_reg)
719 {
720 return (uint32_t *)(p_reg->RXD.PTR);
721 }
722
nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_reg,uint32_t const * p_buffer)723 NRF_STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_reg,
724 uint32_t const * p_buffer)
725 {
726 p_reg->TXD.PTR = (uint32_t)p_buffer;
727 }
728
nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg)729 NRF_STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg)
730 {
731 return (uint32_t *)(p_reg->TXD.PTR);
732 }
733
734 #if NRF_I2S_HAS_CLKCONFIG
nrf_i2s_clk_configure(NRF_I2S_Type * p_reg,nrf_i2s_clksrc_t clksrc,bool enable_bypass)735 NRF_STATIC_INLINE void nrf_i2s_clk_configure(NRF_I2S_Type * p_reg,
736 nrf_i2s_clksrc_t clksrc,
737 bool enable_bypass)
738 {
739 p_reg->CONFIG.CLKCONFIG = ((uint32_t) clksrc << I2S_CONFIG_CLKCONFIG_CLKSRC_Pos) |
740 ((uint32_t) enable_bypass << I2S_CONFIG_CLKCONFIG_BYPASS_Pos);
741 }
742 #endif
743
744 #endif // NRF_DECLARE_ONLY
745
746 /** @} */
747
748 #ifdef __cplusplus
749 }
750 #endif
751
752 #endif // NRF_I2S_H__
753
