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Searched refs:NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK (Results 1 – 16 of 16) sorted by relevance

/Zephyr-latest/modules/hal_nordic/nrfx/
Dnrfx_config_nrf54l20_enga_application.h325 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
326 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f0f macro
Dnrfx_config_nrf54l05_application.h361 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
362 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f0f macro
Dnrfx_config_nrf54l05_flpr.h370 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
371 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 macro
Dnrfx_config_nrf54l10_application.h361 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
362 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f0f macro
Dnrfx_config_nrf54l10_flpr.h370 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
371 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 macro
Dnrfx_config_nrf54l15_application.h361 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
362 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f0f macro
Dnrfx_config_nrf54l15_flpr.h370 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
371 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 macro
Dnrfx_config_nrf54h20_application.h400 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
401 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 macro
Dnrfx_config_nrf54h20_flpr.h295 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
296 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0 macro
Dnrfx_config_nrf54h20_ppr.h355 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
356 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000c0 macro
Dnrfx_config_nrf9230_engb_ppr.h355 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
356 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000c0 macro
Dnrfx_config_nrf54h20_radiocore.h436 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
437 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f00 macro
Dnrfx_config_nrf9230_engb_application.h400 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
401 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x000000f0 macro
Dnrfx_config_nrf9230_engb_radiocore.h440 #ifndef NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK
441 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK 0x00000f00 macro
Dnrfx_config.h993 #define NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK \ macro
/Zephyr-latest/drivers/timer/
Dnrf_grtc_timer.c71 __ASSERT_NO_MSG((NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK & (1UL << (chan))) && \
409 for (uint32_t grtc_chan_mask = NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK; in z_nrf_grtc_wakeup_prepare()
492 int_mask = NRFX_GRTC_CONFIG_ALLOWED_CC_CHANNELS_MASK; in sys_clock_driver_init()