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Searched refs:NRFX_BIT (Results 1 – 12 of 12) sorted by relevance

/hal_nordic-3.6.0/nrfx/helpers/
Dnrfx_flag32_allocator.c55 return (mask & NRFX_BIT(bitpos)) ? false : true; in nrfx_flag32_is_allocated()
74 new_mask = prev_mask & ~NRFX_BIT(idx); in nrfx_flag32_alloc()
86 if ((NRFX_BIT(flag) & *p_mask)) in nrfx_flag32_free()
93 new_mask = prev_mask | NRFX_BIT(flag); in nrfx_flag32_free()
Dnrfx_gppi_dppi_ppib_lumos.c139 nrfy_dppi_channels_set(dppic->dppic, NRFX_BIT((uint32_t)dppi_channel), enable); in virtual_channel_enable_set()
219 nrfy_dppi_channels_set(dppic->dppic, NRFX_BIT((uint32_t)dppi_channel), false); in clear_virtual_channel_path()
395 path.src_dppic->channels_mask &= ~NRFX_BIT(common_channel); in nrfx_gppi_channel_endpoints_setup()
396 path.dst_dppic->channels_mask &= ~NRFX_BIT(common_channel); in nrfx_gppi_channel_endpoints_setup()
397 path.ppib->channels_mask &= ~NRFX_BIT(common_channel); in nrfx_gppi_channel_endpoints_setup()
471 p_src_dppic->channels_mask &= ~NRFX_BIT(common_channel); in nrfx_gppi_channel_endpoints_setup()
472 p_main_dppic->channels_mask &= ~NRFX_BIT(common_channel); in nrfx_gppi_channel_endpoints_setup()
473 p_dst_dppic->channels_mask &= ~NRFX_BIT(common_channel); in nrfx_gppi_channel_endpoints_setup()
474 path_src_to_main.ppib->channels_mask &= ~NRFX_BIT(common_channel); in nrfx_gppi_channel_endpoints_setup()
475 path_main_to_dst.ppib->channels_mask &= ~NRFX_BIT(common_channel); in nrfx_gppi_channel_endpoints_setup()
[all …]
Dnrfx_gppi_dppi_ppib.c105 ~NRFX_BIT(chan_to_alloc)); in channel_allocate()
195 nrf_ipct_shorts_disable(p_src_ipct->p_ipct, NRFX_BIT(src_ipct_chan)); in ipct_connection_remove()
196 nrf_ipct_shorts_disable(p_dst_ipct->p_ipct, NRFX_BIT(dst_ipct_chan)); in ipct_connection_remove()
220 nrfy_dppi_channels_set(p_src_apb->p_dppi, NRFX_BIT(src_dppi_chan), enable); in dppic_channel_set()
221 nrfy_dppi_channels_set(p_dst_apb->p_dppi, NRFX_BIT(dst_dppi_chan), enable); in dppic_channel_set()
225 NRFX_BIT(p_path->dppi_channel), in dppic_channel_set()
241 NRFX_BIT(src_dppi_chan), in dppic_channel_set()
244 NRFX_BIT(dst_dppi_chan), in dppic_channel_set()
306 nrf_ipct_shorts_enable(p_src_ipct->p_ipct, NRFX_BIT(*src_ipct_channel)); in ipct_connection_create()
307 nrf_ipct_shorts_enable(p_dst_ipct->p_ipct, NRFX_BIT(*dst_ipct_channel)); in ipct_connection_create()
[all …]
/hal_nordic-3.6.0/nrfx/drivers/include/
Dnrfx_uarte.h87 #define NRFX_UARTE_RX_ENABLE_CONT NRFX_BIT(0)
99 #define NRFX_UARTE_RX_ENABLE_STOP_ON_END NRFX_BIT(1)
111 #define NRFX_UARTE_RX_ENABLE_KEEP_FIFO_CONTENT NRFX_BIT(2)
133 #define NRFX_UARTE_TX_BLOCKING NRFX_BIT(0)
142 #define NRFX_UARTE_TX_EARLY_RETURN NRFX_BIT(1)
177 #define NRFX_UARTE_TX_LINK NRFX_BIT(2)
185 #define NRFX_UARTE_TX_DONE_ABORTED NRFX_BIT(0)
/hal_nordic-3.6.0/nrfx/samples/src/nrfx_saadc/maximum_performance/
Dmain.c166 nrfx_gppi_channels_enable(NRFX_BIT(m_gppi_channels[SAADC_SAMPLING])); in saadc_handler()
181 nrfx_gppi_channels_disable(NRFX_BIT(m_gppi_channels[SAADC_START_ON_END])); in saadc_handler()
200 nrfx_gppi_channels_disable(NRFX_BIT(m_gppi_channels[SAADC_SAMPLING])); in saadc_handler()
326 nrfx_gppi_channels_enable(NRFX_BIT(m_gppi_channels[SAADC_START_ON_END])); in main()
/hal_nordic-3.6.0/nrfx/drivers/src/
Dnrfx_spim.c72 (~(NRFX_BIT(NRFX_CONCAT(NRFX_, periph, _ENABLED_COUNT)) - 1) | \
90 (~(NRFX_BIT(NRFX_CONCAT(NRFX_, periph, _ENABLED_COUNT)) - 1) | \
124 ((NRFX_BIT(drv_inst_idx)) & datarate32_support_mask))
126 #define SPIM_DCX_PRESENT_VALIDATE(drv_inst_idx) (NRFX_BIT(drv_inst_idx) & dcx_support_mask)
128 #define SPIM_HW_CSN_PRESENT_VALIDATE(drv_inst_idx) (NRFX_BIT(drv_inst_idx) & hw_csn_support_mask)
131 ((rx_len < NRFX_BIT(easydma_support_bits[drv_inst_idx])) && \
132 (tx_len < NRFX_BIT(easydma_support_bits[drv_inst_idx])))
456 bool ext_support = NRFX_BIT(p_instance->drv_inst_idx) & hw_csn_support_mask; in spim_configure()
Dnrfx_gpiote.c103 #define PIN_FLAG_IN_USE NRFX_BIT(0)
105 #define PIN_FLAG_DIR_MASK NRFX_BIT(1)
119 NRFX_STATIC_ASSERT(NRFX_GPIOTE_TRIGGER_MAX <= NRFX_BIT(PIN_FLAG_TRIG_MODE_BITS));
128 #define PIN_FLAG_TE_USED NRFX_BIT(5)
129 #define PIN_FLAG_SKIP_CONFIG NRFX_BIT(6)
131 #define PIN_FLAG_HANDLER_PRESENT NRFX_BIT(8)
159 NRFX_STATIC_ASSERT((NRFX_BIT(PIN_TE_ID_BITS)) >= GPIOTE_CH_NUM);
474 nrfy_gpiote_int_disable(p_instance->p_reg, NRFX_BIT(ch)); in pin_trigger_disable()
1028 nrfy_gpiote_int_enable(p_instance->p_reg, NRFX_BIT(ch)); in pin_trigger_enable()
1580 pins_to_check[i] &= ~NRFX_BIT(rel_pin); in port_event_handle()
[all …]
Dnrfx_dppi.c103 nrfy_dppi_channels_disable(NRF_DPPIC, NRFX_BIT(channel)); in nrfx_dppi_channel_free()
Dnrfx_grtc.c52 #define GRTC_CHANNEL_TO_BITMASK(chan) NRFX_BIT(chan)
Dnrfx_uarte.c84 NRFX_BIT(NRFX_CONCAT(UARTE_FLAG_,type,_OFFSET) + i)
/hal_nordic-3.6.0/nrfx/samples/src/nrfx_saadc/common/
Dsaadc_examples_common.c83 nrfx_gppi_channels_enable(NRFX_BIT(gppi_channel)); in pin_on_event_toggle_setup()
/hal_nordic-3.6.0/nrfx/drivers/
Dnrfx_common.h130 #define NRFX_BIT(x) (1UL << (x)) macro