1 /*
2 
3 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF52840_BITS_H
36 #define __NRF52840_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: AAR */
41 /* Description: Accelerated Address Resolver */
42 
43 /* Register: AAR_TASKS_START */
44 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
45 
46 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
47 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
48 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
49 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
50 
51 /* Register: AAR_TASKS_STOP */
52 /* Description: Stop resolving addresses */
53 
54 /* Bit 0 : Stop resolving addresses */
55 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
56 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
57 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
58 
59 /* Register: AAR_EVENTS_END */
60 /* Description: Address resolution procedure complete */
61 
62 /* Bit 0 : Address resolution procedure complete */
63 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
64 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
65 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
66 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
67 
68 /* Register: AAR_EVENTS_RESOLVED */
69 /* Description: Address resolved */
70 
71 /* Bit 0 : Address resolved */
72 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
73 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
74 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
75 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
76 
77 /* Register: AAR_EVENTS_NOTRESOLVED */
78 /* Description: Address not resolved */
79 
80 /* Bit 0 : Address not resolved */
81 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
82 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
83 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
84 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
85 
86 /* Register: AAR_INTENSET */
87 /* Description: Enable interrupt */
88 
89 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
90 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
91 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
92 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
93 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
94 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
95 
96 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
97 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
98 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
99 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
100 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
101 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
102 
103 /* Bit 0 : Write '1' to enable interrupt for event END */
104 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
105 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
106 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
107 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
108 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
109 
110 /* Register: AAR_INTENCLR */
111 /* Description: Disable interrupt */
112 
113 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
114 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
115 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
116 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
117 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
118 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
119 
120 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
121 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
122 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
123 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
124 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
125 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
126 
127 /* Bit 0 : Write '1' to disable interrupt for event END */
128 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
129 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
130 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
131 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
132 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
133 
134 /* Register: AAR_STATUS */
135 /* Description: Resolution status */
136 
137 /* Bits 3..0 : The IRK that was used last time an address was resolved */
138 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
139 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
140 
141 /* Register: AAR_ENABLE */
142 /* Description: Enable AAR */
143 
144 /* Bits 1..0 : Enable or disable AAR */
145 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
146 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
147 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
148 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
149 
150 /* Register: AAR_NIRK */
151 /* Description: Number of IRKs */
152 
153 /* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */
154 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
155 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
156 
157 /* Register: AAR_IRKPTR */
158 /* Description: Pointer to IRK data structure */
159 
160 /* Bits 31..0 : Pointer to the IRK data structure */
161 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
162 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
163 
164 /* Register: AAR_ADDRPTR */
165 /* Description: Pointer to the resolvable address */
166 
167 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
168 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
169 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
170 
171 /* Register: AAR_SCRATCHPTR */
172 /* Description: Pointer to data area used for temporary storage */
173 
174 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
175 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
176 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
177 
178 
179 /* Peripheral: ACL */
180 /* Description: Access control lists */
181 
182 /* Register: ACL_ACL_ADDR */
183 /* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */
184 
185 /* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */
186 #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
187 #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
188 
189 /* Register: ACL_ACL_SIZE */
190 /* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */
191 
192 /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */
193 #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
194 #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
195 
196 /* Register: ACL_ACL_PERM */
197 /* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */
198 
199 /* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */
200 #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
201 #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
202 #define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */
203 #define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */
204 
205 /* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */
206 #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
207 #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
208 #define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */
209 #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */
210 
211 
212 /* Peripheral: APPROTECT */
213 /* Description: Access Port Protection */
214 
215 /* Register: APPROTECT_FORCEPROTECT */
216 /* Description: Software force enable APPROTECT mechanism until next reset. */
217 
218 /* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */
219 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */
220 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
221 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */
222 
223 /* Register: APPROTECT_DISABLE */
224 /* Description: Software disable APPROTECT mechanism */
225 
226 /* Bits 7..0 : Software disable APPROTECT mechanism */
227 #define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
228 #define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
229 #define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */
230 
231 
232 /* Peripheral: CCM */
233 /* Description: AES CCM mode encryption */
234 
235 /* Register: CCM_TASKS_KSGEN */
236 /* Description: Start generation of keystream. This operation will stop by itself when completed. */
237 
238 /* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */
239 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
240 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
241 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
242 
243 /* Register: CCM_TASKS_CRYPT */
244 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
245 
246 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
247 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
248 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
249 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
250 
251 /* Register: CCM_TASKS_STOP */
252 /* Description: Stop encryption/decryption */
253 
254 /* Bit 0 : Stop encryption/decryption */
255 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
256 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
257 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
258 
259 /* Register: CCM_TASKS_RATEOVERRIDE */
260 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
261 
262 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
263 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
264 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
265 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */
266 
267 /* Register: CCM_EVENTS_ENDKSGEN */
268 /* Description: Keystream generation complete */
269 
270 /* Bit 0 : Keystream generation complete */
271 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
272 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
273 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
274 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
275 
276 /* Register: CCM_EVENTS_ENDCRYPT */
277 /* Description: Encrypt/decrypt complete */
278 
279 /* Bit 0 : Encrypt/decrypt complete */
280 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
281 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
282 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
283 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
284 
285 /* Register: CCM_EVENTS_ERROR */
286 /* Description: Deprecated register - CCM error event */
287 
288 /* Bit 0 : Deprecated field -  CCM error event */
289 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
290 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
291 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
292 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
293 
294 /* Register: CCM_SHORTS */
295 /* Description: Shortcuts between local events and tasks */
296 
297 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
298 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
299 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
300 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
301 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
302 
303 /* Register: CCM_INTENSET */
304 /* Description: Enable interrupt */
305 
306 /* Bit 2 : Deprecated intsetfield -  Write '1' to enable interrupt for event ERROR */
307 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
308 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
309 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
310 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
311 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
312 
313 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
314 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
315 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
316 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
317 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
318 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
319 
320 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
321 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
322 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
323 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
324 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
325 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
326 
327 /* Register: CCM_INTENCLR */
328 /* Description: Disable interrupt */
329 
330 /* Bit 2 : Deprecated intclrfield -  Write '1' to disable interrupt for event ERROR */
331 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
332 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
333 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
334 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
335 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
336 
337 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
338 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
339 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
340 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
341 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
342 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
343 
344 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
345 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
346 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
347 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
348 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
349 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
350 
351 /* Register: CCM_MICSTATUS */
352 /* Description: MIC check result */
353 
354 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
355 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
356 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
357 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
358 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
359 
360 /* Register: CCM_ENABLE */
361 /* Description: Enable */
362 
363 /* Bits 1..0 : Enable or disable CCM */
364 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
365 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
366 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
367 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
368 
369 /* Register: CCM_MODE */
370 /* Description: Operation mode */
371 
372 /* Bit 24 : Packet length configuration */
373 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
374 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
375 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */
376 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
377 
378 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
379 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
380 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
381 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
382 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
383 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */
384 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */
385 
386 /* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */
387 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
388 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
389 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
390 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
391 
392 /* Register: CCM_CNFPTR */
393 /* Description: Pointer to data structure holding the AES key and the NONCE vector */
394 
395 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */
396 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
397 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
398 
399 /* Register: CCM_INPTR */
400 /* Description: Input pointer */
401 
402 /* Bits 31..0 : Input pointer */
403 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
404 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
405 
406 /* Register: CCM_OUTPTR */
407 /* Description: Output pointer */
408 
409 /* Bits 31..0 : Output pointer */
410 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
411 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
412 
413 /* Register: CCM_SCRATCHPTR */
414 /* Description: Pointer to data area used for temporary storage */
415 
416 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation,
417         MIC generation and encryption/decryption. */
418 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
419 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
420 
421 /* Register: CCM_MAXPACKETSIZE */
422 /* Description: Length of keystream generated when MODE.LENGTH = Extended */
423 
424 /* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */
425 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
426 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
427 
428 /* Register: CCM_RATEOVERRIDE */
429 /* Description: Data rate override setting. */
430 
431 /* Bits 1..0 : Data rate override setting */
432 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
433 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
434 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
435 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
436 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */
437 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */
438 
439 
440 /* Peripheral: CC_HOST_RGF */
441 /* Description: CRYPTOCELL HOST_RGF interface */
442 
443 /* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */
444 /* Description: AES hardware key select */
445 
446 /* Bits 1..0 : Select the source of the HW key that is used by the AES engine */
447 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */
448 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */
449 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */
450 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */
451 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */
452 
453 /* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */
454 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
455 
456 /* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */
457 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */
458 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */
459 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */
460 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */
461 
462 /* Register: CC_HOST_RGF_HOST_IOT_KDR0 */
463 /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */
464 
465 /* Bits 31..0 : Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */
466 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */
467 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */
468 
469 /* Register: CC_HOST_RGF_HOST_IOT_KDR1 */
470 /* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
471 
472 /* Bits 31..0 : K_DR bits 63:32 */
473 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */
474 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */
475 
476 /* Register: CC_HOST_RGF_HOST_IOT_KDR2 */
477 /* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
478 
479 /* Bits 31..0 : K_DR bits 95:64 */
480 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */
481 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */
482 
483 /* Register: CC_HOST_RGF_HOST_IOT_KDR3 */
484 /* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */
485 
486 /* Bits 31..0 : K_DR bits 127:96 */
487 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */
488 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */
489 
490 /* Register: CC_HOST_RGF_HOST_IOT_LCS */
491 /* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */
492 
493 /* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */
494 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */
495 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */
496 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */
497 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */
498 
499 /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */
500 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */
501 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */
502 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */
503 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */
504 
505 
506 /* Peripheral: CLOCK */
507 /* Description: Clock control */
508 
509 /* Register: CLOCK_TASKS_HFCLKSTART */
510 /* Description: Start HFXO crystal oscillator */
511 
512 /* Bit 0 : Start HFXO crystal oscillator */
513 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
514 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
515 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
516 
517 /* Register: CLOCK_TASKS_HFCLKSTOP */
518 /* Description: Stop HFXO crystal oscillator */
519 
520 /* Bit 0 : Stop HFXO crystal oscillator */
521 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
522 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
523 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
524 
525 /* Register: CLOCK_TASKS_LFCLKSTART */
526 /* Description: Start LFCLK */
527 
528 /* Bit 0 : Start LFCLK */
529 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
530 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
531 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
532 
533 /* Register: CLOCK_TASKS_LFCLKSTOP */
534 /* Description: Stop LFCLK */
535 
536 /* Bit 0 : Stop LFCLK */
537 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
538 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
539 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
540 
541 /* Register: CLOCK_TASKS_CAL */
542 /* Description: Start calibration of LFRC */
543 
544 /* Bit 0 : Start calibration of LFRC */
545 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
546 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
547 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
548 
549 /* Register: CLOCK_TASKS_CTSTART */
550 /* Description: Start calibration timer */
551 
552 /* Bit 0 : Start calibration timer */
553 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */
554 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */
555 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */
556 
557 /* Register: CLOCK_TASKS_CTSTOP */
558 /* Description: Stop calibration timer */
559 
560 /* Bit 0 : Stop calibration timer */
561 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */
562 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */
563 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */
564 
565 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
566 /* Description: HFXO crystal oscillator started */
567 
568 /* Bit 0 : HFXO crystal oscillator started */
569 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
570 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
571 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
572 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
573 
574 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
575 /* Description: LFCLK started */
576 
577 /* Bit 0 : LFCLK started */
578 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
579 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
580 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
581 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
582 
583 /* Register: CLOCK_EVENTS_DONE */
584 /* Description: Calibration of LFRC completed */
585 
586 /* Bit 0 : Calibration of LFRC completed */
587 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
588 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
589 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
590 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
591 
592 /* Register: CLOCK_EVENTS_CTTO */
593 /* Description: Calibration timer timeout */
594 
595 /* Bit 0 : Calibration timer timeout */
596 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */
597 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */
598 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */
599 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */
600 
601 /* Register: CLOCK_EVENTS_CTSTARTED */
602 /* Description: Calibration timer has been started and is ready to process new tasks */
603 
604 /* Bit 0 : Calibration timer has been started and is ready to process new tasks */
605 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */
606 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */
607 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */
608 #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */
609 
610 /* Register: CLOCK_EVENTS_CTSTOPPED */
611 /* Description: Calibration timer has been stopped and is ready to process new tasks */
612 
613 /* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */
614 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */
615 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */
616 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */
617 #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */
618 
619 /* Register: CLOCK_INTENSET */
620 /* Description: Enable interrupt */
621 
622 /* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */
623 #define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
624 #define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
625 #define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
626 #define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
627 #define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */
628 
629 /* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */
630 #define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
631 #define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
632 #define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
633 #define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
634 #define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */
635 
636 /* Bit 4 : Write '1' to enable interrupt for event CTTO */
637 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
638 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
639 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
640 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
641 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
642 
643 /* Bit 3 : Write '1' to enable interrupt for event DONE */
644 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
645 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
646 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
647 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
648 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
649 
650 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
651 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
652 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
653 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
654 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
655 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
656 
657 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
658 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
659 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
660 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
661 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
662 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
663 
664 /* Register: CLOCK_INTENCLR */
665 /* Description: Disable interrupt */
666 
667 /* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */
668 #define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
669 #define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
670 #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
671 #define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
672 #define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */
673 
674 /* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */
675 #define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
676 #define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
677 #define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
678 #define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
679 #define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */
680 
681 /* Bit 4 : Write '1' to disable interrupt for event CTTO */
682 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
683 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
684 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
685 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
686 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
687 
688 /* Bit 3 : Write '1' to disable interrupt for event DONE */
689 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
690 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
691 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
692 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
693 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
694 
695 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
696 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
697 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
698 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
699 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
700 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
701 
702 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
703 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
704 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
705 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
706 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
707 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
708 
709 /* Register: CLOCK_HFCLKRUN */
710 /* Description: Status indicating that HFCLKSTART task has been triggered */
711 
712 /* Bit 0 : HFCLKSTART task triggered or not */
713 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
714 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
715 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
716 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
717 
718 /* Register: CLOCK_HFCLKSTAT */
719 /* Description: HFCLK status */
720 
721 /* Bit 16 : HFCLK state */
722 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
723 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
724 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
725 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
726 
727 /* Bit 0 : Source of HFCLK */
728 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
729 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
730 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
731 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
732 
733 /* Register: CLOCK_LFCLKRUN */
734 /* Description: Status indicating that LFCLKSTART task has been triggered */
735 
736 /* Bit 0 : LFCLKSTART task triggered or not */
737 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
738 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
739 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
740 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
741 
742 /* Register: CLOCK_LFCLKSTAT */
743 /* Description: LFCLK status */
744 
745 /* Bit 16 : LFCLK state */
746 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
747 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
748 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
749 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
750 
751 /* Bits 1..0 : Source of LFCLK */
752 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
753 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
754 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
755 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
756 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
757 
758 /* Register: CLOCK_LFCLKSRCCOPY */
759 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
760 
761 /* Bits 1..0 : Clock source */
762 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
763 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
764 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
765 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
766 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
767 
768 /* Register: CLOCK_LFCLKSRC */
769 /* Description: Clock source for the LFCLK */
770 
771 /* Bit 17 : Enable or disable external source for LFCLK */
772 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
773 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
774 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
775 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
776 
777 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
778 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
779 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
780 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
781 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
782 
783 /* Bits 1..0 : Clock source */
784 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
785 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
786 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */
787 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */
788 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */
789 
790 /* Register: CLOCK_HFXODEBOUNCE */
791 /* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */
792 
793 /* Bits 7..0 : HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. */
794 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos (0UL) /*!< Position of HFXODEBOUNCE field. */
795 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Msk (0xFFUL << CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos) /*!< Bit mask of HFXODEBOUNCE field. */
796 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. */
797 #define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db1024us (0x40UL) /*!< 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. */
798 
799 /* Register: CLOCK_CTIV */
800 /* Description: Calibration timer interval */
801 
802 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
803 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
804 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
805 
806 /* Register: CLOCK_TRACECONFIG */
807 /* Description: Clocking options for the trace port debug interface */
808 
809 /* Bits 17..16 : Pin multiplexing of trace signals. See pin assignment chapter for more details. */
810 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
811 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
812 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< No trace signals routed to pins. All pins can be used as regular GPIOs. */
813 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. */
814 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. */
815 
816 /* Bits 1..0 : Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. */
817 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
818 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
819 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz trace port clock (TRACECLK = 16 MHz) */
820 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz trace port clock (TRACECLK = 8 MHz) */
821 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz trace port clock (TRACECLK = 4 MHz) */
822 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz trace port clock (TRACECLK = 2 MHz) */
823 
824 /* Register: CLOCK_LFRCMODE */
825 /* Description: LFRC mode configuration */
826 
827 /* Bit 16 : Active LFRC mode. This field is read only. */
828 #define CLOCK_LFRCMODE_STATUS_Pos (16UL) /*!< Position of STATUS field. */
829 #define CLOCK_LFRCMODE_STATUS_Msk (0x1UL << CLOCK_LFRCMODE_STATUS_Pos) /*!< Bit mask of STATUS field. */
830 #define CLOCK_LFRCMODE_STATUS_Normal (0UL) /*!< Normal mode */
831 #define CLOCK_LFRCMODE_STATUS_ULP (1UL) /*!< Ultra-low power mode (ULP) */
832 
833 /* Bit 0 : Set LFRC mode */
834 #define CLOCK_LFRCMODE_MODE_Pos (0UL) /*!< Position of MODE field. */
835 #define CLOCK_LFRCMODE_MODE_Msk (0x1UL << CLOCK_LFRCMODE_MODE_Pos) /*!< Bit mask of MODE field. */
836 #define CLOCK_LFRCMODE_MODE_Normal (0UL) /*!< Normal mode */
837 #define CLOCK_LFRCMODE_MODE_ULP (1UL) /*!< Ultra-low power mode (ULP) */
838 
839 
840 /* Peripheral: COMP */
841 /* Description: Comparator */
842 
843 /* Register: COMP_TASKS_START */
844 /* Description: Start comparator */
845 
846 /* Bit 0 : Start comparator */
847 #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
848 #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
849 #define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
850 
851 /* Register: COMP_TASKS_STOP */
852 /* Description: Stop comparator */
853 
854 /* Bit 0 : Stop comparator */
855 #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
856 #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
857 #define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
858 
859 /* Register: COMP_TASKS_SAMPLE */
860 /* Description: Sample comparator value */
861 
862 /* Bit 0 : Sample comparator value */
863 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
864 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
865 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
866 
867 /* Register: COMP_EVENTS_READY */
868 /* Description: COMP is ready and output is valid */
869 
870 /* Bit 0 : COMP is ready and output is valid */
871 #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
872 #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
873 #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
874 #define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
875 
876 /* Register: COMP_EVENTS_DOWN */
877 /* Description: Downward crossing */
878 
879 /* Bit 0 : Downward crossing */
880 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
881 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
882 #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
883 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
884 
885 /* Register: COMP_EVENTS_UP */
886 /* Description: Upward crossing */
887 
888 /* Bit 0 : Upward crossing */
889 #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
890 #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
891 #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
892 #define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
893 
894 /* Register: COMP_EVENTS_CROSS */
895 /* Description: Downward or upward crossing */
896 
897 /* Bit 0 : Downward or upward crossing */
898 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
899 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
900 #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
901 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
902 
903 /* Register: COMP_SHORTS */
904 /* Description: Shortcuts between local events and tasks */
905 
906 /* Bit 4 : Shortcut between event CROSS and task STOP */
907 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
908 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
909 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
910 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
911 
912 /* Bit 3 : Shortcut between event UP and task STOP */
913 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
914 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
915 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
916 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
917 
918 /* Bit 2 : Shortcut between event DOWN and task STOP */
919 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
920 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
921 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
922 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
923 
924 /* Bit 1 : Shortcut between event READY and task STOP */
925 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
926 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
927 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
928 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
929 
930 /* Bit 0 : Shortcut between event READY and task SAMPLE */
931 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
932 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
933 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
934 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
935 
936 /* Register: COMP_INTEN */
937 /* Description: Enable or disable interrupt */
938 
939 /* Bit 3 : Enable or disable interrupt for event CROSS */
940 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
941 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
942 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
943 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
944 
945 /* Bit 2 : Enable or disable interrupt for event UP */
946 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
947 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
948 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
949 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
950 
951 /* Bit 1 : Enable or disable interrupt for event DOWN */
952 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
953 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
954 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
955 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
956 
957 /* Bit 0 : Enable or disable interrupt for event READY */
958 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
959 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
960 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
961 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
962 
963 /* Register: COMP_INTENSET */
964 /* Description: Enable interrupt */
965 
966 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
967 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
968 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
969 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
970 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
971 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
972 
973 /* Bit 2 : Write '1' to enable interrupt for event UP */
974 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
975 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
976 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
977 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
978 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
979 
980 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
981 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
982 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
983 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
984 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
985 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
986 
987 /* Bit 0 : Write '1' to enable interrupt for event READY */
988 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
989 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
990 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
991 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
992 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
993 
994 /* Register: COMP_INTENCLR */
995 /* Description: Disable interrupt */
996 
997 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
998 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
999 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
1000 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1001 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1002 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1003 
1004 /* Bit 2 : Write '1' to disable interrupt for event UP */
1005 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
1006 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
1007 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1008 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1009 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1010 
1011 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
1012 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1013 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
1014 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1015 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1016 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1017 
1018 /* Bit 0 : Write '1' to disable interrupt for event READY */
1019 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
1020 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
1021 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1022 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1023 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1024 
1025 /* Register: COMP_RESULT */
1026 /* Description: Compare result */
1027 
1028 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
1029 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
1030 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
1031 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
1032 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
1033 
1034 /* Register: COMP_ENABLE */
1035 /* Description: COMP enable */
1036 
1037 /* Bits 1..0 : Enable or disable COMP */
1038 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1039 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1040 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1041 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1042 
1043 /* Register: COMP_PSEL */
1044 /* Description: Pin select */
1045 
1046 /* Bits 2..0 : Analog pin select */
1047 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
1048 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
1049 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
1050 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
1051 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
1052 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
1053 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
1054 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
1055 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
1056 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
1057 
1058 /* Register: COMP_REFSEL */
1059 /* Description: Reference source select for single-ended mode */
1060 
1061 /* Bits 2..0 : Reference select */
1062 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
1063 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
1064 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
1065 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
1066 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
1067 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
1068 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF */
1069 
1070 /* Register: COMP_EXTREFSEL */
1071 /* Description: External reference select */
1072 
1073 /* Bits 2..0 : External analog reference select */
1074 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
1075 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
1076 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
1077 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
1078 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
1079 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
1080 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */
1081 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */
1082 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */
1083 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */
1084 
1085 /* Register: COMP_TH */
1086 /* Description: Threshold configuration for hysteresis unit */
1087 
1088 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
1089 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
1090 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
1091 
1092 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1093 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
1094 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
1095 
1096 /* Register: COMP_MODE */
1097 /* Description: Mode configuration */
1098 
1099 /* Bit 8 : Main operation modes */
1100 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
1101 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
1102 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1103 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1104 
1105 /* Bits 1..0 : Speed and power modes */
1106 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
1107 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
1108 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1109 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1110 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1111 
1112 /* Register: COMP_HYST */
1113 /* Description: Comparator hysteresis enable */
1114 
1115 /* Bit 0 : Comparator hysteresis */
1116 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
1117 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
1118 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1119 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1120 
1121 
1122 /* Peripheral: CRYPTOCELL */
1123 /* Description: ARM TrustZone CryptoCell register interface */
1124 
1125 /* Register: CRYPTOCELL_ENABLE */
1126 /* Description: Enable CRYPTOCELL subsystem */
1127 
1128 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */
1129 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1130 #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1131 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */
1132 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */
1133 
1134 
1135 /* Peripheral: ECB */
1136 /* Description: AES ECB Mode Encryption */
1137 
1138 /* Register: ECB_TASKS_STARTECB */
1139 /* Description: Start ECB block encrypt */
1140 
1141 /* Bit 0 : Start ECB block encrypt */
1142 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
1143 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
1144 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
1145 
1146 /* Register: ECB_TASKS_STOPECB */
1147 /* Description: Abort a possible executing ECB operation */
1148 
1149 /* Bit 0 : Abort a possible executing ECB operation */
1150 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
1151 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
1152 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
1153 
1154 /* Register: ECB_EVENTS_ENDECB */
1155 /* Description: ECB block encrypt complete */
1156 
1157 /* Bit 0 : ECB block encrypt complete */
1158 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
1159 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
1160 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
1161 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
1162 
1163 /* Register: ECB_EVENTS_ERRORECB */
1164 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
1165 
1166 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
1167 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
1168 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
1169 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
1170 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
1171 
1172 /* Register: ECB_INTENSET */
1173 /* Description: Enable interrupt */
1174 
1175 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
1176 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1177 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1178 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1179 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1180 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1181 
1182 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */
1183 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1184 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1185 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1186 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1187 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1188 
1189 /* Register: ECB_INTENCLR */
1190 /* Description: Disable interrupt */
1191 
1192 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
1193 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1194 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1195 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1196 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1197 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1198 
1199 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */
1200 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1201 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1202 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1203 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1204 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1205 
1206 /* Register: ECB_ECBDATAPTR */
1207 /* Description: ECB block encrypt memory pointers */
1208 
1209 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1210 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
1211 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
1212 
1213 
1214 /* Peripheral: EGU */
1215 /* Description: Event generator unit 0 */
1216 
1217 /* Register: EGU_TASKS_TRIGGER */
1218 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
1219 
1220 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
1221 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
1222 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
1223 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
1224 
1225 /* Register: EGU_EVENTS_TRIGGERED */
1226 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
1227 
1228 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
1229 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
1230 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
1231 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
1232 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
1233 
1234 /* Register: EGU_INTEN */
1235 /* Description: Enable or disable interrupt */
1236 
1237 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
1238 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1239 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1240 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1241 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1242 
1243 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
1244 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1245 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1246 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1247 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1248 
1249 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
1250 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1251 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1252 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1253 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1254 
1255 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
1256 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1257 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1258 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1259 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1260 
1261 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
1262 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1263 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1264 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1265 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1266 
1267 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
1268 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1269 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1270 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1271 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1272 
1273 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
1274 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1275 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1276 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1277 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1278 
1279 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
1280 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1281 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1282 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1283 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1284 
1285 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
1286 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1287 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1288 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1289 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1290 
1291 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
1292 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1293 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1294 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1295 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1296 
1297 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
1298 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1299 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1300 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1301 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1302 
1303 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
1304 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1305 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1306 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1307 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1308 
1309 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
1310 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1311 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1312 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1313 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1314 
1315 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
1316 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1317 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1318 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1319 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1320 
1321 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
1322 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1323 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1324 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1325 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1326 
1327 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
1328 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1329 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1330 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1331 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1332 
1333 /* Register: EGU_INTENSET */
1334 /* Description: Enable interrupt */
1335 
1336 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
1337 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1338 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1339 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1340 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1341 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1342 
1343 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
1344 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1345 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1346 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1347 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1348 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1349 
1350 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
1351 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1352 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1353 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1354 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1355 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1356 
1357 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
1358 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1359 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1360 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1361 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1362 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1363 
1364 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
1365 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1366 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1367 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1368 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1369 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1370 
1371 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
1372 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1373 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1374 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1375 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1376 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1377 
1378 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
1379 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1380 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1381 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1382 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1383 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1384 
1385 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
1386 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1387 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1388 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1389 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1390 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1391 
1392 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
1393 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1394 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1395 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1396 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1397 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1398 
1399 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
1400 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1401 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1402 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1403 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1404 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1405 
1406 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
1407 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1408 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1409 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1410 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1411 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1412 
1413 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
1414 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1415 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1416 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1417 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1418 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1419 
1420 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
1421 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1422 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1423 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1424 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1425 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1426 
1427 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
1428 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1429 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1430 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1431 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1432 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1433 
1434 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
1435 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1436 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1437 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1438 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1439 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1440 
1441 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
1442 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1443 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1444 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1445 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1446 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1447 
1448 /* Register: EGU_INTENCLR */
1449 /* Description: Disable interrupt */
1450 
1451 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
1452 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1453 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1454 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1455 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1456 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1457 
1458 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
1459 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1460 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1461 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1462 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1463 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1464 
1465 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
1466 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1467 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1468 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1469 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1470 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1471 
1472 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
1473 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1474 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1475 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1476 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1477 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1478 
1479 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
1480 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1481 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1482 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1483 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1484 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1485 
1486 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
1487 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1488 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1489 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1490 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1491 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1492 
1493 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
1494 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1495 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1496 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1497 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1498 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1499 
1500 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
1501 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1502 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1503 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1504 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1505 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1506 
1507 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
1508 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1509 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1510 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1511 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1512 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1513 
1514 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
1515 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1516 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1517 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1518 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1519 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1520 
1521 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
1522 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1523 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1524 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1525 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1526 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1527 
1528 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
1529 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1530 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1531 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1532 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1533 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1534 
1535 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
1536 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1537 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1538 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1539 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1540 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1541 
1542 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
1543 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1544 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1545 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1546 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1547 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1548 
1549 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
1550 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1551 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1552 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1553 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1554 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1555 
1556 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
1557 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1558 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1559 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1560 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1561 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1562 
1563 
1564 /* Peripheral: FICR */
1565 /* Description: Factory information configuration registers */
1566 
1567 /* Register: FICR_CODEPAGESIZE */
1568 /* Description: Code memory page size */
1569 
1570 /* Bits 31..0 : Code memory page size */
1571 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
1572 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
1573 
1574 /* Register: FICR_CODESIZE */
1575 /* Description: Code memory size */
1576 
1577 /* Bits 31..0 : Code memory size in number of pages */
1578 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
1579 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
1580 
1581 /* Register: FICR_DEVICEID */
1582 /* Description: Description collection: Device identifier */
1583 
1584 /* Bits 31..0 : 64 bit unique device identifier */
1585 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
1586 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
1587 
1588 /* Register: FICR_ER */
1589 /* Description: Description collection: Encryption root, word n */
1590 
1591 /* Bits 31..0 : Encryption root, word n */
1592 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
1593 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
1594 
1595 /* Register: FICR_IR */
1596 /* Description: Description collection: Identity Root, word n */
1597 
1598 /* Bits 31..0 : Identity Root, word n */
1599 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
1600 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
1601 
1602 /* Register: FICR_DEVICEADDRTYPE */
1603 /* Description: Device address type */
1604 
1605 /* Bit 0 : Device address type */
1606 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
1607 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
1608 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
1609 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
1610 
1611 /* Register: FICR_DEVICEADDR */
1612 /* Description: Description collection: Device address n */
1613 
1614 /* Bits 31..0 : 48 bit device address */
1615 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
1616 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
1617 
1618 /* Register: FICR_INFO_PART */
1619 /* Description: Part code */
1620 
1621 /* Bits 31..0 : Part code */
1622 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
1623 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
1624 #define FICR_INFO_PART_PART_N52820 (0x52820UL) /*!< nRF52820 */
1625 #define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */
1626 #define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */
1627 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1628 
1629 /* Register: FICR_INFO_VARIANT */
1630 /* Description: Build code (hardware version and production configuration) */
1631 
1632 /* Bits 31..0 : Build code (hardware version and production configuration). Encoded as ASCII. */
1633 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1634 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1635 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
1636 #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
1637 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
1638 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
1639 #define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */
1640 #define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */
1641 #define FICR_INFO_VARIANT_VARIANT_AAD0 (0x41414430UL) /*!< AAD0 */
1642 #define FICR_INFO_VARIANT_VARIANT_AAD1 (0x41414431UL) /*!< AAD1 */
1643 #define FICR_INFO_VARIANT_VARIANT_AADA (0x41414441UL) /*!< AADA */
1644 #define FICR_INFO_VARIANT_VARIANT_AAEA (0x41414541UL) /*!< AAEA */
1645 #define FICR_INFO_VARIANT_VARIANT_AAF0 (0x41414630UL) /*!< AAF0 */
1646 #define FICR_INFO_VARIANT_VARIANT_AAFA (0x41414641UL) /*!< AAFA */
1647 #define FICR_INFO_VARIANT_VARIANT_BAAA (0x42414141UL) /*!< BAAA */
1648 #define FICR_INFO_VARIANT_VARIANT_CAAA (0x43414141UL) /*!< CAAA */
1649 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1650 
1651 /* Register: FICR_INFO_PACKAGE */
1652 /* Description: Package option */
1653 
1654 /* Bits 31..0 : Package option */
1655 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
1656 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
1657 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 6x6 48-pin QFN */
1658 #define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 7x7 73-pin aQFN */
1659 #define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 3.544 x 3.607 WLCSP */
1660 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1661 
1662 /* Register: FICR_INFO_RAM */
1663 /* Description: RAM variant */
1664 
1665 /* Bits 31..0 : RAM variant */
1666 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1667 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1668 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kB RAM */
1669 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kB RAM */
1670 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kB RAM */
1671 #define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kB RAM */
1672 #define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kB RAM */
1673 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1674 
1675 /* Register: FICR_INFO_FLASH */
1676 /* Description: Flash variant */
1677 
1678 /* Bits 31..0 : Flash variant */
1679 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
1680 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
1681 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kB FLASH */
1682 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kB FLASH */
1683 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kB FLASH */
1684 #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MB FLASH */
1685 #define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MB FLASH */
1686 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1687 
1688 /* Register: FICR_PRODTEST */
1689 /* Description: Description collection: Production test signature n */
1690 
1691 /* Bits 31..0 : Production test signature n */
1692 #define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */
1693 #define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */
1694 #define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */
1695 #define FICR_PRODTEST_PRODTEST_NotDone (0xFFFFFFFFUL) /*!< Production tests not done */
1696 
1697 /* Register: FICR_TEMP_A0 */
1698 /* Description: Slope definition A0 */
1699 
1700 /* Bits 11..0 : A (slope definition) register. */
1701 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
1702 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
1703 
1704 /* Register: FICR_TEMP_A1 */
1705 /* Description: Slope definition A1 */
1706 
1707 /* Bits 11..0 : A (slope definition) register. */
1708 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
1709 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
1710 
1711 /* Register: FICR_TEMP_A2 */
1712 /* Description: Slope definition A2 */
1713 
1714 /* Bits 11..0 : A (slope definition) register. */
1715 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
1716 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
1717 
1718 /* Register: FICR_TEMP_A3 */
1719 /* Description: Slope definition A3 */
1720 
1721 /* Bits 11..0 : A (slope definition) register. */
1722 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
1723 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
1724 
1725 /* Register: FICR_TEMP_A4 */
1726 /* Description: Slope definition A4 */
1727 
1728 /* Bits 11..0 : A (slope definition) register. */
1729 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
1730 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
1731 
1732 /* Register: FICR_TEMP_A5 */
1733 /* Description: Slope definition A5 */
1734 
1735 /* Bits 11..0 : A (slope definition) register. */
1736 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
1737 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
1738 
1739 /* Register: FICR_TEMP_B0 */
1740 /* Description: Y-intercept B0 */
1741 
1742 /* Bits 13..0 : B (y-intercept) */
1743 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
1744 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
1745 
1746 /* Register: FICR_TEMP_B1 */
1747 /* Description: Y-intercept B1 */
1748 
1749 /* Bits 13..0 : B (y-intercept) */
1750 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
1751 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
1752 
1753 /* Register: FICR_TEMP_B2 */
1754 /* Description: Y-intercept B2 */
1755 
1756 /* Bits 13..0 : B (y-intercept) */
1757 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
1758 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
1759 
1760 /* Register: FICR_TEMP_B3 */
1761 /* Description: Y-intercept B3 */
1762 
1763 /* Bits 13..0 : B (y-intercept) */
1764 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
1765 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
1766 
1767 /* Register: FICR_TEMP_B4 */
1768 /* Description: Y-intercept B4 */
1769 
1770 /* Bits 13..0 : B (y-intercept) */
1771 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
1772 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
1773 
1774 /* Register: FICR_TEMP_B5 */
1775 /* Description: Y-intercept B5 */
1776 
1777 /* Bits 13..0 : B (y-intercept) */
1778 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
1779 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
1780 
1781 /* Register: FICR_TEMP_T0 */
1782 /* Description: Segment end T0 */
1783 
1784 /* Bits 7..0 : T (segment end) register */
1785 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
1786 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
1787 
1788 /* Register: FICR_TEMP_T1 */
1789 /* Description: Segment end T1 */
1790 
1791 /* Bits 7..0 : T (segment end) register */
1792 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
1793 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
1794 
1795 /* Register: FICR_TEMP_T2 */
1796 /* Description: Segment end T2 */
1797 
1798 /* Bits 7..0 : T (segment end) register */
1799 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
1800 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
1801 
1802 /* Register: FICR_TEMP_T3 */
1803 /* Description: Segment end T3 */
1804 
1805 /* Bits 7..0 : T (segment end) register */
1806 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
1807 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
1808 
1809 /* Register: FICR_TEMP_T4 */
1810 /* Description: Segment end T4 */
1811 
1812 /* Bits 7..0 : T (segment end) register */
1813 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
1814 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
1815 
1816 /* Register: FICR_NFC_TAGHEADER0 */
1817 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
1818 
1819 /* Bits 31..24 : Unique identifier byte 3 */
1820 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
1821 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
1822 
1823 /* Bits 23..16 : Unique identifier byte 2 */
1824 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
1825 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
1826 
1827 /* Bits 15..8 : Unique identifier byte 1 */
1828 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
1829 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
1830 
1831 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
1832 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
1833 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
1834 
1835 /* Register: FICR_NFC_TAGHEADER1 */
1836 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
1837 
1838 /* Bits 31..24 : Unique identifier byte 7 */
1839 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
1840 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
1841 
1842 /* Bits 23..16 : Unique identifier byte 6 */
1843 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
1844 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
1845 
1846 /* Bits 15..8 : Unique identifier byte 5 */
1847 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
1848 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
1849 
1850 /* Bits 7..0 : Unique identifier byte 4 */
1851 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
1852 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
1853 
1854 /* Register: FICR_NFC_TAGHEADER2 */
1855 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
1856 
1857 /* Bits 31..24 : Unique identifier byte 11 */
1858 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
1859 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
1860 
1861 /* Bits 23..16 : Unique identifier byte 10 */
1862 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
1863 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
1864 
1865 /* Bits 15..8 : Unique identifier byte 9 */
1866 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
1867 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
1868 
1869 /* Bits 7..0 : Unique identifier byte 8 */
1870 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
1871 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
1872 
1873 /* Register: FICR_NFC_TAGHEADER3 */
1874 /* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */
1875 
1876 /* Bits 31..24 : Unique identifier byte 15 */
1877 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
1878 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
1879 
1880 /* Bits 23..16 : Unique identifier byte 14 */
1881 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
1882 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
1883 
1884 /* Bits 15..8 : Unique identifier byte 13 */
1885 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
1886 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
1887 
1888 /* Bits 7..0 : Unique identifier byte 12 */
1889 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
1890 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
1891 
1892 /* Register: FICR_TRNG90B_BYTES */
1893 /* Description: Amount of bytes for the required entropy bits */
1894 
1895 /* Bits 31..0 : Amount of bytes for the required entropy bits */
1896 #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */
1897 #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */
1898 
1899 /* Register: FICR_TRNG90B_RCCUTOFF */
1900 /* Description: Repetition counter cutoff */
1901 
1902 /* Bits 31..0 : Repetition counter cutoff */
1903 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */
1904 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */
1905 
1906 /* Register: FICR_TRNG90B_APCUTOFF */
1907 /* Description: Adaptive proportion cutoff */
1908 
1909 /* Bits 31..0 : Adaptive proportion cutoff */
1910 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */
1911 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */
1912 
1913 /* Register: FICR_TRNG90B_STARTUP */
1914 /* Description: Amount of bytes for the startup tests */
1915 
1916 /* Bits 31..0 : Amount of bytes for the startup tests */
1917 #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */
1918 #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */
1919 
1920 /* Register: FICR_TRNG90B_ROSC1 */
1921 /* Description: Sample count for ring oscillator 1 */
1922 
1923 /* Bits 31..0 : Sample count for ring oscillator 1 */
1924 #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
1925 #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
1926 
1927 /* Register: FICR_TRNG90B_ROSC2 */
1928 /* Description: Sample count for ring oscillator 2 */
1929 
1930 /* Bits 31..0 : Sample count for ring oscillator 2 */
1931 #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */
1932 #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
1933 
1934 /* Register: FICR_TRNG90B_ROSC3 */
1935 /* Description: Sample count for ring oscillator 3 */
1936 
1937 /* Bits 31..0 : Sample count for ring oscillator 3 */
1938 #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */
1939 #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
1940 
1941 /* Register: FICR_TRNG90B_ROSC4 */
1942 /* Description: Sample count for ring oscillator 4 */
1943 
1944 /* Bits 31..0 : Sample count for ring oscillator 4 */
1945 #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */
1946 #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
1947 
1948 
1949 /* Peripheral: GPIOTE */
1950 /* Description: GPIO Tasks and Events */
1951 
1952 /* Register: GPIOTE_TASKS_OUT */
1953 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1954 
1955 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1956 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
1957 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
1958 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
1959 
1960 /* Register: GPIOTE_TASKS_SET */
1961 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1962 
1963 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1964 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
1965 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
1966 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
1967 
1968 /* Register: GPIOTE_TASKS_CLR */
1969 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1970 
1971 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1972 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
1973 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
1974 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
1975 
1976 /* Register: GPIOTE_EVENTS_IN */
1977 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
1978 
1979 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
1980 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
1981 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
1982 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
1983 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
1984 
1985 /* Register: GPIOTE_EVENTS_PORT */
1986 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1987 
1988 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1989 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
1990 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
1991 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
1992 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
1993 
1994 /* Register: GPIOTE_INTENSET */
1995 /* Description: Enable interrupt */
1996 
1997 /* Bit 31 : Write '1' to enable interrupt for event PORT */
1998 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
1999 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
2000 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
2001 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
2002 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
2003 
2004 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
2005 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
2006 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
2007 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
2008 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
2009 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
2010 
2011 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
2012 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
2013 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
2014 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
2015 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
2016 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
2017 
2018 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
2019 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
2020 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
2021 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
2022 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
2023 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
2024 
2025 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
2026 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
2027 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
2028 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
2029 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
2030 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
2031 
2032 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
2033 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
2034 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
2035 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
2036 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
2037 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
2038 
2039 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
2040 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
2041 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
2042 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
2043 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
2044 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
2045 
2046 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
2047 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
2048 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
2049 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
2050 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
2051 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
2052 
2053 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
2054 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
2055 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
2056 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
2057 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
2058 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
2059 
2060 /* Register: GPIOTE_INTENCLR */
2061 /* Description: Disable interrupt */
2062 
2063 /* Bit 31 : Write '1' to disable interrupt for event PORT */
2064 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
2065 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
2066 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
2067 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2068 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
2069 
2070 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
2071 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
2072 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
2073 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
2074 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
2075 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
2076 
2077 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
2078 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
2079 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
2080 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
2081 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
2082 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
2083 
2084 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
2085 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
2086 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
2087 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
2088 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
2089 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
2090 
2091 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
2092 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
2093 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
2094 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
2095 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2096 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
2097 
2098 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
2099 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
2100 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
2101 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2102 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2103 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
2104 
2105 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
2106 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2107 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
2108 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2109 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2110 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
2111 
2112 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
2113 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
2114 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
2115 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2116 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2117 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
2118 
2119 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
2120 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
2121 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
2122 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2123 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2124 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
2125 
2126 /* Register: GPIOTE_CONFIG */
2127 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
2128 
2129 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
2130 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
2131 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
2132 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
2133 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
2134 
2135 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
2136 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
2137 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
2138 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
2139 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
2140 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
2141 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
2142 
2143 /* Bit 13 : Port number */
2144 #define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
2145 #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */
2146 
2147 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
2148 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
2149 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
2150 
2151 /* Bits 1..0 : Mode */
2152 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
2153 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
2154 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
2155 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
2156 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
2157 
2158 
2159 /* Peripheral: I2S */
2160 /* Description: Inter-IC Sound */
2161 
2162 /* Register: I2S_TASKS_START */
2163 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
2164 
2165 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
2166 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
2167 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
2168 #define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
2169 
2170 /* Register: I2S_TASKS_STOP */
2171 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
2172 
2173 /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
2174 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
2175 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
2176 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
2177 
2178 /* Register: I2S_EVENTS_RXPTRUPD */
2179 /* Description: The RXD.PTR register has been copied to internal double-buffers.
2180       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
2181 
2182 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
2183       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
2184 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
2185 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
2186 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
2187 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
2188 
2189 /* Register: I2S_EVENTS_STOPPED */
2190 /* Description: I2S transfer stopped. */
2191 
2192 /* Bit 0 : I2S transfer stopped. */
2193 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
2194 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
2195 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
2196 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
2197 
2198 /* Register: I2S_EVENTS_TXPTRUPD */
2199 /* Description: The TDX.PTR register has been copied to internal double-buffers.
2200       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
2201 
2202 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
2203       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
2204 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
2205 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
2206 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
2207 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
2208 
2209 /* Register: I2S_INTEN */
2210 /* Description: Enable or disable interrupt */
2211 
2212 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
2213 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2214 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2215 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
2216 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
2217 
2218 /* Bit 2 : Enable or disable interrupt for event STOPPED */
2219 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2220 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2221 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
2222 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
2223 
2224 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
2225 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2226 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2227 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
2228 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
2229 
2230 /* Register: I2S_INTENSET */
2231 /* Description: Enable interrupt */
2232 
2233 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
2234 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2235 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2236 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2237 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2238 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
2239 
2240 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
2241 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2242 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2243 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2244 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2245 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
2246 
2247 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
2248 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2249 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2250 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2251 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2252 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
2253 
2254 /* Register: I2S_INTENCLR */
2255 /* Description: Disable interrupt */
2256 
2257 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
2258 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2259 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2260 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2261 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2262 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
2263 
2264 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
2265 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2266 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2267 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2268 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2269 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
2270 
2271 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
2272 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2273 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2274 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2275 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2276 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
2277 
2278 /* Register: I2S_ENABLE */
2279 /* Description: Enable I2S module. */
2280 
2281 /* Bit 0 : Enable I2S module. */
2282 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2283 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2284 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2285 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2286 
2287 /* Register: I2S_CONFIG_MODE */
2288 /* Description: I2S mode. */
2289 
2290 /* Bit 0 : I2S mode. */
2291 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
2292 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
2293 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
2294 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
2295 
2296 /* Register: I2S_CONFIG_RXEN */
2297 /* Description: Reception (RX) enable. */
2298 
2299 /* Bit 0 : Reception (RX) enable. */
2300 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
2301 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
2302 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
2303 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
2304 
2305 /* Register: I2S_CONFIG_TXEN */
2306 /* Description: Transmission (TX) enable. */
2307 
2308 /* Bit 0 : Transmission (TX) enable. */
2309 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
2310 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
2311 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
2312 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2313 
2314 /* Register: I2S_CONFIG_MCKEN */
2315 /* Description: Master clock generator enable. */
2316 
2317 /* Bit 0 : Master clock generator enable. */
2318 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
2319 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
2320 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
2321 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
2322 
2323 /* Register: I2S_CONFIG_MCKFREQ */
2324 /* Description: Master clock generator frequency. */
2325 
2326 /* Bits 31..0 : Master clock generator frequency. */
2327 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
2328 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
2329 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
2330 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
2331 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
2332 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
2333 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
2334 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
2335 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
2336 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
2337 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
2338 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
2339 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
2340 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
2341 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
2342 
2343 /* Register: I2S_CONFIG_RATIO */
2344 /* Description: MCK / LRCK ratio. */
2345 
2346 /* Bits 3..0 : MCK / LRCK ratio. */
2347 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
2348 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
2349 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
2350 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
2351 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
2352 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
2353 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
2354 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
2355 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
2356 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
2357 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
2358 
2359 /* Register: I2S_CONFIG_SWIDTH */
2360 /* Description: Sample width. */
2361 
2362 /* Bits 1..0 : Sample width. */
2363 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
2364 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
2365 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
2366 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
2367 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
2368 
2369 /* Register: I2S_CONFIG_ALIGN */
2370 /* Description: Alignment of sample within a frame. */
2371 
2372 /* Bit 0 : Alignment of sample within a frame. */
2373 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
2374 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
2375 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
2376 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2377 
2378 /* Register: I2S_CONFIG_FORMAT */
2379 /* Description: Frame format. */
2380 
2381 /* Bit 0 : Frame format. */
2382 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
2383 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
2384 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
2385 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2386 
2387 /* Register: I2S_CONFIG_CHANNELS */
2388 /* Description: Enable channels. */
2389 
2390 /* Bits 1..0 : Enable channels. */
2391 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
2392 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
2393 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
2394 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
2395 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2396 
2397 /* Register: I2S_RXD_PTR */
2398 /* Description: Receive buffer RAM start address. */
2399 
2400 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
2401 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2402 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2403 
2404 /* Register: I2S_TXD_PTR */
2405 /* Description: Transmit buffer RAM start address. */
2406 
2407 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
2408 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2409 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2410 
2411 /* Register: I2S_RXTXD_MAXCNT */
2412 /* Description: Size of RXD and TXD buffers. */
2413 
2414 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
2415 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
2416 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
2417 
2418 /* Register: I2S_PSEL_MCK */
2419 /* Description: Pin select for MCK signal. */
2420 
2421 /* Bit 31 : Connection */
2422 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2423 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2424 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
2425 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2426 
2427 /* Bit 5 : Port number */
2428 #define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */
2429 #define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */
2430 
2431 /* Bits 4..0 : Pin number */
2432 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2433 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
2434 
2435 /* Register: I2S_PSEL_SCK */
2436 /* Description: Pin select for SCK signal. */
2437 
2438 /* Bit 31 : Connection */
2439 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2440 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2441 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
2442 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2443 
2444 /* Bit 5 : Port number */
2445 #define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
2446 #define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
2447 
2448 /* Bits 4..0 : Pin number */
2449 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2450 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
2451 
2452 /* Register: I2S_PSEL_LRCK */
2453 /* Description: Pin select for LRCK signal. */
2454 
2455 /* Bit 31 : Connection */
2456 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2457 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2458 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
2459 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2460 
2461 /* Bit 5 : Port number */
2462 #define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */
2463 #define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */
2464 
2465 /* Bits 4..0 : Pin number */
2466 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2467 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
2468 
2469 /* Register: I2S_PSEL_SDIN */
2470 /* Description: Pin select for SDIN signal. */
2471 
2472 /* Bit 31 : Connection */
2473 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2474 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2475 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
2476 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2477 
2478 /* Bit 5 : Port number */
2479 #define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */
2480 #define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */
2481 
2482 /* Bits 4..0 : Pin number */
2483 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
2484 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
2485 
2486 /* Register: I2S_PSEL_SDOUT */
2487 /* Description: Pin select for SDOUT signal. */
2488 
2489 /* Bit 31 : Connection */
2490 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2491 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2492 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
2493 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
2494 
2495 /* Bit 5 : Port number */
2496 #define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */
2497 #define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */
2498 
2499 /* Bits 4..0 : Pin number */
2500 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
2501 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
2502 
2503 
2504 /* Peripheral: LPCOMP */
2505 /* Description: Low-power comparator */
2506 
2507 /* Register: LPCOMP_TASKS_START */
2508 /* Description: Start comparator */
2509 
2510 /* Bit 0 : Start comparator */
2511 #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
2512 #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
2513 #define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
2514 
2515 /* Register: LPCOMP_TASKS_STOP */
2516 /* Description: Stop comparator */
2517 
2518 /* Bit 0 : Stop comparator */
2519 #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
2520 #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
2521 #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
2522 
2523 /* Register: LPCOMP_TASKS_SAMPLE */
2524 /* Description: Sample comparator value */
2525 
2526 /* Bit 0 : Sample comparator value */
2527 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
2528 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
2529 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
2530 
2531 /* Register: LPCOMP_EVENTS_READY */
2532 /* Description: LPCOMP is ready and output is valid */
2533 
2534 /* Bit 0 : LPCOMP is ready and output is valid */
2535 #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
2536 #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
2537 #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
2538 #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
2539 
2540 /* Register: LPCOMP_EVENTS_DOWN */
2541 /* Description: Downward crossing */
2542 
2543 /* Bit 0 : Downward crossing */
2544 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
2545 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
2546 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
2547 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
2548 
2549 /* Register: LPCOMP_EVENTS_UP */
2550 /* Description: Upward crossing */
2551 
2552 /* Bit 0 : Upward crossing */
2553 #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
2554 #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
2555 #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
2556 #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
2557 
2558 /* Register: LPCOMP_EVENTS_CROSS */
2559 /* Description: Downward or upward crossing */
2560 
2561 /* Bit 0 : Downward or upward crossing */
2562 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
2563 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
2564 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
2565 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
2566 
2567 /* Register: LPCOMP_SHORTS */
2568 /* Description: Shortcuts between local events and tasks */
2569 
2570 /* Bit 4 : Shortcut between event CROSS and task STOP */
2571 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
2572 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
2573 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
2574 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
2575 
2576 /* Bit 3 : Shortcut between event UP and task STOP */
2577 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
2578 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
2579 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
2580 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
2581 
2582 /* Bit 2 : Shortcut between event DOWN and task STOP */
2583 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
2584 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
2585 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
2586 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
2587 
2588 /* Bit 1 : Shortcut between event READY and task STOP */
2589 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
2590 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
2591 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
2592 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
2593 
2594 /* Bit 0 : Shortcut between event READY and task SAMPLE */
2595 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
2596 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
2597 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
2598 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
2599 
2600 /* Register: LPCOMP_INTENSET */
2601 /* Description: Enable interrupt */
2602 
2603 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
2604 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2605 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
2606 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
2607 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2608 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
2609 
2610 /* Bit 2 : Write '1' to enable interrupt for event UP */
2611 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2612 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
2613 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
2614 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2615 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
2616 
2617 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
2618 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2619 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
2620 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
2621 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2622 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
2623 
2624 /* Bit 0 : Write '1' to enable interrupt for event READY */
2625 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
2626 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
2627 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
2628 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2629 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
2630 
2631 /* Register: LPCOMP_INTENCLR */
2632 /* Description: Disable interrupt */
2633 
2634 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
2635 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2636 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
2637 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
2638 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2639 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
2640 
2641 /* Bit 2 : Write '1' to disable interrupt for event UP */
2642 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2643 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
2644 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
2645 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2646 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
2647 
2648 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
2649 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2650 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
2651 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
2652 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2653 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
2654 
2655 /* Bit 0 : Write '1' to disable interrupt for event READY */
2656 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
2657 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
2658 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
2659 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2660 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
2661 
2662 /* Register: LPCOMP_RESULT */
2663 /* Description: Compare result */
2664 
2665 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
2666 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
2667 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
2668 #define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-) */
2669 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-) */
2670 
2671 /* Register: LPCOMP_ENABLE */
2672 /* Description: Enable LPCOMP */
2673 
2674 /* Bits 1..0 : Enable or disable LPCOMP */
2675 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2676 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2677 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2678 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2679 
2680 /* Register: LPCOMP_PSEL */
2681 /* Description: Input pin select */
2682 
2683 /* Bits 2..0 : Analog pin select */
2684 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
2685 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
2686 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
2687 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
2688 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
2689 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
2690 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
2691 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
2692 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
2693 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
2694 
2695 /* Register: LPCOMP_REFSEL */
2696 /* Description: Reference select */
2697 
2698 /* Bits 3..0 : Reference select */
2699 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
2700 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
2701 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
2702 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
2703 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
2704 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
2705 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
2706 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
2707 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
2708 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
2709 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
2710 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
2711 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
2712 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
2713 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
2714 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
2715 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
2716 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
2717 
2718 /* Register: LPCOMP_EXTREFSEL */
2719 /* Description: External reference select */
2720 
2721 /* Bit 0 : External analog reference select */
2722 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
2723 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
2724 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
2725 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
2726 
2727 /* Register: LPCOMP_ANADETECT */
2728 /* Description: Analog detect configuration */
2729 
2730 /* Bits 1..0 : Analog detect configuration */
2731 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
2732 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
2733 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
2734 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
2735 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
2736 
2737 /* Register: LPCOMP_HYST */
2738 /* Description: Comparator hysteresis enable */
2739 
2740 /* Bit 0 : Comparator hysteresis enable */
2741 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
2742 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
2743 #define LPCOMP_HYST_HYST_Disabled (0UL) /*!< Comparator hysteresis disabled */
2744 #define LPCOMP_HYST_HYST_Enabled (1UL) /*!< Comparator hysteresis enabled */
2745 
2746 
2747 /* Peripheral: MWU */
2748 /* Description: Memory Watch Unit */
2749 
2750 /* Register: MWU_EVENTS_REGION_WA */
2751 /* Description: Description cluster: Write access to region n detected */
2752 
2753 /* Bit 0 : Write access to region n detected */
2754 #define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
2755 #define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */
2756 #define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
2757 #define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */
2758 
2759 /* Register: MWU_EVENTS_REGION_RA */
2760 /* Description: Description cluster: Read access to region n detected */
2761 
2762 /* Bit 0 : Read access to region n detected */
2763 #define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
2764 #define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */
2765 #define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
2766 #define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */
2767 
2768 /* Register: MWU_EVENTS_PREGION_WA */
2769 /* Description: Description cluster: Write access to peripheral region n detected */
2770 
2771 /* Bit 0 : Write access to peripheral region n detected */
2772 #define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
2773 #define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */
2774 #define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
2775 #define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */
2776 
2777 /* Register: MWU_EVENTS_PREGION_RA */
2778 /* Description: Description cluster: Read access to peripheral region n detected */
2779 
2780 /* Bit 0 : Read access to peripheral region n detected */
2781 #define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
2782 #define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */
2783 #define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
2784 #define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */
2785 
2786 /* Register: MWU_INTEN */
2787 /* Description: Enable or disable interrupt */
2788 
2789 /* Bit 27 : Enable or disable interrupt for event PREGION1RA */
2790 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2791 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2792 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
2793 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2794 
2795 /* Bit 26 : Enable or disable interrupt for event PREGION1WA */
2796 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2797 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2798 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
2799 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2800 
2801 /* Bit 25 : Enable or disable interrupt for event PREGION0RA */
2802 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2803 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2804 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
2805 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2806 
2807 /* Bit 24 : Enable or disable interrupt for event PREGION0WA */
2808 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2809 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2810 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
2811 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2812 
2813 /* Bit 7 : Enable or disable interrupt for event REGION3RA */
2814 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2815 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2816 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
2817 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
2818 
2819 /* Bit 6 : Enable or disable interrupt for event REGION3WA */
2820 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2821 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2822 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
2823 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
2824 
2825 /* Bit 5 : Enable or disable interrupt for event REGION2RA */
2826 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2827 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2828 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
2829 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
2830 
2831 /* Bit 4 : Enable or disable interrupt for event REGION2WA */
2832 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2833 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2834 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
2835 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
2836 
2837 /* Bit 3 : Enable or disable interrupt for event REGION1RA */
2838 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2839 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2840 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
2841 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
2842 
2843 /* Bit 2 : Enable or disable interrupt for event REGION1WA */
2844 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2845 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2846 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
2847 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
2848 
2849 /* Bit 1 : Enable or disable interrupt for event REGION0RA */
2850 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2851 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2852 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
2853 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
2854 
2855 /* Bit 0 : Enable or disable interrupt for event REGION0WA */
2856 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2857 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2858 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
2859 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
2860 
2861 /* Register: MWU_INTENSET */
2862 /* Description: Enable interrupt */
2863 
2864 /* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
2865 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2866 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2867 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2868 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2869 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
2870 
2871 /* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
2872 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2873 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2874 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2875 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2876 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
2877 
2878 /* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
2879 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2880 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2881 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2882 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2883 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
2884 
2885 /* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
2886 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2887 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2888 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2889 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2890 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
2891 
2892 /* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
2893 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2894 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2895 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2896 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2897 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
2898 
2899 /* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
2900 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2901 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2902 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2903 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2904 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
2905 
2906 /* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
2907 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2908 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2909 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2910 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2911 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
2912 
2913 /* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
2914 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2915 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2916 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2917 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2918 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
2919 
2920 /* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
2921 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2922 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2923 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2924 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2925 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
2926 
2927 /* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
2928 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2929 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2930 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2931 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2932 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
2933 
2934 /* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
2935 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2936 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2937 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2938 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2939 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
2940 
2941 /* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
2942 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2943 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2944 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2945 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2946 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
2947 
2948 /* Register: MWU_INTENCLR */
2949 /* Description: Disable interrupt */
2950 
2951 /* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
2952 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2953 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2954 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2955 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2956 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
2957 
2958 /* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
2959 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2960 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2961 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2962 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2963 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
2964 
2965 /* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
2966 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2967 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2968 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2969 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2970 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
2971 
2972 /* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
2973 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2974 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2975 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2976 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2977 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
2978 
2979 /* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
2980 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2981 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2982 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2983 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2984 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
2985 
2986 /* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
2987 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2988 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2989 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2990 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2991 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
2992 
2993 /* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
2994 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2995 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2996 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2997 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2998 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
2999 
3000 /* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
3001 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3002 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3003 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3004 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3005 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3006 
3007 /* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
3008 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3009 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3010 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3011 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3012 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3013 
3014 /* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
3015 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3016 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3017 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3018 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3019 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3020 
3021 /* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
3022 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3023 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3024 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3025 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3026 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3027 
3028 /* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
3029 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3030 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3031 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3032 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3033 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3034 
3035 /* Register: MWU_NMIEN */
3036 /* Description: Enable or disable interrupt */
3037 
3038 /* Bit 27 : Enable or disable interrupt for event PREGION1RA */
3039 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3040 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3041 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
3042 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
3043 
3044 /* Bit 26 : Enable or disable interrupt for event PREGION1WA */
3045 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3046 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3047 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
3048 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
3049 
3050 /* Bit 25 : Enable or disable interrupt for event PREGION0RA */
3051 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3052 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3053 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
3054 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
3055 
3056 /* Bit 24 : Enable or disable interrupt for event PREGION0WA */
3057 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3058 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3059 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
3060 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
3061 
3062 /* Bit 7 : Enable or disable interrupt for event REGION3RA */
3063 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3064 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3065 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
3066 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
3067 
3068 /* Bit 6 : Enable or disable interrupt for event REGION3WA */
3069 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3070 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3071 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
3072 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
3073 
3074 /* Bit 5 : Enable or disable interrupt for event REGION2RA */
3075 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3076 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3077 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
3078 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
3079 
3080 /* Bit 4 : Enable or disable interrupt for event REGION2WA */
3081 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3082 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3083 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
3084 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
3085 
3086 /* Bit 3 : Enable or disable interrupt for event REGION1RA */
3087 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3088 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3089 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
3090 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
3091 
3092 /* Bit 2 : Enable or disable interrupt for event REGION1WA */
3093 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3094 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3095 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
3096 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
3097 
3098 /* Bit 1 : Enable or disable interrupt for event REGION0RA */
3099 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3100 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3101 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
3102 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
3103 
3104 /* Bit 0 : Enable or disable interrupt for event REGION0WA */
3105 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3106 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3107 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
3108 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
3109 
3110 /* Register: MWU_NMIENSET */
3111 /* Description: Enable interrupt */
3112 
3113 /* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
3114 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3115 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3116 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3117 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3118 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
3119 
3120 /* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
3121 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3122 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3123 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3124 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3125 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
3126 
3127 /* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
3128 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3129 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3130 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3131 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3132 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
3133 
3134 /* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
3135 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3136 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3137 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3138 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3139 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
3140 
3141 /* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
3142 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3143 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3144 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3145 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3146 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
3147 
3148 /* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
3149 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3150 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3151 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3152 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3153 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
3154 
3155 /* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
3156 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3157 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3158 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3159 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3160 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
3161 
3162 /* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
3163 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3164 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3165 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3166 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3167 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
3168 
3169 /* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
3170 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3171 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3172 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3173 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3174 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
3175 
3176 /* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
3177 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3178 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3179 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3180 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3181 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
3182 
3183 /* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
3184 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3185 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3186 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3187 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3188 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
3189 
3190 /* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
3191 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3192 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3193 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3194 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3195 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
3196 
3197 /* Register: MWU_NMIENCLR */
3198 /* Description: Disable interrupt */
3199 
3200 /* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
3201 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3202 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3203 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3204 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3205 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3206 
3207 /* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
3208 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3209 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3210 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3211 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3212 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3213 
3214 /* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
3215 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3216 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3217 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3218 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3219 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3220 
3221 /* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
3222 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3223 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3224 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3225 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3226 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3227 
3228 /* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
3229 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3230 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3231 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3232 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3233 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3234 
3235 /* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
3236 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3237 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3238 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3239 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3240 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3241 
3242 /* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
3243 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3244 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3245 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3246 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3247 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3248 
3249 /* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
3250 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3251 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3252 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3253 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3254 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3255 
3256 /* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
3257 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3258 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3259 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3260 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3261 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3262 
3263 /* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
3264 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3265 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3266 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3267 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3268 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3269 
3270 /* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
3271 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3272 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3273 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3274 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3275 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3276 
3277 /* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
3278 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3279 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3280 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3281 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3282 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3283 
3284 /* Register: MWU_PERREGION_SUBSTATWA */
3285 /* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */
3286 
3287 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
3288 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3289 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
3290 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
3291 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
3292 
3293 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
3294 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3295 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
3296 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
3297 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
3298 
3299 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
3300 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3301 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
3302 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
3303 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
3304 
3305 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
3306 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3307 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
3308 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
3309 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
3310 
3311 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
3312 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3313 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
3314 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
3315 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
3316 
3317 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
3318 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3319 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
3320 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
3321 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
3322 
3323 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
3324 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3325 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
3326 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
3327 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
3328 
3329 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
3330 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3331 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
3332 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
3333 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
3334 
3335 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
3336 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3337 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
3338 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
3339 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
3340 
3341 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
3342 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3343 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
3344 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
3345 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
3346 
3347 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
3348 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3349 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
3350 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
3351 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
3352 
3353 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
3354 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3355 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
3356 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
3357 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
3358 
3359 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
3360 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3361 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
3362 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
3363 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
3364 
3365 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
3366 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3367 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
3368 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
3369 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
3370 
3371 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
3372 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3373 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
3374 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
3375 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
3376 
3377 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
3378 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3379 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
3380 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
3381 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
3382 
3383 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
3384 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3385 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
3386 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
3387 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
3388 
3389 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
3390 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3391 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
3392 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
3393 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
3394 
3395 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
3396 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3397 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
3398 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
3399 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
3400 
3401 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
3402 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3403 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
3404 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
3405 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
3406 
3407 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
3408 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3409 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
3410 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
3411 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
3412 
3413 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
3414 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3415 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
3416 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
3417 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
3418 
3419 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
3420 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3421 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
3422 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
3423 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
3424 
3425 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
3426 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3427 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
3428 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
3429 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
3430 
3431 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
3432 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3433 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
3434 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
3435 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
3436 
3437 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
3438 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3439 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
3440 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
3441 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
3442 
3443 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
3444 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3445 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
3446 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
3447 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
3448 
3449 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
3450 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3451 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
3452 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
3453 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
3454 
3455 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
3456 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3457 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
3458 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
3459 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
3460 
3461 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
3462 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3463 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
3464 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
3465 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
3466 
3467 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
3468 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3469 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
3470 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
3471 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
3472 
3473 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
3474 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3475 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
3476 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
3477 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
3478 
3479 /* Register: MWU_PERREGION_SUBSTATRA */
3480 /* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */
3481 
3482 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
3483 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3484 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
3485 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
3486 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
3487 
3488 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
3489 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3490 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
3491 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
3492 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
3493 
3494 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
3495 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3496 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
3497 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
3498 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
3499 
3500 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
3501 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3502 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
3503 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
3504 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
3505 
3506 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
3507 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3508 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
3509 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
3510 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
3511 
3512 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
3513 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3514 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
3515 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
3516 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
3517 
3518 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
3519 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3520 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
3521 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
3522 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
3523 
3524 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
3525 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3526 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
3527 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
3528 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
3529 
3530 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
3531 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3532 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
3533 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
3534 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
3535 
3536 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
3537 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3538 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
3539 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
3540 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
3541 
3542 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
3543 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3544 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
3545 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
3546 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
3547 
3548 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
3549 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3550 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
3551 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
3552 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
3553 
3554 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
3555 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3556 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
3557 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
3558 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
3559 
3560 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
3561 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3562 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
3563 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
3564 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
3565 
3566 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
3567 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3568 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
3569 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
3570 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
3571 
3572 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
3573 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3574 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
3575 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
3576 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
3577 
3578 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
3579 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3580 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
3581 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
3582 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
3583 
3584 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
3585 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3586 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
3587 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
3588 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
3589 
3590 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
3591 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3592 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
3593 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
3594 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
3595 
3596 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
3597 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3598 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
3599 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
3600 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
3601 
3602 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
3603 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3604 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
3605 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
3606 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
3607 
3608 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
3609 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3610 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
3611 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
3612 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
3613 
3614 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
3615 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3616 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
3617 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
3618 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
3619 
3620 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
3621 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3622 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
3623 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
3624 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
3625 
3626 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
3627 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3628 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
3629 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
3630 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
3631 
3632 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
3633 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3634 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
3635 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
3636 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
3637 
3638 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
3639 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3640 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
3641 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
3642 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
3643 
3644 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
3645 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3646 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
3647 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
3648 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
3649 
3650 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
3651 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3652 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
3653 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
3654 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
3655 
3656 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
3657 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3658 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
3659 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
3660 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
3661 
3662 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
3663 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3664 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
3665 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
3666 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
3667 
3668 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
3669 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3670 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
3671 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
3672 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
3673 
3674 /* Register: MWU_REGIONEN */
3675 /* Description: Enable/disable regions watch */
3676 
3677 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3678 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3679 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3680 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3681 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3682 
3683 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3684 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3685 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3686 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3687 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3688 
3689 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3690 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3691 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3692 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3693 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3694 
3695 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3696 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3697 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3698 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3699 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3700 
3701 /* Bit 7 : Enable/disable read access watch in region[3] */
3702 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3703 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3704 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
3705 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3706 
3707 /* Bit 6 : Enable/disable write access watch in region[3] */
3708 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3709 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3710 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
3711 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3712 
3713 /* Bit 5 : Enable/disable read access watch in region[2] */
3714 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3715 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3716 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
3717 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3718 
3719 /* Bit 4 : Enable/disable write access watch in region[2] */
3720 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3721 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3722 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
3723 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3724 
3725 /* Bit 3 : Enable/disable read access watch in region[1] */
3726 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3727 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3728 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
3729 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3730 
3731 /* Bit 2 : Enable/disable write access watch in region[1] */
3732 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3733 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3734 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
3735 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3736 
3737 /* Bit 1 : Enable/disable read access watch in region[0] */
3738 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3739 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3740 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
3741 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3742 
3743 /* Bit 0 : Enable/disable write access watch in region[0] */
3744 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3745 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3746 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
3747 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3748 
3749 /* Register: MWU_REGIONENSET */
3750 /* Description: Enable regions watch */
3751 
3752 /* Bit 27 : Enable read access watch in PREGION[1] */
3753 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3754 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3755 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3756 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3757 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3758 
3759 /* Bit 26 : Enable write access watch in PREGION[1] */
3760 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3761 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3762 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3763 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3764 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3765 
3766 /* Bit 25 : Enable read access watch in PREGION[0] */
3767 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3768 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3769 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3770 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3771 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3772 
3773 /* Bit 24 : Enable write access watch in PREGION[0] */
3774 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3775 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3776 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3777 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3778 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3779 
3780 /* Bit 7 : Enable read access watch in region[3] */
3781 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3782 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3783 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3784 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3785 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3786 
3787 /* Bit 6 : Enable write access watch in region[3] */
3788 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3789 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3790 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3791 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3792 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3793 
3794 /* Bit 5 : Enable read access watch in region[2] */
3795 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3796 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3797 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3798 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3799 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3800 
3801 /* Bit 4 : Enable write access watch in region[2] */
3802 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3803 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3804 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3805 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3806 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3807 
3808 /* Bit 3 : Enable read access watch in region[1] */
3809 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3810 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3811 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3812 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3813 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3814 
3815 /* Bit 2 : Enable write access watch in region[1] */
3816 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3817 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3818 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3819 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3820 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3821 
3822 /* Bit 1 : Enable read access watch in region[0] */
3823 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3824 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3825 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3826 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3827 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3828 
3829 /* Bit 0 : Enable write access watch in region[0] */
3830 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3831 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3832 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3833 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3834 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
3835 
3836 /* Register: MWU_REGIONENCLR */
3837 /* Description: Disable regions watch */
3838 
3839 /* Bit 27 : Disable read access watch in PREGION[1] */
3840 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3841 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3842 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3843 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3844 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3845 
3846 /* Bit 26 : Disable write access watch in PREGION[1] */
3847 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3848 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3849 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3850 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3851 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3852 
3853 /* Bit 25 : Disable read access watch in PREGION[0] */
3854 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3855 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3856 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3857 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3858 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3859 
3860 /* Bit 24 : Disable write access watch in PREGION[0] */
3861 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3862 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3863 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3864 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3865 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3866 
3867 /* Bit 7 : Disable read access watch in region[3] */
3868 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3869 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3870 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3871 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3872 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3873 
3874 /* Bit 6 : Disable write access watch in region[3] */
3875 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3876 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3877 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3878 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3879 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3880 
3881 /* Bit 5 : Disable read access watch in region[2] */
3882 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3883 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3884 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3885 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3886 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3887 
3888 /* Bit 4 : Disable write access watch in region[2] */
3889 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3890 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3891 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3892 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3893 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3894 
3895 /* Bit 3 : Disable read access watch in region[1] */
3896 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3897 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3898 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3899 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3900 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3901 
3902 /* Bit 2 : Disable write access watch in region[1] */
3903 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3904 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3905 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3906 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3907 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3908 
3909 /* Bit 1 : Disable read access watch in region[0] */
3910 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3911 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3912 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3913 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3914 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
3915 
3916 /* Bit 0 : Disable write access watch in region[0] */
3917 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3918 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3919 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3920 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3921 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
3922 
3923 /* Register: MWU_REGION_START */
3924 /* Description: Description cluster: Start address for region n */
3925 
3926 /* Bits 31..0 : Start address for region */
3927 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
3928 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
3929 
3930 /* Register: MWU_REGION_END */
3931 /* Description: Description cluster: End address of region n */
3932 
3933 /* Bits 31..0 : End address of region. */
3934 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
3935 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
3936 
3937 /* Register: MWU_PREGION_START */
3938 /* Description: Description cluster: Reserved for future use */
3939 
3940 /* Bits 31..0 : Reserved for future use */
3941 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
3942 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
3943 
3944 /* Register: MWU_PREGION_END */
3945 /* Description: Description cluster: Reserved for future use */
3946 
3947 /* Bits 31..0 : Reserved for future use */
3948 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
3949 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
3950 
3951 /* Register: MWU_PREGION_SUBS */
3952 /* Description: Description cluster: Subregions of region n */
3953 
3954 /* Bit 31 : Include or exclude subregion 31 in region */
3955 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
3956 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
3957 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
3958 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
3959 
3960 /* Bit 30 : Include or exclude subregion 30 in region */
3961 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
3962 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
3963 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
3964 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
3965 
3966 /* Bit 29 : Include or exclude subregion 29 in region */
3967 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
3968 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
3969 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
3970 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
3971 
3972 /* Bit 28 : Include or exclude subregion 28 in region */
3973 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
3974 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
3975 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
3976 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
3977 
3978 /* Bit 27 : Include or exclude subregion 27 in region */
3979 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
3980 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
3981 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
3982 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
3983 
3984 /* Bit 26 : Include or exclude subregion 26 in region */
3985 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
3986 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
3987 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
3988 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
3989 
3990 /* Bit 25 : Include or exclude subregion 25 in region */
3991 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
3992 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
3993 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
3994 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
3995 
3996 /* Bit 24 : Include or exclude subregion 24 in region */
3997 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
3998 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
3999 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
4000 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
4001 
4002 /* Bit 23 : Include or exclude subregion 23 in region */
4003 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
4004 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
4005 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
4006 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
4007 
4008 /* Bit 22 : Include or exclude subregion 22 in region */
4009 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
4010 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
4011 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
4012 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
4013 
4014 /* Bit 21 : Include or exclude subregion 21 in region */
4015 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
4016 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
4017 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
4018 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
4019 
4020 /* Bit 20 : Include or exclude subregion 20 in region */
4021 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
4022 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
4023 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
4024 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
4025 
4026 /* Bit 19 : Include or exclude subregion 19 in region */
4027 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
4028 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
4029 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
4030 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
4031 
4032 /* Bit 18 : Include or exclude subregion 18 in region */
4033 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
4034 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
4035 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
4036 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
4037 
4038 /* Bit 17 : Include or exclude subregion 17 in region */
4039 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
4040 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
4041 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
4042 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
4043 
4044 /* Bit 16 : Include or exclude subregion 16 in region */
4045 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
4046 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
4047 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
4048 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
4049 
4050 /* Bit 15 : Include or exclude subregion 15 in region */
4051 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
4052 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
4053 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
4054 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
4055 
4056 /* Bit 14 : Include or exclude subregion 14 in region */
4057 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
4058 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
4059 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
4060 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
4061 
4062 /* Bit 13 : Include or exclude subregion 13 in region */
4063 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
4064 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
4065 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
4066 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
4067 
4068 /* Bit 12 : Include or exclude subregion 12 in region */
4069 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
4070 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
4071 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
4072 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
4073 
4074 /* Bit 11 : Include or exclude subregion 11 in region */
4075 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
4076 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
4077 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
4078 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
4079 
4080 /* Bit 10 : Include or exclude subregion 10 in region */
4081 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
4082 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
4083 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
4084 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
4085 
4086 /* Bit 9 : Include or exclude subregion 9 in region */
4087 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
4088 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
4089 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
4090 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
4091 
4092 /* Bit 8 : Include or exclude subregion 8 in region */
4093 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
4094 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
4095 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
4096 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
4097 
4098 /* Bit 7 : Include or exclude subregion 7 in region */
4099 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
4100 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
4101 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
4102 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
4103 
4104 /* Bit 6 : Include or exclude subregion 6 in region */
4105 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
4106 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
4107 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
4108 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
4109 
4110 /* Bit 5 : Include or exclude subregion 5 in region */
4111 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
4112 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
4113 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
4114 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
4115 
4116 /* Bit 4 : Include or exclude subregion 4 in region */
4117 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
4118 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
4119 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
4120 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
4121 
4122 /* Bit 3 : Include or exclude subregion 3 in region */
4123 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
4124 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
4125 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
4126 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
4127 
4128 /* Bit 2 : Include or exclude subregion 2 in region */
4129 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
4130 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
4131 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
4132 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
4133 
4134 /* Bit 1 : Include or exclude subregion 1 in region */
4135 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
4136 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
4137 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
4138 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
4139 
4140 /* Bit 0 : Include or exclude subregion 0 in region */
4141 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
4142 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
4143 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
4144 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
4145 
4146 
4147 /* Peripheral: NFCT */
4148 /* Description: NFC-A compatible radio */
4149 
4150 /* Register: NFCT_TASKS_ACTIVATE */
4151 /* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
4152 
4153 /* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
4154 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
4155 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
4156 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */
4157 
4158 /* Register: NFCT_TASKS_DISABLE */
4159 /* Description: Disable NFCT peripheral */
4160 
4161 /* Bit 0 : Disable NFCT peripheral */
4162 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
4163 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
4164 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
4165 
4166 /* Register: NFCT_TASKS_SENSE */
4167 /* Description: Enable NFC sense field mode, change state to sense mode */
4168 
4169 /* Bit 0 : Enable NFC sense field mode, change state to sense mode */
4170 #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */
4171 #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */
4172 #define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */
4173 
4174 /* Register: NFCT_TASKS_STARTTX */
4175 /* Description: Start transmission of an outgoing frame, change state to transmit */
4176 
4177 /* Bit 0 : Start transmission of an outgoing frame, change state to transmit */
4178 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
4179 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
4180 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
4181 
4182 /* Register: NFCT_TASKS_ENABLERXDATA */
4183 /* Description: Initializes the EasyDMA for receive. */
4184 
4185 /* Bit 0 : Initializes the EasyDMA for receive. */
4186 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */
4187 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */
4188 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */
4189 
4190 /* Register: NFCT_TASKS_GOIDLE */
4191 /* Description: Force state machine to IDLE state */
4192 
4193 /* Bit 0 : Force state machine to IDLE state */
4194 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */
4195 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */
4196 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */
4197 
4198 /* Register: NFCT_TASKS_GOSLEEP */
4199 /* Description: Force state machine to SLEEP_A state */
4200 
4201 /* Bit 0 : Force state machine to SLEEP_A state */
4202 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */
4203 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */
4204 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */
4205 
4206 /* Register: NFCT_EVENTS_READY */
4207 /* Description: The NFCT peripheral is ready to receive and send frames */
4208 
4209 /* Bit 0 : The NFCT peripheral is ready to receive and send frames */
4210 #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
4211 #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
4212 #define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
4213 #define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
4214 
4215 /* Register: NFCT_EVENTS_FIELDDETECTED */
4216 /* Description: Remote NFC field detected */
4217 
4218 /* Bit 0 : Remote NFC field detected */
4219 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */
4220 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */
4221 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */
4222 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */
4223 
4224 /* Register: NFCT_EVENTS_FIELDLOST */
4225 /* Description: Remote NFC field lost */
4226 
4227 /* Bit 0 : Remote NFC field lost */
4228 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */
4229 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */
4230 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */
4231 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */
4232 
4233 /* Register: NFCT_EVENTS_TXFRAMESTART */
4234 /* Description: Marks the start of the first symbol of a transmitted frame */
4235 
4236 /* Bit 0 : Marks the start of the first symbol of a transmitted frame */
4237 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */
4238 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */
4239 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
4240 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */
4241 
4242 /* Register: NFCT_EVENTS_TXFRAMEEND */
4243 /* Description: Marks the end of the last transmitted on-air symbol of a frame */
4244 
4245 /* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
4246 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */
4247 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */
4248 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
4249 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */
4250 
4251 /* Register: NFCT_EVENTS_RXFRAMESTART */
4252 /* Description: Marks the end of the first symbol of a received frame */
4253 
4254 /* Bit 0 : Marks the end of the first symbol of a received frame */
4255 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */
4256 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */
4257 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
4258 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */
4259 
4260 /* Register: NFCT_EVENTS_RXFRAMEEND */
4261 /* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
4262 
4263 /* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
4264 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */
4265 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */
4266 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
4267 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */
4268 
4269 /* Register: NFCT_EVENTS_ERROR */
4270 /* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
4271 
4272 /* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
4273 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
4274 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
4275 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
4276 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
4277 
4278 /* Register: NFCT_EVENTS_RXERROR */
4279 /* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
4280 
4281 /* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
4282 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */
4283 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */
4284 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */
4285 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */
4286 
4287 /* Register: NFCT_EVENTS_ENDRX */
4288 /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
4289 
4290 /* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
4291 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
4292 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
4293 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
4294 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
4295 
4296 /* Register: NFCT_EVENTS_ENDTX */
4297 /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
4298 
4299 /* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
4300 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
4301 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
4302 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
4303 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
4304 
4305 /* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */
4306 /* Description: Auto collision resolution process has started */
4307 
4308 /* Bit 0 : Auto collision resolution process has started */
4309 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */
4310 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */
4311 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */
4312 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */
4313 
4314 /* Register: NFCT_EVENTS_COLLISION */
4315 /* Description: NFC auto collision resolution error reported. */
4316 
4317 /* Bit 0 : NFC auto collision resolution error reported. */
4318 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */
4319 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */
4320 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */
4321 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */
4322 
4323 /* Register: NFCT_EVENTS_SELECTED */
4324 /* Description: NFC auto collision resolution successfully completed */
4325 
4326 /* Bit 0 : NFC auto collision resolution successfully completed */
4327 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */
4328 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */
4329 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */
4330 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */
4331 
4332 /* Register: NFCT_EVENTS_STARTED */
4333 /* Description: EasyDMA is ready to receive or send frames. */
4334 
4335 /* Bit 0 : EasyDMA is ready to receive or send frames. */
4336 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
4337 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
4338 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
4339 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
4340 
4341 /* Register: NFCT_SHORTS */
4342 /* Description: Shortcuts between local events and tasks */
4343 
4344 /* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */
4345 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */
4346 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */
4347 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */
4348 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */
4349 
4350 /* Bit 1 : Shortcut between event FIELDLOST and task SENSE */
4351 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
4352 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
4353 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
4354 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
4355 
4356 /* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
4357 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
4358 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
4359 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
4360 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
4361 
4362 /* Register: NFCT_INTEN */
4363 /* Description: Enable or disable interrupt */
4364 
4365 /* Bit 20 : Enable or disable interrupt for event STARTED */
4366 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4367 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
4368 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4369 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4370 
4371 /* Bit 19 : Enable or disable interrupt for event SELECTED */
4372 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4373 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4374 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
4375 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
4376 
4377 /* Bit 18 : Enable or disable interrupt for event COLLISION */
4378 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4379 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4380 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
4381 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
4382 
4383 /* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
4384 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4385 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4386 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
4387 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
4388 
4389 /* Bit 12 : Enable or disable interrupt for event ENDTX */
4390 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4391 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4392 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
4393 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
4394 
4395 /* Bit 11 : Enable or disable interrupt for event ENDRX */
4396 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4397 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4398 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
4399 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
4400 
4401 /* Bit 10 : Enable or disable interrupt for event RXERROR */
4402 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4403 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4404 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
4405 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
4406 
4407 /* Bit 7 : Enable or disable interrupt for event ERROR */
4408 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4409 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
4410 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
4411 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
4412 
4413 /* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
4414 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4415 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4416 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
4417 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
4418 
4419 /* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
4420 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4421 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4422 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
4423 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
4424 
4425 /* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
4426 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4427 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4428 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
4429 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
4430 
4431 /* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
4432 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4433 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4434 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
4435 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
4436 
4437 /* Bit 2 : Enable or disable interrupt for event FIELDLOST */
4438 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4439 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4440 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
4441 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
4442 
4443 /* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
4444 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4445 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4446 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
4447 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
4448 
4449 /* Bit 0 : Enable or disable interrupt for event READY */
4450 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
4451 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
4452 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
4453 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
4454 
4455 /* Register: NFCT_INTENSET */
4456 /* Description: Enable interrupt */
4457 
4458 /* Bit 20 : Write '1' to enable interrupt for event STARTED */
4459 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4460 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
4461 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4462 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4463 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
4464 
4465 /* Bit 19 : Write '1' to enable interrupt for event SELECTED */
4466 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4467 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4468 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4469 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4470 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
4471 
4472 /* Bit 18 : Write '1' to enable interrupt for event COLLISION */
4473 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4474 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4475 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4476 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4477 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
4478 
4479 /* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
4480 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4481 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4482 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4483 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4484 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
4485 
4486 /* Bit 12 : Write '1' to enable interrupt for event ENDTX */
4487 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4488 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4489 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4490 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4491 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
4492 
4493 /* Bit 11 : Write '1' to enable interrupt for event ENDRX */
4494 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4495 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4496 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4497 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4498 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
4499 
4500 /* Bit 10 : Write '1' to enable interrupt for event RXERROR */
4501 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4502 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4503 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4504 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4505 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
4506 
4507 /* Bit 7 : Write '1' to enable interrupt for event ERROR */
4508 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4509 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
4510 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
4511 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4512 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
4513 
4514 /* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
4515 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4516 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4517 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4518 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4519 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
4520 
4521 /* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
4522 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4523 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4524 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4525 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4526 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
4527 
4528 /* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
4529 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4530 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4531 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4532 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4533 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
4534 
4535 /* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
4536 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4537 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4538 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4539 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4540 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
4541 
4542 /* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
4543 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4544 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4545 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4546 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4547 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
4548 
4549 /* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
4550 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4551 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4552 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4553 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4554 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
4555 
4556 /* Bit 0 : Write '1' to enable interrupt for event READY */
4557 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
4558 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
4559 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
4560 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4561 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
4562 
4563 /* Register: NFCT_INTENCLR */
4564 /* Description: Disable interrupt */
4565 
4566 /* Bit 20 : Write '1' to disable interrupt for event STARTED */
4567 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4568 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
4569 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4570 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4571 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4572 
4573 /* Bit 19 : Write '1' to disable interrupt for event SELECTED */
4574 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4575 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4576 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4577 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4578 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
4579 
4580 /* Bit 18 : Write '1' to disable interrupt for event COLLISION */
4581 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4582 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4583 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4584 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4585 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
4586 
4587 /* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
4588 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4589 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4590 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4591 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4592 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
4593 
4594 /* Bit 12 : Write '1' to disable interrupt for event ENDTX */
4595 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4596 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4597 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4598 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4599 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
4600 
4601 /* Bit 11 : Write '1' to disable interrupt for event ENDRX */
4602 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4603 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4604 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4605 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4606 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
4607 
4608 /* Bit 10 : Write '1' to disable interrupt for event RXERROR */
4609 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4610 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4611 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4612 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4613 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
4614 
4615 /* Bit 7 : Write '1' to disable interrupt for event ERROR */
4616 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4617 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
4618 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
4619 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4620 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
4621 
4622 /* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
4623 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4624 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4625 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4626 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4627 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
4628 
4629 /* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
4630 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4631 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4632 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4633 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4634 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
4635 
4636 /* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
4637 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4638 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4639 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4640 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4641 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
4642 
4643 /* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
4644 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4645 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4646 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4647 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4648 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
4649 
4650 /* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
4651 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4652 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4653 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4654 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4655 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
4656 
4657 /* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
4658 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4659 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4660 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4661 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4662 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
4663 
4664 /* Bit 0 : Write '1' to disable interrupt for event READY */
4665 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
4666 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
4667 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
4668 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4669 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
4670 
4671 /* Register: NFCT_ERRORSTATUS */
4672 /* Description: NFC Error Status register */
4673 
4674 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
4675 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
4676 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
4677 
4678 /* Register: NFCT_FRAMESTATUS_RX */
4679 /* Description: Result of last incoming frame */
4680 
4681 /* Bit 3 : Overrun detected */
4682 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
4683 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
4684 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
4685 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
4686 
4687 /* Bit 2 : Parity status of received frame */
4688 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
4689 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
4690 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
4691 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
4692 
4693 /* Bit 0 : No valid end of frame (EoF) detected */
4694 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
4695 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
4696 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
4697 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
4698 
4699 /* Register: NFCT_NFCTAGSTATE */
4700 /* Description: NfcTag state register */
4701 
4702 /* Bits 2..0 : NfcTag state */
4703 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */
4704 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */
4705 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */
4706 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */
4707 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL) /*!< Idle */
4708 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL) /*!< Receive */
4709 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */
4710 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */
4711 
4712 /* Register: NFCT_SLEEPSTATE */
4713 /* Description: Sleep state during automatic collision resolution */
4714 
4715 /* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE
4716         by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a
4717         GOSLEEP task. */
4718 #define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */
4719 #define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */
4720 #define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0UL) /*!< State is IDLE. */
4721 #define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (1UL) /*!< State is SLEEP_A. */
4722 
4723 /* Register: NFCT_FIELDPRESENT */
4724 /* Description: Indicates the presence or not of a valid field */
4725 
4726 /* Bit 1 : Indicates if the low level has locked to the field */
4727 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
4728 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
4729 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
4730 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
4731 
4732 /* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
4733 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
4734 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
4735 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
4736 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
4737 
4738 /* Register: NFCT_FRAMEDELAYMIN */
4739 /* Description: Minimum frame delay */
4740 
4741 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
4742 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
4743 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
4744 
4745 /* Register: NFCT_FRAMEDELAYMAX */
4746 /* Description: Maximum frame delay */
4747 
4748 /* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clocks */
4749 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
4750 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
4751 
4752 /* Register: NFCT_FRAMEDELAYMODE */
4753 /* Description: Configuration register for the Frame Delay Timer */
4754 
4755 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
4756 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
4757 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
4758 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
4759 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
4760 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
4761 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
4762 
4763 /* Register: NFCT_PACKETPTR */
4764 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
4765 
4766 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
4767 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4768 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
4769 
4770 /* Register: NFCT_MAXLEN */
4771 /* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */
4772 
4773 /* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */
4774 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
4775 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
4776 
4777 /* Register: NFCT_TXD_FRAMECONFIG */
4778 /* Description: Configuration of outgoing frames */
4779 
4780 /* Bit 4 : CRC mode for outgoing frames */
4781 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
4782 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
4783 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
4784 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
4785 
4786 /* Bit 2 : Adding SoF or not in TX frames */
4787 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4788 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4789 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol not added */
4790 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol added */
4791 
4792 /* Bit 1 : Discarding unused bits at start or end of a frame */
4793 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
4794 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
4795 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits are discarded at end of frame (EoF) */
4796 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits are discarded at start of frame (SoF) */
4797 
4798 /* Bit 0 : Indicates if parity is added to the frame */
4799 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4800 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4801 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added to TX frames */
4802 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added to TX frames */
4803 
4804 /* Register: NFCT_TXD_AMOUNT */
4805 /* Description: Size of outgoing frame */
4806 
4807 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
4808 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
4809 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
4810 
4811 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
4812 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
4813 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
4814 
4815 /* Register: NFCT_RXD_FRAMECONFIG */
4816 /* Description: Configuration of incoming frames */
4817 
4818 /* Bit 4 : CRC mode for incoming frames */
4819 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
4820 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
4821 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
4822 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
4823 
4824 /* Bit 2 : SoF expected or not in RX frames */
4825 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4826 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4827 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol is not expected in RX frames */
4828 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol is expected in RX frames */
4829 
4830 /* Bit 0 : Indicates if parity expected in RX frame */
4831 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4832 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4833 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
4834 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
4835 
4836 /* Register: NFCT_RXD_AMOUNT */
4837 /* Description: Size of last incoming frame */
4838 
4839 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
4840 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
4841 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
4842 
4843 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
4844 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
4845 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
4846 
4847 /* Register: NFCT_NFCID1_LAST */
4848 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
4849 
4850 /* Bits 31..24 : NFCID1 byte W */
4851 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
4852 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
4853 
4854 /* Bits 23..16 : NFCID1 byte X */
4855 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
4856 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
4857 
4858 /* Bits 15..8 : NFCID1 byte Y */
4859 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
4860 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
4861 
4862 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
4863 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
4864 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
4865 
4866 /* Register: NFCT_NFCID1_2ND_LAST */
4867 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
4868 
4869 /* Bits 23..16 : NFCID1 byte T */
4870 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
4871 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
4872 
4873 /* Bits 15..8 : NFCID1 byte U */
4874 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
4875 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
4876 
4877 /* Bits 7..0 : NFCID1 byte V */
4878 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
4879 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
4880 
4881 /* Register: NFCT_NFCID1_3RD_LAST */
4882 /* Description: Third last NFCID1 part (10 bytes ID) */
4883 
4884 /* Bits 23..16 : NFCID1 byte Q */
4885 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
4886 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
4887 
4888 /* Bits 15..8 : NFCID1 byte R */
4889 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
4890 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
4891 
4892 /* Bits 7..0 : NFCID1 byte S */
4893 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
4894 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
4895 
4896 /* Register: NFCT_AUTOCOLRESCONFIG */
4897 /* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. */
4898 
4899 /* Bit 0 : Enables/disables auto collision resolution */
4900 #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
4901 #define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
4902 #define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */
4903 #define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */
4904 
4905 /* Register: NFCT_SENSRES */
4906 /* Description: NFC-A SENS_RES auto-response settings */
4907 
4908 /* Bits 15..12 : Reserved for future use. Shall be 0. */
4909 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
4910 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
4911 
4912 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4913 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
4914 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
4915 
4916 /* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */
4917 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
4918 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
4919 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
4920 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
4921 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
4922 
4923 /* Bit 5 : Reserved for future use. Shall be 0. */
4924 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
4925 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
4926 
4927 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4928 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
4929 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
4930 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
4931 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
4932 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
4933 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
4934 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
4935 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
4936 
4937 /* Register: NFCT_SELRES */
4938 /* Description: NFC-A SEL_RES auto-response settings */
4939 
4940 /* Bit 7 : Reserved for future use. Shall be 0. */
4941 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
4942 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
4943 
4944 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4945 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
4946 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
4947 
4948 /* Bits 4..3 : Reserved for future use. Shall be 0. */
4949 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
4950 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
4951 
4952 /* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */
4953 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
4954 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
4955 
4956 /* Bits 1..0 : Reserved for future use. Shall be 0. */
4957 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
4958 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
4959 
4960 
4961 /* Peripheral: NVMC */
4962 /* Description: Non Volatile Memory Controller */
4963 
4964 /* Register: NVMC_READY */
4965 /* Description: Ready flag */
4966 
4967 /* Bit 0 : NVMC is ready or busy */
4968 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
4969 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
4970 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
4971 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
4972 
4973 /* Register: NVMC_READYNEXT */
4974 /* Description: Ready flag */
4975 
4976 /* Bit 0 : NVMC can accept a new write operation */
4977 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
4978 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
4979 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
4980 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
4981 
4982 /* Register: NVMC_CONFIG */
4983 /* Description: Configuration register */
4984 
4985 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
4986 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
4987 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
4988 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
4989 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
4990 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
4991 
4992 /* Register: NVMC_ERASEPAGE */
4993 /* Description: Register for erasing a page in code area */
4994 
4995 /* Bits 31..0 : Register for starting erase of a page in code area */
4996 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
4997 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
4998 
4999 /* Register: NVMC_ERASEPCR1 */
5000 /* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */
5001 
5002 /* Bits 31..0 : Register for erasing a page in code area, equivalent to ERASEPAGE */
5003 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
5004 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
5005 
5006 /* Register: NVMC_ERASEALL */
5007 /* Description: Register for erasing all non-volatile user memory */
5008 
5009 /* Bit 0 : Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */
5010 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
5011 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
5012 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
5013 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
5014 
5015 /* Register: NVMC_ERASEPCR0 */
5016 /* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */
5017 
5018 /* Bits 31..0 : Register for starting erase of a page in code area, equivalent to ERASEPAGE */
5019 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
5020 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
5021 
5022 /* Register: NVMC_ERASEUICR */
5023 /* Description: Register for erasing user information configuration registers */
5024 
5025 /* Bit 0 : Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. */
5026 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
5027 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
5028 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
5029 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
5030 
5031 /* Register: NVMC_ERASEPAGEPARTIAL */
5032 /* Description: Register for partial erase of a page in code area */
5033 
5034 /* Bits 31..0 : Register for starting partial erase of a page in code area */
5035 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */
5036 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */
5037 
5038 /* Register: NVMC_ERASEPAGEPARTIALCFG */
5039 /* Description: Register for partial erase configuration */
5040 
5041 /* Bits 6..0 : Duration of the partial erase in milliseconds */
5042 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
5043 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
5044 
5045 /* Register: NVMC_ICACHECNF */
5046 /* Description: I-code cache configuration register */
5047 
5048 /* Bit 8 : Cache profiling enable */
5049 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
5050 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
5051 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
5052 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
5053 
5054 /* Bit 0 : Cache enable */
5055 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
5056 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
5057 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
5058 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
5059 
5060 /* Register: NVMC_IHIT */
5061 /* Description: I-code cache hit counter */
5062 
5063 /* Bits 31..0 : Number of cache hits. Register is writable, but only to '0'. */
5064 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
5065 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
5066 
5067 /* Register: NVMC_IMISS */
5068 /* Description: I-code cache miss counter */
5069 
5070 /* Bits 31..0 : Number of cache misses. Register is writable, but only to '0'. */
5071 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
5072 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
5073 
5074 
5075 /* Peripheral: GPIO */
5076 /* Description: GPIO Port 1 */
5077 
5078 /* Register: GPIO_OUT */
5079 /* Description: Write GPIO port */
5080 
5081 /* Bit 31 : Pin 31 */
5082 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5083 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5084 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
5085 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
5086 
5087 /* Bit 30 : Pin 30 */
5088 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5089 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5090 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
5091 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
5092 
5093 /* Bit 29 : Pin 29 */
5094 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5095 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5096 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
5097 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
5098 
5099 /* Bit 28 : Pin 28 */
5100 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5101 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5102 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
5103 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
5104 
5105 /* Bit 27 : Pin 27 */
5106 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5107 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5108 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
5109 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
5110 
5111 /* Bit 26 : Pin 26 */
5112 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5113 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5114 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
5115 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
5116 
5117 /* Bit 25 : Pin 25 */
5118 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5119 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5120 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
5121 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
5122 
5123 /* Bit 24 : Pin 24 */
5124 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5125 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5126 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
5127 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
5128 
5129 /* Bit 23 : Pin 23 */
5130 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5131 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5132 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
5133 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
5134 
5135 /* Bit 22 : Pin 22 */
5136 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5137 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5138 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
5139 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
5140 
5141 /* Bit 21 : Pin 21 */
5142 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5143 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5144 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
5145 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
5146 
5147 /* Bit 20 : Pin 20 */
5148 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5149 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5150 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
5151 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
5152 
5153 /* Bit 19 : Pin 19 */
5154 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5155 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5156 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
5157 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
5158 
5159 /* Bit 18 : Pin 18 */
5160 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5161 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5162 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
5163 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
5164 
5165 /* Bit 17 : Pin 17 */
5166 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5167 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5168 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
5169 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
5170 
5171 /* Bit 16 : Pin 16 */
5172 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5173 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5174 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
5175 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
5176 
5177 /* Bit 15 : Pin 15 */
5178 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5179 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5180 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
5181 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
5182 
5183 /* Bit 14 : Pin 14 */
5184 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5185 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5186 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
5187 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
5188 
5189 /* Bit 13 : Pin 13 */
5190 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5191 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5192 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
5193 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
5194 
5195 /* Bit 12 : Pin 12 */
5196 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5197 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5198 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
5199 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
5200 
5201 /* Bit 11 : Pin 11 */
5202 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5203 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5204 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
5205 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
5206 
5207 /* Bit 10 : Pin 10 */
5208 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5209 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5210 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
5211 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
5212 
5213 /* Bit 9 : Pin 9 */
5214 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5215 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5216 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
5217 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
5218 
5219 /* Bit 8 : Pin 8 */
5220 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5221 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5222 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
5223 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
5224 
5225 /* Bit 7 : Pin 7 */
5226 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5227 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5228 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
5229 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
5230 
5231 /* Bit 6 : Pin 6 */
5232 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5233 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5234 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
5235 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
5236 
5237 /* Bit 5 : Pin 5 */
5238 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5239 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5240 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
5241 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
5242 
5243 /* Bit 4 : Pin 4 */
5244 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5245 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5246 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
5247 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
5248 
5249 /* Bit 3 : Pin 3 */
5250 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5251 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5252 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
5253 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
5254 
5255 /* Bit 2 : Pin 2 */
5256 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5257 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5258 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
5259 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
5260 
5261 /* Bit 1 : Pin 1 */
5262 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5263 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5264 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
5265 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
5266 
5267 /* Bit 0 : Pin 0 */
5268 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5269 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5270 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
5271 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
5272 
5273 /* Register: GPIO_OUTSET */
5274 /* Description: Set individual bits in GPIO port */
5275 
5276 /* Bit 31 : Pin 31 */
5277 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5278 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5279 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
5280 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5281 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5282 
5283 /* Bit 30 : Pin 30 */
5284 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5285 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5286 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
5287 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5288 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5289 
5290 /* Bit 29 : Pin 29 */
5291 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5292 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5293 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
5294 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5295 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5296 
5297 /* Bit 28 : Pin 28 */
5298 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5299 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5300 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
5301 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5302 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5303 
5304 /* Bit 27 : Pin 27 */
5305 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5306 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5307 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
5308 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5309 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5310 
5311 /* Bit 26 : Pin 26 */
5312 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5313 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5314 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
5315 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5316 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5317 
5318 /* Bit 25 : Pin 25 */
5319 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5320 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5321 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
5322 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5323 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5324 
5325 /* Bit 24 : Pin 24 */
5326 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5327 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5328 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
5329 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5330 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5331 
5332 /* Bit 23 : Pin 23 */
5333 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5334 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5335 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
5336 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5337 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5338 
5339 /* Bit 22 : Pin 22 */
5340 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5341 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5342 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
5343 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5344 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5345 
5346 /* Bit 21 : Pin 21 */
5347 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5348 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5349 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
5350 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5351 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5352 
5353 /* Bit 20 : Pin 20 */
5354 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5355 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5356 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
5357 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5358 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5359 
5360 /* Bit 19 : Pin 19 */
5361 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5362 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5363 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
5364 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5365 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5366 
5367 /* Bit 18 : Pin 18 */
5368 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5369 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5370 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
5371 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5372 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5373 
5374 /* Bit 17 : Pin 17 */
5375 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5376 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5377 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
5378 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5379 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5380 
5381 /* Bit 16 : Pin 16 */
5382 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5383 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5384 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
5385 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5386 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5387 
5388 /* Bit 15 : Pin 15 */
5389 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5390 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5391 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
5392 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5393 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5394 
5395 /* Bit 14 : Pin 14 */
5396 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5397 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5398 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
5399 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5400 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5401 
5402 /* Bit 13 : Pin 13 */
5403 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5404 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5405 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
5406 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5407 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5408 
5409 /* Bit 12 : Pin 12 */
5410 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5411 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5412 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
5413 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5414 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5415 
5416 /* Bit 11 : Pin 11 */
5417 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5418 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5419 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
5420 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5421 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5422 
5423 /* Bit 10 : Pin 10 */
5424 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5425 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5426 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
5427 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5428 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5429 
5430 /* Bit 9 : Pin 9 */
5431 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5432 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5433 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
5434 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5435 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5436 
5437 /* Bit 8 : Pin 8 */
5438 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5439 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5440 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
5441 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5442 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5443 
5444 /* Bit 7 : Pin 7 */
5445 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5446 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5447 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
5448 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5449 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5450 
5451 /* Bit 6 : Pin 6 */
5452 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5453 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5454 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
5455 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5456 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5457 
5458 /* Bit 5 : Pin 5 */
5459 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5460 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5461 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
5462 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5463 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5464 
5465 /* Bit 4 : Pin 4 */
5466 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5467 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5468 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
5469 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5470 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5471 
5472 /* Bit 3 : Pin 3 */
5473 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5474 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5475 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
5476 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5477 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5478 
5479 /* Bit 2 : Pin 2 */
5480 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5481 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5482 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
5483 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5484 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5485 
5486 /* Bit 1 : Pin 1 */
5487 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5488 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5489 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
5490 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5491 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5492 
5493 /* Bit 0 : Pin 0 */
5494 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5495 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5496 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
5497 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5498 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */
5499 
5500 /* Register: GPIO_OUTCLR */
5501 /* Description: Clear individual bits in GPIO port */
5502 
5503 /* Bit 31 : Pin 31 */
5504 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5505 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5506 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
5507 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5508 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5509 
5510 /* Bit 30 : Pin 30 */
5511 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5512 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5513 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
5514 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5515 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5516 
5517 /* Bit 29 : Pin 29 */
5518 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5519 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5520 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
5521 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5522 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5523 
5524 /* Bit 28 : Pin 28 */
5525 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5526 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5527 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
5528 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5529 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5530 
5531 /* Bit 27 : Pin 27 */
5532 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5533 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5534 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
5535 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5536 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5537 
5538 /* Bit 26 : Pin 26 */
5539 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5540 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5541 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
5542 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
5543 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5544 
5545 /* Bit 25 : Pin 25 */
5546 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5547 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5548 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
5549 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
5550 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5551 
5552 /* Bit 24 : Pin 24 */
5553 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5554 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5555 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
5556 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
5557 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5558 
5559 /* Bit 23 : Pin 23 */
5560 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5561 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5562 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
5563 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
5564 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5565 
5566 /* Bit 22 : Pin 22 */
5567 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5568 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5569 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
5570 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
5571 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5572 
5573 /* Bit 21 : Pin 21 */
5574 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5575 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5576 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
5577 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
5578 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5579 
5580 /* Bit 20 : Pin 20 */
5581 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5582 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5583 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
5584 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
5585 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5586 
5587 /* Bit 19 : Pin 19 */
5588 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5589 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5590 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
5591 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
5592 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5593 
5594 /* Bit 18 : Pin 18 */
5595 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5596 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5597 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
5598 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
5599 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5600 
5601 /* Bit 17 : Pin 17 */
5602 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5603 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5604 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
5605 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
5606 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5607 
5608 /* Bit 16 : Pin 16 */
5609 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5610 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5611 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
5612 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
5613 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5614 
5615 /* Bit 15 : Pin 15 */
5616 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5617 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5618 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
5619 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
5620 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5621 
5622 /* Bit 14 : Pin 14 */
5623 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5624 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5625 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
5626 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
5627 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5628 
5629 /* Bit 13 : Pin 13 */
5630 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5631 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5632 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
5633 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
5634 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5635 
5636 /* Bit 12 : Pin 12 */
5637 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5638 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5639 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
5640 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
5641 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5642 
5643 /* Bit 11 : Pin 11 */
5644 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5645 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5646 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
5647 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
5648 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5649 
5650 /* Bit 10 : Pin 10 */
5651 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5652 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5653 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
5654 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
5655 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5656 
5657 /* Bit 9 : Pin 9 */
5658 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5659 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5660 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
5661 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
5662 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5663 
5664 /* Bit 8 : Pin 8 */
5665 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5666 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5667 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
5668 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
5669 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5670 
5671 /* Bit 7 : Pin 7 */
5672 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5673 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5674 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
5675 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
5676 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5677 
5678 /* Bit 6 : Pin 6 */
5679 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5680 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5681 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
5682 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
5683 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5684 
5685 /* Bit 5 : Pin 5 */
5686 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5687 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5688 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
5689 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
5690 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5691 
5692 /* Bit 4 : Pin 4 */
5693 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5694 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5695 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
5696 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
5697 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5698 
5699 /* Bit 3 : Pin 3 */
5700 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5701 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5702 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
5703 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
5704 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5705 
5706 /* Bit 2 : Pin 2 */
5707 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5708 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5709 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
5710 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
5711 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5712 
5713 /* Bit 1 : Pin 1 */
5714 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5715 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5716 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
5717 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
5718 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5719 
5720 /* Bit 0 : Pin 0 */
5721 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5722 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5723 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
5724 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
5725 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */
5726 
5727 /* Register: GPIO_IN */
5728 /* Description: Read GPIO port */
5729 
5730 /* Bit 31 : Pin 31 */
5731 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5732 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5733 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
5734 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
5735 
5736 /* Bit 30 : Pin 30 */
5737 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5738 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5739 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
5740 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
5741 
5742 /* Bit 29 : Pin 29 */
5743 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5744 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5745 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
5746 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
5747 
5748 /* Bit 28 : Pin 28 */
5749 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5750 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5751 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
5752 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
5753 
5754 /* Bit 27 : Pin 27 */
5755 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5756 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5757 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
5758 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
5759 
5760 /* Bit 26 : Pin 26 */
5761 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5762 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5763 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
5764 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
5765 
5766 /* Bit 25 : Pin 25 */
5767 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5768 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5769 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
5770 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
5771 
5772 /* Bit 24 : Pin 24 */
5773 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5774 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5775 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
5776 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
5777 
5778 /* Bit 23 : Pin 23 */
5779 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5780 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5781 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
5782 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
5783 
5784 /* Bit 22 : Pin 22 */
5785 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5786 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5787 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
5788 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
5789 
5790 /* Bit 21 : Pin 21 */
5791 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5792 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5793 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
5794 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
5795 
5796 /* Bit 20 : Pin 20 */
5797 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5798 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5799 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
5800 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
5801 
5802 /* Bit 19 : Pin 19 */
5803 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5804 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5805 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
5806 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
5807 
5808 /* Bit 18 : Pin 18 */
5809 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5810 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5811 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
5812 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
5813 
5814 /* Bit 17 : Pin 17 */
5815 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5816 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5817 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
5818 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
5819 
5820 /* Bit 16 : Pin 16 */
5821 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5822 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5823 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
5824 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
5825 
5826 /* Bit 15 : Pin 15 */
5827 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5828 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5829 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
5830 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
5831 
5832 /* Bit 14 : Pin 14 */
5833 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5834 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5835 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
5836 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
5837 
5838 /* Bit 13 : Pin 13 */
5839 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5840 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5841 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
5842 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
5843 
5844 /* Bit 12 : Pin 12 */
5845 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5846 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5847 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
5848 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
5849 
5850 /* Bit 11 : Pin 11 */
5851 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5852 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5853 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
5854 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
5855 
5856 /* Bit 10 : Pin 10 */
5857 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5858 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5859 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
5860 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
5861 
5862 /* Bit 9 : Pin 9 */
5863 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5864 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5865 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
5866 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
5867 
5868 /* Bit 8 : Pin 8 */
5869 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5870 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5871 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
5872 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
5873 
5874 /* Bit 7 : Pin 7 */
5875 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5876 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5877 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
5878 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
5879 
5880 /* Bit 6 : Pin 6 */
5881 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5882 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5883 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
5884 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
5885 
5886 /* Bit 5 : Pin 5 */
5887 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5888 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5889 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
5890 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
5891 
5892 /* Bit 4 : Pin 4 */
5893 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5894 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5895 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
5896 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
5897 
5898 /* Bit 3 : Pin 3 */
5899 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5900 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5901 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
5902 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
5903 
5904 /* Bit 2 : Pin 2 */
5905 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5906 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5907 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
5908 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
5909 
5910 /* Bit 1 : Pin 1 */
5911 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5912 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5913 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
5914 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
5915 
5916 /* Bit 0 : Pin 0 */
5917 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5918 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5919 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
5920 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
5921 
5922 /* Register: GPIO_DIR */
5923 /* Description: Direction of GPIO pins */
5924 
5925 /* Bit 31 : Pin 31 */
5926 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5927 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5928 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
5929 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
5930 
5931 /* Bit 30 : Pin 30 */
5932 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5933 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5934 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
5935 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
5936 
5937 /* Bit 29 : Pin 29 */
5938 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5939 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5940 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
5941 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
5942 
5943 /* Bit 28 : Pin 28 */
5944 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5945 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5946 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
5947 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
5948 
5949 /* Bit 27 : Pin 27 */
5950 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5951 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5952 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
5953 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
5954 
5955 /* Bit 26 : Pin 26 */
5956 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5957 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5958 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
5959 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
5960 
5961 /* Bit 25 : Pin 25 */
5962 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5963 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5964 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
5965 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
5966 
5967 /* Bit 24 : Pin 24 */
5968 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5969 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5970 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
5971 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
5972 
5973 /* Bit 23 : Pin 23 */
5974 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5975 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5976 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
5977 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
5978 
5979 /* Bit 22 : Pin 22 */
5980 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5981 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5982 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
5983 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
5984 
5985 /* Bit 21 : Pin 21 */
5986 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5987 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5988 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
5989 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
5990 
5991 /* Bit 20 : Pin 20 */
5992 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5993 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5994 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
5995 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
5996 
5997 /* Bit 19 : Pin 19 */
5998 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5999 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6000 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
6001 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
6002 
6003 /* Bit 18 : Pin 18 */
6004 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6005 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6006 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
6007 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
6008 
6009 /* Bit 17 : Pin 17 */
6010 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6011 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6012 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
6013 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
6014 
6015 /* Bit 16 : Pin 16 */
6016 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6017 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6018 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
6019 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
6020 
6021 /* Bit 15 : Pin 15 */
6022 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6023 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6024 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
6025 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
6026 
6027 /* Bit 14 : Pin 14 */
6028 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6029 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6030 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
6031 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
6032 
6033 /* Bit 13 : Pin 13 */
6034 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6035 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6036 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
6037 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
6038 
6039 /* Bit 12 : Pin 12 */
6040 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6041 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6042 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
6043 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
6044 
6045 /* Bit 11 : Pin 11 */
6046 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6047 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6048 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
6049 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
6050 
6051 /* Bit 10 : Pin 10 */
6052 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6053 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6054 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
6055 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
6056 
6057 /* Bit 9 : Pin 9 */
6058 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6059 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6060 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
6061 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
6062 
6063 /* Bit 8 : Pin 8 */
6064 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6065 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6066 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
6067 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
6068 
6069 /* Bit 7 : Pin 7 */
6070 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6071 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6072 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
6073 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
6074 
6075 /* Bit 6 : Pin 6 */
6076 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6077 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6078 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
6079 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
6080 
6081 /* Bit 5 : Pin 5 */
6082 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6083 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6084 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
6085 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
6086 
6087 /* Bit 4 : Pin 4 */
6088 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6089 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6090 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
6091 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
6092 
6093 /* Bit 3 : Pin 3 */
6094 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6095 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6096 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
6097 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
6098 
6099 /* Bit 2 : Pin 2 */
6100 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6101 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6102 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
6103 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
6104 
6105 /* Bit 1 : Pin 1 */
6106 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6107 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6108 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
6109 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
6110 
6111 /* Bit 0 : Pin 0 */
6112 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6113 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6114 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
6115 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
6116 
6117 /* Register: GPIO_DIRSET */
6118 /* Description: DIR set register */
6119 
6120 /* Bit 31 : Set as output pin 31 */
6121 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6122 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6123 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
6124 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
6125 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6126 
6127 /* Bit 30 : Set as output pin 30 */
6128 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6129 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6130 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
6131 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
6132 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6133 
6134 /* Bit 29 : Set as output pin 29 */
6135 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6136 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6137 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
6138 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
6139 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6140 
6141 /* Bit 28 : Set as output pin 28 */
6142 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6143 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6144 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
6145 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
6146 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6147 
6148 /* Bit 27 : Set as output pin 27 */
6149 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6150 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6151 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
6152 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
6153 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6154 
6155 /* Bit 26 : Set as output pin 26 */
6156 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6157 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6158 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
6159 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
6160 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6161 
6162 /* Bit 25 : Set as output pin 25 */
6163 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6164 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6165 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
6166 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
6167 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6168 
6169 /* Bit 24 : Set as output pin 24 */
6170 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6171 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6172 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
6173 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
6174 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6175 
6176 /* Bit 23 : Set as output pin 23 */
6177 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6178 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6179 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
6180 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
6181 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6182 
6183 /* Bit 22 : Set as output pin 22 */
6184 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6185 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6186 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
6187 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
6188 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6189 
6190 /* Bit 21 : Set as output pin 21 */
6191 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6192 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6193 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
6194 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
6195 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6196 
6197 /* Bit 20 : Set as output pin 20 */
6198 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6199 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6200 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
6201 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
6202 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6203 
6204 /* Bit 19 : Set as output pin 19 */
6205 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6206 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6207 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
6208 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
6209 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6210 
6211 /* Bit 18 : Set as output pin 18 */
6212 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6213 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6214 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
6215 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
6216 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6217 
6218 /* Bit 17 : Set as output pin 17 */
6219 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6220 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6221 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
6222 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
6223 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6224 
6225 /* Bit 16 : Set as output pin 16 */
6226 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6227 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6228 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
6229 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
6230 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6231 
6232 /* Bit 15 : Set as output pin 15 */
6233 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6234 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6235 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
6236 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
6237 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6238 
6239 /* Bit 14 : Set as output pin 14 */
6240 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6241 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6242 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
6243 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
6244 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6245 
6246 /* Bit 13 : Set as output pin 13 */
6247 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6248 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6249 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
6250 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
6251 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6252 
6253 /* Bit 12 : Set as output pin 12 */
6254 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6255 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6256 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
6257 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
6258 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6259 
6260 /* Bit 11 : Set as output pin 11 */
6261 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6262 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6263 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
6264 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
6265 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6266 
6267 /* Bit 10 : Set as output pin 10 */
6268 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6269 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6270 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
6271 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
6272 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6273 
6274 /* Bit 9 : Set as output pin 9 */
6275 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6276 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6277 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
6278 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
6279 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6280 
6281 /* Bit 8 : Set as output pin 8 */
6282 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6283 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6284 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
6285 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
6286 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6287 
6288 /* Bit 7 : Set as output pin 7 */
6289 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6290 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6291 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
6292 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
6293 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6294 
6295 /* Bit 6 : Set as output pin 6 */
6296 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6297 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6298 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
6299 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
6300 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6301 
6302 /* Bit 5 : Set as output pin 5 */
6303 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6304 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6305 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
6306 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
6307 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6308 
6309 /* Bit 4 : Set as output pin 4 */
6310 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6311 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6312 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
6313 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
6314 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6315 
6316 /* Bit 3 : Set as output pin 3 */
6317 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6318 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6319 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
6320 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
6321 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6322 
6323 /* Bit 2 : Set as output pin 2 */
6324 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6325 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6326 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
6327 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
6328 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6329 
6330 /* Bit 1 : Set as output pin 1 */
6331 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6332 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6333 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
6334 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
6335 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6336 
6337 /* Bit 0 : Set as output pin 0 */
6338 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6339 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6340 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
6341 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
6342 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */
6343 
6344 /* Register: GPIO_DIRCLR */
6345 /* Description: DIR clear register */
6346 
6347 /* Bit 31 : Set as input pin 31 */
6348 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6349 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6350 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
6351 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
6352 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6353 
6354 /* Bit 30 : Set as input pin 30 */
6355 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6356 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6357 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
6358 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
6359 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6360 
6361 /* Bit 29 : Set as input pin 29 */
6362 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6363 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6364 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
6365 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
6366 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6367 
6368 /* Bit 28 : Set as input pin 28 */
6369 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6370 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6371 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
6372 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
6373 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6374 
6375 /* Bit 27 : Set as input pin 27 */
6376 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6377 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6378 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
6379 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
6380 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6381 
6382 /* Bit 26 : Set as input pin 26 */
6383 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6384 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6385 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
6386 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
6387 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6388 
6389 /* Bit 25 : Set as input pin 25 */
6390 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6391 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6392 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
6393 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
6394 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6395 
6396 /* Bit 24 : Set as input pin 24 */
6397 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6398 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6399 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
6400 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
6401 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6402 
6403 /* Bit 23 : Set as input pin 23 */
6404 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6405 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6406 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
6407 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
6408 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6409 
6410 /* Bit 22 : Set as input pin 22 */
6411 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6412 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6413 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
6414 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
6415 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6416 
6417 /* Bit 21 : Set as input pin 21 */
6418 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6419 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6420 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
6421 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
6422 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6423 
6424 /* Bit 20 : Set as input pin 20 */
6425 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6426 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6427 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
6428 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
6429 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6430 
6431 /* Bit 19 : Set as input pin 19 */
6432 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6433 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6434 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
6435 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
6436 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6437 
6438 /* Bit 18 : Set as input pin 18 */
6439 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6440 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6441 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
6442 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
6443 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6444 
6445 /* Bit 17 : Set as input pin 17 */
6446 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6447 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6448 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
6449 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
6450 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6451 
6452 /* Bit 16 : Set as input pin 16 */
6453 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6454 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6455 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
6456 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
6457 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6458 
6459 /* Bit 15 : Set as input pin 15 */
6460 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6461 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6462 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
6463 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
6464 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6465 
6466 /* Bit 14 : Set as input pin 14 */
6467 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6468 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6469 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
6470 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
6471 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6472 
6473 /* Bit 13 : Set as input pin 13 */
6474 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6475 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6476 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
6477 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
6478 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6479 
6480 /* Bit 12 : Set as input pin 12 */
6481 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6482 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6483 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
6484 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
6485 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6486 
6487 /* Bit 11 : Set as input pin 11 */
6488 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6489 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6490 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
6491 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
6492 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6493 
6494 /* Bit 10 : Set as input pin 10 */
6495 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6496 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6497 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
6498 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
6499 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6500 
6501 /* Bit 9 : Set as input pin 9 */
6502 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6503 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6504 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
6505 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
6506 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6507 
6508 /* Bit 8 : Set as input pin 8 */
6509 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6510 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6511 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
6512 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
6513 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6514 
6515 /* Bit 7 : Set as input pin 7 */
6516 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6517 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6518 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
6519 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
6520 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6521 
6522 /* Bit 6 : Set as input pin 6 */
6523 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6524 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6525 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
6526 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
6527 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6528 
6529 /* Bit 5 : Set as input pin 5 */
6530 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6531 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6532 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
6533 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
6534 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6535 
6536 /* Bit 4 : Set as input pin 4 */
6537 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6538 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6539 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
6540 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
6541 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6542 
6543 /* Bit 3 : Set as input pin 3 */
6544 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6545 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6546 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
6547 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
6548 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6549 
6550 /* Bit 2 : Set as input pin 2 */
6551 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6552 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6553 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
6554 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
6555 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6556 
6557 /* Bit 1 : Set as input pin 1 */
6558 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6559 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6560 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
6561 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
6562 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6563 
6564 /* Bit 0 : Set as input pin 0 */
6565 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6566 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6567 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
6568 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
6569 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */
6570 
6571 /* Register: GPIO_LATCH */
6572 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
6573 
6574 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
6575 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6576 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6577 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
6578 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
6579 
6580 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
6581 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6582 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6583 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
6584 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
6585 
6586 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
6587 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6588 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6589 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
6590 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
6591 
6592 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
6593 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6594 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6595 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
6596 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
6597 
6598 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
6599 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6600 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6601 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
6602 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
6603 
6604 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
6605 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6606 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6607 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
6608 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
6609 
6610 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
6611 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6612 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6613 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
6614 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
6615 
6616 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
6617 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6618 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6619 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
6620 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
6621 
6622 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
6623 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6624 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6625 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
6626 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
6627 
6628 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
6629 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6630 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6631 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
6632 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
6633 
6634 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
6635 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6636 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6637 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
6638 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
6639 
6640 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
6641 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6642 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6643 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
6644 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
6645 
6646 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
6647 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6648 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6649 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
6650 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
6651 
6652 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
6653 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6654 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6655 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
6656 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
6657 
6658 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
6659 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6660 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6661 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
6662 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
6663 
6664 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
6665 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6666 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6667 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
6668 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
6669 
6670 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
6671 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6672 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6673 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
6674 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
6675 
6676 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
6677 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6678 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6679 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
6680 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
6681 
6682 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
6683 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6684 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6685 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
6686 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
6687 
6688 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
6689 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6690 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6691 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
6692 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
6693 
6694 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
6695 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6696 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6697 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
6698 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
6699 
6700 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
6701 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6702 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6703 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
6704 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
6705 
6706 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
6707 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6708 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6709 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
6710 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
6711 
6712 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
6713 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6714 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6715 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
6716 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
6717 
6718 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
6719 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6720 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6721 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
6722 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
6723 
6724 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
6725 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6726 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6727 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
6728 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
6729 
6730 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
6731 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6732 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6733 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
6734 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
6735 
6736 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
6737 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6738 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6739 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
6740 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
6741 
6742 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
6743 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6744 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6745 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
6746 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
6747 
6748 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
6749 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6750 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6751 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
6752 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
6753 
6754 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
6755 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6756 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6757 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
6758 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
6759 
6760 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
6761 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6762 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6763 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
6764 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
6765 
6766 /* Register: GPIO_DETECTMODE */
6767 /* Description: Select between default DETECT signal behavior and LDETECT mode */
6768 
6769 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
6770 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
6771 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
6772 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
6773 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
6774 
6775 /* Register: GPIO_PIN_CNF */
6776 /* Description: Description collection: Configuration of GPIO pins */
6777 
6778 /* Bits 17..16 : Pin sensing mechanism */
6779 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
6780 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
6781 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
6782 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
6783 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
6784 
6785 /* Bits 10..8 : Drive configuration */
6786 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
6787 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
6788 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
6789 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
6790 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
6791 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
6792 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
6793 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
6794 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
6795 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
6796 
6797 /* Bits 3..2 : Pull configuration */
6798 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
6799 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
6800 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
6801 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
6802 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
6803 
6804 /* Bit 1 : Connect or disconnect input buffer */
6805 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
6806 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
6807 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
6808 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
6809 
6810 /* Bit 0 : Pin direction. Same physical register as DIR register */
6811 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
6812 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
6813 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
6814 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
6815 
6816 
6817 /* Peripheral: PDM */
6818 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
6819 
6820 /* Register: PDM_TASKS_START */
6821 /* Description: Starts continuous PDM transfer */
6822 
6823 /* Bit 0 : Starts continuous PDM transfer */
6824 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6825 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6826 #define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6827 
6828 /* Register: PDM_TASKS_STOP */
6829 /* Description: Stops PDM transfer */
6830 
6831 /* Bit 0 : Stops PDM transfer */
6832 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6833 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6834 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6835 
6836 /* Register: PDM_EVENTS_STARTED */
6837 /* Description: PDM transfer has started */
6838 
6839 /* Bit 0 : PDM transfer has started */
6840 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
6841 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
6842 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
6843 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
6844 
6845 /* Register: PDM_EVENTS_STOPPED */
6846 /* Description: PDM transfer has finished */
6847 
6848 /* Bit 0 : PDM transfer has finished */
6849 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
6850 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
6851 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
6852 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
6853 
6854 /* Register: PDM_EVENTS_END */
6855 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
6856 
6857 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
6858 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
6859 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
6860 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
6861 #define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
6862 
6863 /* Register: PDM_INTEN */
6864 /* Description: Enable or disable interrupt */
6865 
6866 /* Bit 2 : Enable or disable interrupt for event END */
6867 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
6868 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
6869 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
6870 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
6871 
6872 /* Bit 1 : Enable or disable interrupt for event STOPPED */
6873 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6874 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6875 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6876 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6877 
6878 /* Bit 0 : Enable or disable interrupt for event STARTED */
6879 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6880 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
6881 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6882 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6883 
6884 /* Register: PDM_INTENSET */
6885 /* Description: Enable interrupt */
6886 
6887 /* Bit 2 : Write '1' to enable interrupt for event END */
6888 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
6889 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
6890 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6891 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6892 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
6893 
6894 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
6895 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6896 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6897 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6898 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6899 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6900 
6901 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
6902 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6903 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6904 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6905 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6906 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6907 
6908 /* Register: PDM_INTENCLR */
6909 /* Description: Disable interrupt */
6910 
6911 /* Bit 2 : Write '1' to disable interrupt for event END */
6912 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
6913 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
6914 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6915 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6916 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
6917 
6918 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
6919 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6920 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6921 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6922 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6923 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6924 
6925 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
6926 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6927 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
6928 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6929 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6930 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6931 
6932 /* Register: PDM_ENABLE */
6933 /* Description: PDM module enable register */
6934 
6935 /* Bit 0 : Enable or disable PDM module */
6936 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6937 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6938 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
6939 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
6940 
6941 /* Register: PDM_PDMCLKCTRL */
6942 /* Description: PDM clock generator control */
6943 
6944 /* Bits 31..0 : PDM_CLK frequency configuration */
6945 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
6946 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
6947 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
6948 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
6949 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
6950 #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
6951 #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
6952 #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
6953 
6954 /* Register: PDM_MODE */
6955 /* Description: Defines the routing of the connected PDM microphones' signals */
6956 
6957 /* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
6958 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
6959 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
6960 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
6961 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
6962 
6963 /* Bit 0 : Mono or stereo operation */
6964 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
6965 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
6966 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */
6967 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */
6968 
6969 /* Register: PDM_GAINL */
6970 /* Description: Left output gain adjustment */
6971 
6972 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
6973 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
6974 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
6975 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
6976 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
6977 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
6978 
6979 /* Register: PDM_GAINR */
6980 /* Description: Right output gain adjustment */
6981 
6982 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
6983 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
6984 #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
6985 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
6986 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
6987 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
6988 
6989 /* Register: PDM_RATIO */
6990 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
6991 
6992 /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
6993 #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
6994 #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
6995 #define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */
6996 #define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
6997 
6998 /* Register: PDM_PSEL_CLK */
6999 /* Description: Pin number configuration for PDM CLK signal */
7000 
7001 /* Bit 31 : Connection */
7002 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7003 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7004 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
7005 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7006 
7007 /* Bit 5 : Port number */
7008 #define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */
7009 #define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */
7010 
7011 /* Bits 4..0 : Pin number */
7012 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
7013 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
7014 
7015 /* Register: PDM_PSEL_DIN */
7016 /* Description: Pin number configuration for PDM DIN signal */
7017 
7018 /* Bit 31 : Connection */
7019 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7020 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7021 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
7022 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
7023 
7024 /* Bit 5 : Port number */
7025 #define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */
7026 #define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */
7027 
7028 /* Bits 4..0 : Pin number */
7029 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
7030 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
7031 
7032 /* Register: PDM_SAMPLE_PTR */
7033 /* Description: RAM address pointer to write samples to with EasyDMA */
7034 
7035 /* Bits 31..0 : Address to write PDM samples to over DMA */
7036 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
7037 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
7038 
7039 /* Register: PDM_SAMPLE_MAXCNT */
7040 /* Description: Number of samples to allocate memory for in EasyDMA mode */
7041 
7042 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
7043 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
7044 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
7045 
7046 
7047 /* Peripheral: POWER */
7048 /* Description: Power control */
7049 
7050 /* Register: POWER_TASKS_CONSTLAT */
7051 /* Description: Enable Constant Latency mode */
7052 
7053 /* Bit 0 : Enable Constant Latency mode */
7054 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
7055 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
7056 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
7057 
7058 /* Register: POWER_TASKS_LOWPWR */
7059 /* Description: Enable Low-power mode (variable latency) */
7060 
7061 /* Bit 0 : Enable Low-power mode (variable latency) */
7062 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
7063 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
7064 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
7065 
7066 /* Register: POWER_EVENTS_POFWARN */
7067 /* Description: Power failure warning */
7068 
7069 /* Bit 0 : Power failure warning */
7070 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
7071 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
7072 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
7073 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
7074 
7075 /* Register: POWER_EVENTS_SLEEPENTER */
7076 /* Description: CPU entered WFI/WFE sleep */
7077 
7078 /* Bit 0 : CPU entered WFI/WFE sleep */
7079 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
7080 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
7081 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
7082 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
7083 
7084 /* Register: POWER_EVENTS_SLEEPEXIT */
7085 /* Description: CPU exited WFI/WFE sleep */
7086 
7087 /* Bit 0 : CPU exited WFI/WFE sleep */
7088 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
7089 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
7090 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
7091 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
7092 
7093 /* Register: POWER_EVENTS_USBDETECTED */
7094 /* Description: Voltage supply detected on VBUS */
7095 
7096 /* Bit 0 : Voltage supply detected on VBUS */
7097 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */
7098 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */
7099 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */
7100 #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */
7101 
7102 /* Register: POWER_EVENTS_USBREMOVED */
7103 /* Description: Voltage supply removed from VBUS */
7104 
7105 /* Bit 0 : Voltage supply removed from VBUS */
7106 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */
7107 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */
7108 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */
7109 #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */
7110 
7111 /* Register: POWER_EVENTS_USBPWRRDY */
7112 /* Description: USB 3.3 V supply ready */
7113 
7114 /* Bit 0 : USB 3.3 V supply ready */
7115 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */
7116 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */
7117 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */
7118 #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */
7119 
7120 /* Register: POWER_INTENSET */
7121 /* Description: Enable interrupt */
7122 
7123 /* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */
7124 #define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
7125 #define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
7126 #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
7127 #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
7128 #define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */
7129 
7130 /* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */
7131 #define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
7132 #define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
7133 #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
7134 #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
7135 #define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */
7136 
7137 /* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */
7138 #define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
7139 #define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
7140 #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
7141 #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
7142 #define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */
7143 
7144 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
7145 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
7146 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
7147 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
7148 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
7149 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
7150 
7151 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
7152 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
7153 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
7154 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
7155 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
7156 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
7157 
7158 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
7159 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
7160 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
7161 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
7162 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7163 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
7164 
7165 /* Register: POWER_INTENCLR */
7166 /* Description: Disable interrupt */
7167 
7168 /* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */
7169 #define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
7170 #define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
7171 #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
7172 #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
7173 #define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */
7174 
7175 /* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */
7176 #define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
7177 #define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
7178 #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
7179 #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
7180 #define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */
7181 
7182 /* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */
7183 #define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
7184 #define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
7185 #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
7186 #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
7187 #define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */
7188 
7189 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
7190 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
7191 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
7192 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
7193 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
7194 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
7195 
7196 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
7197 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
7198 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
7199 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
7200 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
7201 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
7202 
7203 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
7204 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
7205 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
7206 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
7207 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7208 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
7209 
7210 /* Register: POWER_RESETREAS */
7211 /* Description: Reset reason */
7212 
7213 /* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */
7214 #define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */
7215 #define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
7216 #define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */
7217 #define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */
7218 
7219 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
7220 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
7221 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
7222 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
7223 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
7224 
7225 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
7226 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
7227 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
7228 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
7229 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
7230 
7231 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
7232 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
7233 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
7234 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
7235 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
7236 
7237 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
7238 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
7239 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
7240 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
7241 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
7242 
7243 /* Bit 3 : Reset from CPU lock-up detected */
7244 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
7245 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
7246 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
7247 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
7248 
7249 /* Bit 2 : Reset from soft reset detected */
7250 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
7251 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
7252 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
7253 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
7254 
7255 /* Bit 1 : Reset from watchdog detected */
7256 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
7257 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
7258 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
7259 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
7260 
7261 /* Bit 0 : Reset from pin-reset detected */
7262 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
7263 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
7264 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
7265 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
7266 
7267 /* Register: POWER_RAMSTATUS */
7268 /* Description: Deprecated register - RAM status register */
7269 
7270 /* Bit 3 : RAM block 3 is on or off/powering up */
7271 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
7272 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
7273 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
7274 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
7275 
7276 /* Bit 2 : RAM block 2 is on or off/powering up */
7277 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
7278 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
7279 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
7280 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
7281 
7282 /* Bit 1 : RAM block 1 is on or off/powering up */
7283 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
7284 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
7285 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
7286 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
7287 
7288 /* Bit 0 : RAM block 0 is on or off/powering up */
7289 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
7290 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
7291 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
7292 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
7293 
7294 /* Register: POWER_USBREGSTATUS */
7295 /* Description: USB supply status */
7296 
7297 /* Bit 1 : USB supply output settling time elapsed */
7298 #define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */
7299 #define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */
7300 #define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */
7301 #define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */
7302 
7303 /* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */
7304 #define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */
7305 #define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */
7306 #define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */
7307 #define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */
7308 
7309 /* Register: POWER_SYSTEMOFF */
7310 /* Description: System OFF register */
7311 
7312 /* Bit 0 : Enable System OFF mode */
7313 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
7314 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
7315 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
7316 
7317 /* Register: POWER_POFCON */
7318 /* Description: Power-fail comparator configuration */
7319 
7320 /* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */
7321 #define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */
7322 #define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */
7323 #define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */
7324 #define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */
7325 #define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */
7326 #define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */
7327 #define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */
7328 #define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */
7329 #define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */
7330 #define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */
7331 #define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */
7332 #define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */
7333 #define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */
7334 #define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */
7335 #define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */
7336 #define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */
7337 #define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */
7338 #define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */
7339 
7340 /* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */
7341 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
7342 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
7343 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
7344 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
7345 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
7346 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
7347 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
7348 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
7349 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
7350 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
7351 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
7352 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
7353 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
7354 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
7355 
7356 /* Bit 0 : Enable or disable power failure warning */
7357 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
7358 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
7359 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
7360 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
7361 
7362 /* Register: POWER_GPREGRET */
7363 /* Description: General purpose retention register */
7364 
7365 /* Bits 7..0 : General purpose retention register */
7366 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
7367 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
7368 
7369 /* Register: POWER_GPREGRET2 */
7370 /* Description: General purpose retention register */
7371 
7372 /* Bits 7..0 : General purpose retention register */
7373 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
7374 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
7375 
7376 /* Register: POWER_DCDCEN */
7377 /* Description: Enable DC/DC converter for REG1 stage */
7378 
7379 /* Bit 0 : Enable DC/DC converter for REG1 stage. */
7380 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
7381 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
7382 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
7383 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
7384 
7385 /* Register: POWER_DCDCEN0 */
7386 /* Description: Enable DC/DC converter for REG0 stage */
7387 
7388 /* Bit 0 : Enable DC/DC converter for REG0 stage. */
7389 #define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
7390 #define POWER_DCDCEN0_DCDCEN_Msk (0x1UL << POWER_DCDCEN0_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
7391 #define POWER_DCDCEN0_DCDCEN_Disabled (0UL) /*!< Disable */
7392 #define POWER_DCDCEN0_DCDCEN_Enabled (1UL) /*!< Enable */
7393 
7394 /* Register: POWER_MAINREGSTATUS */
7395 /* Description: Main supply status */
7396 
7397 /* Bit 0 : Main supply status */
7398 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */
7399 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */
7400 #define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */
7401 #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */
7402 
7403 /* Register: POWER_RAM_POWER */
7404 /* Description: Description cluster: RAMn power control register */
7405 
7406 /* Bit 31 : Keep retention on RAM section S15 when RAM section is off */
7407 #define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
7408 #define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
7409 #define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */
7410 #define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */
7411 
7412 /* Bit 30 : Keep retention on RAM section S14 when RAM section is off */
7413 #define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
7414 #define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
7415 #define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */
7416 #define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */
7417 
7418 /* Bit 29 : Keep retention on RAM section S13 when RAM section is off */
7419 #define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
7420 #define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
7421 #define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */
7422 #define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */
7423 
7424 /* Bit 28 : Keep retention on RAM section S12 when RAM section is off */
7425 #define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
7426 #define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
7427 #define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */
7428 #define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */
7429 
7430 /* Bit 27 : Keep retention on RAM section S11 when RAM section is off */
7431 #define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
7432 #define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
7433 #define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */
7434 #define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */
7435 
7436 /* Bit 26 : Keep retention on RAM section S10 when RAM section is off */
7437 #define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
7438 #define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
7439 #define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */
7440 #define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */
7441 
7442 /* Bit 25 : Keep retention on RAM section S9 when RAM section is off */
7443 #define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
7444 #define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
7445 #define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */
7446 #define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */
7447 
7448 /* Bit 24 : Keep retention on RAM section S8 when RAM section is off */
7449 #define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
7450 #define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
7451 #define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */
7452 #define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */
7453 
7454 /* Bit 23 : Keep retention on RAM section S7 when RAM section is off */
7455 #define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
7456 #define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
7457 #define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */
7458 #define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */
7459 
7460 /* Bit 22 : Keep retention on RAM section S6 when RAM section is off */
7461 #define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
7462 #define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
7463 #define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */
7464 #define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */
7465 
7466 /* Bit 21 : Keep retention on RAM section S5 when RAM section is off */
7467 #define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
7468 #define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
7469 #define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */
7470 #define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */
7471 
7472 /* Bit 20 : Keep retention on RAM section S4 when RAM section is off */
7473 #define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
7474 #define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
7475 #define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */
7476 #define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */
7477 
7478 /* Bit 19 : Keep retention on RAM section S3 when RAM section is off */
7479 #define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
7480 #define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
7481 #define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
7482 #define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
7483 
7484 /* Bit 18 : Keep retention on RAM section S2 when RAM section is off */
7485 #define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
7486 #define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
7487 #define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
7488 #define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
7489 
7490 /* Bit 17 : Keep retention on RAM section S1 when RAM section is off */
7491 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7492 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7493 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
7494 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
7495 
7496 /* Bit 16 : Keep retention on RAM section S0 when RAM section is off */
7497 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7498 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7499 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
7500 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
7501 
7502 /* Bit 15 : Keep RAM section S15 on or off in System ON mode. */
7503 #define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
7504 #define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
7505 #define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */
7506 #define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */
7507 
7508 /* Bit 14 : Keep RAM section S14 on or off in System ON mode. */
7509 #define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
7510 #define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
7511 #define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */
7512 #define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */
7513 
7514 /* Bit 13 : Keep RAM section S13 on or off in System ON mode. */
7515 #define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
7516 #define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
7517 #define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */
7518 #define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */
7519 
7520 /* Bit 12 : Keep RAM section S12 on or off in System ON mode. */
7521 #define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
7522 #define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
7523 #define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */
7524 #define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */
7525 
7526 /* Bit 11 : Keep RAM section S11 on or off in System ON mode. */
7527 #define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
7528 #define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
7529 #define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */
7530 #define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */
7531 
7532 /* Bit 10 : Keep RAM section S10 on or off in System ON mode. */
7533 #define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
7534 #define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
7535 #define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */
7536 #define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */
7537 
7538 /* Bit 9 : Keep RAM section S9 on or off in System ON mode. */
7539 #define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
7540 #define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
7541 #define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */
7542 #define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */
7543 
7544 /* Bit 8 : Keep RAM section S8 on or off in System ON mode. */
7545 #define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
7546 #define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
7547 #define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */
7548 #define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */
7549 
7550 /* Bit 7 : Keep RAM section S7 on or off in System ON mode. */
7551 #define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
7552 #define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
7553 #define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */
7554 #define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */
7555 
7556 /* Bit 6 : Keep RAM section S6 on or off in System ON mode. */
7557 #define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
7558 #define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
7559 #define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */
7560 #define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */
7561 
7562 /* Bit 5 : Keep RAM section S5 on or off in System ON mode. */
7563 #define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
7564 #define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
7565 #define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */
7566 #define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */
7567 
7568 /* Bit 4 : Keep RAM section S4 on or off in System ON mode. */
7569 #define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
7570 #define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
7571 #define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */
7572 #define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */
7573 
7574 /* Bit 3 : Keep RAM section S3 on or off in System ON mode. */
7575 #define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
7576 #define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
7577 #define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
7578 #define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */
7579 
7580 /* Bit 2 : Keep RAM section S2 on or off in System ON mode. */
7581 #define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
7582 #define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
7583 #define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
7584 #define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */
7585 
7586 /* Bit 1 : Keep RAM section S1 on or off in System ON mode. */
7587 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7588 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7589 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
7590 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
7591 
7592 /* Bit 0 : Keep RAM section S0 on or off in System ON mode. */
7593 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7594 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7595 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
7596 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
7597 
7598 /* Register: POWER_RAM_POWERSET */
7599 /* Description: Description cluster: RAMn power control set register */
7600 
7601 /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
7602 #define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
7603 #define POWER_RAM_POWERSET_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
7604 #define POWER_RAM_POWERSET_S15RETENTION_On (1UL) /*!< On */
7605 
7606 /* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
7607 #define POWER_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
7608 #define POWER_RAM_POWERSET_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
7609 #define POWER_RAM_POWERSET_S14RETENTION_On (1UL) /*!< On */
7610 
7611 /* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
7612 #define POWER_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
7613 #define POWER_RAM_POWERSET_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
7614 #define POWER_RAM_POWERSET_S13RETENTION_On (1UL) /*!< On */
7615 
7616 /* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
7617 #define POWER_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
7618 #define POWER_RAM_POWERSET_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
7619 #define POWER_RAM_POWERSET_S12RETENTION_On (1UL) /*!< On */
7620 
7621 /* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
7622 #define POWER_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
7623 #define POWER_RAM_POWERSET_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
7624 #define POWER_RAM_POWERSET_S11RETENTION_On (1UL) /*!< On */
7625 
7626 /* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
7627 #define POWER_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
7628 #define POWER_RAM_POWERSET_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
7629 #define POWER_RAM_POWERSET_S10RETENTION_On (1UL) /*!< On */
7630 
7631 /* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
7632 #define POWER_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
7633 #define POWER_RAM_POWERSET_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
7634 #define POWER_RAM_POWERSET_S9RETENTION_On (1UL) /*!< On */
7635 
7636 /* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
7637 #define POWER_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
7638 #define POWER_RAM_POWERSET_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
7639 #define POWER_RAM_POWERSET_S8RETENTION_On (1UL) /*!< On */
7640 
7641 /* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
7642 #define POWER_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
7643 #define POWER_RAM_POWERSET_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
7644 #define POWER_RAM_POWERSET_S7RETENTION_On (1UL) /*!< On */
7645 
7646 /* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
7647 #define POWER_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
7648 #define POWER_RAM_POWERSET_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
7649 #define POWER_RAM_POWERSET_S6RETENTION_On (1UL) /*!< On */
7650 
7651 /* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
7652 #define POWER_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
7653 #define POWER_RAM_POWERSET_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
7654 #define POWER_RAM_POWERSET_S5RETENTION_On (1UL) /*!< On */
7655 
7656 /* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
7657 #define POWER_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
7658 #define POWER_RAM_POWERSET_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
7659 #define POWER_RAM_POWERSET_S4RETENTION_On (1UL) /*!< On */
7660 
7661 /* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
7662 #define POWER_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
7663 #define POWER_RAM_POWERSET_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
7664 #define POWER_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
7665 
7666 /* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
7667 #define POWER_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
7668 #define POWER_RAM_POWERSET_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
7669 #define POWER_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
7670 
7671 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7672 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7673 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7674 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
7675 
7676 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7677 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7678 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7679 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
7680 
7681 /* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
7682 #define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
7683 #define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
7684 #define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */
7685 
7686 /* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
7687 #define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
7688 #define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
7689 #define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */
7690 
7691 /* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
7692 #define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
7693 #define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
7694 #define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */
7695 
7696 /* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
7697 #define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
7698 #define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
7699 #define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */
7700 
7701 /* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
7702 #define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
7703 #define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
7704 #define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */
7705 
7706 /* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
7707 #define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
7708 #define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
7709 #define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */
7710 
7711 /* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
7712 #define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
7713 #define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
7714 #define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */
7715 
7716 /* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
7717 #define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
7718 #define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
7719 #define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */
7720 
7721 /* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
7722 #define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
7723 #define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
7724 #define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */
7725 
7726 /* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
7727 #define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
7728 #define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
7729 #define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */
7730 
7731 /* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
7732 #define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
7733 #define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
7734 #define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */
7735 
7736 /* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
7737 #define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
7738 #define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
7739 #define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */
7740 
7741 /* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
7742 #define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
7743 #define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
7744 #define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
7745 
7746 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
7747 #define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
7748 #define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
7749 #define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
7750 
7751 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
7752 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7753 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7754 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
7755 
7756 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
7757 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7758 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7759 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
7760 
7761 /* Register: POWER_RAM_POWERCLR */
7762 /* Description: Description cluster: RAMn power control clear register */
7763 
7764 /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
7765 #define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
7766 #define POWER_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
7767 #define POWER_RAM_POWERCLR_S15RETENTION_Off (1UL) /*!< Off */
7768 
7769 /* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
7770 #define POWER_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
7771 #define POWER_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
7772 #define POWER_RAM_POWERCLR_S14RETENTION_Off (1UL) /*!< Off */
7773 
7774 /* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
7775 #define POWER_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
7776 #define POWER_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
7777 #define POWER_RAM_POWERCLR_S13RETENTION_Off (1UL) /*!< Off */
7778 
7779 /* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
7780 #define POWER_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
7781 #define POWER_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
7782 #define POWER_RAM_POWERCLR_S12RETENTION_Off (1UL) /*!< Off */
7783 
7784 /* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
7785 #define POWER_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
7786 #define POWER_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
7787 #define POWER_RAM_POWERCLR_S11RETENTION_Off (1UL) /*!< Off */
7788 
7789 /* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
7790 #define POWER_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
7791 #define POWER_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
7792 #define POWER_RAM_POWERCLR_S10RETENTION_Off (1UL) /*!< Off */
7793 
7794 /* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
7795 #define POWER_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
7796 #define POWER_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
7797 #define POWER_RAM_POWERCLR_S9RETENTION_Off (1UL) /*!< Off */
7798 
7799 /* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
7800 #define POWER_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
7801 #define POWER_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
7802 #define POWER_RAM_POWERCLR_S8RETENTION_Off (1UL) /*!< Off */
7803 
7804 /* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
7805 #define POWER_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
7806 #define POWER_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
7807 #define POWER_RAM_POWERCLR_S7RETENTION_Off (1UL) /*!< Off */
7808 
7809 /* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
7810 #define POWER_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
7811 #define POWER_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
7812 #define POWER_RAM_POWERCLR_S6RETENTION_Off (1UL) /*!< Off */
7813 
7814 /* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
7815 #define POWER_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
7816 #define POWER_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
7817 #define POWER_RAM_POWERCLR_S5RETENTION_Off (1UL) /*!< Off */
7818 
7819 /* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
7820 #define POWER_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
7821 #define POWER_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
7822 #define POWER_RAM_POWERCLR_S4RETENTION_Off (1UL) /*!< Off */
7823 
7824 /* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
7825 #define POWER_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
7826 #define POWER_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
7827 #define POWER_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
7828 
7829 /* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
7830 #define POWER_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
7831 #define POWER_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
7832 #define POWER_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
7833 
7834 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7835 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7836 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7837 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
7838 
7839 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7840 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7841 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7842 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
7843 
7844 /* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
7845 #define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
7846 #define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
7847 #define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */
7848 
7849 /* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
7850 #define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
7851 #define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
7852 #define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */
7853 
7854 /* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
7855 #define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
7856 #define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
7857 #define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */
7858 
7859 /* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
7860 #define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
7861 #define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
7862 #define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */
7863 
7864 /* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
7865 #define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
7866 #define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
7867 #define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */
7868 
7869 /* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
7870 #define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
7871 #define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
7872 #define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */
7873 
7874 /* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
7875 #define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
7876 #define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
7877 #define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */
7878 
7879 /* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
7880 #define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
7881 #define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
7882 #define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */
7883 
7884 /* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
7885 #define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
7886 #define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
7887 #define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */
7888 
7889 /* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
7890 #define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
7891 #define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
7892 #define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */
7893 
7894 /* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
7895 #define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
7896 #define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
7897 #define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */
7898 
7899 /* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
7900 #define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
7901 #define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
7902 #define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */
7903 
7904 /* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
7905 #define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
7906 #define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
7907 #define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
7908 
7909 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
7910 #define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
7911 #define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
7912 #define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
7913 
7914 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
7915 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7916 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7917 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
7918 
7919 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
7920 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7921 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7922 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
7923 
7924 
7925 /* Peripheral: PPI */
7926 /* Description: Programmable Peripheral Interconnect */
7927 
7928 /* Register: PPI_TASKS_CHG_EN */
7929 /* Description: Description cluster: Enable channel group n */
7930 
7931 /* Bit 0 : Enable channel group n */
7932 #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
7933 #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
7934 #define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
7935 
7936 /* Register: PPI_TASKS_CHG_DIS */
7937 /* Description: Description cluster: Disable channel group n */
7938 
7939 /* Bit 0 : Disable channel group n */
7940 #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
7941 #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
7942 #define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
7943 
7944 /* Register: PPI_CHEN */
7945 /* Description: Channel enable register */
7946 
7947 /* Bit 31 : Enable or disable channel 31 */
7948 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
7949 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
7950 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
7951 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
7952 
7953 /* Bit 30 : Enable or disable channel 30 */
7954 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
7955 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
7956 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
7957 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
7958 
7959 /* Bit 29 : Enable or disable channel 29 */
7960 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
7961 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
7962 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
7963 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
7964 
7965 /* Bit 28 : Enable or disable channel 28 */
7966 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
7967 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
7968 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
7969 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
7970 
7971 /* Bit 27 : Enable or disable channel 27 */
7972 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
7973 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
7974 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
7975 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
7976 
7977 /* Bit 26 : Enable or disable channel 26 */
7978 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
7979 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
7980 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
7981 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
7982 
7983 /* Bit 25 : Enable or disable channel 25 */
7984 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
7985 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
7986 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
7987 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
7988 
7989 /* Bit 24 : Enable or disable channel 24 */
7990 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
7991 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
7992 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
7993 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
7994 
7995 /* Bit 23 : Enable or disable channel 23 */
7996 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
7997 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
7998 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
7999 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
8000 
8001 /* Bit 22 : Enable or disable channel 22 */
8002 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
8003 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
8004 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
8005 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
8006 
8007 /* Bit 21 : Enable or disable channel 21 */
8008 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
8009 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
8010 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
8011 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
8012 
8013 /* Bit 20 : Enable or disable channel 20 */
8014 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
8015 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
8016 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
8017 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
8018 
8019 /* Bit 19 : Enable or disable channel 19 */
8020 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
8021 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
8022 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
8023 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
8024 
8025 /* Bit 18 : Enable or disable channel 18 */
8026 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
8027 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
8028 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
8029 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
8030 
8031 /* Bit 17 : Enable or disable channel 17 */
8032 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
8033 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
8034 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
8035 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
8036 
8037 /* Bit 16 : Enable or disable channel 16 */
8038 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
8039 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
8040 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
8041 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
8042 
8043 /* Bit 15 : Enable or disable channel 15 */
8044 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
8045 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
8046 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
8047 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
8048 
8049 /* Bit 14 : Enable or disable channel 14 */
8050 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
8051 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
8052 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
8053 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
8054 
8055 /* Bit 13 : Enable or disable channel 13 */
8056 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
8057 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
8058 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
8059 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
8060 
8061 /* Bit 12 : Enable or disable channel 12 */
8062 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
8063 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
8064 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
8065 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
8066 
8067 /* Bit 11 : Enable or disable channel 11 */
8068 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
8069 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
8070 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
8071 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
8072 
8073 /* Bit 10 : Enable or disable channel 10 */
8074 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
8075 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
8076 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
8077 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
8078 
8079 /* Bit 9 : Enable or disable channel 9 */
8080 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
8081 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
8082 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
8083 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
8084 
8085 /* Bit 8 : Enable or disable channel 8 */
8086 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
8087 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
8088 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
8089 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
8090 
8091 /* Bit 7 : Enable or disable channel 7 */
8092 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
8093 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
8094 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
8095 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
8096 
8097 /* Bit 6 : Enable or disable channel 6 */
8098 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
8099 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
8100 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
8101 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
8102 
8103 /* Bit 5 : Enable or disable channel 5 */
8104 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
8105 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
8106 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
8107 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
8108 
8109 /* Bit 4 : Enable or disable channel 4 */
8110 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
8111 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
8112 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
8113 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
8114 
8115 /* Bit 3 : Enable or disable channel 3 */
8116 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
8117 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
8118 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
8119 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
8120 
8121 /* Bit 2 : Enable or disable channel 2 */
8122 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
8123 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
8124 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
8125 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
8126 
8127 /* Bit 1 : Enable or disable channel 1 */
8128 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
8129 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
8130 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
8131 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
8132 
8133 /* Bit 0 : Enable or disable channel 0 */
8134 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
8135 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
8136 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
8137 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
8138 
8139 /* Register: PPI_CHENSET */
8140 /* Description: Channel enable set register */
8141 
8142 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect. */
8143 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
8144 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
8145 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
8146 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
8147 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
8148 
8149 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect. */
8150 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
8151 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
8152 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
8153 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
8154 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
8155 
8156 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect. */
8157 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
8158 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
8159 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
8160 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
8161 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
8162 
8163 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect. */
8164 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
8165 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
8166 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
8167 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
8168 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
8169 
8170 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect. */
8171 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
8172 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
8173 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
8174 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
8175 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
8176 
8177 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect. */
8178 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
8179 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
8180 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
8181 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
8182 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
8183 
8184 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect. */
8185 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
8186 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
8187 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
8188 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
8189 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
8190 
8191 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect. */
8192 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
8193 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
8194 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
8195 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
8196 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
8197 
8198 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect. */
8199 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
8200 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
8201 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
8202 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
8203 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
8204 
8205 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect. */
8206 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
8207 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
8208 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
8209 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
8210 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
8211 
8212 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect. */
8213 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
8214 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
8215 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
8216 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
8217 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
8218 
8219 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect. */
8220 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
8221 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
8222 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
8223 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
8224 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
8225 
8226 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect. */
8227 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
8228 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
8229 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
8230 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
8231 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
8232 
8233 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect. */
8234 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
8235 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
8236 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
8237 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
8238 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
8239 
8240 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect. */
8241 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
8242 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
8243 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
8244 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
8245 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
8246 
8247 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect. */
8248 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
8249 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
8250 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
8251 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
8252 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
8253 
8254 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect. */
8255 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
8256 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
8257 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
8258 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
8259 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
8260 
8261 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect. */
8262 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
8263 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
8264 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
8265 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
8266 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
8267 
8268 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect. */
8269 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
8270 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
8271 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
8272 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
8273 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
8274 
8275 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect. */
8276 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
8277 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
8278 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
8279 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
8280 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
8281 
8282 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect. */
8283 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
8284 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
8285 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
8286 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
8287 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
8288 
8289 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect. */
8290 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
8291 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
8292 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
8293 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
8294 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
8295 
8296 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect. */
8297 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
8298 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
8299 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
8300 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
8301 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
8302 
8303 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect. */
8304 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
8305 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
8306 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
8307 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
8308 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
8309 
8310 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect. */
8311 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
8312 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
8313 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
8314 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
8315 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
8316 
8317 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect. */
8318 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
8319 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
8320 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
8321 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
8322 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
8323 
8324 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect. */
8325 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
8326 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
8327 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
8328 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
8329 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
8330 
8331 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect. */
8332 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
8333 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
8334 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
8335 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
8336 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
8337 
8338 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect. */
8339 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
8340 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
8341 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
8342 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
8343 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
8344 
8345 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect. */
8346 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
8347 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
8348 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
8349 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
8350 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
8351 
8352 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect. */
8353 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
8354 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
8355 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
8356 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
8357 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
8358 
8359 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect. */
8360 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
8361 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
8362 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
8363 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
8364 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
8365 
8366 /* Register: PPI_CHENCLR */
8367 /* Description: Channel enable clear register */
8368 
8369 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect. */
8370 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
8371 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
8372 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
8373 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
8374 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
8375 
8376 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect. */
8377 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
8378 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
8379 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
8380 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
8381 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
8382 
8383 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect. */
8384 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
8385 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
8386 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
8387 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
8388 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
8389 
8390 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect. */
8391 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
8392 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
8393 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
8394 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
8395 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
8396 
8397 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect. */
8398 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
8399 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
8400 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
8401 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
8402 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
8403 
8404 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect. */
8405 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
8406 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
8407 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
8408 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
8409 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
8410 
8411 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect. */
8412 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
8413 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
8414 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
8415 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
8416 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
8417 
8418 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect. */
8419 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
8420 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
8421 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
8422 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
8423 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
8424 
8425 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect. */
8426 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
8427 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
8428 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
8429 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
8430 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
8431 
8432 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect. */
8433 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
8434 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
8435 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
8436 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
8437 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
8438 
8439 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect. */
8440 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
8441 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
8442 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
8443 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
8444 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
8445 
8446 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect. */
8447 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
8448 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
8449 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
8450 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
8451 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
8452 
8453 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect. */
8454 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
8455 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
8456 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
8457 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
8458 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
8459 
8460 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect. */
8461 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
8462 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
8463 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
8464 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
8465 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
8466 
8467 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect. */
8468 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
8469 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
8470 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
8471 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
8472 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
8473 
8474 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect. */
8475 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
8476 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
8477 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
8478 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
8479 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
8480 
8481 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect. */
8482 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
8483 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
8484 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
8485 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
8486 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
8487 
8488 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect. */
8489 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
8490 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
8491 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
8492 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
8493 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
8494 
8495 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect. */
8496 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
8497 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
8498 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
8499 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
8500 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
8501 
8502 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect. */
8503 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
8504 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
8505 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
8506 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
8507 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
8508 
8509 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect. */
8510 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
8511 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
8512 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
8513 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
8514 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
8515 
8516 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect. */
8517 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
8518 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
8519 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
8520 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
8521 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
8522 
8523 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect. */
8524 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
8525 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
8526 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
8527 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
8528 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
8529 
8530 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect. */
8531 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
8532 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
8533 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
8534 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
8535 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
8536 
8537 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect. */
8538 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
8539 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
8540 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
8541 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
8542 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
8543 
8544 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect. */
8545 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
8546 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
8547 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
8548 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
8549 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
8550 
8551 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect. */
8552 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
8553 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
8554 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
8555 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
8556 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
8557 
8558 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect. */
8559 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
8560 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
8561 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
8562 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
8563 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
8564 
8565 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect. */
8566 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
8567 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
8568 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
8569 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
8570 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
8571 
8572 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect. */
8573 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
8574 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
8575 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
8576 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
8577 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
8578 
8579 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect. */
8580 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
8581 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
8582 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
8583 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
8584 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
8585 
8586 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect. */
8587 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
8588 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
8589 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
8590 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
8591 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
8592 
8593 /* Register: PPI_CH_EEP */
8594 /* Description: Description cluster: Channel n event endpoint */
8595 
8596 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
8597 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
8598 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
8599 
8600 /* Register: PPI_CH_TEP */
8601 /* Description: Description cluster: Channel n task endpoint */
8602 
8603 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
8604 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
8605 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
8606 
8607 /* Register: PPI_CHG */
8608 /* Description: Description collection: Channel group n */
8609 
8610 /* Bit 31 : Include or exclude channel 31 */
8611 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
8612 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
8613 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
8614 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
8615 
8616 /* Bit 30 : Include or exclude channel 30 */
8617 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
8618 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
8619 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
8620 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
8621 
8622 /* Bit 29 : Include or exclude channel 29 */
8623 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
8624 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
8625 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
8626 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
8627 
8628 /* Bit 28 : Include or exclude channel 28 */
8629 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
8630 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
8631 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
8632 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
8633 
8634 /* Bit 27 : Include or exclude channel 27 */
8635 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
8636 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
8637 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
8638 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
8639 
8640 /* Bit 26 : Include or exclude channel 26 */
8641 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
8642 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
8643 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
8644 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
8645 
8646 /* Bit 25 : Include or exclude channel 25 */
8647 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
8648 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
8649 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
8650 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
8651 
8652 /* Bit 24 : Include or exclude channel 24 */
8653 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
8654 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
8655 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
8656 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
8657 
8658 /* Bit 23 : Include or exclude channel 23 */
8659 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
8660 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
8661 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
8662 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
8663 
8664 /* Bit 22 : Include or exclude channel 22 */
8665 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
8666 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
8667 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
8668 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
8669 
8670 /* Bit 21 : Include or exclude channel 21 */
8671 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
8672 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
8673 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
8674 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
8675 
8676 /* Bit 20 : Include or exclude channel 20 */
8677 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
8678 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
8679 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
8680 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
8681 
8682 /* Bit 19 : Include or exclude channel 19 */
8683 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
8684 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
8685 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
8686 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
8687 
8688 /* Bit 18 : Include or exclude channel 18 */
8689 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
8690 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
8691 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
8692 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
8693 
8694 /* Bit 17 : Include or exclude channel 17 */
8695 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
8696 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
8697 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
8698 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
8699 
8700 /* Bit 16 : Include or exclude channel 16 */
8701 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
8702 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
8703 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
8704 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
8705 
8706 /* Bit 15 : Include or exclude channel 15 */
8707 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
8708 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
8709 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
8710 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
8711 
8712 /* Bit 14 : Include or exclude channel 14 */
8713 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
8714 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
8715 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
8716 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
8717 
8718 /* Bit 13 : Include or exclude channel 13 */
8719 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
8720 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
8721 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
8722 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
8723 
8724 /* Bit 12 : Include or exclude channel 12 */
8725 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
8726 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
8727 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
8728 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
8729 
8730 /* Bit 11 : Include or exclude channel 11 */
8731 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
8732 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
8733 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
8734 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
8735 
8736 /* Bit 10 : Include or exclude channel 10 */
8737 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
8738 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
8739 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
8740 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
8741 
8742 /* Bit 9 : Include or exclude channel 9 */
8743 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
8744 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
8745 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
8746 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
8747 
8748 /* Bit 8 : Include or exclude channel 8 */
8749 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
8750 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
8751 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
8752 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
8753 
8754 /* Bit 7 : Include or exclude channel 7 */
8755 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
8756 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
8757 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
8758 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
8759 
8760 /* Bit 6 : Include or exclude channel 6 */
8761 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
8762 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
8763 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
8764 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
8765 
8766 /* Bit 5 : Include or exclude channel 5 */
8767 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
8768 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
8769 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
8770 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
8771 
8772 /* Bit 4 : Include or exclude channel 4 */
8773 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
8774 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
8775 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
8776 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
8777 
8778 /* Bit 3 : Include or exclude channel 3 */
8779 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
8780 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
8781 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
8782 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
8783 
8784 /* Bit 2 : Include or exclude channel 2 */
8785 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
8786 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
8787 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
8788 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
8789 
8790 /* Bit 1 : Include or exclude channel 1 */
8791 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
8792 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
8793 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
8794 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
8795 
8796 /* Bit 0 : Include or exclude channel 0 */
8797 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
8798 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
8799 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
8800 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
8801 
8802 /* Register: PPI_FORK_TEP */
8803 /* Description: Description cluster: Channel n task endpoint */
8804 
8805 /* Bits 31..0 : Pointer to task register */
8806 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
8807 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
8808 
8809 
8810 /* Peripheral: PWM */
8811 /* Description: Pulse width modulation unit 0 */
8812 
8813 /* Register: PWM_TASKS_STOP */
8814 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
8815 
8816 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
8817 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8818 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8819 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8820 
8821 /* Register: PWM_TASKS_SEQSTART */
8822 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
8823 
8824 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
8825 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
8826 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
8827 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
8828 
8829 /* Register: PWM_TASKS_NEXTSTEP */
8830 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
8831 
8832 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
8833 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
8834 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
8835 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
8836 
8837 /* Register: PWM_EVENTS_STOPPED */
8838 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
8839 
8840 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
8841 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8842 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8843 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8844 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8845 
8846 /* Register: PWM_EVENTS_SEQSTARTED */
8847 /* Description: Description collection: First PWM period started on sequence n */
8848 
8849 /* Bit 0 : First PWM period started on sequence n */
8850 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
8851 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
8852 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
8853 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
8854 
8855 /* Register: PWM_EVENTS_SEQEND */
8856 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
8857 
8858 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
8859 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
8860 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
8861 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
8862 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
8863 
8864 /* Register: PWM_EVENTS_PWMPERIODEND */
8865 /* Description: Emitted at the end of each PWM period */
8866 
8867 /* Bit 0 : Emitted at the end of each PWM period */
8868 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
8869 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
8870 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
8871 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
8872 
8873 /* Register: PWM_EVENTS_LOOPSDONE */
8874 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
8875 
8876 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
8877 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
8878 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
8879 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
8880 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
8881 
8882 /* Register: PWM_SHORTS */
8883 /* Description: Shortcuts between local events and tasks */
8884 
8885 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
8886 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
8887 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
8888 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
8889 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
8890 
8891 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
8892 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
8893 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
8894 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
8895 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
8896 
8897 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
8898 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
8899 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
8900 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
8901 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
8902 
8903 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
8904 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
8905 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
8906 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
8907 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
8908 
8909 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
8910 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
8911 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
8912 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
8913 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
8914 
8915 /* Register: PWM_INTEN */
8916 /* Description: Enable or disable interrupt */
8917 
8918 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
8919 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8920 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8921 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
8922 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
8923 
8924 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
8925 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8926 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8927 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
8928 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
8929 
8930 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
8931 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8932 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8933 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
8934 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
8935 
8936 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
8937 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8938 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8939 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
8940 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
8941 
8942 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
8943 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8944 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8945 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
8946 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
8947 
8948 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
8949 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8950 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8951 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
8952 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
8953 
8954 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8955 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8956 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8957 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8958 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8959 
8960 /* Register: PWM_INTENSET */
8961 /* Description: Enable interrupt */
8962 
8963 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
8964 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8965 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8966 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8967 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8968 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
8969 
8970 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
8971 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8972 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8973 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8974 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8975 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
8976 
8977 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
8978 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8979 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8980 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8981 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8982 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
8983 
8984 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
8985 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8986 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8987 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8988 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8989 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
8990 
8991 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
8992 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8993 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8994 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8995 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8996 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
8997 
8998 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
8999 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
9000 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
9001 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
9002 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
9003 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
9004 
9005 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9006 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9007 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9008 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9009 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9010 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9011 
9012 /* Register: PWM_INTENCLR */
9013 /* Description: Disable interrupt */
9014 
9015 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
9016 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
9017 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
9018 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
9019 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
9020 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
9021 
9022 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
9023 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
9024 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
9025 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
9026 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
9027 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
9028 
9029 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
9030 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
9031 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
9032 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
9033 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
9034 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
9035 
9036 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
9037 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
9038 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
9039 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
9040 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
9041 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
9042 
9043 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
9044 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
9045 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
9046 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
9047 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
9048 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
9049 
9050 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
9051 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
9052 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
9053 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
9054 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
9055 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
9056 
9057 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9058 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9059 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9060 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9061 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9062 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9063 
9064 /* Register: PWM_ENABLE */
9065 /* Description: PWM module enable register */
9066 
9067 /* Bit 0 : Enable or disable PWM module */
9068 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9069 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9070 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
9071 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
9072 
9073 /* Register: PWM_MODE */
9074 /* Description: Selects operating mode of the wave counter */
9075 
9076 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
9077 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
9078 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
9079 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
9080 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
9081 
9082 /* Register: PWM_COUNTERTOP */
9083 /* Description: Value up to which the pulse generator counter counts */
9084 
9085 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
9086 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
9087 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
9088 
9089 /* Register: PWM_PRESCALER */
9090 /* Description: Configuration for PWM_CLK */
9091 
9092 /* Bits 2..0 : Prescaler of PWM_CLK */
9093 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
9094 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
9095 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */
9096 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
9097 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
9098 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
9099 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */
9100 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */
9101 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */
9102 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */
9103 
9104 /* Register: PWM_DECODER */
9105 /* Description: Configuration of the decoder */
9106 
9107 /* Bit 8 : Selects source for advancing the active sequence */
9108 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
9109 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
9110 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
9111 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
9112 
9113 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
9114 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
9115 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
9116 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
9117 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
9118 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
9119 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
9120 
9121 /* Register: PWM_LOOP */
9122 /* Description: Number of playbacks of a loop */
9123 
9124 /* Bits 15..0 : Number of playbacks of pattern cycles */
9125 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
9126 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
9127 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
9128 
9129 /* Register: PWM_SEQ_PTR */
9130 /* Description: Description cluster: Beginning address in RAM of this sequence */
9131 
9132 /* Bits 31..0 : Beginning address in RAM of this sequence */
9133 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9134 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9135 
9136 /* Register: PWM_SEQ_CNT */
9137 /* Description: Description cluster: Number of values (duty cycles) in this sequence */
9138 
9139 /* Bits 14..0 : Number of values (duty cycles) in this sequence */
9140 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
9141 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
9142 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
9143 
9144 /* Register: PWM_SEQ_REFRESH */
9145 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
9146 
9147 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
9148 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
9149 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
9150 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
9151 
9152 /* Register: PWM_SEQ_ENDDELAY */
9153 /* Description: Description cluster: Time added after the sequence */
9154 
9155 /* Bits 23..0 : Time added after the sequence in PWM periods */
9156 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
9157 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
9158 
9159 /* Register: PWM_PSEL_OUT */
9160 /* Description: Description collection: Output pin select for PWM channel n */
9161 
9162 /* Bit 31 : Connection */
9163 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9164 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9165 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
9166 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
9167 
9168 /* Bit 5 : Port number */
9169 #define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */
9170 #define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */
9171 
9172 /* Bits 4..0 : Pin number */
9173 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
9174 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
9175 
9176 
9177 /* Peripheral: QDEC */
9178 /* Description: Quadrature Decoder */
9179 
9180 /* Register: QDEC_TASKS_START */
9181 /* Description: Task starting the quadrature decoder */
9182 
9183 /* Bit 0 : Task starting the quadrature decoder */
9184 #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
9185 #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
9186 #define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
9187 
9188 /* Register: QDEC_TASKS_STOP */
9189 /* Description: Task stopping the quadrature decoder */
9190 
9191 /* Bit 0 : Task stopping the quadrature decoder */
9192 #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9193 #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9194 #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9195 
9196 /* Register: QDEC_TASKS_READCLRACC */
9197 /* Description: Read and clear ACC and ACCDBL */
9198 
9199 /* Bit 0 : Read and clear ACC and ACCDBL */
9200 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
9201 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
9202 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */
9203 
9204 /* Register: QDEC_TASKS_RDCLRACC */
9205 /* Description: Read and clear ACC */
9206 
9207 /* Bit 0 : Read and clear ACC */
9208 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
9209 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
9210 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */
9211 
9212 /* Register: QDEC_TASKS_RDCLRDBL */
9213 /* Description: Read and clear ACCDBL */
9214 
9215 /* Bit 0 : Read and clear ACCDBL */
9216 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
9217 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
9218 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */
9219 
9220 /* Register: QDEC_EVENTS_SAMPLERDY */
9221 /* Description: Event being generated for every new sample value written to the SAMPLE register */
9222 
9223 /* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
9224 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
9225 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
9226 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */
9227 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */
9228 
9229 /* Register: QDEC_EVENTS_REPORTRDY */
9230 /* Description: Non-null report ready */
9231 
9232 /* Bit 0 : Non-null report ready */
9233 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
9234 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
9235 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */
9236 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */
9237 
9238 /* Register: QDEC_EVENTS_ACCOF */
9239 /* Description: ACC or ACCDBL register overflow */
9240 
9241 /* Bit 0 : ACC or ACCDBL register overflow */
9242 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
9243 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
9244 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */
9245 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */
9246 
9247 /* Register: QDEC_EVENTS_DBLRDY */
9248 /* Description: Double displacement(s) detected */
9249 
9250 /* Bit 0 : Double displacement(s) detected */
9251 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
9252 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
9253 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */
9254 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */
9255 
9256 /* Register: QDEC_EVENTS_STOPPED */
9257 /* Description: QDEC has been stopped */
9258 
9259 /* Bit 0 : QDEC has been stopped */
9260 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9261 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9262 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9263 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9264 
9265 /* Register: QDEC_SHORTS */
9266 /* Description: Shortcuts between local events and tasks */
9267 
9268 /* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
9269 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
9270 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
9271 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9272 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9273 
9274 /* Bit 5 : Shortcut between event DBLRDY and task STOP */
9275 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
9276 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
9277 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9278 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9279 
9280 /* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
9281 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
9282 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
9283 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
9284 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
9285 
9286 /* Bit 3 : Shortcut between event REPORTRDY and task STOP */
9287 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
9288 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
9289 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9290 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9291 
9292 /* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
9293 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
9294 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
9295 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
9296 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
9297 
9298 /* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
9299 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
9300 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
9301 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9302 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9303 
9304 /* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
9305 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
9306 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
9307 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9308 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9309 
9310 /* Register: QDEC_INTENSET */
9311 /* Description: Enable interrupt */
9312 
9313 /* Bit 4 : Write '1' to enable interrupt for event STOPPED */
9314 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
9315 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9316 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9317 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9318 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9319 
9320 /* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
9321 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
9322 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
9323 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9324 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9325 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
9326 
9327 /* Bit 2 : Write '1' to enable interrupt for event ACCOF */
9328 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9329 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
9330 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9331 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9332 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
9333 
9334 /* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
9335 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
9336 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
9337 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9338 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9339 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
9340 
9341 /* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
9342 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
9343 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
9344 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9345 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9346 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
9347 
9348 /* Register: QDEC_INTENCLR */
9349 /* Description: Disable interrupt */
9350 
9351 /* Bit 4 : Write '1' to disable interrupt for event STOPPED */
9352 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
9353 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9354 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9355 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9356 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9357 
9358 /* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
9359 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
9360 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
9361 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9362 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9363 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
9364 
9365 /* Bit 2 : Write '1' to disable interrupt for event ACCOF */
9366 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9367 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
9368 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9369 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9370 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
9371 
9372 /* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
9373 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
9374 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
9375 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9376 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9377 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
9378 
9379 /* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
9380 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
9381 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
9382 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9383 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9384 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
9385 
9386 /* Register: QDEC_ENABLE */
9387 /* Description: Enable the quadrature decoder */
9388 
9389 /* Bit 0 : Enable or disable the quadrature decoder */
9390 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9391 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9392 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
9393 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
9394 
9395 /* Register: QDEC_LEDPOL */
9396 /* Description: LED output pin polarity */
9397 
9398 /* Bit 0 : LED output pin polarity */
9399 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
9400 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
9401 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
9402 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
9403 
9404 /* Register: QDEC_SAMPLEPER */
9405 /* Description: Sample period */
9406 
9407 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
9408 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
9409 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
9410 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
9411 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
9412 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
9413 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
9414 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
9415 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
9416 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
9417 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
9418 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
9419 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
9420 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
9421 
9422 /* Register: QDEC_SAMPLE */
9423 /* Description: Motion sample value */
9424 
9425 /* Bits 31..0 : Last motion sample */
9426 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
9427 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
9428 
9429 /* Register: QDEC_REPORTPER */
9430 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
9431 
9432 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */
9433 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
9434 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
9435 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */
9436 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */
9437 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */
9438 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */
9439 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */
9440 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */
9441 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */
9442 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */
9443 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */
9444 
9445 /* Register: QDEC_ACC */
9446 /* Description: Register accumulating the valid transitions */
9447 
9448 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */
9449 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
9450 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
9451 
9452 /* Register: QDEC_ACCREAD */
9453 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
9454 
9455 /* Bits 31..0 : Snapshot of the ACC register. */
9456 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
9457 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
9458 
9459 /* Register: QDEC_PSEL_LED */
9460 /* Description: Pin select for LED signal */
9461 
9462 /* Bit 31 : Connection */
9463 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9464 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9465 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
9466 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
9467 
9468 /* Bit 5 : Port number */
9469 #define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */
9470 #define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */
9471 
9472 /* Bits 4..0 : Pin number */
9473 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
9474 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
9475 
9476 /* Register: QDEC_PSEL_A */
9477 /* Description: Pin select for A signal */
9478 
9479 /* Bit 31 : Connection */
9480 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9481 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9482 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
9483 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
9484 
9485 /* Bit 5 : Port number */
9486 #define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */
9487 #define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */
9488 
9489 /* Bits 4..0 : Pin number */
9490 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
9491 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
9492 
9493 /* Register: QDEC_PSEL_B */
9494 /* Description: Pin select for B signal */
9495 
9496 /* Bit 31 : Connection */
9497 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9498 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9499 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
9500 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
9501 
9502 /* Bit 5 : Port number */
9503 #define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */
9504 #define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */
9505 
9506 /* Bits 4..0 : Pin number */
9507 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
9508 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
9509 
9510 /* Register: QDEC_DBFEN */
9511 /* Description: Enable input debounce filters */
9512 
9513 /* Bit 0 : Enable input debounce filters */
9514 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
9515 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
9516 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
9517 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
9518 
9519 /* Register: QDEC_LEDPRE */
9520 /* Description: Time period the LED is switched ON prior to sampling */
9521 
9522 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
9523 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
9524 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
9525 
9526 /* Register: QDEC_ACCDBL */
9527 /* Description: Register accumulating the number of detected double transitions */
9528 
9529 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
9530 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
9531 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
9532 
9533 /* Register: QDEC_ACCDBLREAD */
9534 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
9535 
9536 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
9537 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
9538 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
9539 
9540 
9541 /* Peripheral: QSPI */
9542 /* Description: External flash interface */
9543 
9544 /* Register: QSPI_TASKS_ACTIVATE */
9545 /* Description: Activate QSPI interface */
9546 
9547 /* Bit 0 : Activate QSPI interface */
9548 #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
9549 #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
9550 #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */
9551 
9552 /* Register: QSPI_TASKS_READSTART */
9553 /* Description: Start transfer from external flash memory to internal RAM */
9554 
9555 /* Bit 0 : Start transfer from external flash memory to internal RAM */
9556 #define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */
9557 #define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */
9558 #define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (1UL) /*!< Trigger task */
9559 
9560 /* Register: QSPI_TASKS_WRITESTART */
9561 /* Description: Start transfer from internal RAM to external flash memory */
9562 
9563 /* Bit 0 : Start transfer from internal RAM to external flash memory */
9564 #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */
9565 #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */
9566 #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (1UL) /*!< Trigger task */
9567 
9568 /* Register: QSPI_TASKS_ERASESTART */
9569 /* Description: Start external flash memory erase operation */
9570 
9571 /* Bit 0 : Start external flash memory erase operation */
9572 #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */
9573 #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */
9574 #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (1UL) /*!< Trigger task */
9575 
9576 /* Register: QSPI_TASKS_DEACTIVATE */
9577 /* Description: Deactivate QSPI interface */
9578 
9579 /* Bit 0 : Deactivate QSPI interface */
9580 #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */
9581 #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */
9582 #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (1UL) /*!< Trigger task */
9583 
9584 /* Register: QSPI_EVENTS_READY */
9585 /* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */
9586 
9587 /* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */
9588 #define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
9589 #define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
9590 #define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
9591 #define QSPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
9592 
9593 /* Register: QSPI_INTEN */
9594 /* Description: Enable or disable interrupt */
9595 
9596 /* Bit 0 : Enable or disable interrupt for event READY */
9597 #define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
9598 #define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */
9599 #define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */
9600 #define QSPI_INTEN_READY_Enabled (1UL) /*!< Enable */
9601 
9602 /* Register: QSPI_INTENSET */
9603 /* Description: Enable interrupt */
9604 
9605 /* Bit 0 : Write '1' to enable interrupt for event READY */
9606 #define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
9607 #define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
9608 #define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
9609 #define QSPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
9610 #define QSPI_INTENSET_READY_Set (1UL) /*!< Enable */
9611 
9612 /* Register: QSPI_INTENCLR */
9613 /* Description: Disable interrupt */
9614 
9615 /* Bit 0 : Write '1' to disable interrupt for event READY */
9616 #define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
9617 #define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
9618 #define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
9619 #define QSPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
9620 #define QSPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
9621 
9622 /* Register: QSPI_ENABLE */
9623 /* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */
9624 
9625 /* Bit 0 : Enable or disable QSPI */
9626 #define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9627 #define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9628 #define QSPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable QSPI */
9629 #define QSPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QSPI */
9630 
9631 /* Register: QSPI_READ_SRC */
9632 /* Description: Flash memory source address */
9633 
9634 /* Bits 31..0 : Word-aligned flash memory source address. */
9635 #define QSPI_READ_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
9636 #define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
9637 
9638 /* Register: QSPI_READ_DST */
9639 /* Description: RAM destination address */
9640 
9641 /* Bits 31..0 : Word-aligned RAM destination address. */
9642 #define QSPI_READ_DST_DST_Pos (0UL) /*!< Position of DST field. */
9643 #define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos) /*!< Bit mask of DST field. */
9644 
9645 /* Register: QSPI_READ_CNT */
9646 /* Description: Read transfer length */
9647 
9648 /* Bits 17..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */
9649 #define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
9650 #define QSPI_READ_CNT_CNT_Msk (0x3FFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
9651 
9652 /* Register: QSPI_WRITE_DST */
9653 /* Description: Flash destination address */
9654 
9655 /* Bits 31..0 : Word-aligned flash destination address. */
9656 #define QSPI_WRITE_DST_DST_Pos (0UL) /*!< Position of DST field. */
9657 #define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos) /*!< Bit mask of DST field. */
9658 
9659 /* Register: QSPI_WRITE_SRC */
9660 /* Description: RAM source address */
9661 
9662 /* Bits 31..0 : Word-aligned RAM source address. */
9663 #define QSPI_WRITE_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
9664 #define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
9665 
9666 /* Register: QSPI_WRITE_CNT */
9667 /* Description: Write transfer length */
9668 
9669 /* Bits 17..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */
9670 #define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
9671 #define QSPI_WRITE_CNT_CNT_Msk (0x3FFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
9672 
9673 /* Register: QSPI_ERASE_PTR */
9674 /* Description: Start address of flash block to be erased */
9675 
9676 /* Bits 31..0 : Word-aligned start address of block to be erased. */
9677 #define QSPI_ERASE_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9678 #define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9679 
9680 /* Register: QSPI_ERASE_LEN */
9681 /* Description: Size of block to be erased. */
9682 
9683 /* Bits 1..0 : LEN */
9684 #define QSPI_ERASE_LEN_LEN_Pos (0UL) /*!< Position of LEN field. */
9685 #define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos) /*!< Bit mask of LEN field. */
9686 #define QSPI_ERASE_LEN_LEN_4KB (0UL) /*!< Erase 4 kB block (flash command 0x20) */
9687 #define QSPI_ERASE_LEN_LEN_64KB (1UL) /*!< Erase 64 kB block (flash command 0xD8) */
9688 #define QSPI_ERASE_LEN_LEN_All (2UL) /*!< Erase all (flash command 0xC7) */
9689 
9690 /* Register: QSPI_PSEL_SCK */
9691 /* Description: Pin select for serial clock SCK */
9692 
9693 /* Bit 31 : Connection */
9694 #define QSPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9695 #define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9696 #define QSPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
9697 #define QSPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
9698 
9699 /* Bit 5 : Port number */
9700 #define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
9701 #define QSPI_PSEL_SCK_PORT_Msk (0x1UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
9702 
9703 /* Bits 4..0 : Pin number */
9704 #define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
9705 #define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
9706 
9707 /* Register: QSPI_PSEL_CSN */
9708 /* Description: Pin select for chip select signal CSN. */
9709 
9710 /* Bit 31 : Connection */
9711 #define QSPI_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9712 #define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9713 #define QSPI_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
9714 #define QSPI_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
9715 
9716 /* Bit 5 : Port number */
9717 #define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
9718 #define QSPI_PSEL_CSN_PORT_Msk (0x1UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
9719 
9720 /* Bits 4..0 : Pin number */
9721 #define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
9722 #define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
9723 
9724 /* Register: QSPI_PSEL_IO0 */
9725 /* Description: Pin select for serial data MOSI/IO0. */
9726 
9727 /* Bit 31 : Connection */
9728 #define QSPI_PSEL_IO0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9729 #define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9730 #define QSPI_PSEL_IO0_CONNECT_Connected (0UL) /*!< Connect */
9731 #define QSPI_PSEL_IO0_CONNECT_Disconnected (1UL) /*!< Disconnect */
9732 
9733 /* Bit 5 : Port number */
9734 #define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */
9735 #define QSPI_PSEL_IO0_PORT_Msk (0x1UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */
9736 
9737 /* Bits 4..0 : Pin number */
9738 #define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */
9739 #define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos) /*!< Bit mask of PIN field. */
9740 
9741 /* Register: QSPI_PSEL_IO1 */
9742 /* Description: Pin select for serial data MISO/IO1. */
9743 
9744 /* Bit 31 : Connection */
9745 #define QSPI_PSEL_IO1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9746 #define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9747 #define QSPI_PSEL_IO1_CONNECT_Connected (0UL) /*!< Connect */
9748 #define QSPI_PSEL_IO1_CONNECT_Disconnected (1UL) /*!< Disconnect */
9749 
9750 /* Bit 5 : Port number */
9751 #define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */
9752 #define QSPI_PSEL_IO1_PORT_Msk (0x1UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */
9753 
9754 /* Bits 4..0 : Pin number */
9755 #define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */
9756 #define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */
9757 
9758 /* Register: QSPI_PSEL_IO2 */
9759 /* Description: Pin select for serial data IO2. */
9760 
9761 /* Bit 31 : Connection */
9762 #define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9763 #define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9764 #define QSPI_PSEL_IO2_CONNECT_Connected (0UL) /*!< Connect */
9765 #define QSPI_PSEL_IO2_CONNECT_Disconnected (1UL) /*!< Disconnect */
9766 
9767 /* Bit 5 : Port number */
9768 #define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */
9769 #define QSPI_PSEL_IO2_PORT_Msk (0x1UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */
9770 
9771 /* Bits 4..0 : Pin number */
9772 #define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */
9773 #define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */
9774 
9775 /* Register: QSPI_PSEL_IO3 */
9776 /* Description: Pin select for serial data IO3. */
9777 
9778 /* Bit 31 : Connection */
9779 #define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9780 #define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9781 #define QSPI_PSEL_IO3_CONNECT_Connected (0UL) /*!< Connect */
9782 #define QSPI_PSEL_IO3_CONNECT_Disconnected (1UL) /*!< Disconnect */
9783 
9784 /* Bit 5 : Port number */
9785 #define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */
9786 #define QSPI_PSEL_IO3_PORT_Msk (0x1UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */
9787 
9788 /* Bits 4..0 : Pin number */
9789 #define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */
9790 #define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos) /*!< Bit mask of PIN field. */
9791 
9792 /* Register: QSPI_XIPOFFSET */
9793 /* Description: Address offset into the external memory for Execute in Place operation. */
9794 
9795 /* Bits 31..0 : Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. */
9796 #define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL) /*!< Position of XIPOFFSET field. */
9797 #define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos) /*!< Bit mask of XIPOFFSET field. */
9798 
9799 /* Register: QSPI_IFCONFIG0 */
9800 /* Description: Interface configuration. */
9801 
9802 /* Bit 12 : Page size for commands PP, PP2O, PP4O and PP4IO. */
9803 #define QSPI_IFCONFIG0_PPSIZE_Pos (12UL) /*!< Position of PPSIZE field. */
9804 #define QSPI_IFCONFIG0_PPSIZE_Msk (0x1UL << QSPI_IFCONFIG0_PPSIZE_Pos) /*!< Bit mask of PPSIZE field. */
9805 #define QSPI_IFCONFIG0_PPSIZE_256Bytes (0UL) /*!< 256 bytes. */
9806 #define QSPI_IFCONFIG0_PPSIZE_512Bytes (1UL) /*!< 512 bytes. */
9807 
9808 /* Bit 7 : Enable deep power-down mode (DPM) feature. */
9809 #define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */
9810 #define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */
9811 #define QSPI_IFCONFIG0_DPMENABLE_Disable (0UL) /*!< Disable DPM feature. */
9812 #define QSPI_IFCONFIG0_DPMENABLE_Enable (1UL) /*!< Enable DPM feature. */
9813 
9814 /* Bit 6 : Addressing mode. */
9815 #define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL) /*!< Position of ADDRMODE field. */
9816 #define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos) /*!< Bit mask of ADDRMODE field. */
9817 #define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL) /*!< 24-bit addressing. */
9818 #define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL) /*!< 32-bit addressing. */
9819 
9820 /* Bits 5..3 : Configure number of data lines and opcode used for writing. */
9821 #define QSPI_IFCONFIG0_WRITEOC_Pos (3UL) /*!< Position of WRITEOC field. */
9822 #define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos) /*!< Bit mask of WRITEOC field. */
9823 #define QSPI_IFCONFIG0_WRITEOC_PP (0UL) /*!< Single data line SPI. PP (opcode 0x02). */
9824 #define QSPI_IFCONFIG0_WRITEOC_PP2O (1UL) /*!< Dual data line SPI. PP2O (opcode 0xA2). */
9825 #define QSPI_IFCONFIG0_WRITEOC_PP4O (2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */
9826 #define QSPI_IFCONFIG0_WRITEOC_PP4IO (3UL) /*!< Quad data line SPI. PP4IO (opcode 0x38). */
9827 
9828 /* Bits 2..0 : Configure number of data lines and opcode used for reading. */
9829 #define QSPI_IFCONFIG0_READOC_Pos (0UL) /*!< Position of READOC field. */
9830 #define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos) /*!< Bit mask of READOC field. */
9831 #define QSPI_IFCONFIG0_READOC_FASTREAD (0UL) /*!< Single data line SPI. FAST_READ (opcode 0x0B). */
9832 #define QSPI_IFCONFIG0_READOC_READ2O (1UL) /*!< Dual data line SPI. READ2O (opcode 0x3B). */
9833 #define QSPI_IFCONFIG0_READOC_READ2IO (2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */
9834 #define QSPI_IFCONFIG0_READOC_READ4O (3UL) /*!< Quad data line SPI. READ4O (opcode 0x6B). */
9835 #define QSPI_IFCONFIG0_READOC_READ4IO (4UL) /*!< Quad data line SPI. READ4IO (opcode 0xEB). */
9836 
9837 /* Register: QSPI_IFCONFIG1 */
9838 /* Description: Interface configuration. */
9839 
9840 /* Bits 31..28 : SCK frequency is given as 32 MHz / (SCKFREQ + 1). */
9841 #define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */
9842 #define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */
9843 
9844 /* Bit 25 : Select SPI mode. */
9845 #define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */
9846 #define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */
9847 #define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */
9848 #define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */
9849 
9850 /* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */
9851 #define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */
9852 #define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos) /*!< Bit mask of DPMEN field. */
9853 #define QSPI_IFCONFIG1_DPMEN_Exit (0UL) /*!< Exit DPM. */
9854 #define QSPI_IFCONFIG1_DPMEN_Enter (1UL) /*!< Enter DPM. */
9855 
9856 /* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). */
9857 #define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */
9858 #define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */
9859 
9860 /* Register: QSPI_STATUS */
9861 /* Description: Status register. */
9862 
9863 /* Bits 31..24 : Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */
9864 #define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */
9865 #define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */
9866 
9867 /* Bit 3 : Ready status. */
9868 #define QSPI_STATUS_READY_Pos (3UL) /*!< Position of READY field. */
9869 #define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos) /*!< Bit mask of READY field. */
9870 #define QSPI_STATUS_READY_BUSY (0UL) /*!< QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. */
9871 #define QSPI_STATUS_READY_READY (1UL) /*!< QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. */
9872 
9873 /* Bit 2 : Deep power-down mode (DPM) status of external flash. */
9874 #define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */
9875 #define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos) /*!< Bit mask of DPM field. */
9876 #define QSPI_STATUS_DPM_Disabled (0UL) /*!< External flash is not in DPM. */
9877 #define QSPI_STATUS_DPM_Enabled (1UL) /*!< External flash is in DPM. */
9878 
9879 /* Register: QSPI_DPMDUR */
9880 /* Description: Set the duration required to enter/exit deep power-down mode (DPM). */
9881 
9882 /* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. */
9883 #define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */
9884 #define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */
9885 
9886 /* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. */
9887 #define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */
9888 #define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */
9889 
9890 /* Register: QSPI_ADDRCONF */
9891 /* Description: Extended address configuration. */
9892 
9893 /* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */
9894 #define QSPI_ADDRCONF_WREN_Pos (27UL) /*!< Position of WREN field. */
9895 #define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
9896 #define QSPI_ADDRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */
9897 #define QSPI_ADDRCONF_WREN_Enable (1UL) /*!< Send WREN. */
9898 
9899 /* Bit 26 : Wait for write complete before sending command. */
9900 #define QSPI_ADDRCONF_WIPWAIT_Pos (26UL) /*!< Position of WIPWAIT field. */
9901 #define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
9902 #define QSPI_ADDRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */
9903 #define QSPI_ADDRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */
9904 
9905 /* Bits 25..24 : Extended addressing mode. */
9906 #define QSPI_ADDRCONF_MODE_Pos (24UL) /*!< Position of MODE field. */
9907 #define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */
9908 #define QSPI_ADDRCONF_MODE_NoInstr (0UL) /*!< Do not send any instruction. */
9909 #define QSPI_ADDRCONF_MODE_Opcode (1UL) /*!< Send opcode. */
9910 #define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, byte0. */
9911 #define QSPI_ADDRCONF_MODE_All (3UL) /*!< Send opcode, byte0, byte1. */
9912 
9913 /* Bits 23..16 : Byte 1 following byte 0. */
9914 #define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */
9915 #define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
9916 
9917 /* Bits 15..8 : Byte 0 following opcode. */
9918 #define QSPI_ADDRCONF_BYTE0_Pos (8UL) /*!< Position of BYTE0 field. */
9919 #define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
9920 
9921 /* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */
9922 #define QSPI_ADDRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
9923 #define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
9924 
9925 /* Register: QSPI_CINSTRCONF */
9926 /* Description: Custom instruction configuration register. */
9927 
9928 /* Bit 17 : Stop (finalize) long frame transaction */
9929 #define QSPI_CINSTRCONF_LFSTOP_Pos (17UL) /*!< Position of LFSTOP field. */
9930 #define QSPI_CINSTRCONF_LFSTOP_Msk (0x1UL << QSPI_CINSTRCONF_LFSTOP_Pos) /*!< Bit mask of LFSTOP field. */
9931 #define QSPI_CINSTRCONF_LFSTOP_Stop (1UL) /*!< Stop */
9932 
9933 /* Bit 16 : Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. */
9934 #define QSPI_CINSTRCONF_LFEN_Pos (16UL) /*!< Position of LFEN field. */
9935 #define QSPI_CINSTRCONF_LFEN_Msk (0x1UL << QSPI_CINSTRCONF_LFEN_Pos) /*!< Bit mask of LFEN field. */
9936 #define QSPI_CINSTRCONF_LFEN_Disable (0UL) /*!< Long frame mode disabled */
9937 #define QSPI_CINSTRCONF_LFEN_Enable (1UL) /*!< Long frame mode enabled */
9938 
9939 /* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */
9940 #define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */
9941 #define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
9942 #define QSPI_CINSTRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */
9943 #define QSPI_CINSTRCONF_WREN_Enable (1UL) /*!< Send WREN. */
9944 
9945 /* Bit 14 : Wait for write complete before sending command. */
9946 #define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL) /*!< Position of WIPWAIT field. */
9947 #define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
9948 #define QSPI_CINSTRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */
9949 #define QSPI_CINSTRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */
9950 
9951 /* Bit 13 : Level of the IO3 pin (if connected) during transmission of custom instruction. */
9952 #define QSPI_CINSTRCONF_LIO3_Pos (13UL) /*!< Position of LIO3 field. */
9953 #define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos) /*!< Bit mask of LIO3 field. */
9954 
9955 /* Bit 12 : Level of the IO2 pin (if connected) during transmission of custom instruction. */
9956 #define QSPI_CINSTRCONF_LIO2_Pos (12UL) /*!< Position of LIO2 field. */
9957 #define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos) /*!< Bit mask of LIO2 field. */
9958 
9959 /* Bits 11..8 : Length of custom instruction in number of bytes. */
9960 #define QSPI_CINSTRCONF_LENGTH_Pos (8UL) /*!< Position of LENGTH field. */
9961 #define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
9962 #define QSPI_CINSTRCONF_LENGTH_1B (1UL) /*!< Send opcode only. */
9963 #define QSPI_CINSTRCONF_LENGTH_2B (2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */
9964 #define QSPI_CINSTRCONF_LENGTH_3B (3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. */
9965 #define QSPI_CINSTRCONF_LENGTH_4B (4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. */
9966 #define QSPI_CINSTRCONF_LENGTH_5B (5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. */
9967 #define QSPI_CINSTRCONF_LENGTH_6B (6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. */
9968 #define QSPI_CINSTRCONF_LENGTH_7B (7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. */
9969 #define QSPI_CINSTRCONF_LENGTH_8B (8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. */
9970 #define QSPI_CINSTRCONF_LENGTH_9B (9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. */
9971 
9972 /* Bits 7..0 : Opcode of Custom instruction. */
9973 #define QSPI_CINSTRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
9974 #define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
9975 
9976 /* Register: QSPI_CINSTRDAT0 */
9977 /* Description: Custom instruction data register 0. */
9978 
9979 /* Bits 31..24 : Data byte 3 */
9980 #define QSPI_CINSTRDAT0_BYTE3_Pos (24UL) /*!< Position of BYTE3 field. */
9981 #define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos) /*!< Bit mask of BYTE3 field. */
9982 
9983 /* Bits 23..16 : Data byte 2 */
9984 #define QSPI_CINSTRDAT0_BYTE2_Pos (16UL) /*!< Position of BYTE2 field. */
9985 #define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos) /*!< Bit mask of BYTE2 field. */
9986 
9987 /* Bits 15..8 : Data byte 1 */
9988 #define QSPI_CINSTRDAT0_BYTE1_Pos (8UL) /*!< Position of BYTE1 field. */
9989 #define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
9990 
9991 /* Bits 7..0 : Data byte 0 */
9992 #define QSPI_CINSTRDAT0_BYTE0_Pos (0UL) /*!< Position of BYTE0 field. */
9993 #define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
9994 
9995 /* Register: QSPI_CINSTRDAT1 */
9996 /* Description: Custom instruction data register 1. */
9997 
9998 /* Bits 31..24 : Data byte 7 */
9999 #define QSPI_CINSTRDAT1_BYTE7_Pos (24UL) /*!< Position of BYTE7 field. */
10000 #define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos) /*!< Bit mask of BYTE7 field. */
10001 
10002 /* Bits 23..16 : Data byte 6 */
10003 #define QSPI_CINSTRDAT1_BYTE6_Pos (16UL) /*!< Position of BYTE6 field. */
10004 #define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos) /*!< Bit mask of BYTE6 field. */
10005 
10006 /* Bits 15..8 : Data byte 5 */
10007 #define QSPI_CINSTRDAT1_BYTE5_Pos (8UL) /*!< Position of BYTE5 field. */
10008 #define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos) /*!< Bit mask of BYTE5 field. */
10009 
10010 /* Bits 7..0 : Data byte 4 */
10011 #define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */
10012 #define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */
10013 
10014 /* Register: QSPI_IFTIMING */
10015 /* Description: SPI interface timing. */
10016 
10017 /* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. */
10018 #define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */
10019 #define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
10020 
10021 
10022 /* Peripheral: RADIO */
10023 /* Description: 2.4 GHz radio */
10024 
10025 /* Register: RADIO_TASKS_TXEN */
10026 /* Description: Enable RADIO in TX mode */
10027 
10028 /* Bit 0 : Enable RADIO in TX mode */
10029 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
10030 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
10031 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
10032 
10033 /* Register: RADIO_TASKS_RXEN */
10034 /* Description: Enable RADIO in RX mode */
10035 
10036 /* Bit 0 : Enable RADIO in RX mode */
10037 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
10038 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
10039 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
10040 
10041 /* Register: RADIO_TASKS_START */
10042 /* Description: Start RADIO */
10043 
10044 /* Bit 0 : Start RADIO */
10045 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10046 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10047 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
10048 
10049 /* Register: RADIO_TASKS_STOP */
10050 /* Description: Stop RADIO */
10051 
10052 /* Bit 0 : Stop RADIO */
10053 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10054 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10055 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
10056 
10057 /* Register: RADIO_TASKS_DISABLE */
10058 /* Description: Disable RADIO */
10059 
10060 /* Bit 0 : Disable RADIO */
10061 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
10062 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
10063 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
10064 
10065 /* Register: RADIO_TASKS_RSSISTART */
10066 /* Description: Start the RSSI and take one single sample of the receive signal strength */
10067 
10068 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
10069 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
10070 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
10071 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
10072 
10073 /* Register: RADIO_TASKS_RSSISTOP */
10074 /* Description: Stop the RSSI measurement */
10075 
10076 /* Bit 0 : Stop the RSSI measurement */
10077 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
10078 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
10079 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
10080 
10081 /* Register: RADIO_TASKS_BCSTART */
10082 /* Description: Start the bit counter */
10083 
10084 /* Bit 0 : Start the bit counter */
10085 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
10086 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
10087 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
10088 
10089 /* Register: RADIO_TASKS_BCSTOP */
10090 /* Description: Stop the bit counter */
10091 
10092 /* Bit 0 : Stop the bit counter */
10093 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
10094 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
10095 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
10096 
10097 /* Register: RADIO_TASKS_EDSTART */
10098 /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */
10099 
10100 /* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */
10101 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */
10102 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */
10103 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */
10104 
10105 /* Register: RADIO_TASKS_EDSTOP */
10106 /* Description: Stop the energy detect measurement */
10107 
10108 /* Bit 0 : Stop the energy detect measurement */
10109 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */
10110 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */
10111 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */
10112 
10113 /* Register: RADIO_TASKS_CCASTART */
10114 /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */
10115 
10116 /* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */
10117 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */
10118 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */
10119 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */
10120 
10121 /* Register: RADIO_TASKS_CCASTOP */
10122 /* Description: Stop the clear channel assessment */
10123 
10124 /* Bit 0 : Stop the clear channel assessment */
10125 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */
10126 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */
10127 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */
10128 
10129 /* Register: RADIO_EVENTS_READY */
10130 /* Description: RADIO has ramped up and is ready to be started */
10131 
10132 /* Bit 0 : RADIO has ramped up and is ready to be started */
10133 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
10134 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
10135 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
10136 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
10137 
10138 /* Register: RADIO_EVENTS_ADDRESS */
10139 /* Description: Address sent or received */
10140 
10141 /* Bit 0 : Address sent or received */
10142 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
10143 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
10144 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
10145 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
10146 
10147 /* Register: RADIO_EVENTS_PAYLOAD */
10148 /* Description: Packet payload sent or received */
10149 
10150 /* Bit 0 : Packet payload sent or received */
10151 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
10152 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
10153 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
10154 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
10155 
10156 /* Register: RADIO_EVENTS_END */
10157 /* Description: Packet sent or received */
10158 
10159 /* Bit 0 : Packet sent or received */
10160 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
10161 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
10162 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
10163 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
10164 
10165 /* Register: RADIO_EVENTS_DISABLED */
10166 /* Description: RADIO has been disabled */
10167 
10168 /* Bit 0 : RADIO has been disabled */
10169 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
10170 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
10171 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
10172 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
10173 
10174 /* Register: RADIO_EVENTS_DEVMATCH */
10175 /* Description: A device address match occurred on the last received packet */
10176 
10177 /* Bit 0 : A device address match occurred on the last received packet */
10178 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
10179 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
10180 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
10181 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
10182 
10183 /* Register: RADIO_EVENTS_DEVMISS */
10184 /* Description: No device address match occurred on the last received packet */
10185 
10186 /* Bit 0 : No device address match occurred on the last received packet */
10187 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
10188 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
10189 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
10190 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
10191 
10192 /* Register: RADIO_EVENTS_RSSIEND */
10193 /* Description: Sampling of receive signal strength complete */
10194 
10195 /* Bit 0 : Sampling of receive signal strength complete */
10196 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
10197 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
10198 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
10199 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
10200 
10201 /* Register: RADIO_EVENTS_BCMATCH */
10202 /* Description: Bit counter reached bit count value */
10203 
10204 /* Bit 0 : Bit counter reached bit count value */
10205 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
10206 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
10207 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
10208 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
10209 
10210 /* Register: RADIO_EVENTS_CRCOK */
10211 /* Description: Packet received with CRC ok */
10212 
10213 /* Bit 0 : Packet received with CRC ok */
10214 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
10215 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
10216 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
10217 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
10218 
10219 /* Register: RADIO_EVENTS_CRCERROR */
10220 /* Description: Packet received with CRC error */
10221 
10222 /* Bit 0 : Packet received with CRC error */
10223 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
10224 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
10225 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
10226 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
10227 
10228 /* Register: RADIO_EVENTS_FRAMESTART */
10229 /* Description: IEEE 802.15.4 length field received */
10230 
10231 /* Bit 0 : IEEE 802.15.4 length field received */
10232 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */
10233 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */
10234 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */
10235 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */
10236 
10237 /* Register: RADIO_EVENTS_EDEND */
10238 /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
10239 
10240 /* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
10241 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */
10242 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */
10243 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */
10244 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */
10245 
10246 /* Register: RADIO_EVENTS_EDSTOPPED */
10247 /* Description: The sampling of energy detection has stopped */
10248 
10249 /* Bit 0 : The sampling of energy detection has stopped */
10250 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */
10251 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */
10252 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */
10253 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */
10254 
10255 /* Register: RADIO_EVENTS_CCAIDLE */
10256 /* Description: Wireless medium in idle - clear to send */
10257 
10258 /* Bit 0 : Wireless medium in idle - clear to send */
10259 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */
10260 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */
10261 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */
10262 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */
10263 
10264 /* Register: RADIO_EVENTS_CCABUSY */
10265 /* Description: Wireless medium busy - do not send */
10266 
10267 /* Bit 0 : Wireless medium busy - do not send */
10268 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */
10269 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */
10270 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */
10271 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */
10272 
10273 /* Register: RADIO_EVENTS_CCASTOPPED */
10274 /* Description: The CCA has stopped */
10275 
10276 /* Bit 0 : The CCA has stopped */
10277 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */
10278 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */
10279 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */
10280 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */
10281 
10282 /* Register: RADIO_EVENTS_RATEBOOST */
10283 /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
10284 
10285 /* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
10286 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */
10287 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */
10288 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */
10289 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */
10290 
10291 /* Register: RADIO_EVENTS_TXREADY */
10292 /* Description: RADIO has ramped up and is ready to be started TX path */
10293 
10294 /* Bit 0 : RADIO has ramped up and is ready to be started TX path */
10295 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */
10296 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */
10297 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */
10298 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */
10299 
10300 /* Register: RADIO_EVENTS_RXREADY */
10301 /* Description: RADIO has ramped up and is ready to be started RX path */
10302 
10303 /* Bit 0 : RADIO has ramped up and is ready to be started RX path */
10304 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */
10305 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */
10306 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */
10307 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */
10308 
10309 /* Register: RADIO_EVENTS_MHRMATCH */
10310 /* Description: MAC header match found */
10311 
10312 /* Bit 0 : MAC header match found */
10313 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */
10314 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */
10315 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */
10316 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */
10317 
10318 /* Register: RADIO_EVENTS_SYNC */
10319 /* Description: Preamble indicator. */
10320 
10321 /* Bit 0 : Preamble indicator. */
10322 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */
10323 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */
10324 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */
10325 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */
10326 
10327 /* Register: RADIO_EVENTS_PHYEND */
10328 /* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */
10329 
10330 /* Bit 0 : Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */
10331 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */
10332 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */
10333 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */
10334 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */
10335 
10336 /* Register: RADIO_SHORTS */
10337 /* Description: Shortcuts between local events and tasks */
10338 
10339 /* Bit 21 : Shortcut between event PHYEND and task START */
10340 #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */
10341 #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */
10342 #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */
10343 #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */
10344 
10345 /* Bit 20 : Shortcut between event PHYEND and task DISABLE */
10346 #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */
10347 #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */
10348 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
10349 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
10350 
10351 /* Bit 19 : Shortcut between event RXREADY and task START */
10352 #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
10353 #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
10354 #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
10355 #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
10356 
10357 /* Bit 18 : Shortcut between event TXREADY and task START */
10358 #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
10359 #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
10360 #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
10361 #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
10362 
10363 /* Bit 17 : Shortcut between event CCAIDLE and task STOP */
10364 #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */
10365 #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */
10366 #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */
10367 #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */
10368 
10369 /* Bit 16 : Shortcut between event EDEND and task DISABLE */
10370 #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */
10371 #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */
10372 #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
10373 #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
10374 
10375 /* Bit 15 : Shortcut between event READY and task EDSTART */
10376 #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */
10377 #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */
10378 #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */
10379 #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */
10380 
10381 /* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */
10382 #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */
10383 #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */
10384 #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */
10385 #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */
10386 
10387 /* Bit 13 : Shortcut between event CCABUSY and task DISABLE */
10388 #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */
10389 #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
10390 #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */
10391 #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */
10392 
10393 /* Bit 12 : Shortcut between event CCAIDLE and task TXEN */
10394 #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */
10395 #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */
10396 #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */
10397 #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */
10398 
10399 /* Bit 11 : Shortcut between event RXREADY and task CCASTART */
10400 #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */
10401 #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */
10402 #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */
10403 #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */
10404 
10405 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
10406 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
10407 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
10408 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
10409 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
10410 
10411 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
10412 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
10413 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
10414 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
10415 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
10416 
10417 /* Bit 5 : Shortcut between event END and task START */
10418 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
10419 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
10420 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
10421 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
10422 
10423 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
10424 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
10425 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
10426 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
10427 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
10428 
10429 /* Bit 3 : Shortcut between event DISABLED and task RXEN */
10430 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
10431 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
10432 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
10433 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
10434 
10435 /* Bit 2 : Shortcut between event DISABLED and task TXEN */
10436 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
10437 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
10438 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
10439 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
10440 
10441 /* Bit 1 : Shortcut between event END and task DISABLE */
10442 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
10443 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
10444 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
10445 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
10446 
10447 /* Bit 0 : Shortcut between event READY and task START */
10448 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
10449 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
10450 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
10451 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
10452 
10453 /* Register: RADIO_INTENSET */
10454 /* Description: Enable interrupt */
10455 
10456 /* Bit 27 : Write '1' to enable interrupt for event PHYEND */
10457 #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
10458 #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
10459 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */
10460 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */
10461 #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */
10462 
10463 /* Bit 26 : Write '1' to enable interrupt for event SYNC */
10464 #define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */
10465 #define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */
10466 #define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */
10467 #define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */
10468 #define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */
10469 
10470 /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */
10471 #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
10472 #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
10473 #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
10474 #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
10475 #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
10476 
10477 /* Bit 22 : Write '1' to enable interrupt for event RXREADY */
10478 #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
10479 #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
10480 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
10481 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
10482 #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
10483 
10484 /* Bit 21 : Write '1' to enable interrupt for event TXREADY */
10485 #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
10486 #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
10487 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
10488 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
10489 #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
10490 
10491 /* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
10492 #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
10493 #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
10494 #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
10495 #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
10496 #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */
10497 
10498 /* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
10499 #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
10500 #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
10501 #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
10502 #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
10503 #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */
10504 
10505 /* Bit 18 : Write '1' to enable interrupt for event CCABUSY */
10506 #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
10507 #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
10508 #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
10509 #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
10510 #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */
10511 
10512 /* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
10513 #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
10514 #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
10515 #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
10516 #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
10517 #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */
10518 
10519 /* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
10520 #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
10521 #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
10522 #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10523 #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10524 #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */
10525 
10526 /* Bit 15 : Write '1' to enable interrupt for event EDEND */
10527 #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */
10528 #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */
10529 #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
10530 #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
10531 #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */
10532 
10533 /* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */
10534 #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
10535 #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
10536 #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
10537 #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
10538 #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
10539 
10540 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
10541 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
10542 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
10543 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
10544 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
10545 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
10546 
10547 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */
10548 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
10549 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
10550 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
10551 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
10552 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
10553 
10554 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
10555 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
10556 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
10557 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
10558 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
10559 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
10560 
10561 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
10562 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
10563 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
10564 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
10565 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
10566 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
10567 
10568 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
10569 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
10570 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
10571 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
10572 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
10573 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
10574 
10575 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
10576 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
10577 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
10578 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
10579 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
10580 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
10581 
10582 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */
10583 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
10584 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
10585 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
10586 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
10587 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
10588 
10589 /* Bit 3 : Write '1' to enable interrupt for event END */
10590 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
10591 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
10592 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10593 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10594 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
10595 
10596 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
10597 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
10598 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
10599 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
10600 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
10601 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
10602 
10603 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
10604 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
10605 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
10606 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
10607 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
10608 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
10609 
10610 /* Bit 0 : Write '1' to enable interrupt for event READY */
10611 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
10612 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
10613 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
10614 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10615 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
10616 
10617 /* Register: RADIO_INTENCLR */
10618 /* Description: Disable interrupt */
10619 
10620 /* Bit 27 : Write '1' to disable interrupt for event PHYEND */
10621 #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
10622 #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
10623 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */
10624 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */
10625 #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */
10626 
10627 /* Bit 26 : Write '1' to disable interrupt for event SYNC */
10628 #define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */
10629 #define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */
10630 #define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */
10631 #define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */
10632 #define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */
10633 
10634 /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */
10635 #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
10636 #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
10637 #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
10638 #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
10639 #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
10640 
10641 /* Bit 22 : Write '1' to disable interrupt for event RXREADY */
10642 #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
10643 #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
10644 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
10645 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
10646 #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
10647 
10648 /* Bit 21 : Write '1' to disable interrupt for event TXREADY */
10649 #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
10650 #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
10651 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
10652 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
10653 #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
10654 
10655 /* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
10656 #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
10657 #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
10658 #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
10659 #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
10660 #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */
10661 
10662 /* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
10663 #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
10664 #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
10665 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
10666 #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
10667 #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */
10668 
10669 /* Bit 18 : Write '1' to disable interrupt for event CCABUSY */
10670 #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
10671 #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
10672 #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
10673 #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
10674 #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */
10675 
10676 /* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
10677 #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
10678 #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
10679 #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
10680 #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
10681 #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */
10682 
10683 /* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
10684 #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
10685 #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
10686 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10687 #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10688 #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */
10689 
10690 /* Bit 15 : Write '1' to disable interrupt for event EDEND */
10691 #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */
10692 #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */
10693 #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
10694 #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
10695 #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */
10696 
10697 /* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */
10698 #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
10699 #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
10700 #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
10701 #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
10702 #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
10703 
10704 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
10705 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
10706 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
10707 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
10708 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
10709 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
10710 
10711 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */
10712 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
10713 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
10714 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
10715 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
10716 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
10717 
10718 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
10719 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
10720 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
10721 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
10722 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
10723 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
10724 
10725 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
10726 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
10727 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
10728 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
10729 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
10730 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
10731 
10732 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
10733 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
10734 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
10735 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
10736 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
10737 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
10738 
10739 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
10740 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
10741 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
10742 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
10743 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
10744 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
10745 
10746 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */
10747 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
10748 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
10749 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
10750 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
10751 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
10752 
10753 /* Bit 3 : Write '1' to disable interrupt for event END */
10754 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
10755 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
10756 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10757 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10758 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
10759 
10760 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
10761 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
10762 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
10763 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
10764 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
10765 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
10766 
10767 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
10768 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
10769 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
10770 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
10771 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
10772 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
10773 
10774 /* Bit 0 : Write '1' to disable interrupt for event READY */
10775 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
10776 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
10777 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
10778 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10779 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
10780 
10781 /* Register: RADIO_CRCSTATUS */
10782 /* Description: CRC status */
10783 
10784 /* Bit 0 : CRC status of packet received */
10785 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
10786 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
10787 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
10788 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
10789 
10790 /* Register: RADIO_RXMATCH */
10791 /* Description: Received address */
10792 
10793 /* Bits 2..0 : Received address */
10794 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
10795 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
10796 
10797 /* Register: RADIO_RXCRC */
10798 /* Description: CRC field of previously received packet */
10799 
10800 /* Bits 23..0 : CRC field of previously received packet */
10801 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
10802 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
10803 
10804 /* Register: RADIO_DAI */
10805 /* Description: Device address match index */
10806 
10807 /* Bits 2..0 : Device address match index */
10808 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
10809 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
10810 
10811 /* Register: RADIO_PDUSTAT */
10812 /* Description: Payload status */
10813 
10814 /* Bits 2..1 : Status on what rate packet is received with in Long Range */
10815 #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */
10816 #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */
10817 #define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125kbps */
10818 #define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500kbps */
10819 
10820 /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
10821 #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */
10822 #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */
10823 #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */
10824 #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */
10825 
10826 /* Register: RADIO_PACKETPTR */
10827 /* Description: Packet pointer */
10828 
10829 /* Bits 31..0 : Packet pointer */
10830 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
10831 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
10832 
10833 /* Register: RADIO_FREQUENCY */
10834 /* Description: Frequency */
10835 
10836 /* Bit 8 : Channel map selection. */
10837 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
10838 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
10839 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
10840 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
10841 
10842 /* Bits 6..0 : Radio channel frequency */
10843 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
10844 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
10845 
10846 /* Register: RADIO_TXPOWER */
10847 /* Description: Output power */
10848 
10849 /* Bits 7..0 : RADIO output power */
10850 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
10851 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
10852 #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */
10853 #define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */
10854 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */
10855 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */
10856 #define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */
10857 #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */
10858 #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */
10859 #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */
10860 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
10861 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator -  -40 dBm */
10862 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
10863 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
10864 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
10865 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
10866 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
10867 
10868 /* Register: RADIO_MODE */
10869 /* Description: Data rate and modulation */
10870 
10871 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
10872 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
10873 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
10874 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
10875 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
10876 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s BLE */
10877 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s BLE */
10878 #define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
10879 #define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
10880 #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */
10881 
10882 /* Register: RADIO_PCNF0 */
10883 /* Description: Packet configuration register 0 */
10884 
10885 /* Bits 30..29 : Length of TERM field in Long Range operation */
10886 #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */
10887 #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */
10888 
10889 /* Bit 26 : Indicates if LENGTH field contains CRC or not */
10890 #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
10891 #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
10892 #define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */
10893 #define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */
10894 
10895 /* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
10896 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
10897 #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
10898 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
10899 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
10900 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
10901 #define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */
10902 
10903 /* Bits 23..22 : Length of code indicator - long range */
10904 #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */
10905 #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */
10906 
10907 /* Bit 20 : Include or exclude S1 field in RAM */
10908 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
10909 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
10910 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
10911 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
10912 
10913 /* Bits 19..16 : Length on air of S1 field in number of bits. */
10914 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
10915 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
10916 
10917 /* Bit 8 : Length on air of S0 field in number of bytes. */
10918 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
10919 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
10920 
10921 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
10922 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
10923 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
10924 
10925 /* Register: RADIO_PCNF1 */
10926 /* Description: Packet configuration register 1 */
10927 
10928 /* Bit 25 : Enable or disable packet whitening */
10929 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
10930 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
10931 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
10932 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
10933 
10934 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
10935 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
10936 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
10937 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
10938 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
10939 
10940 /* Bits 18..16 : Base address length in number of bytes */
10941 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
10942 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
10943 
10944 /* Bits 15..8 : Static length in number of bytes */
10945 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
10946 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
10947 
10948 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
10949 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
10950 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
10951 
10952 /* Register: RADIO_BASE0 */
10953 /* Description: Base address 0 */
10954 
10955 /* Bits 31..0 : Base address 0 */
10956 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
10957 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
10958 
10959 /* Register: RADIO_BASE1 */
10960 /* Description: Base address 1 */
10961 
10962 /* Bits 31..0 : Base address 1 */
10963 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
10964 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
10965 
10966 /* Register: RADIO_PREFIX0 */
10967 /* Description: Prefixes bytes for logical addresses 0-3 */
10968 
10969 /* Bits 31..24 : Address prefix 3. */
10970 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
10971 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
10972 
10973 /* Bits 23..16 : Address prefix 2. */
10974 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
10975 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
10976 
10977 /* Bits 15..8 : Address prefix 1. */
10978 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
10979 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
10980 
10981 /* Bits 7..0 : Address prefix 0. */
10982 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
10983 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
10984 
10985 /* Register: RADIO_PREFIX1 */
10986 /* Description: Prefixes bytes for logical addresses 4-7 */
10987 
10988 /* Bits 31..24 : Address prefix 7. */
10989 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
10990 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
10991 
10992 /* Bits 23..16 : Address prefix 6. */
10993 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
10994 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
10995 
10996 /* Bits 15..8 : Address prefix 5. */
10997 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
10998 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
10999 
11000 /* Bits 7..0 : Address prefix 4. */
11001 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
11002 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
11003 
11004 /* Register: RADIO_TXADDRESS */
11005 /* Description: Transmit address select */
11006 
11007 /* Bits 2..0 : Transmit address select */
11008 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
11009 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
11010 
11011 /* Register: RADIO_RXADDRESSES */
11012 /* Description: Receive address select */
11013 
11014 /* Bit 7 : Enable or disable reception on logical address 7. */
11015 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
11016 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
11017 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
11018 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
11019 
11020 /* Bit 6 : Enable or disable reception on logical address 6. */
11021 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
11022 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
11023 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
11024 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
11025 
11026 /* Bit 5 : Enable or disable reception on logical address 5. */
11027 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
11028 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
11029 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
11030 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
11031 
11032 /* Bit 4 : Enable or disable reception on logical address 4. */
11033 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
11034 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
11035 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
11036 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
11037 
11038 /* Bit 3 : Enable or disable reception on logical address 3. */
11039 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
11040 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
11041 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
11042 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
11043 
11044 /* Bit 2 : Enable or disable reception on logical address 2. */
11045 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
11046 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
11047 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
11048 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
11049 
11050 /* Bit 1 : Enable or disable reception on logical address 1. */
11051 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
11052 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
11053 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
11054 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
11055 
11056 /* Bit 0 : Enable or disable reception on logical address 0. */
11057 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
11058 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
11059 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
11060 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
11061 
11062 /* Register: RADIO_CRCCNF */
11063 /* Description: CRC configuration */
11064 
11065 /* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
11066 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
11067 #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
11068 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
11069 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
11070 #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */
11071 
11072 /* Bits 1..0 : CRC length in number of bytes. */
11073 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
11074 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
11075 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
11076 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
11077 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
11078 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
11079 
11080 /* Register: RADIO_CRCPOLY */
11081 /* Description: CRC polynomial */
11082 
11083 /* Bits 23..0 : CRC polynomial */
11084 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
11085 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
11086 
11087 /* Register: RADIO_CRCINIT */
11088 /* Description: CRC initial value */
11089 
11090 /* Bits 23..0 : CRC initial value */
11091 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
11092 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
11093 
11094 /* Register: RADIO_TIFS */
11095 /* Description: Interframe spacing in us */
11096 
11097 /* Bits 9..0 : Interframe spacing in us */
11098 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
11099 #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
11100 
11101 /* Register: RADIO_RSSISAMPLE */
11102 /* Description: RSSI sample */
11103 
11104 /* Bits 6..0 : RSSI sample */
11105 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
11106 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
11107 
11108 /* Register: RADIO_STATE */
11109 /* Description: Current radio state */
11110 
11111 /* Bits 3..0 : Current radio state */
11112 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
11113 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
11114 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
11115 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
11116 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
11117 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
11118 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
11119 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
11120 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
11121 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
11122 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
11123 
11124 /* Register: RADIO_DATAWHITEIV */
11125 /* Description: Data whitening initial value */
11126 
11127 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
11128 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
11129 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
11130 
11131 /* Register: RADIO_BCC */
11132 /* Description: Bit counter compare */
11133 
11134 /* Bits 31..0 : Bit counter compare */
11135 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
11136 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
11137 
11138 /* Register: RADIO_DAB */
11139 /* Description: Description collection: Device address base segment n */
11140 
11141 /* Bits 31..0 : Device address base segment n */
11142 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
11143 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
11144 
11145 /* Register: RADIO_DAP */
11146 /* Description: Description collection: Device address prefix n */
11147 
11148 /* Bits 15..0 : Device address prefix n */
11149 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
11150 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
11151 
11152 /* Register: RADIO_DACNF */
11153 /* Description: Device address match configuration */
11154 
11155 /* Bit 15 : TxAdd for device address 7 */
11156 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
11157 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
11158 
11159 /* Bit 14 : TxAdd for device address 6 */
11160 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
11161 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
11162 
11163 /* Bit 13 : TxAdd for device address 5 */
11164 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
11165 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
11166 
11167 /* Bit 12 : TxAdd for device address 4 */
11168 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
11169 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
11170 
11171 /* Bit 11 : TxAdd for device address 3 */
11172 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
11173 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
11174 
11175 /* Bit 10 : TxAdd for device address 2 */
11176 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
11177 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
11178 
11179 /* Bit 9 : TxAdd for device address 1 */
11180 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
11181 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
11182 
11183 /* Bit 8 : TxAdd for device address 0 */
11184 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
11185 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
11186 
11187 /* Bit 7 : Enable or disable device address matching using device address 7 */
11188 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
11189 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
11190 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
11191 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
11192 
11193 /* Bit 6 : Enable or disable device address matching using device address 6 */
11194 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
11195 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
11196 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
11197 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
11198 
11199 /* Bit 5 : Enable or disable device address matching using device address 5 */
11200 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
11201 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
11202 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
11203 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
11204 
11205 /* Bit 4 : Enable or disable device address matching using device address 4 */
11206 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
11207 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
11208 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
11209 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
11210 
11211 /* Bit 3 : Enable or disable device address matching using device address 3 */
11212 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
11213 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
11214 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
11215 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
11216 
11217 /* Bit 2 : Enable or disable device address matching using device address 2 */
11218 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
11219 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
11220 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
11221 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
11222 
11223 /* Bit 1 : Enable or disable device address matching using device address 1 */
11224 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
11225 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
11226 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
11227 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
11228 
11229 /* Bit 0 : Enable or disable device address matching using device address 0 */
11230 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
11231 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
11232 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
11233 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
11234 
11235 /* Register: RADIO_MHRMATCHCONF */
11236 /* Description: Search pattern configuration */
11237 
11238 /* Bits 31..0 : Search pattern configuration */
11239 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */
11240 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */
11241 
11242 /* Register: RADIO_MHRMATCHMAS */
11243 /* Description: Pattern mask */
11244 
11245 /* Bits 31..0 : Pattern mask */
11246 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */
11247 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */
11248 
11249 /* Register: RADIO_MODECNF0 */
11250 /* Description: Radio mode configuration register 0 */
11251 
11252 /* Bits 9..8 : Default TX value */
11253 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
11254 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
11255 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
11256 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
11257 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
11258 
11259 /* Bit 0 : Radio ramp-up time */
11260 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
11261 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
11262 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */
11263 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */
11264 
11265 /* Register: RADIO_SFD */
11266 /* Description: IEEE 802.15.4 start of frame delimiter */
11267 
11268 /* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */
11269 #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */
11270 #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */
11271 
11272 /* Register: RADIO_EDCNT */
11273 /* Description: IEEE 802.15.4 energy detect loop count */
11274 
11275 /* Bits 20..0 : IEEE 802.15.4 energy detect loop count */
11276 #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */
11277 #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */
11278 
11279 /* Register: RADIO_EDSAMPLE */
11280 /* Description: IEEE 802.15.4 energy detect level */
11281 
11282 /* Bits 7..0 : IEEE 802.15.4 energy detect level */
11283 #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */
11284 #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */
11285 
11286 /* Register: RADIO_CCACTRL */
11287 /* Description: IEEE 802.15.4 clear channel assessment control */
11288 
11289 /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
11290 #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
11291 #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
11292 
11293 /* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */
11294 #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
11295 #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
11296 
11297 /* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */
11298 #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */
11299 #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */
11300 
11301 /* Bits 2..0 : CCA mode of operation */
11302 #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */
11303 #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */
11304 #define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */
11305 #define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */
11306 #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */
11307 #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */
11308 #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
11309 
11310 /* Register: RADIO_POWER */
11311 /* Description: Peripheral power control */
11312 
11313 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
11314 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
11315 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
11316 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
11317 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
11318 
11319 
11320 /* Peripheral: RNG */
11321 /* Description: Random Number Generator */
11322 
11323 /* Register: RNG_TASKS_START */
11324 /* Description: Task starting the random number generator */
11325 
11326 /* Bit 0 : Task starting the random number generator */
11327 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11328 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11329 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
11330 
11331 /* Register: RNG_TASKS_STOP */
11332 /* Description: Task stopping the random number generator */
11333 
11334 /* Bit 0 : Task stopping the random number generator */
11335 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
11336 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
11337 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
11338 
11339 /* Register: RNG_EVENTS_VALRDY */
11340 /* Description: Event being generated for every new random number written to the VALUE register */
11341 
11342 /* Bit 0 : Event being generated for every new random number written to the VALUE register */
11343 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
11344 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
11345 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
11346 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
11347 
11348 /* Register: RNG_SHORTS */
11349 /* Description: Shortcuts between local events and tasks */
11350 
11351 /* Bit 0 : Shortcut between event VALRDY and task STOP */
11352 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
11353 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
11354 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
11355 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
11356 
11357 /* Register: RNG_INTENSET */
11358 /* Description: Enable interrupt */
11359 
11360 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */
11361 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
11362 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
11363 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
11364 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
11365 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
11366 
11367 /* Register: RNG_INTENCLR */
11368 /* Description: Disable interrupt */
11369 
11370 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */
11371 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
11372 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
11373 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
11374 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
11375 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
11376 
11377 /* Register: RNG_CONFIG */
11378 /* Description: Configuration register */
11379 
11380 /* Bit 0 : Bias correction */
11381 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
11382 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
11383 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
11384 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
11385 
11386 /* Register: RNG_VALUE */
11387 /* Description: Output random number */
11388 
11389 /* Bits 7..0 : Generated random number */
11390 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
11391 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
11392 
11393 
11394 /* Peripheral: RTC */
11395 /* Description: Real time counter 0 */
11396 
11397 /* Register: RTC_TASKS_START */
11398 /* Description: Start RTC COUNTER */
11399 
11400 /* Bit 0 : Start RTC COUNTER */
11401 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11402 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11403 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
11404 
11405 /* Register: RTC_TASKS_STOP */
11406 /* Description: Stop RTC COUNTER */
11407 
11408 /* Bit 0 : Stop RTC COUNTER */
11409 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
11410 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
11411 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
11412 
11413 /* Register: RTC_TASKS_CLEAR */
11414 /* Description: Clear RTC COUNTER */
11415 
11416 /* Bit 0 : Clear RTC COUNTER */
11417 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
11418 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
11419 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
11420 
11421 /* Register: RTC_TASKS_TRIGOVRFLW */
11422 /* Description: Set COUNTER to 0xFFFFF0 */
11423 
11424 /* Bit 0 : Set COUNTER to 0xFFFFF0 */
11425 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
11426 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
11427 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
11428 
11429 /* Register: RTC_EVENTS_TICK */
11430 /* Description: Event on COUNTER increment */
11431 
11432 /* Bit 0 : Event on COUNTER increment */
11433 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
11434 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
11435 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
11436 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
11437 
11438 /* Register: RTC_EVENTS_OVRFLW */
11439 /* Description: Event on COUNTER overflow */
11440 
11441 /* Bit 0 : Event on COUNTER overflow */
11442 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
11443 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
11444 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
11445 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
11446 
11447 /* Register: RTC_EVENTS_COMPARE */
11448 /* Description: Description collection: Compare event on CC[n] match */
11449 
11450 /* Bit 0 : Compare event on CC[n] match */
11451 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
11452 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
11453 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
11454 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
11455 
11456 /* Register: RTC_INTENSET */
11457 /* Description: Enable interrupt */
11458 
11459 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
11460 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11461 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11462 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11463 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11464 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
11465 
11466 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
11467 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11468 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11469 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11470 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11471 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
11472 
11473 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
11474 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11475 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11476 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11477 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11478 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
11479 
11480 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
11481 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11482 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11483 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11484 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11485 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
11486 
11487 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
11488 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11489 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11490 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11491 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11492 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
11493 
11494 /* Bit 0 : Write '1' to enable interrupt for event TICK */
11495 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
11496 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
11497 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11498 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11499 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
11500 
11501 /* Register: RTC_INTENCLR */
11502 /* Description: Disable interrupt */
11503 
11504 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
11505 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11506 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11507 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11508 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11509 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
11510 
11511 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
11512 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11513 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11514 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11515 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11516 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
11517 
11518 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
11519 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11520 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11521 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11522 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11523 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
11524 
11525 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
11526 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11527 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11528 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11529 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11530 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
11531 
11532 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
11533 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11534 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11535 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11536 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11537 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
11538 
11539 /* Bit 0 : Write '1' to disable interrupt for event TICK */
11540 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
11541 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
11542 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11543 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11544 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
11545 
11546 /* Register: RTC_EVTEN */
11547 /* Description: Enable or disable event routing */
11548 
11549 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
11550 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11551 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11552 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
11553 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
11554 
11555 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
11556 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11557 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11558 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
11559 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
11560 
11561 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
11562 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11563 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11564 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
11565 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
11566 
11567 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
11568 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11569 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11570 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
11571 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
11572 
11573 /* Bit 1 : Enable or disable event routing for event OVRFLW */
11574 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11575 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11576 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
11577 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
11578 
11579 /* Bit 0 : Enable or disable event routing for event TICK */
11580 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
11581 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
11582 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
11583 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
11584 
11585 /* Register: RTC_EVTENSET */
11586 /* Description: Enable event routing */
11587 
11588 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
11589 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11590 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11591 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11592 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11593 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
11594 
11595 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
11596 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11597 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11598 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11599 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11600 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
11601 
11602 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
11603 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11604 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11605 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11606 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11607 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
11608 
11609 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
11610 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11611 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11612 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11613 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11614 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
11615 
11616 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
11617 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11618 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11619 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11620 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11621 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
11622 
11623 /* Bit 0 : Write '1' to enable event routing for event TICK */
11624 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
11625 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
11626 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11627 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11628 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
11629 
11630 /* Register: RTC_EVTENCLR */
11631 /* Description: Disable event routing */
11632 
11633 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
11634 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11635 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11636 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11637 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11638 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
11639 
11640 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
11641 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11642 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11643 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11644 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11645 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
11646 
11647 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
11648 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11649 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11650 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11651 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11652 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
11653 
11654 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
11655 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11656 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11657 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11658 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11659 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
11660 
11661 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
11662 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11663 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11664 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11665 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11666 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
11667 
11668 /* Bit 0 : Write '1' to disable event routing for event TICK */
11669 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
11670 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
11671 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11672 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11673 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
11674 
11675 /* Register: RTC_COUNTER */
11676 /* Description: Current COUNTER value */
11677 
11678 /* Bits 23..0 : Counter value */
11679 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
11680 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
11681 
11682 /* Register: RTC_PRESCALER */
11683 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */
11684 
11685 /* Bits 11..0 : Prescaler value */
11686 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
11687 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
11688 
11689 /* Register: RTC_CC */
11690 /* Description: Description collection: Compare register n */
11691 
11692 /* Bits 23..0 : Compare value */
11693 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
11694 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
11695 
11696 
11697 /* Peripheral: SAADC */
11698 /* Description: Successive approximation register (SAR) analog-to-digital converter */
11699 
11700 /* Register: SAADC_TASKS_START */
11701 /* Description: Starts the SAADC and prepares the result buffer in RAM */
11702 
11703 /* Bit 0 : Starts the SAADC and prepares the result buffer in RAM */
11704 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11705 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11706 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
11707 
11708 /* Register: SAADC_TASKS_SAMPLE */
11709 /* Description: Takes one SAADC sample */
11710 
11711 /* Bit 0 : Takes one SAADC sample */
11712 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
11713 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
11714 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
11715 
11716 /* Register: SAADC_TASKS_STOP */
11717 /* Description: Stops the SAADC and terminates all on-going conversions */
11718 
11719 /* Bit 0 : Stops the SAADC and terminates all on-going conversions */
11720 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
11721 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
11722 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
11723 
11724 /* Register: SAADC_TASKS_CALIBRATEOFFSET */
11725 /* Description: Starts offset auto-calibration */
11726 
11727 /* Bit 0 : Starts offset auto-calibration */
11728 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
11729 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
11730 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
11731 
11732 /* Register: SAADC_EVENTS_STARTED */
11733 /* Description: The SAADC has started */
11734 
11735 /* Bit 0 : The SAADC has started */
11736 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
11737 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
11738 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
11739 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
11740 
11741 /* Register: SAADC_EVENTS_END */
11742 /* Description: The SAADC has filled up the result buffer */
11743 
11744 /* Bit 0 : The SAADC has filled up the result buffer */
11745 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
11746 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
11747 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
11748 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
11749 
11750 /* Register: SAADC_EVENTS_DONE */
11751 /* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */
11752 
11753 /* Bit 0 : A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */
11754 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
11755 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
11756 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
11757 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
11758 
11759 /* Register: SAADC_EVENTS_RESULTDONE */
11760 /* Description: Result ready for transfer to RAM */
11761 
11762 /* Bit 0 : Result ready for transfer to RAM */
11763 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
11764 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
11765 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
11766 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
11767 
11768 /* Register: SAADC_EVENTS_CALIBRATEDONE */
11769 /* Description: Calibration is complete */
11770 
11771 /* Bit 0 : Calibration is complete */
11772 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
11773 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
11774 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
11775 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
11776 
11777 /* Register: SAADC_EVENTS_STOPPED */
11778 /* Description: The SAADC has stopped */
11779 
11780 /* Bit 0 : The SAADC has stopped */
11781 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
11782 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
11783 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
11784 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
11785 
11786 /* Register: SAADC_EVENTS_CH_LIMITH */
11787 /* Description: Description cluster: Last result is equal or above CH[n].LIMIT.HIGH */
11788 
11789 /* Bit 0 : Last result is equal or above CH[n].LIMIT.HIGH */
11790 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
11791 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
11792 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
11793 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
11794 
11795 /* Register: SAADC_EVENTS_CH_LIMITL */
11796 /* Description: Description cluster: Last result is equal or below CH[n].LIMIT.LOW */
11797 
11798 /* Bit 0 : Last result is equal or below CH[n].LIMIT.LOW */
11799 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
11800 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
11801 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
11802 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
11803 
11804 /* Register: SAADC_INTEN */
11805 /* Description: Enable or disable interrupt */
11806 
11807 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
11808 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
11809 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
11810 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
11811 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
11812 
11813 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
11814 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
11815 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
11816 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
11817 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
11818 
11819 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
11820 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
11821 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
11822 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
11823 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
11824 
11825 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
11826 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
11827 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
11828 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
11829 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
11830 
11831 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
11832 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
11833 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
11834 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
11835 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
11836 
11837 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
11838 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
11839 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
11840 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
11841 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
11842 
11843 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
11844 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
11845 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
11846 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
11847 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
11848 
11849 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
11850 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
11851 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
11852 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
11853 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
11854 
11855 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
11856 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
11857 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
11858 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
11859 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
11860 
11861 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
11862 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
11863 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
11864 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
11865 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
11866 
11867 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
11868 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
11869 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
11870 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
11871 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
11872 
11873 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
11874 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
11875 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
11876 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
11877 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
11878 
11879 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
11880 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
11881 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
11882 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
11883 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
11884 
11885 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
11886 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
11887 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
11888 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
11889 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
11890 
11891 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
11892 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
11893 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
11894 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
11895 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
11896 
11897 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
11898 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
11899 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
11900 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
11901 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
11902 
11903 /* Bit 5 : Enable or disable interrupt for event STOPPED */
11904 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
11905 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11906 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11907 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11908 
11909 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
11910 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
11911 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
11912 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
11913 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
11914 
11915 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
11916 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
11917 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
11918 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
11919 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
11920 
11921 /* Bit 2 : Enable or disable interrupt for event DONE */
11922 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
11923 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
11924 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
11925 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
11926 
11927 /* Bit 1 : Enable or disable interrupt for event END */
11928 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
11929 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
11930 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
11931 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
11932 
11933 /* Bit 0 : Enable or disable interrupt for event STARTED */
11934 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
11935 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
11936 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
11937 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
11938 
11939 /* Register: SAADC_INTENSET */
11940 /* Description: Enable interrupt */
11941 
11942 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
11943 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
11944 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
11945 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11946 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11947 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
11948 
11949 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
11950 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
11951 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
11952 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11953 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11954 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
11955 
11956 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
11957 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
11958 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
11959 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11960 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11961 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
11962 
11963 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
11964 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
11965 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
11966 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11967 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11968 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
11969 
11970 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
11971 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
11972 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
11973 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11974 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11975 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
11976 
11977 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
11978 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
11979 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
11980 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11981 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11982 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
11983 
11984 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
11985 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
11986 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
11987 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11988 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11989 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
11990 
11991 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
11992 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
11993 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
11994 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11995 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11996 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
11997 
11998 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
11999 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
12000 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
12001 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
12002 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
12003 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
12004 
12005 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
12006 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
12007 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
12008 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
12009 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
12010 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
12011 
12012 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
12013 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
12014 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
12015 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
12016 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
12017 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
12018 
12019 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
12020 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
12021 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
12022 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
12023 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
12024 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
12025 
12026 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
12027 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
12028 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
12029 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
12030 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
12031 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
12032 
12033 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
12034 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
12035 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
12036 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
12037 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
12038 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
12039 
12040 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
12041 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
12042 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
12043 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
12044 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
12045 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
12046 
12047 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
12048 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
12049 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
12050 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
12051 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
12052 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
12053 
12054 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
12055 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
12056 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12057 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12058 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12059 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
12060 
12061 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
12062 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
12063 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
12064 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
12065 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
12066 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
12067 
12068 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
12069 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
12070 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
12071 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
12072 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
12073 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
12074 
12075 /* Bit 2 : Write '1' to enable interrupt for event DONE */
12076 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
12077 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
12078 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
12079 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
12080 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
12081 
12082 /* Bit 1 : Write '1' to enable interrupt for event END */
12083 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
12084 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
12085 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12086 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12087 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
12088 
12089 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
12090 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
12091 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
12092 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
12093 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
12094 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
12095 
12096 /* Register: SAADC_INTENCLR */
12097 /* Description: Disable interrupt */
12098 
12099 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
12100 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
12101 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
12102 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
12103 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
12104 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
12105 
12106 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
12107 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
12108 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
12109 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
12110 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
12111 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
12112 
12113 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
12114 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
12115 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
12116 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
12117 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
12118 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
12119 
12120 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
12121 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
12122 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
12123 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
12124 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
12125 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
12126 
12127 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
12128 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
12129 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
12130 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
12131 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
12132 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
12133 
12134 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
12135 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
12136 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
12137 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
12138 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
12139 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
12140 
12141 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
12142 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
12143 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
12144 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
12145 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
12146 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
12147 
12148 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
12149 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
12150 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
12151 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
12152 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
12153 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
12154 
12155 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
12156 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
12157 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
12158 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
12159 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
12160 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
12161 
12162 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
12163 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
12164 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
12165 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
12166 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
12167 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
12168 
12169 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
12170 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
12171 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
12172 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
12173 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
12174 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
12175 
12176 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
12177 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
12178 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
12179 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
12180 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
12181 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
12182 
12183 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
12184 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
12185 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
12186 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
12187 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
12188 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
12189 
12190 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
12191 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
12192 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
12193 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
12194 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
12195 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
12196 
12197 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
12198 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
12199 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
12200 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
12201 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
12202 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
12203 
12204 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
12205 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
12206 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
12207 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
12208 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
12209 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
12210 
12211 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
12212 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
12213 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12214 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12215 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12216 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
12217 
12218 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
12219 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
12220 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
12221 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
12222 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
12223 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
12224 
12225 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
12226 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
12227 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
12228 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
12229 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
12230 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
12231 
12232 /* Bit 2 : Write '1' to disable interrupt for event DONE */
12233 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
12234 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
12235 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
12236 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
12237 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
12238 
12239 /* Bit 1 : Write '1' to disable interrupt for event END */
12240 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
12241 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
12242 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12243 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12244 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
12245 
12246 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
12247 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
12248 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
12249 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
12250 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
12251 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
12252 
12253 /* Register: SAADC_STATUS */
12254 /* Description: Status */
12255 
12256 /* Bit 0 : Status */
12257 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
12258 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
12259 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< SAADC is ready. No on-going conversions. */
12260 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< SAADC is busy. Conversion in progress. */
12261 
12262 /* Register: SAADC_ENABLE */
12263 /* Description: Enable or disable SAADC */
12264 
12265 /* Bit 0 : Enable or disable SAADC */
12266 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12267 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12268 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SAADC */
12269 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */
12270 
12271 /* Register: SAADC_CH_PSELP */
12272 /* Description: Description cluster: Input positive pin selection for CH[n] */
12273 
12274 /* Bits 4..0 : Analog positive input channel */
12275 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
12276 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
12277 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
12278 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
12279 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
12280 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
12281 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
12282 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
12283 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
12284 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
12285 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
12286 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
12287 #define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */
12288 
12289 /* Register: SAADC_CH_PSELN */
12290 /* Description: Description cluster: Input negative pin selection for CH[n] */
12291 
12292 /* Bits 4..0 : Analog negative input, enables differential channel */
12293 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
12294 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
12295 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
12296 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
12297 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
12298 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
12299 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
12300 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
12301 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
12302 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
12303 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
12304 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
12305 #define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */
12306 
12307 /* Register: SAADC_CH_CONFIG */
12308 /* Description: Description cluster: Input configuration for CH[n] */
12309 
12310 /* Bit 24 : Enable burst mode */
12311 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
12312 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
12313 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
12314 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
12315 
12316 /* Bit 20 : Enable differential mode */
12317 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
12318 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
12319 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND */
12320 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
12321 
12322 /* Bits 18..16 : Acquisition time, the time the SAADC uses to sample the input voltage */
12323 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
12324 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
12325 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
12326 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
12327 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
12328 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
12329 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
12330 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
12331 
12332 /* Bit 12 : Reference control */
12333 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
12334 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
12335 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
12336 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
12337 
12338 /* Bits 10..8 : Gain control */
12339 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
12340 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
12341 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
12342 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
12343 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
12344 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
12345 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
12346 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
12347 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
12348 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
12349 
12350 /* Bits 5..4 : Negative channel resistor control */
12351 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
12352 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
12353 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
12354 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
12355 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
12356 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
12357 
12358 /* Bits 1..0 : Positive channel resistor control */
12359 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
12360 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
12361 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
12362 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
12363 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
12364 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
12365 
12366 /* Register: SAADC_CH_LIMIT */
12367 /* Description: Description cluster: High/low limits for event monitoring of a channel */
12368 
12369 /* Bits 31..16 : High level limit */
12370 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
12371 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
12372 
12373 /* Bits 15..0 : Low level limit */
12374 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
12375 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
12376 
12377 /* Register: SAADC_RESOLUTION */
12378 /* Description: Resolution configuration */
12379 
12380 /* Bits 2..0 : Set the resolution */
12381 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
12382 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
12383 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bits */
12384 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bits */
12385 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bits */
12386 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bits */
12387 
12388 /* Register: SAADC_OVERSAMPLE */
12389 /* Description: Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
12390 
12391 /* Bits 3..0 : Oversample control */
12392 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
12393 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
12394 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
12395 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
12396 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
12397 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
12398 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
12399 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
12400 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
12401 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
12402 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
12403 
12404 /* Register: SAADC_SAMPLERATE */
12405 /* Description: Controls normal or continuous sample rate */
12406 
12407 /* Bit 12 : Select mode for sample rate control */
12408 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
12409 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
12410 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
12411 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
12412 
12413 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
12414 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
12415 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
12416 
12417 /* Register: SAADC_RESULT_PTR */
12418 /* Description: Data pointer */
12419 
12420 /* Bits 31..0 : Data pointer */
12421 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12422 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12423 
12424 /* Register: SAADC_RESULT_MAXCNT */
12425 /* Description: Maximum number of 16-bit samples to be written to output RAM buffer */
12426 
12427 /* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */
12428 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12429 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12430 
12431 /* Register: SAADC_RESULT_AMOUNT */
12432 /* Description: Number of 16-bit samples written to output RAM buffer since the previous START task */
12433 
12434 /* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. */
12435 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12436 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12437 
12438 
12439 /* Peripheral: SPI */
12440 /* Description: Serial Peripheral Interface 0 */
12441 
12442 /* Register: SPI_EVENTS_READY */
12443 /* Description: TXD byte sent and RXD byte received */
12444 
12445 /* Bit 0 : TXD byte sent and RXD byte received */
12446 #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
12447 #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
12448 #define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
12449 #define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
12450 
12451 /* Register: SPI_INTENSET */
12452 /* Description: Enable interrupt */
12453 
12454 /* Bit 2 : Write '1' to enable interrupt for event READY */
12455 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
12456 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
12457 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
12458 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
12459 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
12460 
12461 /* Register: SPI_INTENCLR */
12462 /* Description: Disable interrupt */
12463 
12464 /* Bit 2 : Write '1' to disable interrupt for event READY */
12465 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
12466 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
12467 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
12468 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
12469 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
12470 
12471 /* Register: SPI_ENABLE */
12472 /* Description: Enable SPI */
12473 
12474 /* Bits 3..0 : Enable or disable SPI */
12475 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12476 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12477 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
12478 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
12479 
12480 /* Register: SPI_PSEL_SCK */
12481 /* Description: Pin select for SCK */
12482 
12483 /* Bit 31 : Connection */
12484 #define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12485 #define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12486 #define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
12487 #define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
12488 
12489 /* Bit 5 : Port number */
12490 #define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
12491 #define SPI_PSEL_SCK_PORT_Msk (0x1UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
12492 
12493 /* Bits 4..0 : Pin number */
12494 #define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
12495 #define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
12496 
12497 /* Register: SPI_PSEL_MOSI */
12498 /* Description: Pin select for MOSI signal */
12499 
12500 /* Bit 31 : Connection */
12501 #define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12502 #define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12503 #define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
12504 #define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
12505 
12506 /* Bit 5 : Port number */
12507 #define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
12508 #define SPI_PSEL_MOSI_PORT_Msk (0x1UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
12509 
12510 /* Bits 4..0 : Pin number */
12511 #define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
12512 #define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
12513 
12514 /* Register: SPI_PSEL_MISO */
12515 /* Description: Pin select for MISO signal */
12516 
12517 /* Bit 31 : Connection */
12518 #define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12519 #define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12520 #define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
12521 #define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
12522 
12523 /* Bit 5 : Port number */
12524 #define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
12525 #define SPI_PSEL_MISO_PORT_Msk (0x1UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
12526 
12527 /* Bits 4..0 : Pin number */
12528 #define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
12529 #define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
12530 
12531 /* Register: SPI_RXD */
12532 /* Description: RXD register */
12533 
12534 /* Bits 7..0 : RX data received. Double buffered */
12535 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
12536 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
12537 
12538 /* Register: SPI_TXD */
12539 /* Description: TXD register */
12540 
12541 /* Bits 7..0 : TX data to send. Double buffered. */
12542 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
12543 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
12544 
12545 /* Register: SPI_FREQUENCY */
12546 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
12547 
12548 /* Bits 31..0 : SPI master data rate */
12549 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
12550 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
12551 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
12552 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
12553 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
12554 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
12555 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
12556 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
12557 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
12558 
12559 /* Register: SPI_CONFIG */
12560 /* Description: Configuration register */
12561 
12562 /* Bit 2 : Serial clock (SCK) polarity */
12563 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12564 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
12565 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12566 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
12567 
12568 /* Bit 1 : Serial clock (SCK) phase */
12569 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
12570 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
12571 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
12572 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
12573 
12574 /* Bit 0 : Bit order */
12575 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
12576 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
12577 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
12578 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
12579 
12580 
12581 /* Peripheral: SPIM */
12582 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
12583 
12584 /* Register: SPIM_TASKS_START */
12585 /* Description: Start SPI transaction */
12586 
12587 /* Bit 0 : Start SPI transaction */
12588 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
12589 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
12590 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
12591 
12592 /* Register: SPIM_TASKS_STOP */
12593 /* Description: Stop SPI transaction */
12594 
12595 /* Bit 0 : Stop SPI transaction */
12596 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12597 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12598 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
12599 
12600 /* Register: SPIM_TASKS_SUSPEND */
12601 /* Description: Suspend SPI transaction */
12602 
12603 /* Bit 0 : Suspend SPI transaction */
12604 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
12605 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
12606 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
12607 
12608 /* Register: SPIM_TASKS_RESUME */
12609 /* Description: Resume SPI transaction */
12610 
12611 /* Bit 0 : Resume SPI transaction */
12612 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
12613 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
12614 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
12615 
12616 /* Register: SPIM_EVENTS_STOPPED */
12617 /* Description: SPI transaction has stopped */
12618 
12619 /* Bit 0 : SPI transaction has stopped */
12620 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
12621 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
12622 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
12623 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
12624 
12625 /* Register: SPIM_EVENTS_ENDRX */
12626 /* Description: End of RXD buffer reached */
12627 
12628 /* Bit 0 : End of RXD buffer reached */
12629 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
12630 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
12631 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
12632 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
12633 
12634 /* Register: SPIM_EVENTS_END */
12635 /* Description: End of RXD buffer and TXD buffer reached */
12636 
12637 /* Bit 0 : End of RXD buffer and TXD buffer reached */
12638 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
12639 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
12640 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
12641 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
12642 
12643 /* Register: SPIM_EVENTS_ENDTX */
12644 /* Description: End of TXD buffer reached */
12645 
12646 /* Bit 0 : End of TXD buffer reached */
12647 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
12648 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
12649 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
12650 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
12651 
12652 /* Register: SPIM_EVENTS_STARTED */
12653 /* Description: Transaction started */
12654 
12655 /* Bit 0 : Transaction started */
12656 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
12657 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
12658 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
12659 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
12660 
12661 /* Register: SPIM_SHORTS */
12662 /* Description: Shortcuts between local events and tasks */
12663 
12664 /* Bit 17 : Shortcut between event END and task START */
12665 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
12666 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
12667 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
12668 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
12669 
12670 /* Register: SPIM_INTENSET */
12671 /* Description: Enable interrupt */
12672 
12673 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
12674 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
12675 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
12676 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
12677 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
12678 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
12679 
12680 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
12681 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12682 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12683 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12684 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12685 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
12686 
12687 /* Bit 6 : Write '1' to enable interrupt for event END */
12688 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
12689 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
12690 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12691 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12692 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
12693 
12694 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
12695 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12696 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12697 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12698 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12699 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12700 
12701 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
12702 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12703 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12704 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12705 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12706 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
12707 
12708 /* Register: SPIM_INTENCLR */
12709 /* Description: Disable interrupt */
12710 
12711 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
12712 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
12713 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
12714 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
12715 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
12716 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
12717 
12718 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
12719 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12720 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12721 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12722 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12723 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
12724 
12725 /* Bit 6 : Write '1' to disable interrupt for event END */
12726 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
12727 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
12728 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12729 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12730 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
12731 
12732 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
12733 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12734 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12735 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12736 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12737 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12738 
12739 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
12740 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12741 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12742 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12743 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12744 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
12745 
12746 /* Register: SPIM_STALLSTAT */
12747 /* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. */
12748 
12749 /* Bit 1 : Stall status for EasyDMA RAM writes */
12750 #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */
12751 #define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */
12752 #define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */
12753 #define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */
12754 
12755 /* Bit 0 : Stall status for EasyDMA RAM reads */
12756 #define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */
12757 #define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */
12758 #define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */
12759 #define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */
12760 
12761 /* Register: SPIM_ENABLE */
12762 /* Description: Enable SPIM */
12763 
12764 /* Bits 3..0 : Enable or disable SPIM */
12765 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12766 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12767 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
12768 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
12769 
12770 /* Register: SPIM_PSEL_SCK */
12771 /* Description: Pin select for SCK */
12772 
12773 /* Bit 31 : Connection */
12774 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12775 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12776 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
12777 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
12778 
12779 /* Bit 5 : Port number */
12780 #define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
12781 #define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
12782 
12783 /* Bits 4..0 : Pin number */
12784 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
12785 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
12786 
12787 /* Register: SPIM_PSEL_MOSI */
12788 /* Description: Pin select for MOSI signal */
12789 
12790 /* Bit 31 : Connection */
12791 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12792 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12793 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
12794 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
12795 
12796 /* Bit 5 : Port number */
12797 #define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
12798 #define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
12799 
12800 /* Bits 4..0 : Pin number */
12801 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
12802 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
12803 
12804 /* Register: SPIM_PSEL_MISO */
12805 /* Description: Pin select for MISO signal */
12806 
12807 /* Bit 31 : Connection */
12808 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12809 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12810 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
12811 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
12812 
12813 /* Bit 5 : Port number */
12814 #define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
12815 #define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
12816 
12817 /* Bits 4..0 : Pin number */
12818 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
12819 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
12820 
12821 /* Register: SPIM_PSEL_CSN */
12822 /* Description: Pin select for CSN */
12823 
12824 /* Bit 31 : Connection */
12825 #define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12826 #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12827 #define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
12828 #define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
12829 
12830 /* Bit 5 : Port number */
12831 #define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
12832 #define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
12833 
12834 /* Bits 4..0 : Pin number */
12835 #define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
12836 #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
12837 
12838 /* Register: SPIM_FREQUENCY */
12839 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
12840 
12841 /* Bits 31..0 : SPI master data rate */
12842 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
12843 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
12844 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
12845 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
12846 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
12847 #define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
12848 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
12849 #define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
12850 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
12851 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
12852 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
12853 
12854 /* Register: SPIM_RXD_PTR */
12855 /* Description: Data pointer */
12856 
12857 /* Bits 31..0 : Data pointer */
12858 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12859 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12860 
12861 /* Register: SPIM_RXD_MAXCNT */
12862 /* Description: Maximum number of bytes in receive buffer */
12863 
12864 /* Bits 15..0 : Maximum number of bytes in receive buffer */
12865 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12866 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12867 
12868 /* Register: SPIM_RXD_AMOUNT */
12869 /* Description: Number of bytes transferred in the last transaction */
12870 
12871 /* Bits 15..0 : Number of bytes transferred in the last transaction */
12872 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12873 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12874 
12875 /* Register: SPIM_RXD_LIST */
12876 /* Description: EasyDMA list type */
12877 
12878 /* Bits 1..0 : List type */
12879 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
12880 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
12881 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12882 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
12883 
12884 /* Register: SPIM_TXD_PTR */
12885 /* Description: Data pointer */
12886 
12887 /* Bits 31..0 : Data pointer */
12888 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12889 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12890 
12891 /* Register: SPIM_TXD_MAXCNT */
12892 /* Description: Number of bytes in transmit buffer */
12893 
12894 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
12895 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12896 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12897 
12898 /* Register: SPIM_TXD_AMOUNT */
12899 /* Description: Number of bytes transferred in the last transaction */
12900 
12901 /* Bits 15..0 : Number of bytes transferred in the last transaction */
12902 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12903 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12904 
12905 /* Register: SPIM_TXD_LIST */
12906 /* Description: EasyDMA list type */
12907 
12908 /* Bits 1..0 : List type */
12909 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
12910 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
12911 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12912 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
12913 
12914 /* Register: SPIM_CONFIG */
12915 /* Description: Configuration register */
12916 
12917 /* Bit 2 : Serial clock (SCK) polarity */
12918 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12919 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
12920 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12921 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
12922 
12923 /* Bit 1 : Serial clock (SCK) phase */
12924 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
12925 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
12926 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
12927 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
12928 
12929 /* Bit 0 : Bit order */
12930 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
12931 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
12932 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
12933 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
12934 
12935 /* Register: SPIM_IFTIMING_RXDELAY */
12936 /* Description: Sample delay for input serial data on MISO */
12937 
12938 /* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */
12939 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */
12940 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
12941 
12942 /* Register: SPIM_IFTIMING_CSNDUR */
12943 /* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */
12944 
12945 /* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */
12946 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
12947 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */
12948 
12949 /* Register: SPIM_CSNPOL */
12950 /* Description: Polarity of CSN output */
12951 
12952 /* Bit 0 : Polarity of CSN output */
12953 #define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */
12954 #define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */
12955 #define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */
12956 #define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */
12957 
12958 /* Register: SPIM_PSELDCX */
12959 /* Description: Pin select for DCX signal */
12960 
12961 /* Bit 31 : Connection */
12962 #define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12963 #define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12964 #define SPIM_PSELDCX_CONNECT_Connected (0UL) /*!< Connect */
12965 #define SPIM_PSELDCX_CONNECT_Disconnected (1UL) /*!< Disconnect */
12966 
12967 /* Bit 5 : Port number */
12968 #define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */
12969 #define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */
12970 
12971 /* Bits 4..0 : Pin number */
12972 #define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */
12973 #define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */
12974 
12975 /* Register: SPIM_DCXCNT */
12976 /* Description: DCX configuration */
12977 
12978 /* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */
12979 #define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */
12980 #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */
12981 
12982 /* Register: SPIM_ORC */
12983 /* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
12984 
12985 /* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
12986 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
12987 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
12988 
12989 
12990 /* Peripheral: SPIS */
12991 /* Description: SPI Slave 0 */
12992 
12993 /* Register: SPIS_TASKS_ACQUIRE */
12994 /* Description: Acquire SPI semaphore */
12995 
12996 /* Bit 0 : Acquire SPI semaphore */
12997 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
12998 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
12999 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
13000 
13001 /* Register: SPIS_TASKS_RELEASE */
13002 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
13003 
13004 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
13005 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
13006 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
13007 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
13008 
13009 /* Register: SPIS_EVENTS_END */
13010 /* Description: Granted transaction completed */
13011 
13012 /* Bit 0 : Granted transaction completed */
13013 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
13014 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
13015 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
13016 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
13017 
13018 /* Register: SPIS_EVENTS_ENDRX */
13019 /* Description: End of RXD buffer reached */
13020 
13021 /* Bit 0 : End of RXD buffer reached */
13022 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
13023 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
13024 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
13025 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
13026 
13027 /* Register: SPIS_EVENTS_ACQUIRED */
13028 /* Description: Semaphore acquired */
13029 
13030 /* Bit 0 : Semaphore acquired */
13031 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
13032 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
13033 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
13034 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
13035 
13036 /* Register: SPIS_SHORTS */
13037 /* Description: Shortcuts between local events and tasks */
13038 
13039 /* Bit 2 : Shortcut between event END and task ACQUIRE */
13040 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
13041 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
13042 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
13043 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
13044 
13045 /* Register: SPIS_INTENSET */
13046 /* Description: Enable interrupt */
13047 
13048 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
13049 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
13050 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
13051 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
13052 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
13053 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
13054 
13055 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
13056 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
13057 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
13058 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
13059 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
13060 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
13061 
13062 /* Bit 1 : Write '1' to enable interrupt for event END */
13063 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
13064 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
13065 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
13066 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
13067 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
13068 
13069 /* Register: SPIS_INTENCLR */
13070 /* Description: Disable interrupt */
13071 
13072 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
13073 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
13074 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
13075 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
13076 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
13077 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
13078 
13079 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
13080 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
13081 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
13082 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
13083 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
13084 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
13085 
13086 /* Bit 1 : Write '1' to disable interrupt for event END */
13087 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
13088 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
13089 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
13090 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
13091 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
13092 
13093 /* Register: SPIS_SEMSTAT */
13094 /* Description: Semaphore status register */
13095 
13096 /* Bits 1..0 : Semaphore status */
13097 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
13098 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
13099 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
13100 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
13101 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
13102 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
13103 
13104 /* Register: SPIS_STATUS */
13105 /* Description: Status from last transaction */
13106 
13107 /* Bit 1 : RX buffer overflow detected, and prevented */
13108 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
13109 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
13110 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
13111 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
13112 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
13113 
13114 /* Bit 0 : TX buffer over-read detected, and prevented */
13115 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
13116 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
13117 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
13118 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
13119 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
13120 
13121 /* Register: SPIS_ENABLE */
13122 /* Description: Enable SPI slave */
13123 
13124 /* Bits 3..0 : Enable or disable SPI slave */
13125 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13126 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13127 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
13128 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
13129 
13130 /* Register: SPIS_PSEL_SCK */
13131 /* Description: Pin select for SCK */
13132 
13133 /* Bit 31 : Connection */
13134 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13135 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13136 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
13137 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
13138 
13139 /* Bit 5 : Port number */
13140 #define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
13141 #define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
13142 
13143 /* Bits 4..0 : Pin number */
13144 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
13145 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
13146 
13147 /* Register: SPIS_PSEL_MISO */
13148 /* Description: Pin select for MISO signal */
13149 
13150 /* Bit 31 : Connection */
13151 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13152 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13153 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
13154 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
13155 
13156 /* Bit 5 : Port number */
13157 #define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
13158 #define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
13159 
13160 /* Bits 4..0 : Pin number */
13161 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
13162 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
13163 
13164 /* Register: SPIS_PSEL_MOSI */
13165 /* Description: Pin select for MOSI signal */
13166 
13167 /* Bit 31 : Connection */
13168 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13169 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13170 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
13171 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
13172 
13173 /* Bit 5 : Port number */
13174 #define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
13175 #define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
13176 
13177 /* Bits 4..0 : Pin number */
13178 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
13179 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
13180 
13181 /* Register: SPIS_PSEL_CSN */
13182 /* Description: Pin select for CSN signal */
13183 
13184 /* Bit 31 : Connection */
13185 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13186 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13187 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
13188 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
13189 
13190 /* Bit 5 : Port number */
13191 #define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
13192 #define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
13193 
13194 /* Bits 4..0 : Pin number */
13195 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
13196 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
13197 
13198 /* Register: SPIS_RXD_PTR */
13199 /* Description: RXD data pointer */
13200 
13201 /* Bits 31..0 : RXD data pointer */
13202 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
13203 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
13204 
13205 /* Register: SPIS_RXD_MAXCNT */
13206 /* Description: Maximum number of bytes in receive buffer */
13207 
13208 /* Bits 15..0 : Maximum number of bytes in receive buffer */
13209 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
13210 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
13211 
13212 /* Register: SPIS_RXD_AMOUNT */
13213 /* Description: Number of bytes received in last granted transaction */
13214 
13215 /* Bits 15..0 : Number of bytes received in the last granted transaction */
13216 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
13217 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
13218 
13219 /* Register: SPIS_RXD_LIST */
13220 /* Description: EasyDMA list type */
13221 
13222 /* Bits 1..0 : List type */
13223 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
13224 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
13225 #define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
13226 #define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
13227 
13228 /* Register: SPIS_TXD_PTR */
13229 /* Description: TXD data pointer */
13230 
13231 /* Bits 31..0 : TXD data pointer */
13232 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
13233 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
13234 
13235 /* Register: SPIS_TXD_MAXCNT */
13236 /* Description: Maximum number of bytes in transmit buffer */
13237 
13238 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
13239 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
13240 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
13241 
13242 /* Register: SPIS_TXD_AMOUNT */
13243 /* Description: Number of bytes transmitted in last granted transaction */
13244 
13245 /* Bits 15..0 : Number of bytes transmitted in last granted transaction */
13246 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
13247 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
13248 
13249 /* Register: SPIS_TXD_LIST */
13250 /* Description: EasyDMA list type */
13251 
13252 /* Bits 1..0 : List type */
13253 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
13254 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
13255 #define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
13256 #define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
13257 
13258 /* Register: SPIS_CONFIG */
13259 /* Description: Configuration register */
13260 
13261 /* Bit 2 : Serial clock (SCK) polarity */
13262 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
13263 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
13264 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
13265 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
13266 
13267 /* Bit 1 : Serial clock (SCK) phase */
13268 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
13269 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
13270 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
13271 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
13272 
13273 /* Bit 0 : Bit order */
13274 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
13275 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
13276 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
13277 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
13278 
13279 /* Register: SPIS_DEF */
13280 /* Description: Default character. Character clocked out in case of an ignored transaction. */
13281 
13282 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
13283 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
13284 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
13285 
13286 /* Register: SPIS_ORC */
13287 /* Description: Over-read character */
13288 
13289 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
13290 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
13291 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
13292 
13293 
13294 /* Peripheral: TEMP */
13295 /* Description: Temperature Sensor */
13296 
13297 /* Register: TEMP_TASKS_START */
13298 /* Description: Start temperature measurement */
13299 
13300 /* Bit 0 : Start temperature measurement */
13301 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
13302 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
13303 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
13304 
13305 /* Register: TEMP_TASKS_STOP */
13306 /* Description: Stop temperature measurement */
13307 
13308 /* Bit 0 : Stop temperature measurement */
13309 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
13310 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
13311 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
13312 
13313 /* Register: TEMP_EVENTS_DATARDY */
13314 /* Description: Temperature measurement complete, data ready */
13315 
13316 /* Bit 0 : Temperature measurement complete, data ready */
13317 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
13318 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
13319 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
13320 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
13321 
13322 /* Register: TEMP_INTENSET */
13323 /* Description: Enable interrupt */
13324 
13325 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */
13326 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
13327 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
13328 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
13329 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
13330 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
13331 
13332 /* Register: TEMP_INTENCLR */
13333 /* Description: Disable interrupt */
13334 
13335 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */
13336 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
13337 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
13338 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
13339 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
13340 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
13341 
13342 /* Register: TEMP_TEMP */
13343 /* Description: Temperature in degC (0.25deg steps) */
13344 
13345 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
13346 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
13347 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
13348 
13349 /* Register: TEMP_A0 */
13350 /* Description: Slope of first piecewise linear function */
13351 
13352 /* Bits 11..0 : Slope of first piecewise linear function */
13353 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
13354 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
13355 
13356 /* Register: TEMP_A1 */
13357 /* Description: Slope of second piecewise linear function */
13358 
13359 /* Bits 11..0 : Slope of second piecewise linear function */
13360 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
13361 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
13362 
13363 /* Register: TEMP_A2 */
13364 /* Description: Slope of third piecewise linear function */
13365 
13366 /* Bits 11..0 : Slope of third piecewise linear function */
13367 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
13368 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
13369 
13370 /* Register: TEMP_A3 */
13371 /* Description: Slope of fourth piecewise linear function */
13372 
13373 /* Bits 11..0 : Slope of fourth piecewise linear function */
13374 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
13375 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
13376 
13377 /* Register: TEMP_A4 */
13378 /* Description: Slope of fifth piecewise linear function */
13379 
13380 /* Bits 11..0 : Slope of fifth piecewise linear function */
13381 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
13382 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
13383 
13384 /* Register: TEMP_A5 */
13385 /* Description: Slope of sixth piecewise linear function */
13386 
13387 /* Bits 11..0 : Slope of sixth piecewise linear function */
13388 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
13389 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
13390 
13391 /* Register: TEMP_B0 */
13392 /* Description: y-intercept of first piecewise linear function */
13393 
13394 /* Bits 13..0 : y-intercept of first piecewise linear function */
13395 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
13396 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
13397 
13398 /* Register: TEMP_B1 */
13399 /* Description: y-intercept of second piecewise linear function */
13400 
13401 /* Bits 13..0 : y-intercept of second piecewise linear function */
13402 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
13403 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
13404 
13405 /* Register: TEMP_B2 */
13406 /* Description: y-intercept of third piecewise linear function */
13407 
13408 /* Bits 13..0 : y-intercept of third piecewise linear function */
13409 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
13410 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
13411 
13412 /* Register: TEMP_B3 */
13413 /* Description: y-intercept of fourth piecewise linear function */
13414 
13415 /* Bits 13..0 : y-intercept of fourth piecewise linear function */
13416 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
13417 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
13418 
13419 /* Register: TEMP_B4 */
13420 /* Description: y-intercept of fifth piecewise linear function */
13421 
13422 /* Bits 13..0 : y-intercept of fifth piecewise linear function */
13423 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
13424 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
13425 
13426 /* Register: TEMP_B5 */
13427 /* Description: y-intercept of sixth piecewise linear function */
13428 
13429 /* Bits 13..0 : y-intercept of sixth piecewise linear function */
13430 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
13431 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
13432 
13433 /* Register: TEMP_T0 */
13434 /* Description: End point of first piecewise linear function */
13435 
13436 /* Bits 7..0 : End point of first piecewise linear function */
13437 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
13438 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
13439 
13440 /* Register: TEMP_T1 */
13441 /* Description: End point of second piecewise linear function */
13442 
13443 /* Bits 7..0 : End point of second piecewise linear function */
13444 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
13445 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
13446 
13447 /* Register: TEMP_T2 */
13448 /* Description: End point of third piecewise linear function */
13449 
13450 /* Bits 7..0 : End point of third piecewise linear function */
13451 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
13452 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
13453 
13454 /* Register: TEMP_T3 */
13455 /* Description: End point of fourth piecewise linear function */
13456 
13457 /* Bits 7..0 : End point of fourth piecewise linear function */
13458 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
13459 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
13460 
13461 /* Register: TEMP_T4 */
13462 /* Description: End point of fifth piecewise linear function */
13463 
13464 /* Bits 7..0 : End point of fifth piecewise linear function */
13465 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
13466 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
13467 
13468 
13469 /* Peripheral: TIMER */
13470 /* Description: Timer/Counter 0 */
13471 
13472 /* Register: TIMER_TASKS_START */
13473 /* Description: Start Timer */
13474 
13475 /* Bit 0 : Start Timer */
13476 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
13477 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
13478 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
13479 
13480 /* Register: TIMER_TASKS_STOP */
13481 /* Description: Stop Timer */
13482 
13483 /* Bit 0 : Stop Timer */
13484 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
13485 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
13486 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
13487 
13488 /* Register: TIMER_TASKS_COUNT */
13489 /* Description: Increment Timer (Counter mode only) */
13490 
13491 /* Bit 0 : Increment Timer (Counter mode only) */
13492 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
13493 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
13494 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
13495 
13496 /* Register: TIMER_TASKS_CLEAR */
13497 /* Description: Clear time */
13498 
13499 /* Bit 0 : Clear time */
13500 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
13501 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
13502 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
13503 
13504 /* Register: TIMER_TASKS_SHUTDOWN */
13505 /* Description: Deprecated register - Shut down timer */
13506 
13507 /* Bit 0 : Deprecated field -  Shut down timer */
13508 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
13509 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
13510 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
13511 
13512 /* Register: TIMER_TASKS_CAPTURE */
13513 /* Description: Description collection: Capture Timer value to CC[n] register */
13514 
13515 /* Bit 0 : Capture Timer value to CC[n] register */
13516 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
13517 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
13518 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
13519 
13520 /* Register: TIMER_EVENTS_COMPARE */
13521 /* Description: Description collection: Compare event on CC[n] match */
13522 
13523 /* Bit 0 : Compare event on CC[n] match */
13524 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
13525 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
13526 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
13527 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
13528 
13529 /* Register: TIMER_SHORTS */
13530 /* Description: Shortcuts between local events and tasks */
13531 
13532 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
13533 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
13534 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
13535 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
13536 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
13537 
13538 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
13539 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
13540 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
13541 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
13542 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
13543 
13544 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
13545 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
13546 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
13547 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
13548 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
13549 
13550 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
13551 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
13552 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
13553 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
13554 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
13555 
13556 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
13557 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
13558 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
13559 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
13560 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
13561 
13562 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
13563 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
13564 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
13565 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
13566 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
13567 
13568 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
13569 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
13570 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
13571 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13572 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13573 
13574 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
13575 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
13576 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
13577 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13578 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13579 
13580 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
13581 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
13582 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
13583 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13584 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13585 
13586 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
13587 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
13588 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
13589 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13590 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13591 
13592 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
13593 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
13594 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
13595 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13596 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13597 
13598 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
13599 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
13600 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
13601 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
13602 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
13603 
13604 /* Register: TIMER_INTENSET */
13605 /* Description: Enable interrupt */
13606 
13607 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
13608 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
13609 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
13610 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
13611 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
13612 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
13613 
13614 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
13615 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
13616 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
13617 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
13618 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
13619 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
13620 
13621 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
13622 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13623 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13624 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
13625 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
13626 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
13627 
13628 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
13629 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13630 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13631 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
13632 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
13633 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
13634 
13635 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
13636 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13637 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13638 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
13639 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
13640 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
13641 
13642 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
13643 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13644 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13645 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
13646 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
13647 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
13648 
13649 /* Register: TIMER_INTENCLR */
13650 /* Description: Disable interrupt */
13651 
13652 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
13653 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
13654 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
13655 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
13656 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
13657 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
13658 
13659 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
13660 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
13661 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
13662 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
13663 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
13664 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
13665 
13666 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
13667 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
13668 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
13669 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
13670 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
13671 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
13672 
13673 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
13674 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
13675 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
13676 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
13677 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
13678 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
13679 
13680 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
13681 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
13682 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
13683 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
13684 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
13685 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
13686 
13687 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
13688 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
13689 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
13690 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
13691 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
13692 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
13693 
13694 /* Register: TIMER_MODE */
13695 /* Description: Timer mode selection */
13696 
13697 /* Bits 1..0 : Timer mode */
13698 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
13699 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
13700 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
13701 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
13702 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
13703 
13704 /* Register: TIMER_BITMODE */
13705 /* Description: Configure the number of bits used by the TIMER */
13706 
13707 /* Bits 1..0 : Timer bit width */
13708 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
13709 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
13710 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
13711 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
13712 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
13713 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
13714 
13715 /* Register: TIMER_PRESCALER */
13716 /* Description: Timer prescaler register */
13717 
13718 /* Bits 3..0 : Prescaler value */
13719 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
13720 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
13721 
13722 /* Register: TIMER_CC */
13723 /* Description: Description collection: Capture/Compare register n */
13724 
13725 /* Bits 31..0 : Capture/Compare value */
13726 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
13727 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
13728 
13729 
13730 /* Peripheral: TWI */
13731 /* Description: I2C compatible Two-Wire Interface 0 */
13732 
13733 /* Register: TWI_TASKS_STARTRX */
13734 /* Description: Start TWI receive sequence */
13735 
13736 /* Bit 0 : Start TWI receive sequence */
13737 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
13738 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
13739 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
13740 
13741 /* Register: TWI_TASKS_STARTTX */
13742 /* Description: Start TWI transmit sequence */
13743 
13744 /* Bit 0 : Start TWI transmit sequence */
13745 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
13746 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
13747 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
13748 
13749 /* Register: TWI_TASKS_STOP */
13750 /* Description: Stop TWI transaction */
13751 
13752 /* Bit 0 : Stop TWI transaction */
13753 #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
13754 #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
13755 #define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
13756 
13757 /* Register: TWI_TASKS_SUSPEND */
13758 /* Description: Suspend TWI transaction */
13759 
13760 /* Bit 0 : Suspend TWI transaction */
13761 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
13762 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
13763 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
13764 
13765 /* Register: TWI_TASKS_RESUME */
13766 /* Description: Resume TWI transaction */
13767 
13768 /* Bit 0 : Resume TWI transaction */
13769 #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
13770 #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
13771 #define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
13772 
13773 /* Register: TWI_EVENTS_STOPPED */
13774 /* Description: TWI stopped */
13775 
13776 /* Bit 0 : TWI stopped */
13777 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
13778 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
13779 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
13780 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
13781 
13782 /* Register: TWI_EVENTS_RXDREADY */
13783 /* Description: TWI RXD byte received */
13784 
13785 /* Bit 0 : TWI RXD byte received */
13786 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */
13787 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */
13788 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */
13789 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */
13790 
13791 /* Register: TWI_EVENTS_TXDSENT */
13792 /* Description: TWI TXD byte sent */
13793 
13794 /* Bit 0 : TWI TXD byte sent */
13795 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */
13796 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */
13797 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */
13798 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */
13799 
13800 /* Register: TWI_EVENTS_ERROR */
13801 /* Description: TWI error */
13802 
13803 /* Bit 0 : TWI error */
13804 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
13805 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
13806 #define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
13807 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
13808 
13809 /* Register: TWI_EVENTS_BB */
13810 /* Description: TWI byte boundary, generated before each byte that is sent or received */
13811 
13812 /* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */
13813 #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */
13814 #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */
13815 #define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */
13816 #define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */
13817 
13818 /* Register: TWI_EVENTS_SUSPENDED */
13819 /* Description: TWI entered the suspended state */
13820 
13821 /* Bit 0 : TWI entered the suspended state */
13822 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
13823 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
13824 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
13825 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
13826 
13827 /* Register: TWI_SHORTS */
13828 /* Description: Shortcuts between local events and tasks */
13829 
13830 /* Bit 1 : Shortcut between event BB and task STOP */
13831 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
13832 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
13833 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
13834 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
13835 
13836 /* Bit 0 : Shortcut between event BB and task SUSPEND */
13837 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
13838 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
13839 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
13840 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
13841 
13842 /* Register: TWI_INTENSET */
13843 /* Description: Enable interrupt */
13844 
13845 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
13846 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
13847 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
13848 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13849 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13850 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
13851 
13852 /* Bit 14 : Write '1' to enable interrupt for event BB */
13853 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
13854 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
13855 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
13856 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
13857 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
13858 
13859 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
13860 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13861 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
13862 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13863 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13864 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
13865 
13866 /* Bit 7 : Write '1' to enable interrupt for event TXDSENT */
13867 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
13868 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
13869 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
13870 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
13871 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
13872 
13873 /* Bit 2 : Write '1' to enable interrupt for event RXDREADY */
13874 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
13875 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
13876 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
13877 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
13878 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
13879 
13880 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
13881 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13882 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13883 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13884 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13885 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
13886 
13887 /* Register: TWI_INTENCLR */
13888 /* Description: Disable interrupt */
13889 
13890 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
13891 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
13892 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
13893 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13894 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13895 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
13896 
13897 /* Bit 14 : Write '1' to disable interrupt for event BB */
13898 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
13899 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
13900 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
13901 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
13902 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
13903 
13904 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
13905 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13906 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
13907 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13908 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13909 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
13910 
13911 /* Bit 7 : Write '1' to disable interrupt for event TXDSENT */
13912 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
13913 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
13914 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
13915 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
13916 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
13917 
13918 /* Bit 2 : Write '1' to disable interrupt for event RXDREADY */
13919 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
13920 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
13921 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
13922 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
13923 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
13924 
13925 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
13926 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13927 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13928 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13929 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13930 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
13931 
13932 /* Register: TWI_ERRORSRC */
13933 /* Description: Error source */
13934 
13935 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
13936 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
13937 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
13938 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
13939 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
13940 
13941 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
13942 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
13943 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
13944 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
13945 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
13946 
13947 /* Bit 0 : Overrun error */
13948 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
13949 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
13950 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
13951 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
13952 
13953 /* Register: TWI_ENABLE */
13954 /* Description: Enable TWI */
13955 
13956 /* Bits 3..0 : Enable or disable TWI */
13957 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13958 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13959 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
13960 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
13961 
13962 /* Register: TWI_PSEL_SCL */
13963 /* Description: Pin select for SCL */
13964 
13965 /* Bit 31 : Connection */
13966 #define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13967 #define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13968 #define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
13969 #define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
13970 
13971 /* Bit 5 : Port number */
13972 #define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
13973 #define TWI_PSEL_SCL_PORT_Msk (0x1UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
13974 
13975 /* Bits 4..0 : Pin number */
13976 #define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
13977 #define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
13978 
13979 /* Register: TWI_PSEL_SDA */
13980 /* Description: Pin select for SDA */
13981 
13982 /* Bit 31 : Connection */
13983 #define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13984 #define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13985 #define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
13986 #define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
13987 
13988 /* Bit 5 : Port number */
13989 #define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
13990 #define TWI_PSEL_SDA_PORT_Msk (0x1UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
13991 
13992 /* Bits 4..0 : Pin number */
13993 #define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
13994 #define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
13995 
13996 /* Register: TWI_RXD */
13997 /* Description: RXD register */
13998 
13999 /* Bits 7..0 : RXD register */
14000 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
14001 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
14002 
14003 /* Register: TWI_TXD */
14004 /* Description: TXD register */
14005 
14006 /* Bits 7..0 : TXD register */
14007 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
14008 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
14009 
14010 /* Register: TWI_FREQUENCY */
14011 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
14012 
14013 /* Bits 31..0 : TWI master clock frequency */
14014 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
14015 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
14016 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
14017 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
14018 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
14019 
14020 /* Register: TWI_ADDRESS */
14021 /* Description: Address used in the TWI transfer */
14022 
14023 /* Bits 6..0 : Address used in the TWI transfer */
14024 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
14025 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
14026 
14027 
14028 /* Peripheral: TWIM */
14029 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
14030 
14031 /* Register: TWIM_TASKS_STARTRX */
14032 /* Description: Start TWI receive sequence */
14033 
14034 /* Bit 0 : Start TWI receive sequence */
14035 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
14036 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
14037 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
14038 
14039 /* Register: TWIM_TASKS_STARTTX */
14040 /* Description: Start TWI transmit sequence */
14041 
14042 /* Bit 0 : Start TWI transmit sequence */
14043 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
14044 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
14045 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
14046 
14047 /* Register: TWIM_TASKS_STOP */
14048 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
14049 
14050 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
14051 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
14052 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
14053 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
14054 
14055 /* Register: TWIM_TASKS_SUSPEND */
14056 /* Description: Suspend TWI transaction */
14057 
14058 /* Bit 0 : Suspend TWI transaction */
14059 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
14060 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
14061 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
14062 
14063 /* Register: TWIM_TASKS_RESUME */
14064 /* Description: Resume TWI transaction */
14065 
14066 /* Bit 0 : Resume TWI transaction */
14067 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
14068 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
14069 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
14070 
14071 /* Register: TWIM_EVENTS_STOPPED */
14072 /* Description: TWI stopped */
14073 
14074 /* Bit 0 : TWI stopped */
14075 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
14076 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
14077 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
14078 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
14079 
14080 /* Register: TWIM_EVENTS_ERROR */
14081 /* Description: TWI error */
14082 
14083 /* Bit 0 : TWI error */
14084 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14085 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14086 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
14087 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
14088 
14089 /* Register: TWIM_EVENTS_SUSPENDED */
14090 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
14091 
14092 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
14093 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
14094 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
14095 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
14096 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
14097 
14098 /* Register: TWIM_EVENTS_RXSTARTED */
14099 /* Description: Receive sequence started */
14100 
14101 /* Bit 0 : Receive sequence started */
14102 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
14103 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
14104 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14105 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
14106 
14107 /* Register: TWIM_EVENTS_TXSTARTED */
14108 /* Description: Transmit sequence started */
14109 
14110 /* Bit 0 : Transmit sequence started */
14111 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
14112 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
14113 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14114 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
14115 
14116 /* Register: TWIM_EVENTS_LASTRX */
14117 /* Description: Byte boundary, starting to receive the last byte */
14118 
14119 /* Bit 0 : Byte boundary, starting to receive the last byte */
14120 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
14121 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
14122 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
14123 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
14124 
14125 /* Register: TWIM_EVENTS_LASTTX */
14126 /* Description: Byte boundary, starting to transmit the last byte */
14127 
14128 /* Bit 0 : Byte boundary, starting to transmit the last byte */
14129 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
14130 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
14131 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
14132 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
14133 
14134 /* Register: TWIM_SHORTS */
14135 /* Description: Shortcuts between local events and tasks */
14136 
14137 /* Bit 12 : Shortcut between event LASTRX and task STOP */
14138 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
14139 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
14140 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
14141 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
14142 
14143 /* Bit 11 : Shortcut between event LASTRX and task SUSPEND */
14144 #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */
14145 #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */
14146 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
14147 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
14148 
14149 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
14150 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
14151 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
14152 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
14153 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
14154 
14155 /* Bit 9 : Shortcut between event LASTTX and task STOP */
14156 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
14157 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
14158 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
14159 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
14160 
14161 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
14162 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
14163 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
14164 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
14165 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
14166 
14167 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
14168 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
14169 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
14170 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
14171 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
14172 
14173 /* Register: TWIM_INTEN */
14174 /* Description: Enable or disable interrupt */
14175 
14176 /* Bit 24 : Enable or disable interrupt for event LASTTX */
14177 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
14178 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
14179 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
14180 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
14181 
14182 /* Bit 23 : Enable or disable interrupt for event LASTRX */
14183 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
14184 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
14185 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
14186 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
14187 
14188 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
14189 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14190 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14191 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
14192 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
14193 
14194 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
14195 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14196 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14197 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
14198 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
14199 
14200 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
14201 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
14202 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
14203 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
14204 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
14205 
14206 /* Bit 9 : Enable or disable interrupt for event ERROR */
14207 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14208 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
14209 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
14210 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
14211 
14212 /* Bit 1 : Enable or disable interrupt for event STOPPED */
14213 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14214 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14215 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
14216 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
14217 
14218 /* Register: TWIM_INTENSET */
14219 /* Description: Enable interrupt */
14220 
14221 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
14222 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
14223 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
14224 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
14225 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
14226 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
14227 
14228 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
14229 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
14230 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
14231 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
14232 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
14233 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
14234 
14235 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
14236 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14237 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14238 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14239 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14240 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
14241 
14242 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
14243 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14244 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14245 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14246 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14247 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
14248 
14249 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
14250 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
14251 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
14252 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
14253 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
14254 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
14255 
14256 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
14257 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14258 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
14259 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14260 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14261 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
14262 
14263 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
14264 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14265 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14266 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14267 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14268 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
14269 
14270 /* Register: TWIM_INTENCLR */
14271 /* Description: Disable interrupt */
14272 
14273 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
14274 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
14275 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
14276 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
14277 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
14278 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
14279 
14280 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
14281 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
14282 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
14283 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
14284 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
14285 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
14286 
14287 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
14288 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14289 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14290 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14291 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14292 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
14293 
14294 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
14295 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14296 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14297 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14298 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14299 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
14300 
14301 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
14302 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
14303 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
14304 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
14305 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
14306 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
14307 
14308 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
14309 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14310 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
14311 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14312 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14313 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
14314 
14315 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
14316 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14317 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14318 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14319 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14320 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
14321 
14322 /* Register: TWIM_ERRORSRC */
14323 /* Description: Error source */
14324 
14325 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
14326 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
14327 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
14328 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
14329 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
14330 
14331 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
14332 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
14333 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
14334 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
14335 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
14336 
14337 /* Bit 0 : Overrun error */
14338 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
14339 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
14340 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
14341 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
14342 
14343 /* Register: TWIM_ENABLE */
14344 /* Description: Enable TWIM */
14345 
14346 /* Bits 3..0 : Enable or disable TWIM */
14347 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14348 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14349 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
14350 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
14351 
14352 /* Register: TWIM_PSEL_SCL */
14353 /* Description: Pin select for SCL signal */
14354 
14355 /* Bit 31 : Connection */
14356 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14357 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14358 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
14359 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
14360 
14361 /* Bit 5 : Port number */
14362 #define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
14363 #define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
14364 
14365 /* Bits 4..0 : Pin number */
14366 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
14367 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
14368 
14369 /* Register: TWIM_PSEL_SDA */
14370 /* Description: Pin select for SDA signal */
14371 
14372 /* Bit 31 : Connection */
14373 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14374 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14375 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
14376 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
14377 
14378 /* Bit 5 : Port number */
14379 #define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
14380 #define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
14381 
14382 /* Bits 4..0 : Pin number */
14383 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
14384 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
14385 
14386 /* Register: TWIM_FREQUENCY */
14387 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
14388 
14389 /* Bits 31..0 : TWI master clock frequency */
14390 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
14391 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
14392 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
14393 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
14394 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
14395 
14396 /* Register: TWIM_RXD_PTR */
14397 /* Description: Data pointer */
14398 
14399 /* Bits 31..0 : Data pointer */
14400 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14401 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14402 
14403 /* Register: TWIM_RXD_MAXCNT */
14404 /* Description: Maximum number of bytes in receive buffer */
14405 
14406 /* Bits 15..0 : Maximum number of bytes in receive buffer */
14407 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14408 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14409 
14410 /* Register: TWIM_RXD_AMOUNT */
14411 /* Description: Number of bytes transferred in the last transaction */
14412 
14413 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
14414 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14415 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14416 
14417 /* Register: TWIM_RXD_LIST */
14418 /* Description: EasyDMA list type */
14419 
14420 /* Bits 2..0 : List type */
14421 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14422 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14423 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14424 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
14425 
14426 /* Register: TWIM_TXD_PTR */
14427 /* Description: Data pointer */
14428 
14429 /* Bits 31..0 : Data pointer */
14430 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14431 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14432 
14433 /* Register: TWIM_TXD_MAXCNT */
14434 /* Description: Maximum number of bytes in transmit buffer */
14435 
14436 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
14437 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14438 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14439 
14440 /* Register: TWIM_TXD_AMOUNT */
14441 /* Description: Number of bytes transferred in the last transaction */
14442 
14443 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
14444 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14445 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14446 
14447 /* Register: TWIM_TXD_LIST */
14448 /* Description: EasyDMA list type */
14449 
14450 /* Bits 2..0 : List type */
14451 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14452 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14453 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14454 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
14455 
14456 /* Register: TWIM_ADDRESS */
14457 /* Description: Address used in the TWI transfer */
14458 
14459 /* Bits 6..0 : Address used in the TWI transfer */
14460 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
14461 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
14462 
14463 
14464 /* Peripheral: TWIS */
14465 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
14466 
14467 /* Register: TWIS_TASKS_STOP */
14468 /* Description: Stop TWI transaction */
14469 
14470 /* Bit 0 : Stop TWI transaction */
14471 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
14472 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
14473 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
14474 
14475 /* Register: TWIS_TASKS_SUSPEND */
14476 /* Description: Suspend TWI transaction */
14477 
14478 /* Bit 0 : Suspend TWI transaction */
14479 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
14480 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
14481 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
14482 
14483 /* Register: TWIS_TASKS_RESUME */
14484 /* Description: Resume TWI transaction */
14485 
14486 /* Bit 0 : Resume TWI transaction */
14487 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
14488 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
14489 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
14490 
14491 /* Register: TWIS_TASKS_PREPARERX */
14492 /* Description: Prepare the TWI slave to respond to a write command */
14493 
14494 /* Bit 0 : Prepare the TWI slave to respond to a write command */
14495 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
14496 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
14497 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
14498 
14499 /* Register: TWIS_TASKS_PREPARETX */
14500 /* Description: Prepare the TWI slave to respond to a read command */
14501 
14502 /* Bit 0 : Prepare the TWI slave to respond to a read command */
14503 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
14504 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
14505 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
14506 
14507 /* Register: TWIS_EVENTS_STOPPED */
14508 /* Description: TWI stopped */
14509 
14510 /* Bit 0 : TWI stopped */
14511 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
14512 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
14513 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
14514 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
14515 
14516 /* Register: TWIS_EVENTS_ERROR */
14517 /* Description: TWI error */
14518 
14519 /* Bit 0 : TWI error */
14520 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14521 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14522 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
14523 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
14524 
14525 /* Register: TWIS_EVENTS_RXSTARTED */
14526 /* Description: Receive sequence started */
14527 
14528 /* Bit 0 : Receive sequence started */
14529 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
14530 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
14531 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14532 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
14533 
14534 /* Register: TWIS_EVENTS_TXSTARTED */
14535 /* Description: Transmit sequence started */
14536 
14537 /* Bit 0 : Transmit sequence started */
14538 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
14539 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
14540 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14541 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
14542 
14543 /* Register: TWIS_EVENTS_WRITE */
14544 /* Description: Write command received */
14545 
14546 /* Bit 0 : Write command received */
14547 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
14548 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
14549 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
14550 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
14551 
14552 /* Register: TWIS_EVENTS_READ */
14553 /* Description: Read command received */
14554 
14555 /* Bit 0 : Read command received */
14556 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
14557 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
14558 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
14559 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
14560 
14561 /* Register: TWIS_SHORTS */
14562 /* Description: Shortcuts between local events and tasks */
14563 
14564 /* Bit 14 : Shortcut between event READ and task SUSPEND */
14565 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
14566 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
14567 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
14568 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
14569 
14570 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
14571 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
14572 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
14573 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
14574 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
14575 
14576 /* Register: TWIS_INTEN */
14577 /* Description: Enable or disable interrupt */
14578 
14579 /* Bit 26 : Enable or disable interrupt for event READ */
14580 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
14581 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
14582 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
14583 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
14584 
14585 /* Bit 25 : Enable or disable interrupt for event WRITE */
14586 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
14587 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
14588 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
14589 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
14590 
14591 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
14592 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14593 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14594 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
14595 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
14596 
14597 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
14598 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14599 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14600 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
14601 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
14602 
14603 /* Bit 9 : Enable or disable interrupt for event ERROR */
14604 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14605 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
14606 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
14607 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
14608 
14609 /* Bit 1 : Enable or disable interrupt for event STOPPED */
14610 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14611 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14612 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
14613 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
14614 
14615 /* Register: TWIS_INTENSET */
14616 /* Description: Enable interrupt */
14617 
14618 /* Bit 26 : Write '1' to enable interrupt for event READ */
14619 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
14620 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
14621 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
14622 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
14623 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
14624 
14625 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
14626 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
14627 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
14628 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
14629 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
14630 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
14631 
14632 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
14633 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14634 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14635 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14636 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14637 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
14638 
14639 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
14640 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14641 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14642 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14643 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14644 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
14645 
14646 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
14647 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14648 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
14649 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14650 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14651 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
14652 
14653 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
14654 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14655 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14656 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14657 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14658 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
14659 
14660 /* Register: TWIS_INTENCLR */
14661 /* Description: Disable interrupt */
14662 
14663 /* Bit 26 : Write '1' to disable interrupt for event READ */
14664 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
14665 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
14666 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
14667 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
14668 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
14669 
14670 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
14671 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
14672 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
14673 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
14674 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
14675 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
14676 
14677 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
14678 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14679 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14680 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14681 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14682 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
14683 
14684 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
14685 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14686 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14687 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14688 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14689 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
14690 
14691 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
14692 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14693 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
14694 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14695 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14696 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
14697 
14698 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
14699 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14700 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14701 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14702 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14703 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
14704 
14705 /* Register: TWIS_ERRORSRC */
14706 /* Description: Error source */
14707 
14708 /* Bit 3 : TX buffer over-read detected, and prevented */
14709 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
14710 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
14711 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
14712 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
14713 
14714 /* Bit 2 : NACK sent after receiving a data byte */
14715 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
14716 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
14717 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
14718 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
14719 
14720 /* Bit 0 : RX buffer overflow detected, and prevented */
14721 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
14722 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
14723 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
14724 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
14725 
14726 /* Register: TWIS_MATCH */
14727 /* Description: Status register indicating which address had a match */
14728 
14729 /* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */
14730 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
14731 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
14732 
14733 /* Register: TWIS_ENABLE */
14734 /* Description: Enable TWIS */
14735 
14736 /* Bits 3..0 : Enable or disable TWIS */
14737 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14738 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14739 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
14740 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
14741 
14742 /* Register: TWIS_PSEL_SCL */
14743 /* Description: Pin select for SCL signal */
14744 
14745 /* Bit 31 : Connection */
14746 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14747 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14748 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
14749 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
14750 
14751 /* Bit 5 : Port number */
14752 #define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
14753 #define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
14754 
14755 /* Bits 4..0 : Pin number */
14756 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
14757 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
14758 
14759 /* Register: TWIS_PSEL_SDA */
14760 /* Description: Pin select for SDA signal */
14761 
14762 /* Bit 31 : Connection */
14763 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14764 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14765 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
14766 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
14767 
14768 /* Bit 5 : Port number */
14769 #define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
14770 #define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
14771 
14772 /* Bits 4..0 : Pin number */
14773 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
14774 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
14775 
14776 /* Register: TWIS_RXD_PTR */
14777 /* Description: RXD Data pointer */
14778 
14779 /* Bits 31..0 : RXD Data pointer */
14780 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14781 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14782 
14783 /* Register: TWIS_RXD_MAXCNT */
14784 /* Description: Maximum number of bytes in RXD buffer */
14785 
14786 /* Bits 15..0 : Maximum number of bytes in RXD buffer */
14787 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14788 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14789 
14790 /* Register: TWIS_RXD_AMOUNT */
14791 /* Description: Number of bytes transferred in the last RXD transaction */
14792 
14793 /* Bits 15..0 : Number of bytes transferred in the last RXD transaction */
14794 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14795 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14796 
14797 /* Register: TWIS_RXD_LIST */
14798 /* Description: EasyDMA list type */
14799 
14800 /* Bits 1..0 : List type */
14801 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14802 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14803 #define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14804 #define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
14805 
14806 /* Register: TWIS_TXD_PTR */
14807 /* Description: TXD Data pointer */
14808 
14809 /* Bits 31..0 : TXD Data pointer */
14810 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14811 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14812 
14813 /* Register: TWIS_TXD_MAXCNT */
14814 /* Description: Maximum number of bytes in TXD buffer */
14815 
14816 /* Bits 15..0 : Maximum number of bytes in TXD buffer */
14817 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14818 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14819 
14820 /* Register: TWIS_TXD_AMOUNT */
14821 /* Description: Number of bytes transferred in the last TXD transaction */
14822 
14823 /* Bits 15..0 : Number of bytes transferred in the last TXD transaction */
14824 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14825 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14826 
14827 /* Register: TWIS_TXD_LIST */
14828 /* Description: EasyDMA list type */
14829 
14830 /* Bits 1..0 : List type */
14831 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14832 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14833 #define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14834 #define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
14835 
14836 /* Register: TWIS_ADDRESS */
14837 /* Description: Description collection: TWI slave address n */
14838 
14839 /* Bits 6..0 : TWI slave address */
14840 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
14841 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
14842 
14843 /* Register: TWIS_CONFIG */
14844 /* Description: Configuration register for the address match mechanism */
14845 
14846 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
14847 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
14848 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
14849 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
14850 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
14851 
14852 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
14853 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
14854 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
14855 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
14856 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
14857 
14858 /* Register: TWIS_ORC */
14859 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
14860 
14861 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
14862 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
14863 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
14864 
14865 
14866 /* Peripheral: UART */
14867 /* Description: Universal Asynchronous Receiver/Transmitter */
14868 
14869 /* Register: UART_TASKS_STARTRX */
14870 /* Description: Start UART receiver */
14871 
14872 /* Bit 0 : Start UART receiver */
14873 #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
14874 #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
14875 #define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
14876 
14877 /* Register: UART_TASKS_STOPRX */
14878 /* Description: Stop UART receiver */
14879 
14880 /* Bit 0 : Stop UART receiver */
14881 #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
14882 #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
14883 #define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
14884 
14885 /* Register: UART_TASKS_STARTTX */
14886 /* Description: Start UART transmitter */
14887 
14888 /* Bit 0 : Start UART transmitter */
14889 #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
14890 #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
14891 #define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
14892 
14893 /* Register: UART_TASKS_STOPTX */
14894 /* Description: Stop UART transmitter */
14895 
14896 /* Bit 0 : Stop UART transmitter */
14897 #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
14898 #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
14899 #define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
14900 
14901 /* Register: UART_TASKS_SUSPEND */
14902 /* Description: Suspend UART */
14903 
14904 /* Bit 0 : Suspend UART */
14905 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
14906 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
14907 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
14908 
14909 /* Register: UART_EVENTS_CTS */
14910 /* Description: CTS is activated (set low). Clear To Send. */
14911 
14912 /* Bit 0 : CTS is activated (set low). Clear To Send. */
14913 #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
14914 #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
14915 #define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
14916 #define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
14917 
14918 /* Register: UART_EVENTS_NCTS */
14919 /* Description: CTS is deactivated (set high). Not Clear To Send. */
14920 
14921 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
14922 #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
14923 #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
14924 #define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
14925 #define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
14926 
14927 /* Register: UART_EVENTS_RXDRDY */
14928 /* Description: Data received in RXD */
14929 
14930 /* Bit 0 : Data received in RXD */
14931 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
14932 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
14933 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
14934 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
14935 
14936 /* Register: UART_EVENTS_TXDRDY */
14937 /* Description: Data sent from TXD */
14938 
14939 /* Bit 0 : Data sent from TXD */
14940 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
14941 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
14942 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
14943 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
14944 
14945 /* Register: UART_EVENTS_ERROR */
14946 /* Description: Error detected */
14947 
14948 /* Bit 0 : Error detected */
14949 #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14950 #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14951 #define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
14952 #define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
14953 
14954 /* Register: UART_EVENTS_RXTO */
14955 /* Description: Receiver timeout */
14956 
14957 /* Bit 0 : Receiver timeout */
14958 #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
14959 #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
14960 #define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
14961 #define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
14962 
14963 /* Register: UART_SHORTS */
14964 /* Description: Shortcuts between local events and tasks */
14965 
14966 /* Bit 4 : Shortcut between event NCTS and task STOPRX */
14967 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
14968 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
14969 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
14970 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
14971 
14972 /* Bit 3 : Shortcut between event CTS and task STARTRX */
14973 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
14974 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
14975 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
14976 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
14977 
14978 /* Register: UART_INTENSET */
14979 /* Description: Enable interrupt */
14980 
14981 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
14982 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
14983 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
14984 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
14985 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
14986 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
14987 
14988 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
14989 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14990 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
14991 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14992 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14993 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
14994 
14995 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
14996 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
14997 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
14998 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14999 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
15000 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
15001 
15002 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
15003 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15004 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15005 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15006 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15007 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
15008 
15009 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
15010 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15011 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
15012 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
15013 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
15014 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
15015 
15016 /* Bit 0 : Write '1' to enable interrupt for event CTS */
15017 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
15018 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
15019 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
15020 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
15021 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
15022 
15023 /* Register: UART_INTENCLR */
15024 /* Description: Disable interrupt */
15025 
15026 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
15027 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15028 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
15029 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
15030 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
15031 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
15032 
15033 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
15034 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15035 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
15036 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
15037 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
15038 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
15039 
15040 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
15041 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15042 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15043 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
15044 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
15045 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
15046 
15047 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
15048 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15049 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15050 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15051 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15052 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
15053 
15054 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
15055 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15056 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
15057 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
15058 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
15059 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
15060 
15061 /* Bit 0 : Write '1' to disable interrupt for event CTS */
15062 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
15063 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
15064 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
15065 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
15066 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
15067 
15068 /* Register: UART_ERRORSRC */
15069 /* Description: Error source */
15070 
15071 /* Bit 3 : Break condition */
15072 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
15073 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
15074 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
15075 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
15076 
15077 /* Bit 2 : Framing error occurred */
15078 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
15079 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
15080 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
15081 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
15082 
15083 /* Bit 1 : Parity error */
15084 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
15085 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
15086 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
15087 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
15088 
15089 /* Bit 0 : Overrun error */
15090 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
15091 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
15092 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
15093 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
15094 
15095 /* Register: UART_ENABLE */
15096 /* Description: Enable UART */
15097 
15098 /* Bits 3..0 : Enable or disable UART */
15099 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
15100 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
15101 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
15102 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
15103 
15104 /* Register: UART_PSEL_RTS */
15105 /* Description: Pin select for RTS */
15106 
15107 /* Bit 31 : Connection */
15108 #define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15109 #define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15110 #define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
15111 #define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
15112 
15113 /* Bit 5 : Port number */
15114 #define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
15115 #define UART_PSEL_RTS_PORT_Msk (0x1UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
15116 
15117 /* Bits 4..0 : Pin number */
15118 #define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
15119 #define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
15120 
15121 /* Register: UART_PSEL_TXD */
15122 /* Description: Pin select for TXD */
15123 
15124 /* Bit 31 : Connection */
15125 #define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15126 #define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15127 #define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
15128 #define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
15129 
15130 /* Bit 5 : Port number */
15131 #define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
15132 #define UART_PSEL_TXD_PORT_Msk (0x1UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
15133 
15134 /* Bits 4..0 : Pin number */
15135 #define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
15136 #define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
15137 
15138 /* Register: UART_PSEL_CTS */
15139 /* Description: Pin select for CTS */
15140 
15141 /* Bit 31 : Connection */
15142 #define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15143 #define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15144 #define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
15145 #define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
15146 
15147 /* Bit 5 : Port number */
15148 #define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
15149 #define UART_PSEL_CTS_PORT_Msk (0x1UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
15150 
15151 /* Bits 4..0 : Pin number */
15152 #define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
15153 #define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
15154 
15155 /* Register: UART_PSEL_RXD */
15156 /* Description: Pin select for RXD */
15157 
15158 /* Bit 31 : Connection */
15159 #define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15160 #define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15161 #define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
15162 #define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
15163 
15164 /* Bit 5 : Port number */
15165 #define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
15166 #define UART_PSEL_RXD_PORT_Msk (0x1UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
15167 
15168 /* Bits 4..0 : Pin number */
15169 #define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
15170 #define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
15171 
15172 /* Register: UART_RXD */
15173 /* Description: RXD register */
15174 
15175 /* Bits 7..0 : RX data received in previous transfers, double buffered */
15176 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
15177 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
15178 
15179 /* Register: UART_TXD */
15180 /* Description: TXD register */
15181 
15182 /* Bits 7..0 : TX data to be transferred */
15183 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
15184 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
15185 
15186 /* Register: UART_BAUDRATE */
15187 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
15188 
15189 /* Bits 31..0 : Baud rate */
15190 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
15191 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
15192 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
15193 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
15194 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
15195 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
15196 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
15197 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
15198 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
15199 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
15200 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
15201 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
15202 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
15203 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
15204 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
15205 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
15206 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
15207 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
15208 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
15209 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
15210 
15211 /* Register: UART_CONFIG */
15212 /* Description: Configuration of parity and hardware flow control */
15213 
15214 /* Bit 4 : Stop bits */
15215 #define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
15216 #define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
15217 #define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */
15218 #define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
15219 
15220 /* Bits 3..1 : Parity */
15221 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
15222 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
15223 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
15224 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
15225 
15226 /* Bit 0 : Hardware flow control */
15227 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
15228 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
15229 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
15230 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
15231 
15232 
15233 /* Peripheral: UARTE */
15234 /* Description: UART with EasyDMA 0 */
15235 
15236 /* Register: UARTE_TASKS_STARTRX */
15237 /* Description: Start UART receiver */
15238 
15239 /* Bit 0 : Start UART receiver */
15240 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
15241 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
15242 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
15243 
15244 /* Register: UARTE_TASKS_STOPRX */
15245 /* Description: Stop UART receiver */
15246 
15247 /* Bit 0 : Stop UART receiver */
15248 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
15249 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
15250 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
15251 
15252 /* Register: UARTE_TASKS_STARTTX */
15253 /* Description: Start UART transmitter */
15254 
15255 /* Bit 0 : Start UART transmitter */
15256 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
15257 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
15258 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
15259 
15260 /* Register: UARTE_TASKS_STOPTX */
15261 /* Description: Stop UART transmitter */
15262 
15263 /* Bit 0 : Stop UART transmitter */
15264 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
15265 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
15266 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
15267 
15268 /* Register: UARTE_TASKS_FLUSHRX */
15269 /* Description: Flush RX FIFO into RX buffer */
15270 
15271 /* Bit 0 : Flush RX FIFO into RX buffer */
15272 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
15273 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
15274 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
15275 
15276 /* Register: UARTE_EVENTS_CTS */
15277 /* Description: CTS is activated (set low). Clear To Send. */
15278 
15279 /* Bit 0 : CTS is activated (set low). Clear To Send. */
15280 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
15281 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
15282 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
15283 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
15284 
15285 /* Register: UARTE_EVENTS_NCTS */
15286 /* Description: CTS is deactivated (set high). Not Clear To Send. */
15287 
15288 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
15289 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
15290 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
15291 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
15292 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
15293 
15294 /* Register: UARTE_EVENTS_RXDRDY */
15295 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
15296 
15297 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
15298 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
15299 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
15300 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
15301 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
15302 
15303 /* Register: UARTE_EVENTS_ENDRX */
15304 /* Description: Receive buffer is filled up */
15305 
15306 /* Bit 0 : Receive buffer is filled up */
15307 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
15308 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
15309 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
15310 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
15311 
15312 /* Register: UARTE_EVENTS_TXDRDY */
15313 /* Description: Data sent from TXD */
15314 
15315 /* Bit 0 : Data sent from TXD */
15316 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
15317 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
15318 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
15319 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
15320 
15321 /* Register: UARTE_EVENTS_ENDTX */
15322 /* Description: Last TX byte transmitted */
15323 
15324 /* Bit 0 : Last TX byte transmitted */
15325 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
15326 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
15327 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
15328 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
15329 
15330 /* Register: UARTE_EVENTS_ERROR */
15331 /* Description: Error detected */
15332 
15333 /* Bit 0 : Error detected */
15334 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
15335 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
15336 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
15337 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
15338 
15339 /* Register: UARTE_EVENTS_RXTO */
15340 /* Description: Receiver timeout */
15341 
15342 /* Bit 0 : Receiver timeout */
15343 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
15344 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
15345 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
15346 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
15347 
15348 /* Register: UARTE_EVENTS_RXSTARTED */
15349 /* Description: UART receiver has started */
15350 
15351 /* Bit 0 : UART receiver has started */
15352 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
15353 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
15354 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
15355 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
15356 
15357 /* Register: UARTE_EVENTS_TXSTARTED */
15358 /* Description: UART transmitter has started */
15359 
15360 /* Bit 0 : UART transmitter has started */
15361 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
15362 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
15363 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
15364 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
15365 
15366 /* Register: UARTE_EVENTS_TXSTOPPED */
15367 /* Description: Transmitter stopped */
15368 
15369 /* Bit 0 : Transmitter stopped */
15370 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
15371 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
15372 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
15373 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
15374 
15375 /* Register: UARTE_SHORTS */
15376 /* Description: Shortcuts between local events and tasks */
15377 
15378 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
15379 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
15380 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
15381 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
15382 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
15383 
15384 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
15385 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
15386 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
15387 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
15388 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
15389 
15390 /* Register: UARTE_INTEN */
15391 /* Description: Enable or disable interrupt */
15392 
15393 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
15394 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15395 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15396 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
15397 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
15398 
15399 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
15400 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15401 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15402 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
15403 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
15404 
15405 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
15406 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15407 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15408 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
15409 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
15410 
15411 /* Bit 17 : Enable or disable interrupt for event RXTO */
15412 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15413 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
15414 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
15415 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
15416 
15417 /* Bit 9 : Enable or disable interrupt for event ERROR */
15418 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15419 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
15420 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
15421 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
15422 
15423 /* Bit 8 : Enable or disable interrupt for event ENDTX */
15424 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15425 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15426 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
15427 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
15428 
15429 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
15430 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15431 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15432 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
15433 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
15434 
15435 /* Bit 4 : Enable or disable interrupt for event ENDRX */
15436 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15437 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15438 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
15439 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
15440 
15441 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
15442 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15443 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15444 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
15445 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
15446 
15447 /* Bit 1 : Enable or disable interrupt for event NCTS */
15448 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15449 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
15450 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
15451 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
15452 
15453 /* Bit 0 : Enable or disable interrupt for event CTS */
15454 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
15455 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
15456 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
15457 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
15458 
15459 /* Register: UARTE_INTENSET */
15460 /* Description: Enable interrupt */
15461 
15462 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
15463 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15464 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15465 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
15466 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
15467 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
15468 
15469 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
15470 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15471 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15472 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15473 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15474 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
15475 
15476 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
15477 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15478 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15479 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15480 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15481 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
15482 
15483 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
15484 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15485 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
15486 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
15487 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
15488 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
15489 
15490 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
15491 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15492 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
15493 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
15494 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
15495 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
15496 
15497 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
15498 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15499 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15500 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
15501 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
15502 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
15503 
15504 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
15505 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15506 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15507 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
15508 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
15509 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
15510 
15511 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
15512 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15513 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15514 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
15515 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
15516 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
15517 
15518 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
15519 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15520 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15521 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15522 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15523 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
15524 
15525 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
15526 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15527 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
15528 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
15529 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
15530 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
15531 
15532 /* Bit 0 : Write '1' to enable interrupt for event CTS */
15533 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
15534 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
15535 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
15536 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
15537 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
15538 
15539 /* Register: UARTE_INTENCLR */
15540 /* Description: Disable interrupt */
15541 
15542 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
15543 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15544 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15545 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
15546 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
15547 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
15548 
15549 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
15550 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15551 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15552 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15553 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15554 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
15555 
15556 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
15557 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15558 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15559 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15560 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15561 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
15562 
15563 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
15564 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15565 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
15566 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
15567 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
15568 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
15569 
15570 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
15571 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15572 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
15573 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
15574 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
15575 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
15576 
15577 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
15578 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15579 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15580 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
15581 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
15582 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
15583 
15584 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
15585 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15586 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15587 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
15588 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
15589 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
15590 
15591 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
15592 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15593 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15594 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
15595 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
15596 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
15597 
15598 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
15599 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15600 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15601 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15602 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15603 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
15604 
15605 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
15606 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15607 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
15608 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
15609 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
15610 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
15611 
15612 /* Bit 0 : Write '1' to disable interrupt for event CTS */
15613 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
15614 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
15615 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
15616 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
15617 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
15618 
15619 /* Register: UARTE_ERRORSRC */
15620 /* Description: Error source This register is read/write one to clear. */
15621 
15622 /* Bit 3 : Break condition */
15623 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
15624 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
15625 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
15626 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
15627 
15628 /* Bit 2 : Framing error occurred */
15629 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
15630 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
15631 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
15632 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
15633 
15634 /* Bit 1 : Parity error */
15635 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
15636 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
15637 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
15638 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
15639 
15640 /* Bit 0 : Overrun error */
15641 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
15642 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
15643 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
15644 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
15645 
15646 /* Register: UARTE_ENABLE */
15647 /* Description: Enable UART */
15648 
15649 /* Bits 3..0 : Enable or disable UARTE */
15650 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
15651 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
15652 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
15653 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
15654 
15655 /* Register: UARTE_PSEL_RTS */
15656 /* Description: Pin select for RTS signal */
15657 
15658 /* Bit 31 : Connection */
15659 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15660 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15661 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
15662 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
15663 
15664 /* Bit 5 : Port number */
15665 #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
15666 #define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
15667 
15668 /* Bits 4..0 : Pin number */
15669 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
15670 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
15671 
15672 /* Register: UARTE_PSEL_TXD */
15673 /* Description: Pin select for TXD signal */
15674 
15675 /* Bit 31 : Connection */
15676 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15677 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15678 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
15679 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
15680 
15681 /* Bit 5 : Port number */
15682 #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
15683 #define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
15684 
15685 /* Bits 4..0 : Pin number */
15686 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
15687 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
15688 
15689 /* Register: UARTE_PSEL_CTS */
15690 /* Description: Pin select for CTS signal */
15691 
15692 /* Bit 31 : Connection */
15693 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15694 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15695 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
15696 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
15697 
15698 /* Bit 5 : Port number */
15699 #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
15700 #define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
15701 
15702 /* Bits 4..0 : Pin number */
15703 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
15704 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
15705 
15706 /* Register: UARTE_PSEL_RXD */
15707 /* Description: Pin select for RXD signal */
15708 
15709 /* Bit 31 : Connection */
15710 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15711 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15712 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
15713 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
15714 
15715 /* Bit 5 : Port number */
15716 #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
15717 #define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
15718 
15719 /* Bits 4..0 : Pin number */
15720 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
15721 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
15722 
15723 /* Register: UARTE_BAUDRATE */
15724 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
15725 
15726 /* Bits 31..0 : Baud rate */
15727 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
15728 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
15729 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
15730 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
15731 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
15732 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
15733 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
15734 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
15735 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
15736 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
15737 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
15738 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
15739 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
15740 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
15741 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
15742 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
15743 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
15744 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
15745 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
15746 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
15747 
15748 /* Register: UARTE_RXD_PTR */
15749 /* Description: Data pointer */
15750 
15751 /* Bits 31..0 : Data pointer */
15752 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
15753 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
15754 
15755 /* Register: UARTE_RXD_MAXCNT */
15756 /* Description: Maximum number of bytes in receive buffer */
15757 
15758 /* Bits 15..0 : Maximum number of bytes in receive buffer */
15759 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
15760 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
15761 
15762 /* Register: UARTE_RXD_AMOUNT */
15763 /* Description: Number of bytes transferred in the last transaction */
15764 
15765 /* Bits 15..0 : Number of bytes transferred in the last transaction */
15766 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
15767 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
15768 
15769 /* Register: UARTE_TXD_PTR */
15770 /* Description: Data pointer */
15771 
15772 /* Bits 31..0 : Data pointer */
15773 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
15774 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
15775 
15776 /* Register: UARTE_TXD_MAXCNT */
15777 /* Description: Maximum number of bytes in transmit buffer */
15778 
15779 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
15780 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
15781 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
15782 
15783 /* Register: UARTE_TXD_AMOUNT */
15784 /* Description: Number of bytes transferred in the last transaction */
15785 
15786 /* Bits 15..0 : Number of bytes transferred in the last transaction */
15787 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
15788 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
15789 
15790 /* Register: UARTE_CONFIG */
15791 /* Description: Configuration of parity and hardware flow control */
15792 
15793 /* Bit 4 : Stop bits */
15794 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
15795 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
15796 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
15797 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
15798 
15799 /* Bits 3..1 : Parity */
15800 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
15801 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
15802 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
15803 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
15804 
15805 /* Bit 0 : Hardware flow control */
15806 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
15807 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
15808 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
15809 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
15810 
15811 
15812 /* Peripheral: UICR */
15813 /* Description: User information configuration registers */
15814 
15815 /* Register: UICR_NRFFW */
15816 /* Description: Description collection: Reserved for Nordic firmware design */
15817 
15818 /* Bits 31..0 : Reserved for Nordic firmware design */
15819 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
15820 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
15821 
15822 /* Register: UICR_NRFHW */
15823 /* Description: Description collection: Reserved for Nordic hardware design */
15824 
15825 /* Bits 31..0 : Reserved for Nordic hardware design */
15826 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
15827 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
15828 
15829 /* Register: UICR_CUSTOMER */
15830 /* Description: Description collection: Reserved for customer */
15831 
15832 /* Bits 31..0 : Reserved for customer */
15833 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
15834 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
15835 
15836 /* Register: UICR_PSELRESET */
15837 /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */
15838 
15839 /* Bit 31 : Connection */
15840 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15841 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15842 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
15843 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
15844 
15845 /* Bit 5 : Port number onto which nRESET is exposed */
15846 #define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */
15847 #define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */
15848 
15849 /* Bits 4..0 : GPIO pin number onto which nRESET is exposed */
15850 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
15851 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
15852 
15853 /* Register: UICR_APPROTECT */
15854 /* Description: Access port protection */
15855 
15856 /* Bits 7..0 : Enable or disable access port protection. */
15857 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
15858 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
15859 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
15860 #define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */
15861 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */
15862 
15863 /* Register: UICR_NFCPINS */
15864 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
15865 
15866 /* Bit 0 : Setting of pins dedicated to NFC functionality */
15867 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
15868 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
15869 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */
15870 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */
15871 
15872 /* Register: UICR_DEBUGCTRL */
15873 /* Description: Processor debug control */
15874 
15875 /* Bits 15..8 : Configure CPU flash patch and breakpoint (FPB) unit behavior */
15876 #define UICR_DEBUGCTRL_CPUFPBEN_Pos (8UL) /*!< Position of CPUFPBEN field. */
15877 #define UICR_DEBUGCTRL_CPUFPBEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUFPBEN_Pos) /*!< Bit mask of CPUFPBEN field. */
15878 #define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB registers will be ignored. */
15879 #define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */
15880 
15881 /* Bits 7..0 : Configure CPU non-intrusive debug features */
15882 #define UICR_DEBUGCTRL_CPUNIDEN_Pos (0UL) /*!< Position of CPUNIDEN field. */
15883 #define UICR_DEBUGCTRL_CPUNIDEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUNIDEN_Pos) /*!< Bit mask of CPUNIDEN field. */
15884 #define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */
15885 #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */
15886 
15887 /* Register: UICR_REGOUT0 */
15888 /* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */
15889 
15890 /* Bits 2..0 : Output voltage from REG0 regulator stage. */
15891 #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */
15892 #define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */
15893 #define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */
15894 #define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */
15895 #define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */
15896 #define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */
15897 #define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */
15898 #define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */
15899 #define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */
15900 
15901 
15902 /* Peripheral: USBD */
15903 /* Description: Universal serial bus device */
15904 
15905 /* Register: USBD_TASKS_STARTEPIN */
15906 /* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
15907 
15908 /* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
15909 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */
15910 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */
15911 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */
15912 
15913 /* Register: USBD_TASKS_STARTISOIN */
15914 /* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
15915 
15916 /* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
15917 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */
15918 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */
15919 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */
15920 
15921 /* Register: USBD_TASKS_STARTEPOUT */
15922 /* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
15923 
15924 /* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
15925 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */
15926 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */
15927 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */
15928 
15929 /* Register: USBD_TASKS_STARTISOOUT */
15930 /* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
15931 
15932 /* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
15933 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */
15934 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */
15935 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */
15936 
15937 /* Register: USBD_TASKS_EP0RCVOUT */
15938 /* Description: Allows OUT data stage on control endpoint 0 */
15939 
15940 /* Bit 0 : Allows OUT data stage on control endpoint 0 */
15941 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */
15942 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */
15943 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */
15944 
15945 /* Register: USBD_TASKS_EP0STATUS */
15946 /* Description: Allows status stage on control endpoint 0 */
15947 
15948 /* Bit 0 : Allows status stage on control endpoint 0 */
15949 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */
15950 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */
15951 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */
15952 
15953 /* Register: USBD_TASKS_EP0STALL */
15954 /* Description: Stalls data and status stage on control endpoint 0 */
15955 
15956 /* Bit 0 : Stalls data and status stage on control endpoint 0 */
15957 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */
15958 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */
15959 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */
15960 
15961 /* Register: USBD_TASKS_DPDMDRIVE */
15962 /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */
15963 
15964 /* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */
15965 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */
15966 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */
15967 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */
15968 
15969 /* Register: USBD_TASKS_DPDMNODRIVE */
15970 /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */
15971 
15972 /* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */
15973 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */
15974 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */
15975 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */
15976 
15977 /* Register: USBD_EVENTS_USBRESET */
15978 /* Description: Signals that a USB reset condition has been detected on USB lines */
15979 
15980 /* Bit 0 : Signals that a USB reset condition has been detected on USB lines */
15981 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */
15982 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */
15983 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */
15984 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */
15985 
15986 /* Register: USBD_EVENTS_STARTED */
15987 /* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
15988 
15989 /* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
15990 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
15991 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
15992 #define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
15993 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
15994 
15995 /* Register: USBD_EVENTS_ENDEPIN */
15996 /* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
15997 
15998 /* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
15999 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */
16000 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */
16001 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */
16002 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */
16003 
16004 /* Register: USBD_EVENTS_EP0DATADONE */
16005 /* Description: An acknowledged data transfer has taken place on the control endpoint */
16006 
16007 /* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */
16008 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */
16009 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */
16010 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */
16011 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */
16012 
16013 /* Register: USBD_EVENTS_ENDISOIN */
16014 /* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
16015 
16016 /* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
16017 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */
16018 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */
16019 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */
16020 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */
16021 
16022 /* Register: USBD_EVENTS_ENDEPOUT */
16023 /* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
16024 
16025 /* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
16026 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */
16027 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */
16028 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */
16029 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */
16030 
16031 /* Register: USBD_EVENTS_ENDISOOUT */
16032 /* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
16033 
16034 /* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
16035 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */
16036 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */
16037 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */
16038 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */
16039 
16040 /* Register: USBD_EVENTS_SOF */
16041 /* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */
16042 
16043 /* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */
16044 #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */
16045 #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */
16046 #define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */
16047 #define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */
16048 
16049 /* Register: USBD_EVENTS_USBEVENT */
16050 /* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
16051 
16052 /* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
16053 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */
16054 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */
16055 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */
16056 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */
16057 
16058 /* Register: USBD_EVENTS_EP0SETUP */
16059 /* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */
16060 
16061 /* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */
16062 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */
16063 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */
16064 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */
16065 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */
16066 
16067 /* Register: USBD_EVENTS_EPDATA */
16068 /* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
16069 
16070 /* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
16071 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */
16072 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */
16073 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */
16074 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */
16075 
16076 /* Register: USBD_SHORTS */
16077 /* Description: Shortcuts between local events and tasks */
16078 
16079 /* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */
16080 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */
16081 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */
16082 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */
16083 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */
16084 
16085 /* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */
16086 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */
16087 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */
16088 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
16089 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
16090 
16091 /* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */
16092 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
16093 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */
16094 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
16095 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
16096 
16097 /* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */
16098 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */
16099 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */
16100 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */
16101 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */
16102 
16103 /* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */
16104 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */
16105 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */
16106 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */
16107 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */
16108 
16109 /* Register: USBD_INTEN */
16110 /* Description: Enable or disable interrupt */
16111 
16112 /* Bit 24 : Enable or disable interrupt for event EPDATA */
16113 #define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
16114 #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
16115 #define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */
16116 #define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */
16117 
16118 /* Bit 23 : Enable or disable interrupt for event EP0SETUP */
16119 #define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
16120 #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
16121 #define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */
16122 #define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */
16123 
16124 /* Bit 22 : Enable or disable interrupt for event USBEVENT */
16125 #define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
16126 #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
16127 #define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */
16128 #define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */
16129 
16130 /* Bit 21 : Enable or disable interrupt for event SOF */
16131 #define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
16132 #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
16133 #define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */
16134 #define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */
16135 
16136 /* Bit 20 : Enable or disable interrupt for event ENDISOOUT */
16137 #define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
16138 #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
16139 #define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */
16140 #define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */
16141 
16142 /* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */
16143 #define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
16144 #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
16145 #define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */
16146 #define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */
16147 
16148 /* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */
16149 #define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
16150 #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
16151 #define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */
16152 #define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */
16153 
16154 /* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */
16155 #define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
16156 #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
16157 #define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */
16158 #define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */
16159 
16160 /* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */
16161 #define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
16162 #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
16163 #define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */
16164 #define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */
16165 
16166 /* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */
16167 #define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
16168 #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
16169 #define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */
16170 #define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */
16171 
16172 /* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */
16173 #define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
16174 #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
16175 #define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */
16176 #define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */
16177 
16178 /* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */
16179 #define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
16180 #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
16181 #define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */
16182 #define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */
16183 
16184 /* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */
16185 #define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
16186 #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
16187 #define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */
16188 #define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */
16189 
16190 /* Bit 11 : Enable or disable interrupt for event ENDISOIN */
16191 #define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
16192 #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
16193 #define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */
16194 #define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */
16195 
16196 /* Bit 10 : Enable or disable interrupt for event EP0DATADONE */
16197 #define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
16198 #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
16199 #define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */
16200 #define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */
16201 
16202 /* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */
16203 #define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
16204 #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
16205 #define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */
16206 #define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */
16207 
16208 /* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */
16209 #define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
16210 #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
16211 #define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */
16212 #define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */
16213 
16214 /* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */
16215 #define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
16216 #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
16217 #define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */
16218 #define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */
16219 
16220 /* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */
16221 #define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
16222 #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
16223 #define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */
16224 #define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */
16225 
16226 /* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */
16227 #define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
16228 #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
16229 #define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */
16230 #define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */
16231 
16232 /* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */
16233 #define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
16234 #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
16235 #define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */
16236 #define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */
16237 
16238 /* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */
16239 #define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
16240 #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
16241 #define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */
16242 #define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */
16243 
16244 /* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */
16245 #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
16246 #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
16247 #define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */
16248 #define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */
16249 
16250 /* Bit 1 : Enable or disable interrupt for event STARTED */
16251 #define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
16252 #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
16253 #define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */
16254 #define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */
16255 
16256 /* Bit 0 : Enable or disable interrupt for event USBRESET */
16257 #define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
16258 #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
16259 #define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */
16260 #define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */
16261 
16262 /* Register: USBD_INTENSET */
16263 /* Description: Enable interrupt */
16264 
16265 /* Bit 24 : Write '1' to enable interrupt for event EPDATA */
16266 #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
16267 #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
16268 #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */
16269 #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */
16270 #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */
16271 
16272 /* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */
16273 #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
16274 #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
16275 #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
16276 #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
16277 #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */
16278 
16279 /* Bit 22 : Write '1' to enable interrupt for event USBEVENT */
16280 #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
16281 #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
16282 #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
16283 #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
16284 #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */
16285 
16286 /* Bit 21 : Write '1' to enable interrupt for event SOF */
16287 #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
16288 #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
16289 #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
16290 #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
16291 #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */
16292 
16293 /* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */
16294 #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
16295 #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
16296 #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
16297 #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
16298 #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */
16299 
16300 /* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */
16301 #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
16302 #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
16303 #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
16304 #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
16305 #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */
16306 
16307 /* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */
16308 #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
16309 #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
16310 #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
16311 #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
16312 #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */
16313 
16314 /* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */
16315 #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
16316 #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
16317 #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
16318 #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
16319 #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */
16320 
16321 /* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */
16322 #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
16323 #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
16324 #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
16325 #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
16326 #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */
16327 
16328 /* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */
16329 #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
16330 #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
16331 #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
16332 #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
16333 #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */
16334 
16335 /* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */
16336 #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
16337 #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
16338 #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
16339 #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
16340 #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */
16341 
16342 /* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */
16343 #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
16344 #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
16345 #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
16346 #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
16347 #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */
16348 
16349 /* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */
16350 #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
16351 #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
16352 #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
16353 #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
16354 #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */
16355 
16356 /* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */
16357 #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
16358 #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
16359 #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
16360 #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
16361 #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */
16362 
16363 /* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */
16364 #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
16365 #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
16366 #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
16367 #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
16368 #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */
16369 
16370 /* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */
16371 #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
16372 #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
16373 #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
16374 #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
16375 #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */
16376 
16377 /* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */
16378 #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
16379 #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
16380 #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
16381 #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
16382 #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */
16383 
16384 /* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */
16385 #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
16386 #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
16387 #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
16388 #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
16389 #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */
16390 
16391 /* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */
16392 #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
16393 #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
16394 #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
16395 #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
16396 #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */
16397 
16398 /* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */
16399 #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
16400 #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
16401 #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
16402 #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
16403 #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */
16404 
16405 /* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */
16406 #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
16407 #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
16408 #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
16409 #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
16410 #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */
16411 
16412 /* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */
16413 #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
16414 #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
16415 #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
16416 #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
16417 #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */
16418 
16419 /* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */
16420 #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
16421 #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
16422 #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
16423 #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
16424 #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */
16425 
16426 /* Bit 1 : Write '1' to enable interrupt for event STARTED */
16427 #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */
16428 #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
16429 #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
16430 #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
16431 #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */
16432 
16433 /* Bit 0 : Write '1' to enable interrupt for event USBRESET */
16434 #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
16435 #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
16436 #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */
16437 #define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */
16438 #define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */
16439 
16440 /* Register: USBD_INTENCLR */
16441 /* Description: Disable interrupt */
16442 
16443 /* Bit 24 : Write '1' to disable interrupt for event EPDATA */
16444 #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
16445 #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
16446 #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */
16447 #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */
16448 #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */
16449 
16450 /* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */
16451 #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
16452 #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
16453 #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
16454 #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
16455 #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */
16456 
16457 /* Bit 22 : Write '1' to disable interrupt for event USBEVENT */
16458 #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
16459 #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
16460 #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
16461 #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
16462 #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */
16463 
16464 /* Bit 21 : Write '1' to disable interrupt for event SOF */
16465 #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
16466 #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
16467 #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
16468 #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
16469 #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */
16470 
16471 /* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */
16472 #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
16473 #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
16474 #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
16475 #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
16476 #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */
16477 
16478 /* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */
16479 #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
16480 #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
16481 #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
16482 #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
16483 #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */
16484 
16485 /* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */
16486 #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
16487 #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
16488 #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
16489 #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
16490 #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */
16491 
16492 /* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */
16493 #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
16494 #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
16495 #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
16496 #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
16497 #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */
16498 
16499 /* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */
16500 #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
16501 #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
16502 #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
16503 #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
16504 #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */
16505 
16506 /* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */
16507 #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
16508 #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
16509 #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
16510 #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
16511 #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */
16512 
16513 /* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */
16514 #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
16515 #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
16516 #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
16517 #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
16518 #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */
16519 
16520 /* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */
16521 #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
16522 #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
16523 #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
16524 #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
16525 #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */
16526 
16527 /* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */
16528 #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
16529 #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
16530 #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
16531 #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
16532 #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */
16533 
16534 /* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */
16535 #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
16536 #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
16537 #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
16538 #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
16539 #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */
16540 
16541 /* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */
16542 #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
16543 #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
16544 #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
16545 #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
16546 #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */
16547 
16548 /* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */
16549 #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
16550 #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
16551 #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
16552 #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
16553 #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */
16554 
16555 /* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */
16556 #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
16557 #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
16558 #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
16559 #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
16560 #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */
16561 
16562 /* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */
16563 #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
16564 #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
16565 #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
16566 #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
16567 #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */
16568 
16569 /* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */
16570 #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
16571 #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
16572 #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
16573 #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
16574 #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */
16575 
16576 /* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */
16577 #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
16578 #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
16579 #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
16580 #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
16581 #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */
16582 
16583 /* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */
16584 #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
16585 #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
16586 #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
16587 #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
16588 #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */
16589 
16590 /* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */
16591 #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
16592 #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
16593 #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
16594 #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
16595 #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */
16596 
16597 /* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */
16598 #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
16599 #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
16600 #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
16601 #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
16602 #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */
16603 
16604 /* Bit 1 : Write '1' to disable interrupt for event STARTED */
16605 #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */
16606 #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
16607 #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
16608 #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
16609 #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
16610 
16611 /* Bit 0 : Write '1' to disable interrupt for event USBRESET */
16612 #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
16613 #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
16614 #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */
16615 #define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */
16616 #define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */
16617 
16618 /* Register: USBD_EVENTCAUSE */
16619 /* Description: Details on what caused the USBEVENT event */
16620 
16621 /* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */
16622 #define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
16623 #define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
16624 #define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
16625 #define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */
16626 
16627 /* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
16628 #define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */
16629 #define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */
16630 #define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */
16631 #define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */
16632 
16633 /* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */
16634 #define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
16635 #define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
16636 #define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */
16637 #define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */
16638 
16639 /* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */
16640 #define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
16641 #define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
16642 #define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */
16643 #define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */
16644 
16645 /* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
16646 #define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */
16647 #define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */
16648 #define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */
16649 #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */
16650 
16651 /* Register: USBD_HALTED_EPIN */
16652 /* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
16653 
16654 /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
16655 #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
16656 #define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
16657 #define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
16658 #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
16659 
16660 /* Register: USBD_HALTED_EPOUT */
16661 /* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
16662 
16663 /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
16664 #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
16665 #define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
16666 #define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
16667 #define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
16668 
16669 /* Register: USBD_EPSTATUS */
16670 /* Description: Provides information on which endpoint's EasyDMA registers have been captured */
16671 
16672 /* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16673 #define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */
16674 #define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */
16675 #define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16676 #define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16677 
16678 /* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16679 #define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
16680 #define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
16681 #define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16682 #define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16683 
16684 /* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16685 #define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
16686 #define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
16687 #define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16688 #define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16689 
16690 /* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16691 #define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
16692 #define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
16693 #define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16694 #define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16695 
16696 /* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16697 #define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
16698 #define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
16699 #define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16700 #define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16701 
16702 /* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16703 #define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
16704 #define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
16705 #define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16706 #define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16707 
16708 /* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16709 #define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
16710 #define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
16711 #define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16712 #define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16713 
16714 /* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16715 #define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
16716 #define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
16717 #define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16718 #define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16719 
16720 /* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16721 #define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */
16722 #define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */
16723 #define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16724 #define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16725 
16726 /* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16727 #define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */
16728 #define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */
16729 #define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16730 #define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16731 
16732 /* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16733 #define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
16734 #define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
16735 #define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16736 #define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16737 
16738 /* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16739 #define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
16740 #define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
16741 #define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16742 #define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16743 
16744 /* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16745 #define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
16746 #define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
16747 #define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16748 #define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16749 
16750 /* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16751 #define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
16752 #define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
16753 #define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16754 #define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16755 
16756 /* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16757 #define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
16758 #define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
16759 #define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16760 #define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16761 
16762 /* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16763 #define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
16764 #define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
16765 #define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16766 #define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16767 
16768 /* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16769 #define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
16770 #define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
16771 #define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16772 #define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16773 
16774 /* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
16775 #define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */
16776 #define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */
16777 #define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
16778 #define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
16779 
16780 /* Register: USBD_EPDATASTATUS */
16781 /* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */
16782 
16783 /* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16784 #define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
16785 #define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
16786 #define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16787 #define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16788 
16789 /* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16790 #define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
16791 #define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
16792 #define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16793 #define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16794 
16795 /* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16796 #define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
16797 #define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
16798 #define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16799 #define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16800 
16801 /* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16802 #define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
16803 #define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
16804 #define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16805 #define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16806 
16807 /* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16808 #define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
16809 #define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
16810 #define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16811 #define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16812 
16813 /* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16814 #define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
16815 #define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
16816 #define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16817 #define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16818 
16819 /* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
16820 #define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
16821 #define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
16822 #define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
16823 #define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16824 
16825 /* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16826 #define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
16827 #define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
16828 #define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16829 #define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16830 
16831 /* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16832 #define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
16833 #define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
16834 #define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16835 #define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16836 
16837 /* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16838 #define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
16839 #define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
16840 #define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16841 #define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16842 
16843 /* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16844 #define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
16845 #define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
16846 #define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16847 #define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16848 
16849 /* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16850 #define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
16851 #define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
16852 #define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16853 #define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16854 
16855 /* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16856 #define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
16857 #define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
16858 #define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16859 #define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16860 
16861 /* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
16862 #define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
16863 #define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
16864 #define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
16865 #define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
16866 
16867 /* Register: USBD_USBADDR */
16868 /* Description: Device USB address */
16869 
16870 /* Bits 6..0 : Device USB address */
16871 #define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
16872 #define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
16873 
16874 /* Register: USBD_BMREQUESTTYPE */
16875 /* Description: SETUP data, byte 0, bmRequestType */
16876 
16877 /* Bit 7 : Data transfer direction */
16878 #define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */
16879 #define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */
16880 #define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */
16881 #define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */
16882 
16883 /* Bits 6..5 : Data transfer type */
16884 #define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */
16885 #define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */
16886 #define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */
16887 #define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */
16888 #define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */
16889 
16890 /* Bits 4..0 : Data transfer type */
16891 #define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */
16892 #define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */
16893 #define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */
16894 #define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */
16895 #define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */
16896 #define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */
16897 
16898 /* Register: USBD_BREQUEST */
16899 /* Description: SETUP data, byte 1, bRequest */
16900 
16901 /* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */
16902 #define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */
16903 #define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */
16904 #define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */
16905 #define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */
16906 #define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */
16907 #define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */
16908 #define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */
16909 #define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */
16910 #define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */
16911 #define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */
16912 #define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */
16913 #define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */
16914 #define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */
16915 
16916 /* Register: USBD_WVALUEL */
16917 /* Description: SETUP data, byte 2, LSB of wValue */
16918 
16919 /* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
16920 #define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */
16921 #define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */
16922 
16923 /* Register: USBD_WVALUEH */
16924 /* Description: SETUP data, byte 3, MSB of wValue */
16925 
16926 /* Bits 7..0 : SETUP data, byte 3, MSB of wValue */
16927 #define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */
16928 #define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */
16929 
16930 /* Register: USBD_WINDEXL */
16931 /* Description: SETUP data, byte 4, LSB of wIndex */
16932 
16933 /* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */
16934 #define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */
16935 #define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */
16936 
16937 /* Register: USBD_WINDEXH */
16938 /* Description: SETUP data, byte 5, MSB of wIndex */
16939 
16940 /* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */
16941 #define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */
16942 #define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */
16943 
16944 /* Register: USBD_WLENGTHL */
16945 /* Description: SETUP data, byte 6, LSB of wLength */
16946 
16947 /* Bits 7..0 : SETUP data, byte 6, LSB of wLength */
16948 #define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */
16949 #define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */
16950 
16951 /* Register: USBD_WLENGTHH */
16952 /* Description: SETUP data, byte 7, MSB of wLength */
16953 
16954 /* Bits 7..0 : SETUP data, byte 7, MSB of wLength */
16955 #define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */
16956 #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */
16957 
16958 /* Register: USBD_SIZE_EPOUT */
16959 /* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */
16960 
16961 /* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */
16962 #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
16963 #define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
16964 
16965 /* Register: USBD_SIZE_ISOOUT */
16966 /* Description: Number of bytes received last on this ISO OUT data endpoint */
16967 
16968 /* Bit 16 : Zero-length data packet received */
16969 #define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
16970 #define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
16971 #define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
16972 #define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
16973 
16974 /* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */
16975 #define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
16976 #define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
16977 
16978 /* Register: USBD_ENABLE */
16979 /* Description: Enable USB */
16980 
16981 /* Bit 0 : Enable USB */
16982 #define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
16983 #define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
16984 #define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */
16985 #define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */
16986 
16987 /* Register: USBD_USBPULLUP */
16988 /* Description: Control of the USB pull-up */
16989 
16990 /* Bit 0 : Control of the USB pull-up on the D+ line */
16991 #define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */
16992 #define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16993 #define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */
16994 #define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */
16995 
16996 /* Register: USBD_DPDMVALUE */
16997 /* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */
16998 
16999 /* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
17000 #define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
17001 #define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
17002 #define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */
17003 #define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
17004 #define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
17005 
17006 /* Register: USBD_DTOGGLE */
17007 /* Description: Data toggle control and status */
17008 
17009 /* Bits 9..8 : Data toggle value */
17010 #define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
17011 #define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
17012 #define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */
17013 #define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
17014 #define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
17015 
17016 /* Bit 7 : Selects IN or OUT endpoint */
17017 #define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */
17018 #define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */
17019 #define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */
17020 #define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */
17021 
17022 /* Bits 2..0 : Select bulk endpoint number */
17023 #define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */
17024 #define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */
17025 
17026 /* Register: USBD_EPINEN */
17027 /* Description: Endpoint IN enable */
17028 
17029 /* Bit 8 : Enable ISO IN endpoint */
17030 #define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
17031 #define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
17032 #define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */
17033 #define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */
17034 
17035 /* Bit 7 : Enable IN endpoint 7 */
17036 #define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
17037 #define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
17038 #define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
17039 #define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */
17040 
17041 /* Bit 6 : Enable IN endpoint 6 */
17042 #define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
17043 #define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
17044 #define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
17045 #define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
17046 
17047 /* Bit 5 : Enable IN endpoint 5 */
17048 #define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
17049 #define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
17050 #define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
17051 #define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
17052 
17053 /* Bit 4 : Enable IN endpoint 4 */
17054 #define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
17055 #define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
17056 #define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
17057 #define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
17058 
17059 /* Bit 3 : Enable IN endpoint 3 */
17060 #define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
17061 #define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
17062 #define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
17063 #define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
17064 
17065 /* Bit 2 : Enable IN endpoint 2 */
17066 #define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
17067 #define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
17068 #define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
17069 #define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
17070 
17071 /* Bit 1 : Enable IN endpoint 1 */
17072 #define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
17073 #define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
17074 #define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
17075 #define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
17076 
17077 /* Bit 0 : Enable IN endpoint 0 */
17078 #define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
17079 #define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
17080 #define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
17081 #define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
17082 
17083 /* Register: USBD_EPOUTEN */
17084 /* Description: Endpoint OUT enable */
17085 
17086 /* Bit 8 : Enable ISO OUT endpoint 8 */
17087 #define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
17088 #define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
17089 #define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */
17090 #define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */
17091 
17092 /* Bit 7 : Enable OUT endpoint 7 */
17093 #define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
17094 #define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
17095 #define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
17096 #define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
17097 
17098 /* Bit 6 : Enable OUT endpoint 6 */
17099 #define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
17100 #define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
17101 #define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
17102 #define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
17103 
17104 /* Bit 5 : Enable OUT endpoint 5 */
17105 #define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
17106 #define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
17107 #define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
17108 #define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
17109 
17110 /* Bit 4 : Enable OUT endpoint 4 */
17111 #define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
17112 #define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
17113 #define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
17114 #define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
17115 
17116 /* Bit 3 : Enable OUT endpoint 3 */
17117 #define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
17118 #define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
17119 #define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
17120 #define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
17121 
17122 /* Bit 2 : Enable OUT endpoint 2 */
17123 #define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
17124 #define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
17125 #define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
17126 #define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
17127 
17128 /* Bit 1 : Enable OUT endpoint 1 */
17129 #define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
17130 #define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
17131 #define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
17132 #define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
17133 
17134 /* Bit 0 : Enable OUT endpoint 0 */
17135 #define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
17136 #define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
17137 #define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
17138 #define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
17139 
17140 /* Register: USBD_EPSTALL */
17141 /* Description: STALL endpoints */
17142 
17143 /* Bit 8 : Stall selected endpoint */
17144 #define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
17145 #define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
17146 #define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */
17147 #define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */
17148 
17149 /* Bit 7 : Selects IN or OUT endpoint */
17150 #define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */
17151 #define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */
17152 #define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */
17153 #define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */
17154 
17155 /* Bits 2..0 : Select endpoint number */
17156 #define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */
17157 #define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */
17158 
17159 /* Register: USBD_ISOSPLIT */
17160 /* Description: Controls the split of ISO buffers */
17161 
17162 /* Bits 15..0 : Controls the split of ISO buffers */
17163 #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
17164 #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
17165 #define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */
17166 #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */
17167 
17168 /* Register: USBD_FRAMECNTR */
17169 /* Description: Returns the current value of the start of frame counter */
17170 
17171 /* Bits 10..0 : Returns the current value of the start of frame counter */
17172 #define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */
17173 #define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */
17174 
17175 /* Register: USBD_LOWPOWER */
17176 /* Description: Controls USBD peripheral low power mode during USB suspend */
17177 
17178 /* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */
17179 #define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */
17180 #define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */
17181 #define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */
17182 #define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */
17183 
17184 /* Register: USBD_ISOINCONFIG */
17185 /* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
17186 
17187 /* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
17188 #define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
17189 #define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
17190 #define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */
17191 #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */
17192 
17193 /* Register: USBD_EPIN_PTR */
17194 /* Description: Description cluster: Data pointer */
17195 
17196 /* Bits 31..0 : Data pointer */
17197 #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
17198 #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
17199 
17200 /* Register: USBD_EPIN_MAXCNT */
17201 /* Description: Description cluster: Maximum number of bytes to transfer */
17202 
17203 /* Bits 6..0 : Maximum number of bytes to transfer */
17204 #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
17205 #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
17206 
17207 /* Register: USBD_EPIN_AMOUNT */
17208 /* Description: Description cluster: Number of bytes transferred in the last transaction */
17209 
17210 /* Bits 6..0 : Number of bytes transferred in the last transaction */
17211 #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
17212 #define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
17213 
17214 /* Register: USBD_ISOIN_PTR */
17215 /* Description: Data pointer */
17216 
17217 /* Bits 31..0 : Data pointer */
17218 #define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
17219 #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
17220 
17221 /* Register: USBD_ISOIN_MAXCNT */
17222 /* Description: Maximum number of bytes to transfer */
17223 
17224 /* Bits 9..0 : Maximum number of bytes to transfer */
17225 #define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
17226 #define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
17227 
17228 /* Register: USBD_ISOIN_AMOUNT */
17229 /* Description: Number of bytes transferred in the last transaction */
17230 
17231 /* Bits 9..0 : Number of bytes transferred in the last transaction */
17232 #define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
17233 #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
17234 
17235 /* Register: USBD_EPOUT_PTR */
17236 /* Description: Description cluster: Data pointer */
17237 
17238 /* Bits 31..0 : Data pointer */
17239 #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
17240 #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
17241 
17242 /* Register: USBD_EPOUT_MAXCNT */
17243 /* Description: Description cluster: Maximum number of bytes to transfer */
17244 
17245 /* Bits 6..0 : Maximum number of bytes to transfer */
17246 #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
17247 #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
17248 
17249 /* Register: USBD_EPOUT_AMOUNT */
17250 /* Description: Description cluster: Number of bytes transferred in the last transaction */
17251 
17252 /* Bits 6..0 : Number of bytes transferred in the last transaction */
17253 #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
17254 #define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
17255 
17256 /* Register: USBD_ISOOUT_PTR */
17257 /* Description: Data pointer */
17258 
17259 /* Bits 31..0 : Data pointer */
17260 #define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
17261 #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
17262 
17263 /* Register: USBD_ISOOUT_MAXCNT */
17264 /* Description: Maximum number of bytes to transfer */
17265 
17266 /* Bits 9..0 : Maximum number of bytes to transfer */
17267 #define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
17268 #define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
17269 
17270 /* Register: USBD_ISOOUT_AMOUNT */
17271 /* Description: Number of bytes transferred in the last transaction */
17272 
17273 /* Bits 9..0 : Number of bytes transferred in the last transaction */
17274 #define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
17275 #define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
17276 
17277 
17278 /* Peripheral: WDT */
17279 /* Description: Watchdog Timer */
17280 
17281 /* Register: WDT_TASKS_START */
17282 /* Description: Start the watchdog */
17283 
17284 /* Bit 0 : Start the watchdog */
17285 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
17286 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
17287 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
17288 
17289 /* Register: WDT_EVENTS_TIMEOUT */
17290 /* Description: Watchdog timeout */
17291 
17292 /* Bit 0 : Watchdog timeout */
17293 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
17294 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
17295 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
17296 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
17297 
17298 /* Register: WDT_INTENSET */
17299 /* Description: Enable interrupt */
17300 
17301 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
17302 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
17303 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
17304 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
17305 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
17306 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
17307 
17308 /* Register: WDT_INTENCLR */
17309 /* Description: Disable interrupt */
17310 
17311 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
17312 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
17313 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
17314 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
17315 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
17316 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
17317 
17318 /* Register: WDT_RUNSTATUS */
17319 /* Description: Run status */
17320 
17321 /* Bit 0 : Indicates whether or not the watchdog is running */
17322 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
17323 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
17324 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
17325 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
17326 
17327 /* Register: WDT_REQSTATUS */
17328 /* Description: Request status */
17329 
17330 /* Bit 7 : Request status for RR[7] register */
17331 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
17332 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
17333 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
17334 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
17335 
17336 /* Bit 6 : Request status for RR[6] register */
17337 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
17338 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
17339 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
17340 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
17341 
17342 /* Bit 5 : Request status for RR[5] register */
17343 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
17344 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
17345 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
17346 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
17347 
17348 /* Bit 4 : Request status for RR[4] register */
17349 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
17350 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
17351 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
17352 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
17353 
17354 /* Bit 3 : Request status for RR[3] register */
17355 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
17356 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
17357 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
17358 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
17359 
17360 /* Bit 2 : Request status for RR[2] register */
17361 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
17362 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
17363 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
17364 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
17365 
17366 /* Bit 1 : Request status for RR[1] register */
17367 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
17368 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
17369 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
17370 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
17371 
17372 /* Bit 0 : Request status for RR[0] register */
17373 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
17374 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
17375 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
17376 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
17377 
17378 /* Register: WDT_CRV */
17379 /* Description: Counter reload value */
17380 
17381 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
17382 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
17383 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
17384 
17385 /* Register: WDT_RREN */
17386 /* Description: Enable register for reload request registers */
17387 
17388 /* Bit 7 : Enable or disable RR[7] register */
17389 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
17390 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
17391 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
17392 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
17393 
17394 /* Bit 6 : Enable or disable RR[6] register */
17395 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
17396 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
17397 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
17398 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
17399 
17400 /* Bit 5 : Enable or disable RR[5] register */
17401 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
17402 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
17403 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
17404 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
17405 
17406 /* Bit 4 : Enable or disable RR[4] register */
17407 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
17408 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
17409 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
17410 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
17411 
17412 /* Bit 3 : Enable or disable RR[3] register */
17413 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
17414 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
17415 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
17416 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
17417 
17418 /* Bit 2 : Enable or disable RR[2] register */
17419 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
17420 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
17421 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
17422 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
17423 
17424 /* Bit 1 : Enable or disable RR[1] register */
17425 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
17426 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
17427 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
17428 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
17429 
17430 /* Bit 0 : Enable or disable RR[0] register */
17431 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
17432 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
17433 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
17434 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
17435 
17436 /* Register: WDT_CONFIG */
17437 /* Description: Configuration register */
17438 
17439 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
17440 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
17441 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
17442 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
17443 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
17444 
17445 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
17446 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
17447 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
17448 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
17449 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
17450 
17451 /* Register: WDT_RR */
17452 /* Description: Description collection: Reload request n */
17453 
17454 /* Bits 31..0 : Reload request register */
17455 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
17456 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
17457 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
17458 
17459 
17460 /*lint --flb "Leave library region" */
17461 #endif
17462