Searched refs:reg (Results 1 – 5 of 5) sorted by relevance
858 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); in nrf_gpio_cfg() local859 uint32_t cnf = reg->PIN_CNF[pin_number]; in nrf_gpio_cfg()884 reg->PIN_CNF[pin_number] = cnf; in nrf_gpio_cfg()894 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); in nrf_gpio_reconfigure() local895 uint32_t cnf = reg->PIN_CNF[pin_number]; in nrf_gpio_reconfigure()918 reg->PIN_CNF[pin_number] = cnf; in nrf_gpio_reconfigure()1007 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); in nrf_gpio_pin_dir_set() local1008 reg->DIRSET = (1UL << pin_number); in nrf_gpio_pin_dir_set()1015 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); in nrf_gpio_pin_set() local1017 nrf_gpio_port_out_set(reg, 1UL << pin_number); in nrf_gpio_pin_set()[all …]
873 uint32_t reg = 0; in nrf_qspi_cinstrdata_set() local880 reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos; in nrf_qspi_cinstrdata_set()883 reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos; in nrf_qspi_cinstrdata_set()886 reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos; in nrf_qspi_cinstrdata_set()889 reg |= ((uint32_t)p_tx_data_8[4]); in nrf_qspi_cinstrdata_set()890 p_reg->CINSTRDAT1 = reg; in nrf_qspi_cinstrdata_set()891 reg = 0; in nrf_qspi_cinstrdata_set()894 reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos; in nrf_qspi_cinstrdata_set()897 reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos; in nrf_qspi_cinstrdata_set()900 reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos; in nrf_qspi_cinstrdata_set()[all …]
694 volatile CACHEDATA_SET_WAY_Type const * reg = &p_reg->SET[set].WAY[way]; in nrf_cache_data_get()697 case 0: return reg->DATA0; in nrf_cache_data_get()698 case 1: return reg->DATA1; in nrf_cache_data_get()699 case 2: return reg->DATA2; in nrf_cache_data_get()700 case 3: return reg->DATA3; in nrf_cache_data_get()
416 /* fix placement of <sup>®</sup> */
412 /* fix placement of <sup>®</sup> */
