1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_TWIM_H__
35 #define NRF_TWIM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_twim_hal TWIM HAL
45 * @{
46 * @ingroup nrf_twim
47 * @brief Hardware access layer for managing the TWIM peripheral.
48 */
49
50 /**
51 * @brief Macro getting pointer to the structure of registers of the TWIM peripheral.
52 *
53 * @param[in] idx TWIM instance index.
54 *
55 * @return Pointer to the structure of registers of the TWIM peripheral.
56 */
57 #define NRF_TWIM_INST_GET(idx) NRFX_CONCAT_2(NRF_TWIM, idx)
58
59 #if defined(TWIM_FREQUENCY_FREQUENCY_K1000) || defined(__NRFX_DOXYGEN__)
60 /** @brief Symbol indicating whether 1000 kHz clock frequency is available. */
61 #define NRF_TWIM_HAS_1000_KHZ_FREQ 1
62 #else
63 #define NRF_TWIM_HAS_1000_KHZ_FREQ 0
64 #endif
65
66 #if defined(TWIM_TXD_LIST_LIST_ArrayList) || defined(__NRFX_DOXYGEN__)
67 /** @brief Symbol indicating whether EasyDMA array list feature is present. */
68 #define NRF_TWIM_HAS_ARRAY_LIST 1
69 #else
70 #define NRF_TWIM_HAS_ARRAY_LIST 0
71 #endif
72
73 #if defined(TWIM_DMA_RX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
74 /** @brief Symbol indicating whether dedicated DMA register is present. */
75 #define NRF_TWIM_HAS_DMA_REG 1
76 #else
77 #define NRF_TWIM_HAS_DMA_REG 0
78 #endif
79
80 #if (defined(TWIM_TASKS_DMA_RX_START_START_Msk) && defined(TWIM_EVENTS_DMA_RX_END_END_Msk)) || \
81 defined(__NRFX_DOXYGEN__)
82 /** @brief Symbol indicating whether TWIM DMA tasks and events are present. */
83 #define NRF_TWIM_HAS_DMA_TASKS_EVENTS 1
84 #else
85 #define NRF_TWIM_HAS_DMA_TASKS_EVENTS 0
86 #endif
87
88 #if NRF_TWIM_HAS_DMA_REG
89 /** @brief Max number of RX patterns. */
90 #define NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT TWIM_DMA_RX_MATCH_CANDIDATE_MaxCount
91 #endif
92
93 /** @brief TWIM tasks. */
94 typedef enum
95 {
96 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
97 NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.START), ///< Start TWI receive sequence.
98 NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_DMA.TX.START), ///< Start TWI transmit sequence.
99 NRF_TWIM_TASK_ENABLERXMATCH0 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.ENABLEMATCH[0]), ///< Enable TWI pattern matching functionality for pattern 0.
100 NRF_TWIM_TASK_ENABLERXMATCH1 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.ENABLEMATCH[1]), ///< Enable TWI pattern matching functionality for pattern 1.
101 NRF_TWIM_TASK_ENABLERXMATCH2 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.ENABLEMATCH[2]), ///< Enable TWI pattern matching functionality for pattern 2.
102 NRF_TWIM_TASK_ENABLERXMATCH3 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.ENABLEMATCH[3]), ///< Enable TWI pattern matching functionality for pattern 3.
103 NRF_TWIM_TASK_DISABLERXMATCH0 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.DISABLEMATCH[0]), ///< Disable TWI pattern matching functionality for pattern 0.
104 NRF_TWIM_TASK_DISABLERXMATCH1 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.DISABLEMATCH[1]), ///< Disable TWI pattern matching functionality for pattern 1.
105 NRF_TWIM_TASK_DISABLERXMATCH2 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.DISABLEMATCH[2]), ///< Disable TWI pattern matching functionality for pattern 2.
106 NRF_TWIM_TASK_DISABLERXMATCH3 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.DISABLEMATCH[3]), ///< Disable TWI pattern matching functionality for pattern 3.
107 #else
108 NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
109 NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
110 #endif
111 NRF_TWIM_TASK_STOP = offsetof(NRF_TWIM_Type, TASKS_STOP), ///< Stop TWI transaction.
112 NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
113 NRF_TWIM_TASK_RESUME = offsetof(NRF_TWIM_Type, TASKS_RESUME) ///< Resume TWI transaction.
114 } nrf_twim_task_t;
115
116 /** @brief TWIM events. */
117 typedef enum
118 {
119 NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped.
120 NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error.
121 NRF_TWIM_EVENT_SUSPENDED = offsetof(NRF_TWIM_Type, EVENTS_SUSPENDED), ///< TWI suspended.
122 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
123 NRF_TWIM_EVENT_ENDRX = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.END), ///< Receive sequence finished.
124 NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.READY), ///< Receive sequence started.
125 NRF_TWIM_EVENT_RXBUSERROR = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.BUSERROR), ///< Memory bus error occurred during the RX transfer.
126 NRF_TWIM_EVENT_RXMATCH0 = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.MATCH[0]), ///< Pattern match for pattern 0 detected.
127 NRF_TWIM_EVENT_RXMATCH1 = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.MATCH[1]), ///< Pattern match for pattern 1 detected.
128 NRF_TWIM_EVENT_RXMATCH2 = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.MATCH[2]), ///< Pattern match for pattern 2 detected.
129 NRF_TWIM_EVENT_RXMATCH3 = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.MATCH[3]), ///< Pattern match for pattern 3 detected.
130 NRF_TWIM_EVENT_ENDTX = offsetof(NRF_TWIM_Type, EVENTS_DMA.TX.END), ///< Transmit sequence finished.
131 NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_DMA.TX.READY), ///< Transmit sequence started.
132 NRF_TWIM_EVENT_TXBUSERROR = offsetof(NRF_TWIM_Type, EVENTS_DMA.TX.BUSERROR), ///< Memory bus error occurred during the TX transfer.
133 #else
134 NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started.
135 NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started.
136 #endif
137 NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte.
138 NRF_TWIM_EVENT_LASTTX = offsetof(NRF_TWIM_Type, EVENTS_LASTTX) ///< Byte boundary, starting to transmit the last byte.
139 } nrf_twim_event_t;
140
141 /** @brief TWIM shortcuts. */
142 typedef enum
143 {
144 NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task.
145 NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK = TWIM_SHORTS_LASTTX_SUSPEND_Msk, ///< Shortcut between LASTTX event and SUSPEND task.
146 NRF_TWIM_SHORT_LASTTX_STOP_MASK = TWIM_SHORTS_LASTTX_STOP_Msk, ///< Shortcut between LASTTX event and STOP task.
147 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
148 NRF_TWIM_SHORT_RXMATCH0_ENABLERXMATCH1_MASK = TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.ENABLEMATCH1 task.
149 NRF_TWIM_SHORT_RXMATCH1_ENABLERXMATCH2_MASK = TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.ENABLEMATCH2 task.
150 NRF_TWIM_SHORT_RXMATCH2_ENABLERXMATCH3_MASK = TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH0 task.
151 NRF_TWIM_SHORT_RXMATCH3_ENABLERXMATCH0_MASK = TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH1 task.
152 NRF_TWIM_SHORT_RXMATCH0_DISABLERXMATCH0_MASK = TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.DISABLEMATCH0 task.
153 NRF_TWIM_SHORT_RXMATCH1_DISABLERXMATCH1_MASK = TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.DISABLEMATCH1 task.
154 NRF_TWIM_SHORT_RXMATCH2_DISABLERXMATCH2_MASK = TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.DISABLEMATCH2 task.
155 NRF_TWIM_SHORT_RXMATCH3_DISABLERXMATCH3_MASK = TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.DISABLEMATCH3 task.
156 #endif
157 NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_STARTTX_Msk, ///< Shortcut between LASTRX event and STARTTX task.
158 NRF_TWIM_SHORT_LASTRX_STOP_MASK = TWIM_SHORTS_LASTRX_STOP_Msk, ///< Shortcut between LASTRX event and STOP task.
159 NRF_TWIM_ALL_SHORTS_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk |
160 TWIM_SHORTS_LASTTX_SUSPEND_Msk |
161 TWIM_SHORTS_LASTTX_STOP_Msk |
162 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
163 TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk |
164 TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk |
165 TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk |
166 TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk |
167 TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk |
168 TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk |
169 TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk |
170 TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk |
171 #endif
172 TWIM_SHORTS_LASTRX_STARTTX_Msk |
173 TWIM_SHORTS_LASTRX_STOP_Msk ///< All TWIM shortcuts.
174 } nrf_twim_short_mask_t;
175
176 /** @brief TWIM interrupts. */
177 typedef enum
178 {
179 NRF_TWIM_INT_STOPPED_MASK = TWIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
180 NRF_TWIM_INT_ERROR_MASK = TWIM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
181 NRF_TWIM_INT_SUSPENDED_MASK = TWIM_INTENSET_SUSPENDED_Msk, ///< Interrupt on SUSPENDED event.
182 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
183 NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_DMARXREADY_Msk, ///< Interrupt on RXSTARTED event.
184 NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_DMATXREADY_Msk, ///< Interrupt on TXSTARTED event.
185 NRF_TWIM_INT_ENDRX_MASK = TWIM_INTENSET_DMARXEND_Msk, ///< Interrupt on DMA.RX.END event.
186 NRF_TWIM_INT_RXREADY_MASK = TWIM_INTENSET_DMARXREADY_Msk, ///< Interrupt on DMA.RX.READY event.
187 NRF_TWIM_INT_RXBUSERROR_MASK = TWIM_INTENSET_DMARXBUSERROR_Msk, ///< Interrupt on DMA.RX.BUSERROR event.
188 NRF_TWIM_INT_RXMATCH0_MASK = TWIM_INTENSET_DMARXMATCH0_Msk, ///< Interrupt on DMA.RX.MATCH0 event.
189 NRF_TWIM_INT_RXMATCH1_MASK = TWIM_INTENSET_DMARXMATCH1_Msk, ///< Interrupt on DMA.RX.MATCH1 event.
190 NRF_TWIM_INT_RXMATCH2_MASK = TWIM_INTENSET_DMARXMATCH2_Msk, ///< Interrupt on DMA.RX.MATCH2 event.
191 NRF_TWIM_INT_RXMATCH3_MASK = TWIM_INTENSET_DMARXMATCH3_Msk, ///< Interrupt on DMA.RX.MATCH3 event.
192 NRF_TWIM_INT_ENDTX_MASK = TWIM_INTENSET_DMATXEND_Msk, ///< Interrupt on DMA.TX.END event.
193 NRF_TWIM_INT_TXREADY_MASK = TWIM_INTENSET_DMATXREADY_Msk, ///< Interrupt on DMA.TX.READY event.
194 NRF_TWIM_INT_TXBUSERROR_MASK = TWIM_INTENSET_DMATXBUSERROR_Msk, ///< Interrupt on DMA.TX.BUSERROR event.
195 #else
196 NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
197 NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
198 #endif
199 NRF_TWIM_INT_LASTRX_MASK = TWIM_INTENSET_LASTRX_Msk, ///< Interrupt on LASTRX event.
200 NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk, ///< Interrupt on LASTTX event.
201 NRF_TWIM_ALL_INTS_MASK = NRF_TWIM_INT_STOPPED_MASK |
202 NRF_TWIM_INT_ERROR_MASK |
203 NRF_TWIM_INT_SUSPENDED_MASK |
204 NRF_TWIM_INT_RXSTARTED_MASK |
205 NRF_TWIM_INT_TXSTARTED_MASK |
206 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
207 NRF_TWIM_INT_ENDRX_MASK |
208 NRF_TWIM_INT_RXREADY_MASK |
209 NRF_TWIM_INT_RXBUSERROR_MASK |
210 NRF_TWIM_INT_RXMATCH0_MASK |
211 NRF_TWIM_INT_RXMATCH1_MASK |
212 NRF_TWIM_INT_RXMATCH2_MASK |
213 NRF_TWIM_INT_RXMATCH3_MASK |
214 NRF_TWIM_INT_ENDTX_MASK |
215 NRF_TWIM_INT_TXREADY_MASK |
216 NRF_TWIM_INT_TXBUSERROR_MASK |
217 #endif
218 NRF_TWIM_INT_LASTRX_MASK |
219 NRF_TWIM_INT_LASTTX_MASK ///< All TWIM interrupts.
220 } nrf_twim_int_mask_t;
221
222 /** @brief TWIM master clock frequency. */
223 typedef enum
224 {
225 NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
226 NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
227 NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400, ///< 400 kbps.
228 #if NRF_TWIM_HAS_1000_KHZ_FREQ
229 NRF_TWIM_FREQ_1000K = TWIM_FREQUENCY_FREQUENCY_K1000 ///< 1000 kbps.
230 #endif
231 } nrf_twim_frequency_t;
232
233 /** @brief TWIM error source. */
234 typedef enum
235 {
236 NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
237 NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk, ///< NACK received after sending a data byte.
238 NRF_TWIM_ERROR_OVERRUN = TWIM_ERRORSRC_OVERRUN_Msk ///< Overrun error.
239 /**< A new byte was received before the previous byte was
240 * handled by peripheral. (previous data is lost). */
241 } nrf_twim_error_t;
242
243
244 /**
245 * @brief Function for activating the specified TWIM task.
246 *
247 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
248 * @param[in] task Task to be activated.
249 */
250 NRF_STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
251 nrf_twim_task_t task);
252
253 /**
254 * @brief Function for getting the address of the specified TWIM task register.
255 *
256 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
257 * @param[in] task The specified task.
258 *
259 * @return Address of the specified task register.
260 */
261 NRF_STATIC_INLINE uint32_t nrf_twim_task_address_get(NRF_TWIM_Type const * p_reg,
262 nrf_twim_task_t task);
263
264 /**
265 * @brief Function for clearing the specified TWIM event.
266 *
267 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
268 * @param[in] event Event to clear.
269 */
270 NRF_STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
271 nrf_twim_event_t event);
272
273 /**
274 * @brief Function for retrieving the state of the TWIM event.
275 *
276 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
277 * @param[in] event Event to be checked.
278 *
279 * @retval true The event has been generated.
280 * @retval false The event has not been generated.
281 */
282 NRF_STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type const * p_reg,
283 nrf_twim_event_t event);
284
285 /**
286 * @brief Function for getting the address of the specified TWIM event register.
287 *
288 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
289 * @param[in] event The specified event.
290 *
291 * @return Address of the specified event register.
292 */
293 NRF_STATIC_INLINE uint32_t nrf_twim_event_address_get(NRF_TWIM_Type const * p_reg,
294 nrf_twim_event_t event);
295
296 /**
297 * @brief Function for enabling the specified shortcuts.
298 *
299 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
300 * @param[in] mask Shortcuts to be enabled.
301 */
302 NRF_STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
303 uint32_t mask);
304
305 /**
306 * @brief Function for disabling the specified shortcuts.
307 *
308 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
309 * @param[in] mask Shortcuts to be disabled.
310 */
311 NRF_STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
312 uint32_t mask);
313
314 /**
315 * @brief Function for enabling the specified interrupts.
316 *
317 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
318 * @param[in] mask Mask of interrupts to be enabled.
319 */
320 NRF_STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
321 uint32_t mask);
322
323 /**
324 * @brief Function for disabling the specified interrupts.
325 *
326 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
327 * @param[in] mask Mask of interrupts to be disabled.
328 */
329 NRF_STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
330 uint32_t mask);
331
332 /**
333 * @brief Function for checking if the specified interrupts are enabled.
334 *
335 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
336 * @param[in] mask Mask of interrupts to be checked.
337 *
338 * @return Mask of enabled interrupts.
339 */
340 NRF_STATIC_INLINE uint32_t nrf_twim_int_enable_check(NRF_TWIM_Type const * p_reg, uint32_t mask);
341
342 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
343 /**
344 * @brief Function for setting the subscribe configuration for a given
345 * TWIM task.
346 *
347 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
348 * @param[in] task Task for which to set the configuration.
349 * @param[in] channel Channel through which to subscribe events.
350 */
351 NRF_STATIC_INLINE void nrf_twim_subscribe_set(NRF_TWIM_Type * p_reg,
352 nrf_twim_task_t task,
353 uint8_t channel);
354
355 /**
356 * @brief Function for clearing the subscribe configuration for a given
357 * TWIM task.
358 *
359 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
360 * @param[in] task Task for which to clear the configuration.
361 */
362 NRF_STATIC_INLINE void nrf_twim_subscribe_clear(NRF_TWIM_Type * p_reg,
363 nrf_twim_task_t task);
364
365 /**
366 * @brief Function for setting the publish configuration for a given
367 * TWIM event.
368 *
369 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
370 * @param[in] event Event for which to set the configuration.
371 * @param[in] channel Channel through which to publish the event.
372 */
373 NRF_STATIC_INLINE void nrf_twim_publish_set(NRF_TWIM_Type * p_reg,
374 nrf_twim_event_t event,
375 uint8_t channel);
376
377 /**
378 * @brief Function for clearing the publish configuration for a given
379 * TWIM event.
380 *
381 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
382 * @param[in] event Event for which to clear the configuration.
383 */
384 NRF_STATIC_INLINE void nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,
385 nrf_twim_event_t event);
386 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
387
388 /**
389 * @brief Function for enabling the TWIM peripheral.
390 *
391 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
392 */
393 NRF_STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg);
394
395 /**
396 * @brief Function for disabling the TWIM peripheral.
397 *
398 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
399 */
400 NRF_STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg);
401
402 /**
403 * @brief Function for configuring TWI pins.
404 *
405 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
406 * @param[in] scl_pin SCL pin number.
407 * @param[in] sda_pin SDA pin number.
408 */
409 NRF_STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
410 uint32_t scl_pin,
411 uint32_t sda_pin);
412
413 /**
414 * @brief Function for retrieving the SCL pin selection.
415 *
416 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
417 *
418 * @return SCL pin selection.
419 */
420 NRF_STATIC_INLINE uint32_t nrf_twim_scl_pin_get(NRF_TWIM_Type const * p_reg);
421
422 /**
423 * @brief Function for retrieving the SDA pin selection.
424 *
425 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
426 *
427 * @return SDA pin selection.
428 */
429 NRF_STATIC_INLINE uint32_t nrf_twim_sda_pin_get(NRF_TWIM_Type const * p_reg);
430
431 /**
432 * @brief Function for setting the TWI master clock frequency.
433 *
434 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
435 * @param[in] frequency TWI frequency.
436 */
437 NRF_STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
438 nrf_twim_frequency_t frequency);
439
440 /**
441 * @brief Function for checking the TWI error source.
442 *
443 * The error flags are cleared after reading.
444 *
445 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
446 *
447 * @return Mask with error source flags.
448 */
449 NRF_STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg);
450
451 /**
452 * @brief Function for setting the address to be used in TWI transfers.
453 *
454 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
455 * @param[in] address Address to be used in transfers.
456 */
457 NRF_STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
458 uint8_t address);
459
460 /**
461 * @brief Function for getting the address to be used in TWI transfers.
462 *
463 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
464 *
465 * @return Address to be used in TWI transfers.
466 */
467 NRF_STATIC_INLINE uint8_t nrf_twim_address_get(NRF_TWIM_Type const * p_reg);
468
469 /**
470 * @brief Function for setting the transmit buffer.
471 *
472 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
473 * @param[in] p_buffer Pointer to the buffer with data to send.
474 * @param[in] length Maximum number of data bytes to transmit.
475 */
476 NRF_STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
477 uint8_t const * p_buffer,
478 size_t length);
479
480 /**
481 * @brief Function for setting the receive buffer.
482 *
483 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
484 * @param[in] p_buffer Pointer to the buffer for received data.
485 * @param[in] length Maximum number of data bytes to receive.
486 */
487 NRF_STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
488 uint8_t * p_buffer,
489 size_t length);
490
491 /**
492 * @brief Function for setting the specified shortcuts.
493 *
494 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
495 * @param[in] mask Shortcuts to be set.
496 */
497 NRF_STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
498 uint32_t mask);
499
500 /**
501 * @brief Function for getting the shortcut setting.
502 *
503 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
504 *
505 * @return Current shortcut configuration.
506 */
507 NRF_STATIC_INLINE uint32_t nrf_twim_shorts_get(NRF_TWIM_Type const * p_reg);
508
509 /**
510 * @brief Function for getting the amount of transmitted bytes.
511 *
512 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
513 *
514 * @return Amount of transmitted bytes.
515 */
516 NRF_STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type const * p_reg);
517
518 /**
519 * @brief Function for getting the amount of received bytes.
520 *
521 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
522 *
523 * @return Amount of received bytes.
524 */
525 NRF_STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type const * p_reg);
526
527 #if NRF_TWIM_HAS_ARRAY_LIST
528 /**
529 * @brief Function for enabling the TX list feature.
530 *
531 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
532 */
533 NRF_STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg);
534
535 /**
536 * @brief Function for disabling the TX list feature.
537 *
538 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
539 */
540 NRF_STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg);
541
542 /**
543 * @brief Function for enabling the RX list feature.
544 *
545 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
546 */
547 NRF_STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg);
548
549 /**
550 * @brief Function for disabling the RX list feature.
551 *
552 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
553 */
554 NRF_STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg);
555 #endif
556
557 #if NRF_TWIM_HAS_DMA_REG
558 /**
559 * @brief Function for enabling individual pattern match filters.
560 *
561 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
562 * @param[in] index Index of pattern match filter.
563 * @param[in] enable True if pattern match filter is to be enabled, false otherwise.
564 */
565 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_enable_set(NRF_TWIM_Type * p_reg,
566 uint8_t index,
567 bool enable);
568
569 /**
570 * @brief Function for checking if the specified pattern match filter is enabled.
571 *
572 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
573 * @param[in] index Index of pattern match filter.
574 *
575 * @retval true Pattern match filter is enabled.
576 * @retval false Pattern match filter is disabled.
577 */
578 NRF_STATIC_INLINE bool nrf_twim_rx_pattern_match_enable_check(NRF_TWIM_Type const * p_reg,
579 uint8_t index);
580
581 /**
582 * @brief Function for enabling one-shot operation for the specified match filter.
583 *
584 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
585 * @param[in] index Index of pattern match filter.
586 */
587 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_one_shot_enable(NRF_TWIM_Type * p_reg,
588 uint8_t index);
589
590 /**
591 * @brief Function for disabling one-shot operation for the specified match filter.
592 *
593 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
594 * @param[in] index Index of pattern match filter.
595 */
596 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_one_shot_disable(NRF_TWIM_Type * p_reg,
597 uint8_t index);
598
599 /**
600 * @brief Function for checking if specified pattern match filter is configured as one-shot.
601 *
602 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
603 * @param[in] index Index of pattern match filter.
604 *
605 * @retval true Pattern match filter is configured as one-shot.
606 * @retval false Pattern match filter is configured as continuous.
607 */
608 NRF_STATIC_INLINE bool nrf_twim_rx_pattern_match_one_shot_check(NRF_TWIM_Type const * p_reg,
609 uint8_t index);
610
611 /**
612 * @brief Function for setting the pattern to be looked for by the specified match filter.
613 *
614 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
615 * @param[in] index Index of pattern match filter.
616 * @param[in] pattern Pattern to be looked for.
617 * Match will trigger the corresponding event, if enabled.
618 */
619 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_candidate_set(NRF_TWIM_Type * p_reg,
620 uint8_t index,
621 uint32_t pattern);
622
623 /**
624 * @brief Function for getting the pattern that the specified match filter is looking for.
625 *
626 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
627 * @param[in] index Index of pattern match filter.
628 *
629 * @return Pattern that the specified match filter is looking for.
630 */
631 NRF_STATIC_INLINE uint32_t nrf_twim_rx_pattern_match_candidate_get(NRF_TWIM_Type const * p_reg,
632 uint8_t index);
633 #endif // NRF_TWIM_HAS_DMA_REG
634
635 #ifndef NRF_DECLARE_ONLY
636
nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,nrf_twim_task_t task)637 NRF_STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
638 nrf_twim_task_t task)
639 {
640 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
641 }
642
nrf_twim_task_address_get(NRF_TWIM_Type const * p_reg,nrf_twim_task_t task)643 NRF_STATIC_INLINE uint32_t nrf_twim_task_address_get(NRF_TWIM_Type const * p_reg,
644 nrf_twim_task_t task)
645 {
646 return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
647 }
648
nrf_twim_event_clear(NRF_TWIM_Type * p_reg,nrf_twim_event_t event)649 NRF_STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
650 nrf_twim_event_t event)
651 {
652 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
653 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
654 }
655
nrf_twim_event_check(NRF_TWIM_Type const * p_reg,nrf_twim_event_t event)656 NRF_STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type const * p_reg,
657 nrf_twim_event_t event)
658 {
659 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
660 }
661
nrf_twim_event_address_get(NRF_TWIM_Type const * p_reg,nrf_twim_event_t event)662 NRF_STATIC_INLINE uint32_t nrf_twim_event_address_get(NRF_TWIM_Type const * p_reg,
663 nrf_twim_event_t event)
664 {
665 return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
666 }
667
nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,uint32_t mask)668 NRF_STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
669 uint32_t mask)
670 {
671 p_reg->SHORTS |= mask;
672 }
673
nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,uint32_t mask)674 NRF_STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
675 uint32_t mask)
676 {
677 p_reg->SHORTS &= ~(mask);
678 }
679
nrf_twim_int_enable(NRF_TWIM_Type * p_reg,uint32_t mask)680 NRF_STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
681 uint32_t mask)
682 {
683 p_reg->INTENSET = mask;
684 }
685
nrf_twim_int_disable(NRF_TWIM_Type * p_reg,uint32_t mask)686 NRF_STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
687 uint32_t mask)
688 {
689 p_reg->INTENCLR = mask;
690 }
691
nrf_twim_int_enable_check(NRF_TWIM_Type const * p_reg,uint32_t mask)692 NRF_STATIC_INLINE uint32_t nrf_twim_int_enable_check(NRF_TWIM_Type const * p_reg, uint32_t mask)
693 {
694 return p_reg->INTENSET & mask;
695 }
696
697 #if defined(DPPI_PRESENT)
nrf_twim_subscribe_set(NRF_TWIM_Type * p_reg,nrf_twim_task_t task,uint8_t channel)698 NRF_STATIC_INLINE void nrf_twim_subscribe_set(NRF_TWIM_Type * p_reg,
699 nrf_twim_task_t task,
700 uint8_t channel)
701 {
702 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
703 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
704 }
705
nrf_twim_subscribe_clear(NRF_TWIM_Type * p_reg,nrf_twim_task_t task)706 NRF_STATIC_INLINE void nrf_twim_subscribe_clear(NRF_TWIM_Type * p_reg,
707 nrf_twim_task_t task)
708 {
709 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
710 }
711
nrf_twim_publish_set(NRF_TWIM_Type * p_reg,nrf_twim_event_t event,uint8_t channel)712 NRF_STATIC_INLINE void nrf_twim_publish_set(NRF_TWIM_Type * p_reg,
713 nrf_twim_event_t event,
714 uint8_t channel)
715 {
716 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
717 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
718 }
719
nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,nrf_twim_event_t event)720 NRF_STATIC_INLINE void nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,
721 nrf_twim_event_t event)
722 {
723 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
724 }
725 #endif // defined(DPPI_PRESENT)
726
nrf_twim_enable(NRF_TWIM_Type * p_reg)727 NRF_STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg)
728 {
729 p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
730 }
731
nrf_twim_disable(NRF_TWIM_Type * p_reg)732 NRF_STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg)
733 {
734 p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos);
735 }
736
nrf_twim_pins_set(NRF_TWIM_Type * p_reg,uint32_t scl_pin,uint32_t sda_pin)737 NRF_STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
738 uint32_t scl_pin,
739 uint32_t sda_pin)
740 {
741 p_reg->PSEL.SCL = scl_pin;
742 p_reg->PSEL.SDA = sda_pin;
743 }
744
nrf_twim_scl_pin_get(NRF_TWIM_Type const * p_reg)745 NRF_STATIC_INLINE uint32_t nrf_twim_scl_pin_get(NRF_TWIM_Type const * p_reg)
746 {
747 return p_reg->PSEL.SCL;
748 }
749
nrf_twim_sda_pin_get(NRF_TWIM_Type const * p_reg)750 NRF_STATIC_INLINE uint32_t nrf_twim_sda_pin_get(NRF_TWIM_Type const * p_reg)
751 {
752 return p_reg->PSEL.SDA;
753 }
754
nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,nrf_twim_frequency_t frequency)755 NRF_STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
756 nrf_twim_frequency_t frequency)
757 {
758 p_reg->FREQUENCY = frequency;
759 }
760
nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg)761 NRF_STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg)
762 {
763 uint32_t error_source = p_reg->ERRORSRC;
764
765 // [error flags are cleared by writing '1' on their position]
766 p_reg->ERRORSRC = error_source;
767
768 return error_source;
769 }
770
nrf_twim_address_set(NRF_TWIM_Type * p_reg,uint8_t address)771 NRF_STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
772 uint8_t address)
773 {
774 p_reg->ADDRESS = address;
775 }
776
nrf_twim_address_get(NRF_TWIM_Type const * p_reg)777 NRF_STATIC_INLINE uint8_t nrf_twim_address_get(NRF_TWIM_Type const * p_reg)
778 {
779 return (uint8_t)(p_reg->ADDRESS & TWIM_ADDRESS_ADDRESS_Msk);
780 }
781
nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,uint8_t const * p_buffer,size_t length)782 NRF_STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
783 uint8_t const * p_buffer,
784 size_t length)
785 {
786 #if NRF_TWIM_HAS_DMA_REG
787 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
788 p_reg->DMA.TX.MAXCNT = length;
789 #else
790 p_reg->TXD.PTR = (uint32_t)p_buffer;
791 p_reg->TXD.MAXCNT = length;
792 #endif
793 }
794
nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,uint8_t * p_buffer,size_t length)795 NRF_STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
796 uint8_t * p_buffer,
797 size_t length)
798 {
799 #if NRF_TWIM_HAS_DMA_REG
800 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
801 p_reg->DMA.RX.MAXCNT = length;
802 #else
803 p_reg->RXD.PTR = (uint32_t)p_buffer;
804 p_reg->RXD.MAXCNT = length;
805 #endif
806 }
807
nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,uint32_t mask)808 NRF_STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
809 uint32_t mask)
810 {
811 p_reg->SHORTS = mask;
812 }
813
nrf_twim_shorts_get(NRF_TWIM_Type const * p_reg)814 NRF_STATIC_INLINE uint32_t nrf_twim_shorts_get(NRF_TWIM_Type const * p_reg)
815 {
816 return p_reg->SHORTS;
817 }
818
nrf_twim_txd_amount_get(NRF_TWIM_Type const * p_reg)819 NRF_STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type const * p_reg)
820 {
821 #if NRF_TWIM_HAS_DMA_REG
822 return p_reg->DMA.TX.AMOUNT;
823 #else
824 return p_reg->TXD.AMOUNT;
825 #endif
826 }
827
nrf_twim_rxd_amount_get(NRF_TWIM_Type const * p_reg)828 NRF_STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type const * p_reg)
829 {
830 #if NRF_TWIM_HAS_DMA_REG
831 return p_reg->DMA.RX.AMOUNT;
832 #else
833 return p_reg->RXD.AMOUNT;
834 #endif
835 }
836
837 #if NRF_TWIM_HAS_ARRAY_LIST
nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg)838 NRF_STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg)
839 {
840 p_reg->TXD.LIST = TWIM_TXD_LIST_LIST_ArrayList << TWIM_TXD_LIST_LIST_Pos;
841 }
842
nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg)843 NRF_STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg)
844 {
845 p_reg->TXD.LIST = TWIM_TXD_LIST_LIST_Disabled << TWIM_TXD_LIST_LIST_Pos;
846 }
847
nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg)848 NRF_STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg)
849 {
850 p_reg->RXD.LIST = TWIM_RXD_LIST_LIST_ArrayList << TWIM_RXD_LIST_LIST_Pos;
851 }
852
nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg)853 NRF_STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg)
854 {
855 p_reg->RXD.LIST = TWIM_RXD_LIST_LIST_Disabled << TWIM_RXD_LIST_LIST_Pos;
856 }
857 #endif
858
859 #if NRF_TWIM_HAS_DMA_REG
nrf_twim_rx_pattern_match_enable_set(NRF_TWIM_Type * p_reg,uint8_t index,bool enable)860 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_enable_set(NRF_TWIM_Type * p_reg,
861 uint8_t index,
862 bool enable)
863 {
864 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
865 switch (index)
866 {
867 case 0:
868 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
869 ~TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) |
870 ((enable ?
871 TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled :
872 TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled)
873 << TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos));
874 break;
875 case 1:
876 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
877 ~TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) |
878 ((enable ?
879 TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled :
880 TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled)
881 << TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos));
882 break;
883 case 2:
884 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
885 ~TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) |
886 ((enable ?
887 TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled :
888 TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled)
889 << TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos));
890 break;
891 case 3:
892 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
893 ~TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) |
894 ((enable ?
895 TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled :
896 TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled)
897 << TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos));
898 break;
899 default:
900 NRFX_ASSERT(false);
901 break;
902 }
903 }
904
nrf_twim_rx_pattern_match_enable_check(NRF_TWIM_Type const * p_reg,uint8_t index)905 NRF_STATIC_INLINE bool nrf_twim_rx_pattern_match_enable_check(NRF_TWIM_Type const * p_reg,
906 uint8_t index)
907 {
908 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
909 switch (index)
910 {
911 case 0:
912 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk)
913 >> TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) ==
914 TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled;
915 case 1:
916 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk)
917 >> TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) ==
918 TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled;
919 case 2:
920 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk)
921 >> TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) ==
922 TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled;
923 case 3:
924 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk)
925 >> TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) ==
926 TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled;
927 default:
928 NRFX_ASSERT(false);
929 return 0;
930 }
931 }
932
nrf_twim_rx_pattern_match_one_shot_enable(NRF_TWIM_Type * p_reg,uint8_t index)933 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_one_shot_enable(NRF_TWIM_Type * p_reg,
934 uint8_t index)
935 {
936 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
937 switch (index)
938 {
939 case 0:
940 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk;
941 break;
942 case 1:
943 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk;
944 break;
945 case 2:
946 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk;
947 break;
948 case 3:
949 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk;
950 break;
951 default:
952 NRFX_ASSERT(false);
953 break;
954 }
955 }
956
nrf_twim_rx_pattern_match_one_shot_disable(NRF_TWIM_Type * p_reg,uint8_t index)957 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_one_shot_disable(NRF_TWIM_Type * p_reg,
958 uint8_t index)
959 {
960 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
961 switch (index)
962 {
963 case 0:
964 p_reg->DMA.RX.MATCH.CONFIG &= ~(TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk);
965 break;
966 case 1:
967 p_reg->DMA.RX.MATCH.CONFIG &= ~(TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk);
968 break;
969 case 2:
970 p_reg->DMA.RX.MATCH.CONFIG &= ~(TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk);
971 break;
972 case 3:
973 p_reg->DMA.RX.MATCH.CONFIG &= ~(TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk);
974 break;
975 default:
976 NRFX_ASSERT(false);
977 break;
978 }
979 }
980
nrf_twim_rx_pattern_match_one_shot_check(NRF_TWIM_Type const * p_reg,uint8_t index)981 NRF_STATIC_INLINE bool nrf_twim_rx_pattern_match_one_shot_check(NRF_TWIM_Type const * p_reg,
982 uint8_t index)
983 {
984 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
985 switch (index)
986 {
987 case 0:
988 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk)
989 >> TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) ==
990 TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot;
991 case 1:
992 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk)
993 >> TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) ==
994 TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot;
995 case 2:
996 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk)
997 >> TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) ==
998 TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot;
999 case 3:
1000 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk)
1001 >> TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) ==
1002 TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot;
1003 default:
1004 NRFX_ASSERT(false);
1005 return 0;
1006 }
1007 }
1008
nrf_twim_rx_pattern_match_candidate_set(NRF_TWIM_Type * p_reg,uint8_t index,uint32_t pattern)1009 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_candidate_set(NRF_TWIM_Type * p_reg,
1010 uint8_t index,
1011 uint32_t pattern)
1012 {
1013 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
1014 p_reg->DMA.RX.MATCH.CANDIDATE[index] = pattern;
1015 }
1016
nrf_twim_rx_pattern_match_candidate_get(NRF_TWIM_Type const * p_reg,uint8_t index)1017 NRF_STATIC_INLINE uint32_t nrf_twim_rx_pattern_match_candidate_get(NRF_TWIM_Type const * p_reg,
1018 uint8_t index)
1019 {
1020 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
1021 return p_reg->DMA.RX.MATCH.CANDIDATE[index];
1022 }
1023 #endif // NRF_TWIM_HAS_DMA_REG
1024
1025 #endif // NRF_DECLARE_ONLY
1026
1027 /** @} */
1028
1029 #ifdef __cplusplus
1030 }
1031 #endif
1032
1033 #endif // NRF_TWIM_H__
1034
