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Searched refs:TEMP_T1_T1_Pos (Results 1 – 8 of 8) sorted by relevance

/hal_nordic-3.5.0/nrfx/mdk/
Dnrf52805_bitfields.h7816 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ macro
7817 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
Dnrf52811_bitfields.h9529 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ macro
9530 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
Dnrf52810_bitfields.h8824 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ macro
8825 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
Dnrf5340_network_bitfields.h9851 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ macro
9852 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
Dnrf52820_bitfields.h8167 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ macro
8168 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
Dnrf52_bitfields.h12235 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ macro
12236 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
Dnrf52833_bitfields.h13081 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ macro
13082 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
Dnrf52840_bitfields.h13444 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ macro
13445 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */