1 /* 2 3 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF51_DEPRECATED_H 36 #define NRF51_DEPRECATED_H 37 38 /*lint ++flb "Enter library region */ 39 40 /* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 41 * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these 42 * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. 43 */ 44 45 /* NVMC */ 46 /* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */ 47 #define ERASEPROTECTEDPAGE ERASEPCR0 48 49 50 /* LPCOMP */ 51 /* The interrupt ISR was renamed. Adding old name to the macros. */ 52 #define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler 53 #define LPCOMP_COMP_IRQn LPCOMP_IRQn 54 /* Corrected typo in RESULT register. */ 55 #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below 56 57 58 /* MPU */ 59 /* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */ 60 #define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos 61 #define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk 62 #define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1 63 #define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0 64 65 66 /* POWER */ 67 /* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 68 #define POWER_RAMON_OFFRAM3_Pos (19UL) 69 #define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) 70 #define POWER_RAMON_OFFRAM3_RAM3Off (0UL) 71 #define POWER_RAMON_OFFRAM3_RAM3On (1UL) 72 /* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 73 #define POWER_RAMON_OFFRAM2_Pos (18UL) 74 #define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) 75 #define POWER_RAMON_OFFRAM2_RAM2Off (0UL) 76 #define POWER_RAMON_OFFRAM2_RAM2On (1UL) 77 /* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 78 #define POWER_RAMON_ONRAM3_Pos (3UL) 79 #define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) 80 #define POWER_RAMON_ONRAM3_RAM3Off (0UL) 81 #define POWER_RAMON_ONRAM3_RAM3On (1UL) 82 /* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 83 #define POWER_RAMON_ONRAM2_Pos (2UL) 84 #define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) 85 #define POWER_RAMON_ONRAM2_RAM2Off (0UL) 86 #define POWER_RAMON_ONRAM2_RAM2On (1UL) 87 88 89 /* RADIO */ 90 /* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */ 91 #define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm 92 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 93 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 94 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 95 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 96 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 97 /* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */ 98 #define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos 99 #define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk 100 #define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled 101 #define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled 102 /* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */ 103 #define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos 104 #define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk 105 #define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled 106 #define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled 107 108 109 /* FICR */ 110 /* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */ 111 #define SIZERAMBLOCK0 SIZERAMBLOCKS 112 #define SIZERAMBLOCK1 SIZERAMBLOCKS 113 #define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ 114 #define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ 115 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 116 #define DEVICEID0 DEVICEID[0] 117 #define DEVICEID1 DEVICEID[1] 118 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 119 #define ER0 ER[0] 120 #define ER1 ER[1] 121 #define ER2 ER[2] 122 #define ER3 ER[3] 123 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 124 #define IR0 IR[0] 125 #define IR1 IR[1] 126 #define IR2 IR[2] 127 #define IR3 IR[3] 128 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 129 #define DEVICEADDR0 DEVICEADDR[0] 130 #define DEVICEADDR1 DEVICEADDR[1] 131 132 133 /* PPI */ 134 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 135 #define TASKS_CHG0EN TASKS_CHG[0].EN 136 #define TASKS_CHG0DIS TASKS_CHG[0].DIS 137 #define TASKS_CHG1EN TASKS_CHG[1].EN 138 #define TASKS_CHG1DIS TASKS_CHG[1].DIS 139 #define TASKS_CHG2EN TASKS_CHG[2].EN 140 #define TASKS_CHG2DIS TASKS_CHG[2].DIS 141 #define TASKS_CHG3EN TASKS_CHG[3].EN 142 #define TASKS_CHG3DIS TASKS_CHG[3].DIS 143 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 144 #define CH0_EEP CH[0].EEP 145 #define CH0_TEP CH[0].TEP 146 #define CH1_EEP CH[1].EEP 147 #define CH1_TEP CH[1].TEP 148 #define CH2_EEP CH[2].EEP 149 #define CH2_TEP CH[2].TEP 150 #define CH3_EEP CH[3].EEP 151 #define CH3_TEP CH[3].TEP 152 #define CH4_EEP CH[4].EEP 153 #define CH4_TEP CH[4].TEP 154 #define CH5_EEP CH[5].EEP 155 #define CH5_TEP CH[5].TEP 156 #define CH6_EEP CH[6].EEP 157 #define CH6_TEP CH[6].TEP 158 #define CH7_EEP CH[7].EEP 159 #define CH7_TEP CH[7].TEP 160 #define CH8_EEP CH[8].EEP 161 #define CH8_TEP CH[8].TEP 162 #define CH9_EEP CH[9].EEP 163 #define CH9_TEP CH[9].TEP 164 #define CH10_EEP CH[10].EEP 165 #define CH10_TEP CH[10].TEP 166 #define CH11_EEP CH[11].EEP 167 #define CH11_TEP CH[11].TEP 168 #define CH12_EEP CH[12].EEP 169 #define CH12_TEP CH[12].TEP 170 #define CH13_EEP CH[13].EEP 171 #define CH13_TEP CH[13].TEP 172 #define CH14_EEP CH[14].EEP 173 #define CH14_TEP CH[14].TEP 174 #define CH15_EEP CH[15].EEP 175 #define CH15_TEP CH[15].TEP 176 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 177 #define CHG0 CHG[0] 178 #define CHG1 CHG[1] 179 #define CHG2 CHG[2] 180 #define CHG3 CHG[3] 181 /* All bitfield macros for the CHGx registers therefore changed name. */ 182 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 183 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 184 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 185 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 186 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 187 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 188 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 189 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 190 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 191 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 192 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 193 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 194 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 195 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 196 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 197 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 198 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 199 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 200 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 201 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 202 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 203 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 204 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 205 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 206 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 207 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 208 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 209 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 210 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 211 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 212 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 213 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 214 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 215 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 216 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 217 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 218 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 219 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 220 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 221 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 222 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 223 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 224 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 225 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 226 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 227 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 228 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 229 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 230 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 231 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 232 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 233 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 234 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 235 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 236 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 237 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 238 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 239 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 240 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 241 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 242 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 243 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 244 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 245 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 246 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 247 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 248 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 249 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 250 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 251 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 252 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 253 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 254 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 255 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 256 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 257 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 258 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 259 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 260 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 261 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 262 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 263 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 264 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 265 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 266 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 267 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 268 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 269 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 270 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 271 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 272 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 273 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 274 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 275 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 276 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 277 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 278 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 279 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 280 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 281 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 282 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 283 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 284 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 285 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 286 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 287 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 288 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 289 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 290 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 291 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 292 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 293 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 294 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 295 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 296 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 297 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 298 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 299 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 300 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 301 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 302 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 303 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 304 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 305 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 306 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 307 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 308 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 309 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 310 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 311 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 312 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 313 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 314 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 315 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 316 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 317 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 318 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 319 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 320 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 321 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 322 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 323 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 324 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 325 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 326 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 327 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 328 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 329 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 330 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 331 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 332 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 333 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 334 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 335 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 336 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 337 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 338 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 339 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 340 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 341 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 342 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 343 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 344 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 345 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 346 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 347 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 348 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 349 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 350 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 351 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 352 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 353 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 354 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 355 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 356 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 357 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 358 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 359 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 360 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 361 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 362 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 363 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 364 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 365 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 366 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 367 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 368 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 369 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 370 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 371 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 372 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 373 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 374 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 375 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 376 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 377 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 378 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 379 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 380 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 381 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 382 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 383 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 384 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 385 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 386 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 387 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 388 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 389 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 390 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 391 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 392 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 393 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 394 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 395 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 396 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 397 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 398 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 399 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 400 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 401 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 402 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 403 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 404 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 405 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 406 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 407 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 408 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 409 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 410 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 411 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 412 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 413 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 414 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 415 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 416 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 417 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 418 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 419 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 420 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 421 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 422 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 423 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 424 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 425 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 426 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 427 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 428 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 429 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 430 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 431 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 432 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 433 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 434 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 435 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 436 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 437 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 438 439 /* SPIS */ 440 /* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */ 441 #define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE 442 443 444 445 /*lint --flb "Leave library region" */ 446 447 #endif /* NRF51_DEPRECATED_H */ 448 449
