1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_UARTE_H__
35 #define NRF_UARTE_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF
44
45 /**
46 * @defgroup nrf_uarte_hal UARTE HAL
47 * @{
48 * @ingroup nrf_uarte
49 * @brief Hardware access layer for managing the UARTE peripheral.
50 */
51
52 /**
53 * @brief Macro getting pointer to the structure of registers of the UARTE peripheral.
54 *
55 * @param[in] idx UARTE instance index.
56 *
57 * @return Pointer to the structure of registers of the UARTE peripheral.
58 */
59 #define NRF_UARTE_INST_GET(idx) NRFX_CONCAT_2(NRF_UARTE, idx)
60
61 #if defined(UARTE_DMA_RX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
62 /** @brief Symbol indicating whether dedicated DMA register is present. */
63 #define NRF_UARTE_HAS_DMA_REG 1
64 #else
65 #define NRF_UARTE_HAS_DMA_REG 0
66 #endif
67
68 #if (defined(UARTE_TASKS_DMA_RX_START_START_Msk) && defined(UARTE_EVENTS_DMA_RX_END_END_Msk)) || \
69 defined(__NRFX_DOXYGEN__)
70 /** @brief Symbol indicating whether UARTE DMA tasks and events are present. */
71 #define NRF_UARTE_HAS_DMA_TASKS_EVENTS 1
72 #else
73 #define NRF_UARTE_HAS_DMA_TASKS_EVENTS 0
74 #endif
75
76 /** @brief UARTE tasks. */
77 typedef enum
78 {
79 #if NRF_UARTE_HAS_DMA_TASKS_EVENTS
80 NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_DMA.RX.START), ///< Start UART receiver.
81 NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_DMA.RX.STOP), ///< Stop UART receiver.
82 NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_DMA.TX.START), ///< Start UART transmitter.
83 NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_DMA.TX.STOP), ///< Stop UART transmitter.
84 #else
85 NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver.
86 NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
87 NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter.
88 NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
89 #endif
90 NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
91 } nrf_uarte_task_t;
92
93 /** @brief UARTE events. */
94 typedef enum
95 {
96 NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
97 NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
98 NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
99 NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
100 NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
101 NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
102 NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED), ///< Transmitted stopped.
103 #if NRF_UARTE_HAS_DMA_TASKS_EVENTS
104 NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_DMA.RX.END), ///< Receive buffer is filled up.
105 NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_DMA.TX.END), ///< Last TX byte transmitted.
106 NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_DMA.RX.READY), ///< Receiver has started.
107 NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_DMA.TX.READY), ///< Transmitter has started.
108 #else
109 NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
110 NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
111 NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started.
112 NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started.
113 #endif
114 } nrf_uarte_event_t;
115
116 /** @brief Types of UARTE shortcuts. */
117 typedef enum
118 {
119 NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task.
120 NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk ///< Shortcut between ENDRX event and STOPRX task.
121 } nrf_uarte_short_t;
122
123
124 /** @brief UARTE interrupts. */
125 typedef enum
126 {
127 NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
128 NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
129 NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event.
130 NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event.
131 NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
132 NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
133 NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk, ///< Interrupt on TXSTOPPED event.
134 #if NRF_UARTE_HAS_DMA_TASKS_EVENTS
135 NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_DMARXEND_Msk, ///< Interrupt on ENDRX event.
136 NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_DMATXEND_Msk, ///< Interrupt on ENDTX event.
137 NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_DMARXREADY_Msk, ///< Interrupt on RXSTARTED event.
138 NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_DMATXREADY_Msk, ///< Interrupt on TXSTARTED event.
139 #else
140 NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
141 NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
142 NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
143 NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
144 #endif
145 } nrf_uarte_int_mask_t;
146
147 /** @brief Baudrates supported by UARTE. */
148 typedef enum
149 {
150 NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
151 NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
152 NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
153 NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
154 NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
155 NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
156 NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
157 NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud.
158 NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
159 NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud.
160 NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
161 NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
162 NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
163 NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
164 NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
165 NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
166 NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
167 NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud.
168 } nrf_uarte_baudrate_t;
169
170 /** @brief Types of UARTE error masks. */
171 typedef enum
172 {
173 NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error.
174 NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error.
175 NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error.
176 NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error.
177 } nrf_uarte_error_mask_t;
178
179 /** @brief Types of UARTE parity modes. */
180 typedef enum
181 {
182 NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
183 NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included.
184 } nrf_uarte_parity_t;
185
186 /** @brief Types of UARTE flow control modes. */
187 typedef enum
188 {
189 NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< Hardware flow control disabled.
190 NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< Hardware flow control enabled.
191 } nrf_uarte_hwfc_t;
192
193 #if defined(UARTE_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__)
194 /** @brief Types of UARTE stop bit modes. */
195 typedef enum
196 {
197 NRF_UARTE_STOP_ONE = UARTE_CONFIG_STOP_One << UARTE_CONFIG_STOP_Pos, ///< One stop bit.
198 NRF_UARTE_STOP_TWO = UARTE_CONFIG_STOP_Two << UARTE_CONFIG_STOP_Pos ///< Two stop bits.
199 } nrf_uarte_stop_t;
200 #endif
201
202 #if defined(UARTE_CONFIG_PARITYTYPE_Msk) || defined(__NRFX_DOXYGEN__)
203 /** @brief Types of UARTE parity types. */
204 typedef enum
205 {
206 NRF_UARTE_PARITYTYPE_EVEN = UARTE_CONFIG_PARITYTYPE_Even << UARTE_CONFIG_PARITYTYPE_Pos, ///< Parity even.
207 NRF_UARTE_PARITYTYPE_ODD = UARTE_CONFIG_PARITYTYPE_Odd << UARTE_CONFIG_PARITYTYPE_Pos, ///< Parity odd.
208 } nrf_uarte_paritytype_t;
209 #endif
210
211 /** @brief Structure for UARTE transmission configuration. */
212 typedef struct
213 {
214 nrf_uarte_hwfc_t hwfc; ///< Flow control configuration.
215 nrf_uarte_parity_t parity; ///< Parity configuration.
216 #if defined(UARTE_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__)
217 nrf_uarte_stop_t stop; ///< Stop bits.
218 #endif
219 #if defined(UARTE_CONFIG_PARITYTYPE_Msk) || defined(__NRFX_DOXYGEN__)
220 nrf_uarte_paritytype_t paritytype; ///< Parity type.
221 #endif
222 } nrf_uarte_config_t;
223
224 /**
225 * @brief Function for clearing a specific UARTE event.
226 *
227 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
228 * @param[in] event Event to clear.
229 */
230 NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
231
232 /**
233 * @brief Function for retrieving the state of the UARTE event.
234 *
235 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
236 * @param[in] event Event to be checked.
237 *
238 * @retval true The event has been generated.
239 * @retval false The event has not been generated.
240 */
241 NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,
242 nrf_uarte_event_t event);
243
244 /**
245 * @brief Function for returning the address of the specified UARTE event register.
246 *
247 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
248 * @param[in] event The specified event.
249 *
250 * @return Address of specified event register.
251 */
252 NRF_STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
253 nrf_uarte_event_t event);
254
255 /**
256 * @brief Function for enabling UARTE shortcuts.
257 *
258 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
259 * @param[in] mask Shortcuts to be enabled.
260 */
261 NRF_STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
262
263 /**
264 * @brief Function for disabling UARTE shortcuts.
265 *
266 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
267 * @param[in] mask Shortcuts to be disabled.
268 */
269 NRF_STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
270
271 /**
272 * @brief Function for enabling UARTE interrupts.
273 *
274 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
275 * @param[in] mask Mask of interrupts to be enabled.
276 */
277 NRF_STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
278
279 /**
280 * @brief Function for checking if the specified interrupts are enabled.
281 *
282 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
283 * @param[in] mask Mask of interrupts to be checked.
284 *
285 * @return Mask of enabled interrupts.
286 */
287 NRF_STATIC_INLINE uint32_t nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg, uint32_t mask);
288
289 /**
290 * @brief Function for disabling the specified interrupts.
291 *
292 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
293 * @param[in] mask Mask of interrupts to be disabled.
294 */
295 NRF_STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
296
297 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
298 /**
299 * @brief Function for setting the subscribe configuration for a given
300 * UARTE task.
301 *
302 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
303 * @param[in] task Task for which to set the configuration.
304 * @param[in] channel Channel through which to subscribe events.
305 */
306 NRF_STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
307 nrf_uarte_task_t task,
308 uint8_t channel);
309
310 /**
311 * @brief Function for clearing the subscribe configuration for a given
312 * UARTE task.
313 *
314 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
315 * @param[in] task Task for which to clear the configuration.
316 */
317 NRF_STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
318 nrf_uarte_task_t task);
319
320 /**
321 * @brief Function for setting the publish configuration for a given
322 * UARTE event.
323 *
324 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
325 * @param[in] event Event for which to set the configuration.
326 * @param[in] channel Channel through which to publish the event.
327 */
328 NRF_STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
329 nrf_uarte_event_t event,
330 uint8_t channel);
331
332 /**
333 * @brief Function for clearing the publish configuration for a given
334 * UARTE event.
335 *
336 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
337 * @param[in] event Event for which to clear the configuration.
338 */
339 NRF_STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
340 nrf_uarte_event_t event);
341 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
342
343 /**
344 * @brief Function for getting error source mask. Function is clearing error source flags after reading.
345 *
346 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
347 *
348 * @return Mask with error source flags.
349 */
350 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
351
352 /**
353 * @brief Function for enabling UARTE.
354 *
355 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
356 */
357 NRF_STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
358
359 /**
360 * @brief Function for disabling UARTE.
361 *
362 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
363 */
364 NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
365
366 /**
367 * @brief Function for configuring TX/RX pins.
368 *
369 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
370 * @param[in] pseltxd TXD pin number.
371 * @param[in] pselrxd RXD pin number.
372 */
373 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
374 uint32_t pseltxd,
375 uint32_t pselrxd);
376
377 /**
378 * @brief Function for disconnecting TX/RX pins.
379 *
380 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
381 */
382 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
383
384 /**
385 * @brief Function for getting TX pin selection.
386 *
387 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
388 *
389 * @return TX pin selection.
390 */
391 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg);
392
393 /**
394 * @brief Function for getting RX pin selection.
395 *
396 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
397 *
398 * @return RX pin selection.
399 */
400 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg);
401
402 /**
403 * @brief Function for getting RTS pin selection.
404 *
405 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
406 *
407 * @return RTS pin selection.
408 */
409 NRF_STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg);
410
411 /**
412 * @brief Function for getting CTS pin selection.
413 *
414 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
415 *
416 * @return CTS pin selection.
417 */
418 NRF_STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg);
419
420 /**
421 * @brief Function for configuring flow control pins.
422 *
423 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
424 * @param[in] pselrts RTS pin number.
425 * @param[in] pselcts CTS pin number.
426 */
427 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
428 uint32_t pselrts,
429 uint32_t pselcts);
430
431 /**
432 * @brief Function for disconnecting flow control pins.
433 *
434 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
435 */
436 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
437
438 /**
439 * @brief Function for starting an UARTE task.
440 *
441 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
442 * @param[in] task Task.
443 */
444 NRF_STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
445
446 /**
447 * @brief Function for returning the address of the specified task register.
448 *
449 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
450 * @param[in] task Task.
451 *
452 * @return Task address.
453 */
454 NRF_STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
455 nrf_uarte_task_t task);
456
457 /**
458 * @brief Function for configuring UARTE.
459 *
460 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
461 * @param[in] p_cfg Pointer to UARTE settings structure.
462 */
463 NRF_STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
464 nrf_uarte_config_t const * p_cfg);
465
466 /**
467 * @brief Function for setting UARTE baud rate.
468 *
469 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
470 * @param[in] baudrate Baud rate.
471 */
472 NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg,
473 nrf_uarte_baudrate_t baudrate);
474
475 /**
476 * @brief Function for setting the transmit buffer.
477 *
478 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
479 * @param[in] p_buffer Pointer to the buffer with data to send.
480 * @param[in] length Maximum number of data bytes to transmit.
481 */
482 NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
483 uint8_t const * p_buffer,
484 size_t length);
485
486 /**
487 * @brief Function for getting number of bytes transmitted in the last transaction.
488 *
489 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
490 *
491 * @retval Amount of bytes transmitted.
492 */
493 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg);
494
495 /**
496 * @brief Function for setting the receive buffer.
497 *
498 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
499 * @param[in] p_buffer Pointer to the buffer for received data.
500 * @param[in] length Maximum number of data bytes to receive.
501 */
502 NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
503 uint8_t * p_buffer,
504 size_t length);
505
506 /**
507 * @brief Function for getting number of bytes received in the last transaction.
508 *
509 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
510 *
511 * @retval Amount of bytes received.
512 */
513 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg);
514
515 #ifndef NRF_DECLARE_ONLY
nrf_uarte_event_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)516 NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
517 {
518 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
519 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
520 }
521
nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)522 NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,
523 nrf_uarte_event_t event)
524 {
525 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
526 }
527
nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)528 NRF_STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
529 nrf_uarte_event_t event)
530 {
531 return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
532 }
533
nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg,uint32_t mask)534 NRF_STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
535 {
536 p_reg->SHORTS |= mask;
537 }
538
nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg,uint32_t mask)539 NRF_STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
540 {
541 p_reg->SHORTS &= ~(mask);
542 }
543
nrf_uarte_int_enable(NRF_UARTE_Type * p_reg,uint32_t mask)544 NRF_STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
545 {
546 p_reg->INTENSET = mask;
547 }
548
nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg,uint32_t mask)549 NRF_STATIC_INLINE uint32_t nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg, uint32_t mask)
550 {
551 return p_reg->INTENSET & mask;
552 }
553
nrf_uarte_int_disable(NRF_UARTE_Type * p_reg,uint32_t mask)554 NRF_STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
555 {
556 p_reg->INTENCLR = mask;
557 }
558
559 #if defined(DPPI_PRESENT)
nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task,uint8_t channel)560 NRF_STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
561 nrf_uarte_task_t task,
562 uint8_t channel)
563 {
564 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
565 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
566 }
567
nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)568 NRF_STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
569 nrf_uarte_task_t task)
570 {
571 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
572 }
573
nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event,uint8_t channel)574 NRF_STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
575 nrf_uarte_event_t event,
576 uint8_t channel)
577 {
578 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
579 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
580 }
581
nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)582 NRF_STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
583 nrf_uarte_event_t event)
584 {
585 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
586 }
587 #endif // defined(DPPI_PRESENT)
588
nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)589 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
590 {
591 uint32_t errsrc_mask = p_reg->ERRORSRC;
592 p_reg->ERRORSRC = errsrc_mask;
593 return errsrc_mask;
594 }
595
nrf_uarte_enable(NRF_UARTE_Type * p_reg)596 NRF_STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg)
597 {
598 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
599 }
600
nrf_uarte_disable(NRF_UARTE_Type * p_reg)601 NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
602 {
603 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
604 }
605
nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,uint32_t pseltxd,uint32_t pselrxd)606 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
607 uint32_t pseltxd,
608 uint32_t pselrxd)
609 {
610 p_reg->PSEL.TXD = pseltxd;
611 p_reg->PSEL.RXD = pselrxd;
612 }
613
nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)614 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
615 {
616 nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
617 }
618
nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)619 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)
620 {
621 return p_reg->PSEL.TXD;
622 }
623
nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)624 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)
625 {
626 return p_reg->PSEL.RXD;
627 }
628
nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)629 NRF_STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)
630 {
631 return p_reg->PSEL.RTS;
632 }
633
nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)634 NRF_STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)
635 {
636 return p_reg->PSEL.CTS;
637 }
638
nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,uint32_t pselrts,uint32_t pselcts)639 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
640 uint32_t pselrts,
641 uint32_t pselcts)
642 {
643 p_reg->PSEL.RTS = pselrts;
644 p_reg->PSEL.CTS = pselcts;
645 }
646
nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)647 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
648 {
649 nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
650 }
651
nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)652 NRF_STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
653 {
654 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
655 }
656
nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_task_t task)657 NRF_STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
658 nrf_uarte_task_t task)
659 {
660 return (uint32_t)p_reg + (uint32_t)task;
661 }
662
nrf_uarte_configure(NRF_UARTE_Type * p_reg,nrf_uarte_config_t const * p_cfg)663 NRF_STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
664 nrf_uarte_config_t const * p_cfg)
665 {
666 p_reg->CONFIG = (uint32_t)p_cfg->parity
667 #if defined(UARTE_CONFIG_STOP_Msk)
668 | (uint32_t)p_cfg->stop
669 #endif
670 #if defined(UARTE_CONFIG_PARITYTYPE_Msk)
671 | (uint32_t)p_cfg->paritytype
672 #endif
673 | (uint32_t)p_cfg->hwfc;
674 }
675
nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg,nrf_uarte_baudrate_t baudrate)676 NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
677 {
678 p_reg->BAUDRATE = baudrate;
679 }
680
nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t const * p_buffer,size_t length)681 NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
682 uint8_t const * p_buffer,
683 size_t length)
684 {
685 #if NRF_UARTE_HAS_DMA_REG
686 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
687 p_reg->DMA.TX.MAXCNT = length;
688 #else
689 p_reg->TXD.PTR = (uint32_t)p_buffer;
690 p_reg->TXD.MAXCNT = length;
691 #endif
692 }
693
nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)694 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)
695 {
696 #if NRF_UARTE_HAS_DMA_REG
697 return p_reg->DMA.TX.AMOUNT;
698 #else
699 return p_reg->TXD.AMOUNT;
700 #endif
701 }
702
nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t * p_buffer,size_t length)703 NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
704 uint8_t * p_buffer,
705 size_t length)
706 {
707 #if NRF_UARTE_HAS_DMA_REG
708 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
709 p_reg->DMA.RX.MAXCNT = length;
710 #else
711 p_reg->RXD.PTR = (uint32_t)p_buffer;
712 p_reg->RXD.MAXCNT = length;
713 #endif
714 }
715
nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)716 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)
717 {
718 #if NRF_UARTE_HAS_DMA_REG
719 return p_reg->DMA.RX.AMOUNT;
720 #else
721 return p_reg->RXD.AMOUNT;
722 #endif
723 }
724 #endif // NRF_DECLARE_ONLY
725
726 /** @} */
727
728 #ifdef __cplusplus
729 }
730 #endif
731
732 #endif // NRF_UARTE_H__
733
