1 /*
2 
3 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF5340_APPLICATION_BITS_H
36 #define __NRF5340_APPLICATION_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: CACHEDATA */
41 /* Description: CACHEDATA */
42 
43 /* Register: CACHEDATA_SET_WAY_DATA0 */
44 /* Description: Description cluster: Cache data bits [31:0] of SET[n], WAY[o]. */
45 
46 /* Bits 31..0 : Data */
47 #define CACHEDATA_SET_WAY_DATA0_Data_Pos (0UL) /*!< Position of Data field. */
48 #define CACHEDATA_SET_WAY_DATA0_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA0_Data_Pos) /*!< Bit mask of Data field. */
49 
50 /* Register: CACHEDATA_SET_WAY_DATA1 */
51 /* Description: Description cluster: Cache data bits [63:32] of SET[n], WAY[o]. */
52 
53 /* Bits 31..0 : Data */
54 #define CACHEDATA_SET_WAY_DATA1_Data_Pos (0UL) /*!< Position of Data field. */
55 #define CACHEDATA_SET_WAY_DATA1_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA1_Data_Pos) /*!< Bit mask of Data field. */
56 
57 /* Register: CACHEDATA_SET_WAY_DATA2 */
58 /* Description: Description cluster: Cache data bits [95:64] of SET[n], WAY[o]. */
59 
60 /* Bits 31..0 : Data */
61 #define CACHEDATA_SET_WAY_DATA2_Data_Pos (0UL) /*!< Position of Data field. */
62 #define CACHEDATA_SET_WAY_DATA2_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA2_Data_Pos) /*!< Bit mask of Data field. */
63 
64 /* Register: CACHEDATA_SET_WAY_DATA3 */
65 /* Description: Description cluster: Cache data bits [127:96] of SET[n], WAY[o]. */
66 
67 /* Bits 31..0 : Data */
68 #define CACHEDATA_SET_WAY_DATA3_Data_Pos (0UL) /*!< Position of Data field. */
69 #define CACHEDATA_SET_WAY_DATA3_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DATA3_Data_Pos) /*!< Bit mask of Data field. */
70 
71 
72 /* Peripheral: CACHEINFO */
73 /* Description: CACHEINFO */
74 
75 /* Register: CACHEINFO_SET_WAY */
76 /* Description: Description collection: Cache information for SET[n], WAY[o]. */
77 
78 /* Bit 31 : Most recently used way. */
79 #define CACHEINFO_SET_WAY_MRU_Pos (31UL) /*!< Position of MRU field. */
80 #define CACHEINFO_SET_WAY_MRU_Msk (0x1UL << CACHEINFO_SET_WAY_MRU_Pos) /*!< Bit mask of MRU field. */
81 #define CACHEINFO_SET_WAY_MRU_Way0 (0UL) /*!< Way0 was most recently used */
82 #define CACHEINFO_SET_WAY_MRU_Way1 (1UL) /*!< Way1 was most recently used */
83 
84 /* Bit 30 : Valid bit */
85 #define CACHEINFO_SET_WAY_V_Pos (30UL) /*!< Position of V field. */
86 #define CACHEINFO_SET_WAY_V_Msk (0x1UL << CACHEINFO_SET_WAY_V_Pos) /*!< Bit mask of V field. */
87 #define CACHEINFO_SET_WAY_V_Invalid (0UL) /*!< Invalid cache line */
88 #define CACHEINFO_SET_WAY_V_Valid (1UL) /*!< Valid cache line */
89 
90 /* Bits 16..0 : Cache tag. */
91 #define CACHEINFO_SET_WAY_TAG_Pos (0UL) /*!< Position of TAG field. */
92 #define CACHEINFO_SET_WAY_TAG_Msk (0x1FFFFUL << CACHEINFO_SET_WAY_TAG_Pos) /*!< Bit mask of TAG field. */
93 
94 
95 /* Peripheral: CACHE */
96 /* Description: Cache */
97 
98 /* Register: CACHE_PROFILING_IHIT */
99 /* Description: Description cluster: Instruction fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. */
100 
101 /* Bits 31..0 : Number of instruction cache hits */
102 #define CACHE_PROFILING_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
103 #define CACHE_PROFILING_IHIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
104 
105 /* Register: CACHE_PROFILING_IMISS */
106 /* Description: Description cluster: Instruction fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. */
107 
108 /* Bits 31..0 : Number of instruction cache misses */
109 #define CACHE_PROFILING_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
110 #define CACHE_PROFILING_IMISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
111 
112 /* Register: CACHE_PROFILING_DHIT */
113 /* Description: Description cluster: Data fetch cache hit counter for cache region n, where n=0 means Flash and n=1 means XIP. */
114 
115 /* Bits 31..0 : Number of data cache hits */
116 #define CACHE_PROFILING_DHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
117 #define CACHE_PROFILING_DHIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_DHIT_HITS_Pos) /*!< Bit mask of HITS field. */
118 
119 /* Register: CACHE_PROFILING_DMISS */
120 /* Description: Description cluster: Data fetch cache miss counter for cache region n, where n=0 means Flash and n=1 means XIP. */
121 
122 /* Bits 31..0 : Number of data cache misses */
123 #define CACHE_PROFILING_DMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
124 #define CACHE_PROFILING_DMISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_DMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
125 
126 /* Register: CACHE_ENABLE */
127 /* Description: Enable cache. */
128 
129 /* Bit 0 : Enable cache */
130 #define CACHE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
131 #define CACHE_ENABLE_ENABLE_Msk (0x1UL << CACHE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
132 #define CACHE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable cache */
133 #define CACHE_ENABLE_ENABLE_Enabled (1UL) /*!< Enable cache */
134 
135 /* Register: CACHE_INVALIDATE */
136 /* Description: Invalidate the cache. */
137 
138 /* Bit 0 : Invalidate the cache */
139 #define CACHE_INVALIDATE_INVALIDATE_Pos (0UL) /*!< Position of INVALIDATE field. */
140 #define CACHE_INVALIDATE_INVALIDATE_Msk (0x1UL << CACHE_INVALIDATE_INVALIDATE_Pos) /*!< Bit mask of INVALIDATE field. */
141 #define CACHE_INVALIDATE_INVALIDATE_Invalidate (1UL) /*!< Invalidate the cache */
142 
143 /* Register: CACHE_ERASE */
144 /* Description: Erase the cache. */
145 
146 /* Bit 0 : Erase the cache */
147 #define CACHE_ERASE_ERASE_Pos (0UL) /*!< Position of ERASE field. */
148 #define CACHE_ERASE_ERASE_Msk (0x1UL << CACHE_ERASE_ERASE_Pos) /*!< Bit mask of ERASE field. */
149 #define CACHE_ERASE_ERASE_Erase (1UL) /*!< Erase cache */
150 
151 /* Register: CACHE_PROFILINGENABLE */
152 /* Description: Enable the profiling counters. */
153 
154 /* Bit 0 : Enable the profiling counters */
155 #define CACHE_PROFILINGENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
156 #define CACHE_PROFILINGENABLE_ENABLE_Msk (0x1UL << CACHE_PROFILINGENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
157 #define CACHE_PROFILINGENABLE_ENABLE_Disable (0UL) /*!< Disable profiling */
158 #define CACHE_PROFILINGENABLE_ENABLE_Enable (1UL) /*!< Enable profiling */
159 
160 /* Register: CACHE_PROFILINGCLEAR */
161 /* Description: Clear the profiling counters. */
162 
163 /* Bit 0 : Clearing the profiling counters */
164 #define CACHE_PROFILINGCLEAR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */
165 #define CACHE_PROFILINGCLEAR_CLEAR_Msk (0x1UL << CACHE_PROFILINGCLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */
166 #define CACHE_PROFILINGCLEAR_CLEAR_Clear (1UL) /*!< Clear the profiling counters */
167 
168 /* Register: CACHE_MODE */
169 /* Description: Cache mode. Switching from Cache to Ram mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. */
170 
171 /* Bit 0 : Cache mode */
172 #define CACHE_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
173 #define CACHE_MODE_MODE_Msk (0x1UL << CACHE_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
174 #define CACHE_MODE_MODE_Cache (0UL) /*!< Cache mode */
175 #define CACHE_MODE_MODE_Ram (1UL) /*!< RAM mode */
176 
177 /* Register: CACHE_DEBUGLOCK */
178 /* Description: Lock debug mode. */
179 
180 /* Bit 0 : Lock debug mode */
181 #define CACHE_DEBUGLOCK_DEBUGLOCK_Pos (0UL) /*!< Position of DEBUGLOCK field. */
182 #define CACHE_DEBUGLOCK_DEBUGLOCK_Msk (0x1UL << CACHE_DEBUGLOCK_DEBUGLOCK_Pos) /*!< Bit mask of DEBUGLOCK field. */
183 #define CACHE_DEBUGLOCK_DEBUGLOCK_Unlocked (0UL) /*!< Debug mode unlocked */
184 #define CACHE_DEBUGLOCK_DEBUGLOCK_Locked (1UL) /*!< Debug mode locked */
185 
186 /* Register: CACHE_ERASESTATUS */
187 /* Description: Cache erase status. */
188 
189 /* Bit 0 : Cache erase status */
190 #define CACHE_ERASESTATUS_ERASESTATUS_Pos (0UL) /*!< Position of ERASESTATUS field. */
191 #define CACHE_ERASESTATUS_ERASESTATUS_Msk (0x1UL << CACHE_ERASESTATUS_ERASESTATUS_Pos) /*!< Bit mask of ERASESTATUS field. */
192 #define CACHE_ERASESTATUS_ERASESTATUS_Idle (0UL) /*!< Erase is not complete or hasn't started */
193 #define CACHE_ERASESTATUS_ERASESTATUS_Finished (1UL) /*!< Cache erase is finished */
194 
195 /* Register: CACHE_WRITELOCK */
196 /* Description: Lock cache updates. Prevents updating of cache content on cache misses, but will continue to lookup instruction/data fetches in content already present in the cache. Ignored in RAM mode. */
197 
198 /* Bit 0 : Lock cache updates */
199 #define CACHE_WRITELOCK_WRITELOCK_Pos (0UL) /*!< Position of WRITELOCK field. */
200 #define CACHE_WRITELOCK_WRITELOCK_Msk (0x1UL << CACHE_WRITELOCK_WRITELOCK_Pos) /*!< Bit mask of WRITELOCK field. */
201 #define CACHE_WRITELOCK_WRITELOCK_Unlocked (0UL) /*!< Cache updates unlocked */
202 #define CACHE_WRITELOCK_WRITELOCK_Locked (1UL) /*!< Cache updates locked */
203 
204 
205 /* Peripheral: CLOCK */
206 /* Description: Clock management 0 */
207 
208 /* Register: CLOCK_TASKS_HFCLKSTART */
209 /* Description: Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */
210 
211 /* Bit 0 : Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */
212 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
213 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
214 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
215 
216 /* Register: CLOCK_TASKS_HFCLKSTOP */
217 /* Description: Stop HFCLK128M/HFCLK64M source */
218 
219 /* Bit 0 : Stop HFCLK128M/HFCLK64M source */
220 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
221 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
222 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
223 
224 /* Register: CLOCK_TASKS_LFCLKSTART */
225 /* Description: Start LFCLK source as selected in LFCLKSRC */
226 
227 /* Bit 0 : Start LFCLK source as selected in LFCLKSRC */
228 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
229 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
230 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
231 
232 /* Register: CLOCK_TASKS_LFCLKSTOP */
233 /* Description: Stop LFCLK source */
234 
235 /* Bit 0 : Stop LFCLK source */
236 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
237 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
238 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
239 
240 /* Register: CLOCK_TASKS_CAL */
241 /* Description: Start calibration of LFRC oscillator */
242 
243 /* Bit 0 : Start calibration of LFRC oscillator */
244 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
245 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
246 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
247 
248 /* Register: CLOCK_TASKS_HFCLKAUDIOSTART */
249 /* Description: Start HFCLKAUDIO source */
250 
251 /* Bit 0 : Start HFCLKAUDIO source */
252 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTART field. */
253 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTART field. */
254 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Trigger (1UL) /*!< Trigger task */
255 
256 /* Register: CLOCK_TASKS_HFCLKAUDIOSTOP */
257 /* Description: Stop HFCLKAUDIO source */
258 
259 /* Bit 0 : Stop HFCLKAUDIO source */
260 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTOP field. */
261 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTOP field. */
262 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Trigger (1UL) /*!< Trigger task */
263 
264 /* Register: CLOCK_TASKS_HFCLK192MSTART */
265 /* Description: Start HFCLK192M source as selected in HFCLK192MSRC */
266 
267 /* Bit 0 : Start HFCLK192M source as selected in HFCLK192MSRC */
268 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTART field. */
269 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos) /*!< Bit mask of TASKS_HFCLK192MSTART field. */
270 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Trigger (1UL) /*!< Trigger task */
271 
272 /* Register: CLOCK_TASKS_HFCLK192MSTOP */
273 /* Description: Stop HFCLK192M source */
274 
275 /* Bit 0 : Stop HFCLK192M source */
276 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTOP field. */
277 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos) /*!< Bit mask of TASKS_HFCLK192MSTOP field. */
278 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Trigger (1UL) /*!< Trigger task */
279 
280 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */
281 /* Description: Subscribe configuration for task HFCLKSTART */
282 
283 /* Bit 31 :   */
284 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
285 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
286 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
287 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
288 
289 /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */
290 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
291 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
292 
293 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */
294 /* Description: Subscribe configuration for task HFCLKSTOP */
295 
296 /* Bit 31 :   */
297 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
298 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
299 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
300 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
301 
302 /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */
303 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
304 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
305 
306 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */
307 /* Description: Subscribe configuration for task LFCLKSTART */
308 
309 /* Bit 31 :   */
310 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
311 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
312 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
313 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
314 
315 /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */
316 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
317 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
318 
319 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */
320 /* Description: Subscribe configuration for task LFCLKSTOP */
321 
322 /* Bit 31 :   */
323 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
324 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
325 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
326 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
327 
328 /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */
329 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
330 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
331 
332 /* Register: CLOCK_SUBSCRIBE_CAL */
333 /* Description: Subscribe configuration for task CAL */
334 
335 /* Bit 31 :   */
336 #define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL) /*!< Position of EN field. */
337 #define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos) /*!< Bit mask of EN field. */
338 #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0UL) /*!< Disable subscription */
339 #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (1UL) /*!< Enable subscription */
340 
341 /* Bits 7..0 : DPPI channel that task CAL will subscribe to */
342 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
343 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
344 
345 /* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTART */
346 /* Description: Subscribe configuration for task HFCLKAUDIOSTART */
347 
348 /* Bit 31 :   */
349 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos (31UL) /*!< Position of EN field. */
350 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos) /*!< Bit mask of EN field. */
351 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Disabled (0UL) /*!< Disable subscription */
352 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Enabled (1UL) /*!< Enable subscription */
353 
354 /* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTART will subscribe to */
355 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
356 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
357 
358 /* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP */
359 /* Description: Subscribe configuration for task HFCLKAUDIOSTOP */
360 
361 /* Bit 31 :   */
362 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos (31UL) /*!< Position of EN field. */
363 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos) /*!< Bit mask of EN field. */
364 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Disabled (0UL) /*!< Disable subscription */
365 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Enabled (1UL) /*!< Enable subscription */
366 
367 /* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTOP will subscribe to */
368 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
369 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
370 
371 /* Register: CLOCK_SUBSCRIBE_HFCLK192MSTART */
372 /* Description: Subscribe configuration for task HFCLK192MSTART */
373 
374 /* Bit 31 :   */
375 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos (31UL) /*!< Position of EN field. */
376 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos) /*!< Bit mask of EN field. */
377 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Disabled (0UL) /*!< Disable subscription */
378 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Enabled (1UL) /*!< Enable subscription */
379 
380 /* Bits 7..0 : DPPI channel that task HFCLK192MSTART will subscribe to */
381 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
382 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
383 
384 /* Register: CLOCK_SUBSCRIBE_HFCLK192MSTOP */
385 /* Description: Subscribe configuration for task HFCLK192MSTOP */
386 
387 /* Bit 31 :   */
388 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos (31UL) /*!< Position of EN field. */
389 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos) /*!< Bit mask of EN field. */
390 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Disabled (0UL) /*!< Disable subscription */
391 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Enabled (1UL) /*!< Enable subscription */
392 
393 /* Bits 7..0 : DPPI channel that task HFCLK192MSTOP will subscribe to */
394 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
395 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
396 
397 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
398 /* Description: HFCLK128M/HFCLK64M source started */
399 
400 /* Bit 0 : HFCLK128M/HFCLK64M source started */
401 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
402 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
403 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
404 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
405 
406 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
407 /* Description: LFCLK source started */
408 
409 /* Bit 0 : LFCLK source started */
410 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
411 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
412 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
413 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
414 
415 /* Register: CLOCK_EVENTS_DONE */
416 /* Description: Calibration of LFRC oscillator complete event */
417 
418 /* Bit 0 : Calibration of LFRC oscillator complete event */
419 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
420 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
421 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
422 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
423 
424 /* Register: CLOCK_EVENTS_HFCLKAUDIOSTARTED */
425 /* Description: HFCLKAUDIO source started */
426 
427 /* Bit 0 : HFCLKAUDIO source started */
428 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKAUDIOSTARTED field. */
429 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKAUDIOSTARTED field. */
430 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_NotGenerated (0UL) /*!< Event not generated */
431 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Generated (1UL) /*!< Event generated */
432 
433 /* Register: CLOCK_EVENTS_HFCLK192MSTARTED */
434 /* Description: HFCLK192M source started */
435 
436 /* Bit 0 : HFCLK192M source started */
437 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLK192MSTARTED field. */
438 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLK192MSTARTED field. */
439 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_NotGenerated (0UL) /*!< Event not generated */
440 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Generated (1UL) /*!< Event generated */
441 
442 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */
443 /* Description: Publish configuration for event HFCLKSTARTED */
444 
445 /* Bit 31 :   */
446 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
447 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
448 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
449 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
450 
451 /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to. */
452 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
453 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
454 
455 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */
456 /* Description: Publish configuration for event LFCLKSTARTED */
457 
458 /* Bit 31 :   */
459 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
460 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
461 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
462 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
463 
464 /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to. */
465 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
466 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
467 
468 /* Register: CLOCK_PUBLISH_DONE */
469 /* Description: Publish configuration for event DONE */
470 
471 /* Bit 31 :   */
472 #define CLOCK_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
473 #define CLOCK_PUBLISH_DONE_EN_Msk (0x1UL << CLOCK_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
474 #define CLOCK_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */
475 #define CLOCK_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
476 
477 /* Bits 7..0 : DPPI channel that event DONE will publish to. */
478 #define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
479 #define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
480 
481 /* Register: CLOCK_PUBLISH_HFCLKAUDIOSTARTED */
482 /* Description: Publish configuration for event HFCLKAUDIOSTARTED */
483 
484 /* Bit 31 :   */
485 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
486 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos) /*!< Bit mask of EN field. */
487 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
488 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
489 
490 /* Bits 7..0 : DPPI channel that event HFCLKAUDIOSTARTED will publish to. */
491 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
492 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
493 
494 /* Register: CLOCK_PUBLISH_HFCLK192MSTARTED */
495 /* Description: Publish configuration for event HFCLK192MSTARTED */
496 
497 /* Bit 31 :   */
498 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
499 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos) /*!< Bit mask of EN field. */
500 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
501 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
502 
503 /* Bits 7..0 : DPPI channel that event HFCLK192MSTARTED will publish to. */
504 #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
505 #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
506 
507 /* Register: CLOCK_INTEN */
508 /* Description: Enable or disable interrupt */
509 
510 /* Bit 9 : Enable or disable interrupt for event HFCLK192MSTARTED */
511 #define CLOCK_INTEN_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
512 #define CLOCK_INTEN_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
513 #define CLOCK_INTEN_HFCLK192MSTARTED_Disabled (0UL) /*!< Disable */
514 #define CLOCK_INTEN_HFCLK192MSTARTED_Enabled (1UL) /*!< Enable */
515 
516 /* Bit 8 : Enable or disable interrupt for event HFCLKAUDIOSTARTED */
517 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
518 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
519 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Disable */
520 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Enable */
521 
522 /* Bit 7 : Enable or disable interrupt for event DONE */
523 #define CLOCK_INTEN_DONE_Pos (7UL) /*!< Position of DONE field. */
524 #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
525 #define CLOCK_INTEN_DONE_Disabled (0UL) /*!< Disable */
526 #define CLOCK_INTEN_DONE_Enabled (1UL) /*!< Enable */
527 
528 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
529 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
530 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
531 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */
532 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */
533 
534 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
535 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
536 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
537 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */
538 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */
539 
540 /* Register: CLOCK_INTENSET */
541 /* Description: Enable interrupt */
542 
543 /* Bit 9 : Write '1' to enable interrupt for event HFCLK192MSTARTED */
544 #define CLOCK_INTENSET_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
545 #define CLOCK_INTENSET_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
546 #define CLOCK_INTENSET_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */
547 #define CLOCK_INTENSET_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */
548 #define CLOCK_INTENSET_HFCLK192MSTARTED_Set (1UL) /*!< Enable */
549 
550 /* Bit 8 : Write '1' to enable interrupt for event HFCLKAUDIOSTARTED */
551 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
552 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
553 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */
554 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */
555 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Set (1UL) /*!< Enable */
556 
557 /* Bit 7 : Write '1' to enable interrupt for event DONE */
558 #define CLOCK_INTENSET_DONE_Pos (7UL) /*!< Position of DONE field. */
559 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
560 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
561 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
562 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
563 
564 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
565 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
566 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
567 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
568 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
569 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
570 
571 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
572 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
573 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
574 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
575 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
576 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
577 
578 /* Register: CLOCK_INTENCLR */
579 /* Description: Disable interrupt */
580 
581 /* Bit 9 : Write '1' to disable interrupt for event HFCLK192MSTARTED */
582 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
583 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
584 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */
585 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */
586 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Clear (1UL) /*!< Disable */
587 
588 /* Bit 8 : Write '1' to disable interrupt for event HFCLKAUDIOSTARTED */
589 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
590 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
591 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */
592 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */
593 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Clear (1UL) /*!< Disable */
594 
595 /* Bit 7 : Write '1' to disable interrupt for event DONE */
596 #define CLOCK_INTENCLR_DONE_Pos (7UL) /*!< Position of DONE field. */
597 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
598 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
599 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
600 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
601 
602 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
603 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
604 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
605 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
606 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
607 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
608 
609 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
610 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
611 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
612 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
613 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
614 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
615 
616 /* Register: CLOCK_INTPEND */
617 /* Description: Pending interrupts */
618 
619 /* Bit 9 : Read pending status of interrupt for event HFCLK192MSTARTED */
620 #define CLOCK_INTPEND_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
621 #define CLOCK_INTPEND_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
622 #define CLOCK_INTPEND_HFCLK192MSTARTED_NotPending (0UL) /*!< Read: Not pending */
623 #define CLOCK_INTPEND_HFCLK192MSTARTED_Pending (1UL) /*!< Read: Pending */
624 
625 /* Bit 8 : Read pending status of interrupt for event HFCLKAUDIOSTARTED */
626 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
627 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
628 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_NotPending (0UL) /*!< Read: Not pending */
629 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pending (1UL) /*!< Read: Pending */
630 
631 /* Bit 7 : Read pending status of interrupt for event DONE */
632 #define CLOCK_INTPEND_DONE_Pos (7UL) /*!< Position of DONE field. */
633 #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos) /*!< Bit mask of DONE field. */
634 #define CLOCK_INTPEND_DONE_NotPending (0UL) /*!< Read: Not pending */
635 #define CLOCK_INTPEND_DONE_Pending (1UL) /*!< Read: Pending */
636 
637 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
638 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
639 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
640 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
641 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
642 
643 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */
644 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
645 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
646 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
647 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
648 
649 /* Register: CLOCK_HFCLKRUN */
650 /* Description: Status indicating that HFCLKSTART task has been triggered */
651 
652 /* Bit 0 : HFCLKSTART task triggered or not */
653 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
654 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
655 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
656 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
657 
658 /* Register: CLOCK_HFCLKSTAT */
659 /* Description: Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */
660 
661 /* Bit 16 : HFCLK state */
662 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
663 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
664 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
665 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
666 
667 /* Bit 4 : ALWAYSRUN activated */
668 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
669 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
670 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
671 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
672 
673 /* Bit 0 : Active clock source */
674 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
675 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
676 #define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - 128 MHz on-chip oscillator */
677 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator */
678 
679 /* Register: CLOCK_LFCLKRUN */
680 /* Description: Status indicating that LFCLKSTART task has been triggered */
681 
682 /* Bit 0 : LFCLKSTART task triggered or not */
683 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
684 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
685 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
686 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
687 
688 /* Register: CLOCK_LFCLKSTAT */
689 /* Description: Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */
690 
691 /* Bit 16 : LFCLK state */
692 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
693 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
694 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
695 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
696 
697 /* Bit 4 : ALWAYSRUN activated */
698 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
699 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
700 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
701 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
702 
703 /* Bits 1..0 : Active clock source */
704 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
705 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
706 #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
707 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
708 #define CLOCK_LFCLKSTAT_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */
709 
710 /* Register: CLOCK_LFCLKSRCCOPY */
711 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
712 
713 /* Bits 1..0 : Clock source */
714 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
715 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
716 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
717 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
718 #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */
719 
720 /* Register: CLOCK_HFCLKAUDIORUN */
721 /* Description: Status indicating that HFCLKAUDIOSTART task has been triggered */
722 
723 /* Bit 0 : HFCLKAUDIOSTART task triggered or not */
724 #define CLOCK_HFCLKAUDIORUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
725 #define CLOCK_HFCLKAUDIORUN_STATUS_Msk (0x1UL << CLOCK_HFCLKAUDIORUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
726 #define CLOCK_HFCLKAUDIORUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
727 #define CLOCK_HFCLKAUDIORUN_STATUS_Triggered (1UL) /*!< Task triggered */
728 
729 /* Register: CLOCK_HFCLKAUDIOSTAT */
730 /* Description: Status indicating which HFCLKAUDIO source is running */
731 
732 /* Bit 16 : HFCLKAUDIO state */
733 #define CLOCK_HFCLKAUDIOSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
734 #define CLOCK_HFCLKAUDIOSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
735 #define CLOCK_HFCLKAUDIOSTAT_STATE_NotRunning (0UL) /*!< HFCLKAUDIO not running */
736 #define CLOCK_HFCLKAUDIOSTAT_STATE_Running (1UL) /*!< HFCLKAUDIO running */
737 
738 /* Bit 4 : ALWAYSRUN activated */
739 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
740 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
741 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
742 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
743 
744 /* Register: CLOCK_HFCLK192MRUN */
745 /* Description: Status indicating that HFCLK192MSTART task has been triggered */
746 
747 /* Bit 0 : HFCLK192MSTART task triggered or not */
748 #define CLOCK_HFCLK192MRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
749 #define CLOCK_HFCLK192MRUN_STATUS_Msk (0x1UL << CLOCK_HFCLK192MRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
750 #define CLOCK_HFCLK192MRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
751 #define CLOCK_HFCLK192MRUN_STATUS_Triggered (1UL) /*!< Task triggered */
752 
753 /* Register: CLOCK_HFCLK192MSTAT */
754 /* Description: Status indicating which HFCLK192M source is running */
755 
756 /* Bit 16 : HFCLK192M state */
757 #define CLOCK_HFCLK192MSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
758 #define CLOCK_HFCLK192MSTAT_STATE_Msk (0x1UL << CLOCK_HFCLK192MSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
759 #define CLOCK_HFCLK192MSTAT_STATE_NotRunning (0UL) /*!< HFCLK192M not running */
760 #define CLOCK_HFCLK192MSTAT_STATE_Running (1UL) /*!< HFCLK192M running */
761 
762 /* Bit 4 : ALWAYSRUN activated */
763 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
764 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
765 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
766 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
767 
768 /* Bit 0 : Active clock source */
769 #define CLOCK_HFCLK192MSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
770 #define CLOCK_HFCLK192MSTAT_SRC_Msk (0x1UL << CLOCK_HFCLK192MSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
771 #define CLOCK_HFCLK192MSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - on-chip oscillator */
772 #define CLOCK_HFCLK192MSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - derived from external 32 MHz crystal oscillator */
773 
774 /* Register: CLOCK_HFCLKSRC */
775 /* Description: Clock source for HFCLK128M/HFCLK64M */
776 
777 /* Bit 0 : Select which HFCLK source is started by the HFCLKSTART task */
778 #define CLOCK_HFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
779 #define CLOCK_HFCLKSRC_SRC_Msk (0x1UL << CLOCK_HFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
780 #define CLOCK_HFCLKSRC_SRC_HFINT (0UL) /*!< HFCLKSTART task starts HFINT oscillator */
781 #define CLOCK_HFCLKSRC_SRC_HFXO (1UL) /*!< HFCLKSTART task starts HFXO oscillator */
782 
783 /* Register: CLOCK_LFCLKSRC */
784 /* Description: Clock source for LFCLK */
785 
786 /* Bits 1..0 : Select which LFCLK source is started by the LFCLKSTART task */
787 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
788 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
789 #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
790 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
791 #define CLOCK_LFCLKSRC_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */
792 
793 /* Register: CLOCK_HFCLKCTRL */
794 /* Description: HFCLK128M frequency configuration */
795 
796 /* Bits 1..0 : High frequency clock HCLK */
797 #define CLOCK_HFCLKCTRL_HCLK_Pos (0UL) /*!< Position of HCLK field. */
798 #define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */
799 #define CLOCK_HFCLKCTRL_HCLK_Div1 (0UL) /*!< Divide HFCLK by 1 */
800 #define CLOCK_HFCLKCTRL_HCLK_Div2 (1UL) /*!< Divide HFCLK by 2 */
801 
802 /* Register: CLOCK_HFCLKAUDIO_FREQUENCY */
803 /* Description: Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands */
804 
805 /* Bits 15..0 : Frequency 0: 10.666 MHz 65535: 13.333 MHz */
806 #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
807 #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Msk (0xFFFFUL << CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
808 
809 /* Register: CLOCK_HFCLKALWAYSRUN */
810 /* Description: Automatic or manual control of HFCLK128M/HFCLK64M */
811 
812 /* Bit 0 : Ensure clock is always running */
813 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
814 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
815 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
816 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
817 
818 /* Register: CLOCK_LFCLKALWAYSRUN */
819 /* Description: Automatic or manual control of LFCLK */
820 
821 /* Bit 0 : Ensure clock is always running */
822 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
823 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
824 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
825 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
826 
827 /* Register: CLOCK_HFCLKAUDIOALWAYSRUN */
828 /* Description: Automatic or manual control of HFCLKAUDIO */
829 
830 /* Bit 0 : Ensure clock is always running */
831 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
832 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
833 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
834 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
835 
836 /* Register: CLOCK_HFCLK192MSRC */
837 /* Description: Clock source for HFCLK192M */
838 
839 /* Bit 0 : Select which HFCLK192M source is started by the HFCLK192MSTART task */
840 #define CLOCK_HFCLK192MSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
841 #define CLOCK_HFCLK192MSRC_SRC_Msk (0x1UL << CLOCK_HFCLK192MSRC_SRC_Pos) /*!< Bit mask of SRC field. */
842 #define CLOCK_HFCLK192MSRC_SRC_HFINT (0UL) /*!< HFCLK192MSTART task starts HFINT oscillator */
843 #define CLOCK_HFCLK192MSRC_SRC_HFXO (1UL) /*!< HFCLK192MSTART task starts HFXO oscillator */
844 
845 /* Register: CLOCK_HFCLK192MALWAYSRUN */
846 /* Description: Automatic or manual control of HFCLK192M */
847 
848 /* Bit 0 : Ensure clock is always running */
849 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
850 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
851 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
852 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
853 
854 /* Register: CLOCK_HFCLK192MCTRL */
855 /* Description: HFCLK192M frequency configuration */
856 
857 /* Bits 1..0 : High frequency clock HCLK192M */
858 #define CLOCK_HFCLK192MCTRL_HCLK192M_Pos (0UL) /*!< Position of HCLK192M field. */
859 #define CLOCK_HFCLK192MCTRL_HCLK192M_Msk (0x3UL << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) /*!< Bit mask of HCLK192M field. */
860 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div1 (0UL) /*!< Divide HFCLK192M by 1 */
861 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div2 (1UL) /*!< Divide HFCLK192M by 2 */
862 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div4 (2UL) /*!< Divide HFCLK192M by 4 */
863 
864 
865 /* Peripheral: COMP */
866 /* Description: Comparator 0 */
867 
868 /* Register: COMP_TASKS_START */
869 /* Description: Start comparator */
870 
871 /* Bit 0 : Start comparator */
872 #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
873 #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
874 #define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
875 
876 /* Register: COMP_TASKS_STOP */
877 /* Description: Stop comparator */
878 
879 /* Bit 0 : Stop comparator */
880 #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
881 #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
882 #define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
883 
884 /* Register: COMP_TASKS_SAMPLE */
885 /* Description: Sample comparator value */
886 
887 /* Bit 0 : Sample comparator value */
888 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
889 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
890 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
891 
892 /* Register: COMP_SUBSCRIBE_START */
893 /* Description: Subscribe configuration for task START */
894 
895 /* Bit 31 :   */
896 #define COMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
897 #define COMP_SUBSCRIBE_START_EN_Msk (0x1UL << COMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
898 #define COMP_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
899 #define COMP_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
900 
901 /* Bits 7..0 : DPPI channel that task START will subscribe to */
902 #define COMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
903 #define COMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
904 
905 /* Register: COMP_SUBSCRIBE_STOP */
906 /* Description: Subscribe configuration for task STOP */
907 
908 /* Bit 31 :   */
909 #define COMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
910 #define COMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << COMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
911 #define COMP_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
912 #define COMP_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
913 
914 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
915 #define COMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
916 #define COMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
917 
918 /* Register: COMP_SUBSCRIBE_SAMPLE */
919 /* Description: Subscribe configuration for task SAMPLE */
920 
921 /* Bit 31 :   */
922 #define COMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
923 #define COMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << COMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
924 #define COMP_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */
925 #define COMP_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */
926 
927 /* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
928 #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
929 #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
930 
931 /* Register: COMP_EVENTS_READY */
932 /* Description: COMP is ready and output is valid */
933 
934 /* Bit 0 : COMP is ready and output is valid */
935 #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
936 #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
937 #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
938 #define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
939 
940 /* Register: COMP_EVENTS_DOWN */
941 /* Description: Downward crossing */
942 
943 /* Bit 0 : Downward crossing */
944 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
945 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
946 #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
947 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
948 
949 /* Register: COMP_EVENTS_UP */
950 /* Description: Upward crossing */
951 
952 /* Bit 0 : Upward crossing */
953 #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
954 #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
955 #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
956 #define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
957 
958 /* Register: COMP_EVENTS_CROSS */
959 /* Description: Downward or upward crossing */
960 
961 /* Bit 0 : Downward or upward crossing */
962 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
963 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
964 #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
965 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
966 
967 /* Register: COMP_PUBLISH_READY */
968 /* Description: Publish configuration for event READY */
969 
970 /* Bit 31 :   */
971 #define COMP_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
972 #define COMP_PUBLISH_READY_EN_Msk (0x1UL << COMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
973 #define COMP_PUBLISH_READY_EN_Disabled (0UL) /*!< Disable publishing */
974 #define COMP_PUBLISH_READY_EN_Enabled (1UL) /*!< Enable publishing */
975 
976 /* Bits 7..0 : DPPI channel that event READY will publish to. */
977 #define COMP_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
978 #define COMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << COMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
979 
980 /* Register: COMP_PUBLISH_DOWN */
981 /* Description: Publish configuration for event DOWN */
982 
983 /* Bit 31 :   */
984 #define COMP_PUBLISH_DOWN_EN_Pos (31UL) /*!< Position of EN field. */
985 #define COMP_PUBLISH_DOWN_EN_Msk (0x1UL << COMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field. */
986 #define COMP_PUBLISH_DOWN_EN_Disabled (0UL) /*!< Disable publishing */
987 #define COMP_PUBLISH_DOWN_EN_Enabled (1UL) /*!< Enable publishing */
988 
989 /* Bits 7..0 : DPPI channel that event DOWN will publish to. */
990 #define COMP_PUBLISH_DOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
991 #define COMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << COMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
992 
993 /* Register: COMP_PUBLISH_UP */
994 /* Description: Publish configuration for event UP */
995 
996 /* Bit 31 :   */
997 #define COMP_PUBLISH_UP_EN_Pos (31UL) /*!< Position of EN field. */
998 #define COMP_PUBLISH_UP_EN_Msk (0x1UL << COMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field. */
999 #define COMP_PUBLISH_UP_EN_Disabled (0UL) /*!< Disable publishing */
1000 #define COMP_PUBLISH_UP_EN_Enabled (1UL) /*!< Enable publishing */
1001 
1002 /* Bits 7..0 : DPPI channel that event UP will publish to. */
1003 #define COMP_PUBLISH_UP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1004 #define COMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << COMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1005 
1006 /* Register: COMP_PUBLISH_CROSS */
1007 /* Description: Publish configuration for event CROSS */
1008 
1009 /* Bit 31 :   */
1010 #define COMP_PUBLISH_CROSS_EN_Pos (31UL) /*!< Position of EN field. */
1011 #define COMP_PUBLISH_CROSS_EN_Msk (0x1UL << COMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field. */
1012 #define COMP_PUBLISH_CROSS_EN_Disabled (0UL) /*!< Disable publishing */
1013 #define COMP_PUBLISH_CROSS_EN_Enabled (1UL) /*!< Enable publishing */
1014 
1015 /* Bits 7..0 : DPPI channel that event CROSS will publish to. */
1016 #define COMP_PUBLISH_CROSS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1017 #define COMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << COMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1018 
1019 /* Register: COMP_SHORTS */
1020 /* Description: Shortcuts between local events and tasks */
1021 
1022 /* Bit 4 : Shortcut between event CROSS and task STOP */
1023 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
1024 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
1025 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
1026 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
1027 
1028 /* Bit 3 : Shortcut between event UP and task STOP */
1029 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
1030 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
1031 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
1032 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
1033 
1034 /* Bit 2 : Shortcut between event DOWN and task STOP */
1035 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
1036 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
1037 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
1038 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
1039 
1040 /* Bit 1 : Shortcut between event READY and task STOP */
1041 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
1042 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
1043 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
1044 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
1045 
1046 /* Bit 0 : Shortcut between event READY and task SAMPLE */
1047 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
1048 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
1049 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
1050 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
1051 
1052 /* Register: COMP_INTEN */
1053 /* Description: Enable or disable interrupt */
1054 
1055 /* Bit 3 : Enable or disable interrupt for event CROSS */
1056 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1057 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
1058 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
1059 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
1060 
1061 /* Bit 2 : Enable or disable interrupt for event UP */
1062 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
1063 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
1064 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
1065 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
1066 
1067 /* Bit 1 : Enable or disable interrupt for event DOWN */
1068 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1069 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
1070 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
1071 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
1072 
1073 /* Bit 0 : Enable or disable interrupt for event READY */
1074 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
1075 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
1076 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
1077 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
1078 
1079 /* Register: COMP_INTENSET */
1080 /* Description: Enable interrupt */
1081 
1082 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
1083 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1084 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
1085 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1086 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1087 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
1088 
1089 /* Bit 2 : Write '1' to enable interrupt for event UP */
1090 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
1091 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
1092 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1093 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1094 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
1095 
1096 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
1097 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1098 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
1099 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1100 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1101 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
1102 
1103 /* Bit 0 : Write '1' to enable interrupt for event READY */
1104 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
1105 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
1106 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1107 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1108 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
1109 
1110 /* Register: COMP_INTENCLR */
1111 /* Description: Disable interrupt */
1112 
1113 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
1114 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1115 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
1116 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1117 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1118 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1119 
1120 /* Bit 2 : Write '1' to disable interrupt for event UP */
1121 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
1122 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
1123 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1124 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1125 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1126 
1127 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
1128 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1129 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
1130 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1131 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1132 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1133 
1134 /* Bit 0 : Write '1' to disable interrupt for event READY */
1135 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
1136 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
1137 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1138 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1139 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1140 
1141 /* Register: COMP_RESULT */
1142 /* Description: Compare result */
1143 
1144 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
1145 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
1146 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
1147 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
1148 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
1149 
1150 /* Register: COMP_ENABLE */
1151 /* Description: COMP enable */
1152 
1153 /* Bits 1..0 : Enable or disable COMP */
1154 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1155 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1156 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1157 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1158 
1159 /* Register: COMP_PSEL */
1160 /* Description: Pin select */
1161 
1162 /* Bits 2..0 : Analog pin select */
1163 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
1164 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
1165 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
1166 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
1167 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
1168 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
1169 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
1170 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
1171 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
1172 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
1173 
1174 /* Register: COMP_REFSEL */
1175 /* Description: Reference source select for single-ended mode */
1176 
1177 /* Bits 2..0 : Reference select */
1178 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
1179 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
1180 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
1181 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
1182 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
1183 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
1184 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF */
1185 
1186 /* Register: COMP_EXTREFSEL */
1187 /* Description: External reference select */
1188 
1189 /* Bits 2..0 : External analog reference select */
1190 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
1191 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
1192 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
1193 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
1194 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
1195 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
1196 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */
1197 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */
1198 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */
1199 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */
1200 
1201 /* Register: COMP_TH */
1202 /* Description: Threshold configuration for hysteresis unit */
1203 
1204 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
1205 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
1206 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
1207 
1208 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1209 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
1210 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
1211 
1212 /* Register: COMP_MODE */
1213 /* Description: Mode configuration */
1214 
1215 /* Bit 8 : Main operation modes */
1216 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
1217 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
1218 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1219 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1220 
1221 /* Bits 1..0 : Speed and power modes */
1222 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
1223 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
1224 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1225 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1226 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1227 
1228 /* Register: COMP_HYST */
1229 /* Description: Comparator hysteresis enable */
1230 
1231 /* Bit 0 : Comparator hysteresis */
1232 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
1233 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
1234 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1235 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1236 
1237 /* Register: COMP_ISOURCE */
1238 /* Description: Current source select on analog input */
1239 
1240 /* Bits 1..0 : Comparator hysteresis */
1241 #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
1242 #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
1243 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
1244 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
1245 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
1246 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
1247 
1248 
1249 /* Peripheral: CRYPTOCELL */
1250 /* Description: ARM TrustZone CryptoCell register interface */
1251 
1252 /* Register: CRYPTOCELL_ENABLE */
1253 /* Description: Enable CRYPTOCELL subsystem. */
1254 
1255 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem. */
1256 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1257 #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1258 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled. */
1259 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */
1260 
1261 
1262 /* Peripheral: CTI */
1263 /* Description: Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. */
1264 
1265 /* Register: CTI_CTICONTROL */
1266 /* Description: CTI Control register */
1267 
1268 /* Bit 0 : Enables or disables the CTI. */
1269 #define CTI_CTICONTROL_GLBEN_Pos (0UL) /*!< Position of GLBEN field. */
1270 #define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos) /*!< Bit mask of GLBEN field. */
1271 #define CTI_CTICONTROL_GLBEN_Disabled (0UL) /*!< All cross-triggering mapping logic functionality is disabled. */
1272 #define CTI_CTICONTROL_GLBEN_Enabled (1UL) /*!< Cross-triggering mapping logic functionality is enabled. */
1273 
1274 /* Register: CTI_CTIINTACK */
1275 /* Description: CTI Interrupt Acknowledge register */
1276 
1277 /* Bit 7 : ETM Event Input 3 */
1278 #define CTI_CTIINTACK_ETMEVTIN3_Pos (7UL) /*!< Position of ETMEVTIN3 field. */
1279 #define CTI_CTIINTACK_ETMEVTIN3_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN3_Pos) /*!< Bit mask of ETMEVTIN3 field. */
1280 #define CTI_CTIINTACK_ETMEVTIN3_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1281 
1282 /* Bit 6 : ETM Event Input 2 */
1283 #define CTI_CTIINTACK_ETMEVTIN2_Pos (6UL) /*!< Position of ETMEVTIN2 field. */
1284 #define CTI_CTIINTACK_ETMEVTIN2_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN2_Pos) /*!< Bit mask of ETMEVTIN2 field. */
1285 #define CTI_CTIINTACK_ETMEVTIN2_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1286 
1287 /* Bit 5 : ETM Event Input 1 */
1288 #define CTI_CTIINTACK_ETMEVTIN1_Pos (5UL) /*!< Position of ETMEVTIN1 field. */
1289 #define CTI_CTIINTACK_ETMEVTIN1_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN1_Pos) /*!< Bit mask of ETMEVTIN1 field. */
1290 #define CTI_CTIINTACK_ETMEVTIN1_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1291 
1292 /* Bit 4 : ETM Event Input 0 */
1293 #define CTI_CTIINTACK_ETMEVTIN0_Pos (4UL) /*!< Position of ETMEVTIN0 field. */
1294 #define CTI_CTIINTACK_ETMEVTIN0_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN0_Pos) /*!< Bit mask of ETMEVTIN0 field. */
1295 #define CTI_CTIINTACK_ETMEVTIN0_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1296 
1297 /* Bit 3 : N/A */
1298 #define CTI_CTIINTACK_UNUSED1_Pos (3UL) /*!< Position of UNUSED1 field. */
1299 #define CTI_CTIINTACK_UNUSED1_Msk (0x1UL << CTI_CTIINTACK_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */
1300 #define CTI_CTIINTACK_UNUSED1_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1301 
1302 /* Bit 2 : N/A */
1303 #define CTI_CTIINTACK_UNUSED0_Pos (2UL) /*!< Position of UNUSED0 field. */
1304 #define CTI_CTIINTACK_UNUSED0_Msk (0x1UL << CTI_CTIINTACK_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */
1305 #define CTI_CTIINTACK_UNUSED0_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1306 
1307 /* Bit 1 : Processor Restart */
1308 #define CTI_CTIINTACK_CPURESTART_Pos (1UL) /*!< Position of CPURESTART field. */
1309 #define CTI_CTIINTACK_CPURESTART_Msk (0x1UL << CTI_CTIINTACK_CPURESTART_Pos) /*!< Bit mask of CPURESTART field. */
1310 #define CTI_CTIINTACK_CPURESTART_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1311 
1312 /* Bit 0 : Processor debug request */
1313 #define CTI_CTIINTACK_DEBUGREQ_Pos (0UL) /*!< Position of DEBUGREQ field. */
1314 #define CTI_CTIINTACK_DEBUGREQ_Msk (0x1UL << CTI_CTIINTACK_DEBUGREQ_Pos) /*!< Bit mask of DEBUGREQ field. */
1315 #define CTI_CTIINTACK_DEBUGREQ_Acknowledge (1UL) /*!< Clears the ctitrigout. */
1316 
1317 /* Register: CTI_CTIAPPSET */
1318 /* Description: CTI Application Trigger Set register */
1319 
1320 /* Bit 3 : Application trigger event for channel 3. */
1321 #define CTI_CTIAPPSET_APPSET_3_Pos (3UL) /*!< Position of APPSET_3 field. */
1322 #define CTI_CTIAPPSET_APPSET_3_Msk (0x1UL << CTI_CTIAPPSET_APPSET_3_Pos) /*!< Bit mask of APPSET_3 field. */
1323 #define CTI_CTIAPPSET_APPSET_3_Inactive (0UL) /*!< Application trigger 3 is inactive. */
1324 #define CTI_CTIAPPSET_APPSET_3_Active (1UL) /*!< Application trigger 3 is active. */
1325 #define CTI_CTIAPPSET_APPSET_3_Activate (1UL) /*!< Generate channel event for channel 3. */
1326 
1327 /* Bit 2 : Application trigger event for channel 2. */
1328 #define CTI_CTIAPPSET_APPSET_2_Pos (2UL) /*!< Position of APPSET_2 field. */
1329 #define CTI_CTIAPPSET_APPSET_2_Msk (0x1UL << CTI_CTIAPPSET_APPSET_2_Pos) /*!< Bit mask of APPSET_2 field. */
1330 #define CTI_CTIAPPSET_APPSET_2_Inactive (0UL) /*!< Application trigger 2 is inactive. */
1331 #define CTI_CTIAPPSET_APPSET_2_Active (1UL) /*!< Application trigger 2 is active. */
1332 #define CTI_CTIAPPSET_APPSET_2_Activate (1UL) /*!< Generate channel event for channel 2. */
1333 
1334 /* Bit 1 : Application trigger event for channel 1. */
1335 #define CTI_CTIAPPSET_APPSET_1_Pos (1UL) /*!< Position of APPSET_1 field. */
1336 #define CTI_CTIAPPSET_APPSET_1_Msk (0x1UL << CTI_CTIAPPSET_APPSET_1_Pos) /*!< Bit mask of APPSET_1 field. */
1337 #define CTI_CTIAPPSET_APPSET_1_Inactive (0UL) /*!< Application trigger 1 is inactive. */
1338 #define CTI_CTIAPPSET_APPSET_1_Active (1UL) /*!< Application trigger 1 is active. */
1339 #define CTI_CTIAPPSET_APPSET_1_Activate (1UL) /*!< Generate channel event for channel 1. */
1340 
1341 /* Bit 0 : Application trigger event for channel 0. */
1342 #define CTI_CTIAPPSET_APPSET_0_Pos (0UL) /*!< Position of APPSET_0 field. */
1343 #define CTI_CTIAPPSET_APPSET_0_Msk (0x1UL << CTI_CTIAPPSET_APPSET_0_Pos) /*!< Bit mask of APPSET_0 field. */
1344 #define CTI_CTIAPPSET_APPSET_0_Inactive (0UL) /*!< Application trigger 0 is inactive. */
1345 #define CTI_CTIAPPSET_APPSET_0_Active (1UL) /*!< Application trigger 0 is active. */
1346 #define CTI_CTIAPPSET_APPSET_0_Activate (1UL) /*!< Generate channel event for channel 0. */
1347 
1348 /* Register: CTI_CTIAPPCLEAR */
1349 /* Description: CTI Application Trigger Clear register */
1350 
1351 /* Bit 3 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
1352 #define CTI_CTIAPPCLEAR_APPCLEAR_3_Pos (3UL) /*!< Position of APPCLEAR_3 field. */
1353 #define CTI_CTIAPPCLEAR_APPCLEAR_3_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_3_Pos) /*!< Bit mask of APPCLEAR_3 field. */
1354 #define CTI_CTIAPPCLEAR_APPCLEAR_3_Clear (1UL) /*!< Clears the event for channel 3. */
1355 
1356 /* Bit 2 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
1357 #define CTI_CTIAPPCLEAR_APPCLEAR_2_Pos (2UL) /*!< Position of APPCLEAR_2 field. */
1358 #define CTI_CTIAPPCLEAR_APPCLEAR_2_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_2_Pos) /*!< Bit mask of APPCLEAR_2 field. */
1359 #define CTI_CTIAPPCLEAR_APPCLEAR_2_Clear (1UL) /*!< Clears the event for channel 2. */
1360 
1361 /* Bit 1 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
1362 #define CTI_CTIAPPCLEAR_APPCLEAR_1_Pos (1UL) /*!< Position of APPCLEAR_1 field. */
1363 #define CTI_CTIAPPCLEAR_APPCLEAR_1_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_1_Pos) /*!< Bit mask of APPCLEAR_1 field. */
1364 #define CTI_CTIAPPCLEAR_APPCLEAR_1_Clear (1UL) /*!< Clears the event for channel 1. */
1365 
1366 /* Bit 0 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
1367 #define CTI_CTIAPPCLEAR_APPCLEAR_0_Pos (0UL) /*!< Position of APPCLEAR_0 field. */
1368 #define CTI_CTIAPPCLEAR_APPCLEAR_0_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_0_Pos) /*!< Bit mask of APPCLEAR_0 field. */
1369 #define CTI_CTIAPPCLEAR_APPCLEAR_0_Clear (1UL) /*!< Clears the event for channel 0. */
1370 
1371 /* Register: CTI_CTIAPPPULSE */
1372 /* Description: CTI Application Pulse register */
1373 
1374 /* Bit 3 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
1375 #define CTI_CTIAPPPULSE_APPULSE_3_Pos (3UL) /*!< Position of APPULSE_3 field. */
1376 #define CTI_CTIAPPPULSE_APPULSE_3_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_3_Pos) /*!< Bit mask of APPULSE_3 field. */
1377 #define CTI_CTIAPPPULSE_APPULSE_3_Generate (1UL) /*!< Generates an event pulse on channel 3. */
1378 
1379 /* Bit 2 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
1380 #define CTI_CTIAPPPULSE_APPULSE_2_Pos (2UL) /*!< Position of APPULSE_2 field. */
1381 #define CTI_CTIAPPPULSE_APPULSE_2_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_2_Pos) /*!< Bit mask of APPULSE_2 field. */
1382 #define CTI_CTIAPPPULSE_APPULSE_2_Generate (1UL) /*!< Generates an event pulse on channel 2. */
1383 
1384 /* Bit 1 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
1385 #define CTI_CTIAPPPULSE_APPULSE_1_Pos (1UL) /*!< Position of APPULSE_1 field. */
1386 #define CTI_CTIAPPPULSE_APPULSE_1_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_1_Pos) /*!< Bit mask of APPULSE_1 field. */
1387 #define CTI_CTIAPPPULSE_APPULSE_1_Generate (1UL) /*!< Generates an event pulse on channel 1. */
1388 
1389 /* Bit 0 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */
1390 #define CTI_CTIAPPPULSE_APPULSE_0_Pos (0UL) /*!< Position of APPULSE_0 field. */
1391 #define CTI_CTIAPPPULSE_APPULSE_0_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_0_Pos) /*!< Bit mask of APPULSE_0 field. */
1392 #define CTI_CTIAPPPULSE_APPULSE_0_Generate (1UL) /*!< Generates an event pulse on channel 0. */
1393 
1394 /* Register: CTI_CTIINEN */
1395 /* Description: Description collection: CTI Trigger input */
1396 
1397 /* Bit 3 : Enables a cross trigger event to channel 3 when a ctitrigin input is activated. */
1398 #define CTI_CTIINEN_TRIGINEN_3_Pos (3UL) /*!< Position of TRIGINEN_3 field. */
1399 #define CTI_CTIINEN_TRIGINEN_3_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_3_Pos) /*!< Bit mask of TRIGINEN_3 field. */
1400 #define CTI_CTIINEN_TRIGINEN_3_Disabled (0UL) /*!< Input trigger n events are ignored by channel 3. */
1401 #define CTI_CTIINEN_TRIGINEN_3_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. */
1402 
1403 /* Bit 2 : Enables a cross trigger event to channel 2 when a ctitrigin input is activated. */
1404 #define CTI_CTIINEN_TRIGINEN_2_Pos (2UL) /*!< Position of TRIGINEN_2 field. */
1405 #define CTI_CTIINEN_TRIGINEN_2_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_2_Pos) /*!< Bit mask of TRIGINEN_2 field. */
1406 #define CTI_CTIINEN_TRIGINEN_2_Disabled (0UL) /*!< Input trigger n events are ignored by channel 2. */
1407 #define CTI_CTIINEN_TRIGINEN_2_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. */
1408 
1409 /* Bit 1 : Enables a cross trigger event to channel 1 when a ctitrigin input is activated. */
1410 #define CTI_CTIINEN_TRIGINEN_1_Pos (1UL) /*!< Position of TRIGINEN_1 field. */
1411 #define CTI_CTIINEN_TRIGINEN_1_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_1_Pos) /*!< Bit mask of TRIGINEN_1 field. */
1412 #define CTI_CTIINEN_TRIGINEN_1_Disabled (0UL) /*!< Input trigger n events are ignored by channel 1. */
1413 #define CTI_CTIINEN_TRIGINEN_1_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. */
1414 
1415 /* Bit 0 : Enables a cross trigger event to channel 0 when a ctitrigin input is activated. */
1416 #define CTI_CTIINEN_TRIGINEN_0_Pos (0UL) /*!< Position of TRIGINEN_0 field. */
1417 #define CTI_CTIINEN_TRIGINEN_0_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_0_Pos) /*!< Bit mask of TRIGINEN_0 field. */
1418 #define CTI_CTIINEN_TRIGINEN_0_Disabled (0UL) /*!< Input trigger n events are ignored by channel 0. */
1419 #define CTI_CTIINEN_TRIGINEN_0_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. */
1420 
1421 /* Register: CTI_CTIOUTEN */
1422 /* Description: Description collection: CTI Trigger output */
1423 
1424 /* Bit 3 : Enables a cross trigger event to ctitrigout when channel 3 is activated. */
1425 #define CTI_CTIOUTEN_TRIGOUTEN_3_Pos (3UL) /*!< Position of TRIGOUTEN_3 field. */
1426 #define CTI_CTIOUTEN_TRIGOUTEN_3_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_3_Pos) /*!< Bit mask of TRIGOUTEN_3 field. */
1427 #define CTI_CTIOUTEN_TRIGOUTEN_3_Disabled (0UL) /*!< Channel 3 is ignored by output trigger n. */
1428 #define CTI_CTIOUTEN_TRIGOUTEN_3_Enabled (1UL) /*!< When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). */
1429 
1430 /* Bit 2 : Enables a cross trigger event to ctitrigout when channel 2 is activated. */
1431 #define CTI_CTIOUTEN_TRIGOUTEN_2_Pos (2UL) /*!< Position of TRIGOUTEN_2 field. */
1432 #define CTI_CTIOUTEN_TRIGOUTEN_2_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_2_Pos) /*!< Bit mask of TRIGOUTEN_2 field. */
1433 #define CTI_CTIOUTEN_TRIGOUTEN_2_Disabled (0UL) /*!< Channel 2 is ignored by output trigger n. */
1434 #define CTI_CTIOUTEN_TRIGOUTEN_2_Enabled (1UL) /*!< When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). */
1435 
1436 /* Bit 1 : Enables a cross trigger event to ctitrigout when channel 1 is activated. */
1437 #define CTI_CTIOUTEN_TRIGOUTEN_1_Pos (1UL) /*!< Position of TRIGOUTEN_1 field. */
1438 #define CTI_CTIOUTEN_TRIGOUTEN_1_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_1_Pos) /*!< Bit mask of TRIGOUTEN_1 field. */
1439 #define CTI_CTIOUTEN_TRIGOUTEN_1_Disabled (0UL) /*!< Channel 1 is ignored by output trigger n. */
1440 #define CTI_CTIOUTEN_TRIGOUTEN_1_Enabled (1UL) /*!< When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). */
1441 
1442 /* Bit 0 : Enables a cross trigger event to ctitrigout when channel 0 is activated. */
1443 #define CTI_CTIOUTEN_TRIGOUTEN_0_Pos (0UL) /*!< Position of TRIGOUTEN_0 field. */
1444 #define CTI_CTIOUTEN_TRIGOUTEN_0_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_0_Pos) /*!< Bit mask of TRIGOUTEN_0 field. */
1445 #define CTI_CTIOUTEN_TRIGOUTEN_0_Disabled (0UL) /*!< Channel 0 is ignored by output trigger n. */
1446 #define CTI_CTIOUTEN_TRIGOUTEN_0_Enabled (1UL) /*!< When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). */
1447 
1448 /* Register: CTI_CTITRIGINSTATUS */
1449 /* Description: CTI Trigger In Status register */
1450 
1451 /* Bit 7 : N/A */
1452 #define CTI_CTITRIGINSTATUS_UNUSED1_Pos (7UL) /*!< Position of UNUSED1 field. */
1453 #define CTI_CTITRIGINSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */
1454 #define CTI_CTITRIGINSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigin 7 is inactive. */
1455 #define CTI_CTITRIGINSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigin 7 is active. */
1456 
1457 /* Bit 6 : N/A */
1458 #define CTI_CTITRIGINSTATUS_UNUSED0_Pos (6UL) /*!< Position of UNUSED0 field. */
1459 #define CTI_CTITRIGINSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */
1460 #define CTI_CTITRIGINSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigin 6 is inactive. */
1461 #define CTI_CTITRIGINSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigin 6 is active. */
1462 
1463 /* Bit 5 : ETM Event Output 1 */
1464 #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Pos (5UL) /*!< Position of ETMEVTOUT1 field. */
1465 #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Msk (0x1UL << CTI_CTITRIGINSTATUS_ETMEVTOUT1_Pos) /*!< Bit mask of ETMEVTOUT1 field. */
1466 #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Inactive (0UL) /*!< Ctitrigin 5 is inactive. */
1467 #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Active (1UL) /*!< Ctitrigin 5 is active. */
1468 
1469 /* Bit 4 : ETM Event Output 0 */
1470 #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Pos (4UL) /*!< Position of ETMEVTOUT0 field. */
1471 #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Msk (0x1UL << CTI_CTITRIGINSTATUS_ETMEVTOUT0_Pos) /*!< Bit mask of ETMEVTOUT0 field. */
1472 #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Inactive (0UL) /*!< Ctitrigin 4 is inactive. */
1473 #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Active (1UL) /*!< Ctitrigin 4 is active. */
1474 
1475 /* Bit 3 : DWT Comparator Output 2 */
1476 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos (3UL) /*!< Position of DWTCOMPOUT2 field. */
1477 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos) /*!< Bit mask of DWTCOMPOUT2 field. */
1478 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Inactive (0UL) /*!< Ctitrigin 3 is inactive. */
1479 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Active (1UL) /*!< Ctitrigin 3 is active. */
1480 
1481 /* Bit 2 : DWT Comparator Output 1 */
1482 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos (2UL) /*!< Position of DWTCOMPOUT1 field. */
1483 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos) /*!< Bit mask of DWTCOMPOUT1 field. */
1484 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Inactive (0UL) /*!< Ctitrigin 2 is inactive. */
1485 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Active (1UL) /*!< Ctitrigin 2 is active. */
1486 
1487 /* Bit 1 : DWT Comparator Output 0 */
1488 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos (1UL) /*!< Position of DWTCOMPOUT0 field. */
1489 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos) /*!< Bit mask of DWTCOMPOUT0 field. */
1490 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Inactive (0UL) /*!< Ctitrigin 1 is inactive. */
1491 #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Active (1UL) /*!< Ctitrigin 1 is active. */
1492 
1493 /* Bit 0 : Processor Halted */
1494 #define CTI_CTITRIGINSTATUS_CPUHALTED_Pos (0UL) /*!< Position of CPUHALTED field. */
1495 #define CTI_CTITRIGINSTATUS_CPUHALTED_Msk (0x1UL << CTI_CTITRIGINSTATUS_CPUHALTED_Pos) /*!< Bit mask of CPUHALTED field. */
1496 #define CTI_CTITRIGINSTATUS_CPUHALTED_Inactive (0UL) /*!< Ctitrigin 0 is inactive. */
1497 #define CTI_CTITRIGINSTATUS_CPUHALTED_Active (1UL) /*!< Ctitrigin 0 is active. */
1498 
1499 /* Register: CTI_CTITRIGOUTSTATUS */
1500 /* Description: CTI Trigger Out Status register */
1501 
1502 /* Bit 7 : ETM Event Input 3 */
1503 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Pos (7UL) /*!< Position of ETMEVTIN3 field. */
1504 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Pos) /*!< Bit mask of ETMEVTIN3 field. */
1505 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Inactive (0UL) /*!< Ctitrigout 7 is inactive. */
1506 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Active (1UL) /*!< Ctitrigout 7 is active. */
1507 
1508 /* Bit 6 : ETM Event Input 2 */
1509 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Pos (6UL) /*!< Position of ETMEVTIN2 field. */
1510 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Pos) /*!< Bit mask of ETMEVTIN2 field. */
1511 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Inactive (0UL) /*!< Ctitrigout 6 is inactive. */
1512 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Active (1UL) /*!< Ctitrigout 6 is active. */
1513 
1514 /* Bit 5 : ETM Event Input 1 */
1515 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Pos (5UL) /*!< Position of ETMEVTIN1 field. */
1516 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Pos) /*!< Bit mask of ETMEVTIN1 field. */
1517 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Inactive (0UL) /*!< Ctitrigout 5 is inactive. */
1518 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Active (1UL) /*!< Ctitrigout 5 is active. */
1519 
1520 /* Bit 4 : ETM Event Input 0 */
1521 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Pos (4UL) /*!< Position of ETMEVTIN0 field. */
1522 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Pos) /*!< Bit mask of ETMEVTIN0 field. */
1523 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Inactive (0UL) /*!< Ctitrigout 4 is inactive. */
1524 #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Active (1UL) /*!< Ctitrigout 4 is active. */
1525 
1526 /* Bit 3 : N/A */
1527 #define CTI_CTITRIGOUTSTATUS_UNUSED1_Pos (3UL) /*!< Position of UNUSED1 field. */
1528 #define CTI_CTITRIGOUTSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */
1529 #define CTI_CTITRIGOUTSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigout 3 is inactive. */
1530 #define CTI_CTITRIGOUTSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigout 3 is active. */
1531 
1532 /* Bit 2 : N/A */
1533 #define CTI_CTITRIGOUTSTATUS_UNUSED0_Pos (2UL) /*!< Position of UNUSED0 field. */
1534 #define CTI_CTITRIGOUTSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */
1535 #define CTI_CTITRIGOUTSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigout 2 is inactive. */
1536 #define CTI_CTITRIGOUTSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigout 2 is active. */
1537 
1538 /* Bit 1 : Processor Restart */
1539 #define CTI_CTITRIGOUTSTATUS_CPURESTART_Pos (1UL) /*!< Position of CPURESTART field. */
1540 #define CTI_CTITRIGOUTSTATUS_CPURESTART_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_CPURESTART_Pos) /*!< Bit mask of CPURESTART field. */
1541 #define CTI_CTITRIGOUTSTATUS_CPURESTART_Inactive (0UL) /*!< Ctitrigout 1 is inactive. */
1542 #define CTI_CTITRIGOUTSTATUS_CPURESTART_Active (1UL) /*!< Ctitrigout 1 is active. */
1543 
1544 /* Bit 0 : Processor debug request */
1545 #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos (0UL) /*!< Position of DEBUGREQ field. */
1546 #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos) /*!< Bit mask of DEBUGREQ field. */
1547 #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Inactive (0UL) /*!< Ctitrigout 0 is inactive. */
1548 #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Active (1UL) /*!< Ctitrigout 0 is active. */
1549 
1550 /* Register: CTI_CTICHINSTATUS */
1551 /* Description: CTI Channel In Status register */
1552 
1553 /* Bit 3 : Shows the status of the ctitrigin 3 input. */
1554 #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos (3UL) /*!< Position of CTICHINSTATUS_3 field. */
1555 #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos) /*!< Bit mask of CTICHINSTATUS_3 field. */
1556 #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Inactive (0UL) /*!< Ctichin 3 is inactive. */
1557 #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Active (1UL) /*!< Ctichin 3 is active. */
1558 
1559 /* Bit 2 : Shows the status of the ctitrigin 2 input. */
1560 #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos (2UL) /*!< Position of CTICHINSTATUS_2 field. */
1561 #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos) /*!< Bit mask of CTICHINSTATUS_2 field. */
1562 #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Inactive (0UL) /*!< Ctichin 2 is inactive. */
1563 #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Active (1UL) /*!< Ctichin 2 is active. */
1564 
1565 /* Bit 1 : Shows the status of the ctitrigin 1 input. */
1566 #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos (1UL) /*!< Position of CTICHINSTATUS_1 field. */
1567 #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos) /*!< Bit mask of CTICHINSTATUS_1 field. */
1568 #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Inactive (0UL) /*!< Ctichin 1 is inactive. */
1569 #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Active (1UL) /*!< Ctichin 1 is active. */
1570 
1571 /* Bit 0 : Shows the status of the ctitrigin 0 input. */
1572 #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos (0UL) /*!< Position of CTICHINSTATUS_0 field. */
1573 #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos) /*!< Bit mask of CTICHINSTATUS_0 field. */
1574 #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Inactive (0UL) /*!< Ctichin 0 is inactive. */
1575 #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Active (1UL) /*!< Ctichin 0 is active. */
1576 
1577 /* Register: CTI_CTIGATE */
1578 /* Description: Enable CTI Channel Gate register */
1579 
1580 /* Bit 3 : Enable ctichout3. */
1581 #define CTI_CTIGATE_CTIGATEEN_3_Pos (3UL) /*!< Position of CTIGATEEN_3 field. */
1582 #define CTI_CTIGATE_CTIGATEEN_3_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_3_Pos) /*!< Bit mask of CTIGATEEN_3 field. */
1583 #define CTI_CTIGATE_CTIGATEEN_3_Disabled (0UL) /*!< Disable ctichout channel 3 propagation. */
1584 #define CTI_CTIGATE_CTIGATEEN_3_Enabled (1UL) /*!< Enable ctichout channel 3 propagation. */
1585 
1586 /* Bit 2 : Enable ctichout2. */
1587 #define CTI_CTIGATE_CTIGATEEN_2_Pos (2UL) /*!< Position of CTIGATEEN_2 field. */
1588 #define CTI_CTIGATE_CTIGATEEN_2_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_2_Pos) /*!< Bit mask of CTIGATEEN_2 field. */
1589 #define CTI_CTIGATE_CTIGATEEN_2_Disabled (0UL) /*!< Disable ctichout channel 2 propagation. */
1590 #define CTI_CTIGATE_CTIGATEEN_2_Enabled (1UL) /*!< Enable ctichout channel 2 propagation. */
1591 
1592 /* Bit 1 : Enable ctichout1. */
1593 #define CTI_CTIGATE_CTIGATEEN_1_Pos (1UL) /*!< Position of CTIGATEEN_1 field. */
1594 #define CTI_CTIGATE_CTIGATEEN_1_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_1_Pos) /*!< Bit mask of CTIGATEEN_1 field. */
1595 #define CTI_CTIGATE_CTIGATEEN_1_Disabled (0UL) /*!< Disable ctichout channel 1 propagation. */
1596 #define CTI_CTIGATE_CTIGATEEN_1_Enabled (1UL) /*!< Enable ctichout channel 1 propagation. */
1597 
1598 /* Bit 0 : Enable ctichout0. */
1599 #define CTI_CTIGATE_CTIGATEEN_0_Pos (0UL) /*!< Position of CTIGATEEN_0 field. */
1600 #define CTI_CTIGATE_CTIGATEEN_0_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_0_Pos) /*!< Bit mask of CTIGATEEN_0 field. */
1601 #define CTI_CTIGATE_CTIGATEEN_0_Disabled (0UL) /*!< Disable ctichout channel 0 propagation. */
1602 #define CTI_CTIGATE_CTIGATEEN_0_Enabled (1UL) /*!< Enable ctichout channel 0 propagation. */
1603 
1604 /* Register: CTI_DEVARCH */
1605 /* Description: Device Architecture register */
1606 
1607 /* Bit 0 : Contains the CTI device architecture. */
1608 #define CTI_DEVARCH_Architecture_Pos (0UL) /*!< Position of Architecture field. */
1609 #define CTI_DEVARCH_Architecture_Msk (0x1UL << CTI_DEVARCH_Architecture_Pos) /*!< Bit mask of Architecture field. */
1610 
1611 /* Register: CTI_DEVID */
1612 /* Description: Device Configuration register */
1613 
1614 /* Bits 19..16 : Number of ECT channels available. */
1615 #define CTI_DEVID_NUMCH_Pos (16UL) /*!< Position of NUMCH field. */
1616 #define CTI_DEVID_NUMCH_Msk (0xFUL << CTI_DEVID_NUMCH_Pos) /*!< Bit mask of NUMCH field. */
1617 
1618 /* Bits 15..8 : Number of ECT triggers available. */
1619 #define CTI_DEVID_NUMTRIG_Pos (8UL) /*!< Position of NUMTRIG field. */
1620 #define CTI_DEVID_NUMTRIG_Msk (0xFFUL << CTI_DEVID_NUMTRIG_Pos) /*!< Bit mask of NUMTRIG field. */
1621 
1622 /* Bits 4..0 : Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl.
1623                     The default value of 0b00000 indicates that no multiplexing is present. */
1624 #define CTI_DEVID_EXTMUXNUM_Pos (0UL) /*!< Position of EXTMUXNUM field. */
1625 #define CTI_DEVID_EXTMUXNUM_Msk (0x1FUL << CTI_DEVID_EXTMUXNUM_Pos) /*!< Bit mask of EXTMUXNUM field. */
1626 
1627 /* Register: CTI_DEVTYPE */
1628 /* Description: Device Type Identifier register */
1629 
1630 /* Bits 7..4 : Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within
1631                     the major classification as specified in the MAJOR field. */
1632 #define CTI_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */
1633 #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */
1634 #define CTI_DEVTYPE_SUB_Crosstrigger (1UL) /*!< Indicates that this component is a sub-triggering component. */
1635 
1636 /* Bits 3..0 : Major classification of the type of the debug component as specified in the Arm Architecture Specification for this
1637                     debug and trace component. */
1638 #define CTI_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */
1639 #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */
1640 #define CTI_DEVTYPE_MAJOR_Controller (4UL) /*!< Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. */
1641 
1642 /* Register: CTI_PIDR4 */
1643 /* Description: Peripheral ID4 Register */
1644 
1645 /* Bits 7..4 : Always 0b0000. Indicates that the device only occupies 4KB of memory. */
1646 #define CTI_PIDR4_SIZE_Pos (4UL) /*!< Position of SIZE field. */
1647 #define CTI_PIDR4_SIZE_Msk (0xFUL << CTI_PIDR4_SIZE_Pos) /*!< Bit mask of SIZE field. */
1648 
1649 /* Bits 3..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
1650 #define CTI_PIDR4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */
1651 #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field. */
1652 #define CTI_PIDR4_DES_2_Code (4UL) /*!< JEDEC continuation code. */
1653 
1654 /* Register: CTI_PIDR0 */
1655 /* Description: Peripheral ID0 Register */
1656 
1657 /* Bits 7..0 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. */
1658 #define CTI_PIDR0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */
1659 #define CTI_PIDR0_PART_0_Msk (0xFFUL << CTI_PIDR0_PART_0_Pos) /*!< Bit mask of PART_0 field. */
1660 #define CTI_PIDR0_PART_0_PartnumberL (0x21UL) /*!< Indicates bits[7:0] of the part number of the component. */
1661 
1662 /* Register: CTI_PIDR1 */
1663 /* Description: Peripheral ID1 Register */
1664 
1665 /* Bits 7..4 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
1666 #define CTI_PIDR1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */
1667 #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field. */
1668 #define CTI_PIDR1_DES_0_Arm (11UL) /*!< Arm. Bits[3:0] of the JEDEC JEP106 Identity Code */
1669 
1670 /* Bits 3..0 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. */
1671 #define CTI_PIDR1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */
1672 #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field. */
1673 #define CTI_PIDR1_PART_1_PartnumberH (13UL) /*!< Indicates bits[11:8] of the part number of the component. */
1674 
1675 /* Register: CTI_PIDR2 */
1676 /* Description: Peripheral ID2 Register */
1677 
1678 /* Bits 7..4 : Peripheral revision */
1679 #define CTI_PIDR2_REVISION_Pos (4UL) /*!< Position of REVISION field. */
1680 #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field. */
1681 #define CTI_PIDR2_REVISION_Rev0p0 (0UL) /*!< This device is at r0p0 */
1682 
1683 /* Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used. */
1684 #define CTI_PIDR2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */
1685 #define CTI_PIDR2_JEDEC_Msk (0x1UL << CTI_PIDR2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */
1686 
1687 /* Bits 2..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
1688 #define CTI_PIDR2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */
1689 #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field. */
1690 #define CTI_PIDR2_DES_1_Arm (3UL) /*!< Arm. Bits[6:4] of the JEDEC JEP106 Identity Code */
1691 
1692 /* Register: CTI_PIDR3 */
1693 /* Description: Peripheral ID3 Register */
1694 
1695 /* Bits 7..4 : Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after
1696                     implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a
1697                     metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. */
1698 #define CTI_PIDR3_REVAND_Pos (4UL) /*!< Position of REVAND field. */
1699 #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field. */
1700 #define CTI_PIDR3_REVAND_NoErrata (0UL) /*!< Indicates that there are no errata fixes to this component. */
1701 
1702 /* Bits 3..0 : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases,
1703                     this field is 0b0000. Customers change this value when they make authorized modifications to this component. */
1704 #define CTI_PIDR3_CMOD_Pos (0UL) /*!< Position of CMOD field. */
1705 #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field. */
1706 #define CTI_PIDR3_CMOD_Unmodified (0UL) /*!< Indicates that the customer has not modified this component. */
1707 
1708 /* Register: CTI_CIDR0 */
1709 /* Description: Component ID0 Register */
1710 
1711 /* Bits 7..0 : Preamble[0]. Contains bits[7:0] of the component identification code. */
1712 #define CTI_CIDR0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */
1713 #define CTI_CIDR0_PRMBL_0_Msk (0xFFUL << CTI_CIDR0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */
1714 #define CTI_CIDR0_PRMBL_0_Value (0x0DUL) /*!< Bits[7:0] of the identification code. */
1715 
1716 /* Register: CTI_CIDR1 */
1717 /* Description: Component ID1 Register */
1718 
1719 /* Bits 7..4 : Class of the component, for example, whether the component is a ROM table or a generic CoreSight component.
1720                     Contains bits[15:12] of the component identification code */
1721 #define CTI_CIDR1_CLASS_Pos (4UL) /*!< Position of CLASS field. */
1722 #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field. */
1723 #define CTI_CIDR1_CLASS_Coresight (9UL) /*!< Indicates that the component is a CoreSight component. */
1724 
1725 /* Bits 3..0 : Preamble[1]. Contains bits[11:8] of the component identification code. */
1726 #define CTI_CIDR1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */
1727 #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */
1728 #define CTI_CIDR1_PRMBL_1_Value (0UL) /*!< Bits[11:8] of the identification code. */
1729 
1730 /* Register: CTI_CIDR2 */
1731 /* Description: Component ID2 Register */
1732 
1733 /* Bits 7..0 : Preamble[2]. Contains bits[23:16] of the component identification code. */
1734 #define CTI_CIDR2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */
1735 #define CTI_CIDR2_PRMBL_2_Msk (0xFFUL << CTI_CIDR2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */
1736 #define CTI_CIDR2_PRMBL_2_Value (0x05UL) /*!< Bits[23:16] of the identification code. */
1737 
1738 /* Register: CTI_CIDR3 */
1739 /* Description: Component ID3 Register */
1740 
1741 /* Bits 7..0 : Preamble[3]. Contains bits[31:24] of the component identification code. */
1742 #define CTI_CIDR3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */
1743 #define CTI_CIDR3_PRMBL_3_Msk (0xFFUL << CTI_CIDR3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */
1744 #define CTI_CIDR3_PRMBL_3_Value (0xB1UL) /*!< Bits[31:24] of the identification code. */
1745 
1746 
1747 /* Peripheral: CTRLAPPERI */
1748 /* Description: Control access port 0 */
1749 
1750 /* Register: CTRLAPPERI_MAILBOX_RXDATA */
1751 /* Description: Data sent from the debugger to the CPU. */
1752 
1753 /* Bits 31..0 : Data received from debugger */
1754 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */
1755 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */
1756 
1757 /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */
1758 /* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */
1759 
1760 /* Bit 0 : Status of data in register RXDATA */
1761 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */
1762 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */
1763 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL) /*!< No data pending in register RXDATA */
1764 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */
1765 
1766 /* Register: CTRLAPPERI_MAILBOX_TXDATA */
1767 /* Description: Data sent from the CPU to the debugger. */
1768 
1769 /* Bits 31..0 : Data sent to debugger */
1770 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */
1771 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */
1772 
1773 /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */
1774 /* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */
1775 
1776 /* Bit 0 : Status of data in register TXDATA */
1777 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */
1778 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */
1779 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL) /*!< No data pending in register TXDATA */
1780 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */
1781 
1782 /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */
1783 /* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */
1784 
1785 /* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */
1786 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
1787 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
1788 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */
1789 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */
1790 
1791 /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */
1792 /* Description: This register disables the ERASEPROTECT register and performs an  ERASEALL operation. */
1793 
1794 /* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */
1795 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
1796 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
1797 
1798 /* Register: CTRLAPPERI_APPROTECT_LOCK */
1799 /* Description: This register locks the APPROTECT.DISABLE register from being written to until next reset. */
1800 
1801 /* Bit 0 : Lock the APPROTECT.DISABLE register from being written to until next reset */
1802 #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
1803 #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
1804 #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register APPROTECT.DISABLE is writeable */
1805 #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register APPROTECT.DISABLE is read-only */
1806 
1807 /* Register: CTRLAPPERI_APPROTECT_DISABLE */
1808 /* Description: This register disables the APPROTECT register and enables debug access to non-secure mode. */
1809 
1810 /* Bits 31..0 : If the value of the KEY field is non-zero, and the KEY fields match on both the
1811         CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until
1812         the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. */
1813 #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
1814 #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
1815 
1816 /* Register: CTRLAPPERI_SECUREAPPROTECT_LOCK */
1817 /* Description: This register locks the SECUREAPPROTECT.DISABLE register from being written until next reset. */
1818 
1819 /* Bit 0 : Lock register SECUREAPPROTECT.DISABLE from being written until next reset */
1820 #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
1821 #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
1822 #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register SECUREAPPROTECT.DISABLE is writeable */
1823 #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register SECUREAPPROTECT.DISABLE is read-only */
1824 
1825 /* Register: CTRLAPPERI_SECUREAPPROTECT_DISABLE */
1826 /* Description: This register disables the SECUREAPPROTECT register and enables debug access to secure mode. */
1827 
1828 /* Bits 31..0 : If the value of the KEY field is non-zero, and the KEY fields match on both the
1829         CPU and debugger sides, disable SECUREAPPROTECT and enable debug access to secure mode until
1830         the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.SECUREAPPROTECT protection needs to be disabled. */
1831 #define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
1832 #define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
1833 
1834 /* Register: CTRLAPPERI_STATUS */
1835 /* Description: Status bits for CTRL-AP peripheral. */
1836 
1837 /* Bit 2 : Status bit for device debug interface mode */
1838 #define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (2UL) /*!< Position of DBGIFACEMODE field. */
1839 #define CTRLAPPERI_STATUS_DBGIFACEMODE_Msk (0x1UL << CTRLAPPERI_STATUS_DBGIFACEMODE_Pos) /*!< Bit mask of DBGIFACEMODE field. */
1840 #define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL) /*!< No debugger attached */
1841 #define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL) /*!< Debugger is attached and device is in debug interface mode */
1842 
1843 /* Bit 1 : Status bit for UICR part of secure access port protection at last reset. */
1844 #define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Pos (1UL) /*!< Position of UICRSECUREAPPROTECT field. */
1845 #define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Pos) /*!< Bit mask of UICRSECUREAPPROTECT field. */
1846 #define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Enabled (0UL) /*!< SECUREAPPROTECT was enabled in UICR */
1847 #define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Disabled (1UL) /*!< SECUREAPPROTECT was disabled in UICR */
1848 
1849 /* Bit 0 : Status bit for UICR part of access port protection at last reset. */
1850 #define CTRLAPPERI_STATUS_UICRAPPROTECT_Pos (0UL) /*!< Position of UICRAPPROTECT field. */
1851 #define CTRLAPPERI_STATUS_UICRAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_UICRAPPROTECT_Pos) /*!< Bit mask of UICRAPPROTECT field. */
1852 #define CTRLAPPERI_STATUS_UICRAPPROTECT_Enabled (0UL) /*!< APPROTECT was enabled in UICR */
1853 #define CTRLAPPERI_STATUS_UICRAPPROTECT_Disabled (1UL) /*!< APPROTECT wasdisabled in UICR */
1854 
1855 
1856 /* Peripheral: DCNF */
1857 /* Description: Domain configuration management 0 */
1858 
1859 /* Register: DCNF_CPUID */
1860 /* Description: CPU ID of this subsystem */
1861 
1862 /* Bits 7..0 : CPU ID */
1863 #define DCNF_CPUID_CPUID_Pos (0UL) /*!< Position of CPUID field. */
1864 #define DCNF_CPUID_CPUID_Msk (0xFFUL << DCNF_CPUID_CPUID_Pos) /*!< Bit mask of CPUID field. */
1865 
1866 /* Register: DCNF_EXTPERI_PROTECT */
1867 /* Description: Description cluster: Control access for master connected to AMLI master port EXTPERI[n] */
1868 
1869 /* Bit 0 : Control access to slave 0 of master EXTPERI[n] */
1870 #define DCNF_EXTPERI_PROTECT_SLAVE0_Pos (0UL) /*!< Position of SLAVE0 field. */
1871 #define DCNF_EXTPERI_PROTECT_SLAVE0_Msk (0x1UL << DCNF_EXTPERI_PROTECT_SLAVE0_Pos) /*!< Bit mask of SLAVE0 field. */
1872 #define DCNF_EXTPERI_PROTECT_SLAVE0_Allowed (0UL) /*!< Access to slave is allowed */
1873 #define DCNF_EXTPERI_PROTECT_SLAVE0_Blocked (1UL) /*!< Access to slave is blocked */
1874 
1875 /* Register: DCNF_EXTRAM_PROTECT */
1876 /* Description: Description cluster: Control access from master connected to AMLI master port EXTRAM[n] */
1877 
1878 /* Bit 7 : Control access to slave 7 of master EXTRAM[n] */
1879 #define DCNF_EXTRAM_PROTECT_SLAVE7_Pos (7UL) /*!< Position of SLAVE7 field. */
1880 #define DCNF_EXTRAM_PROTECT_SLAVE7_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE7_Pos) /*!< Bit mask of SLAVE7 field. */
1881 #define DCNF_EXTRAM_PROTECT_SLAVE7_Allowed (0UL) /*!< Access to slave is allowed */
1882 #define DCNF_EXTRAM_PROTECT_SLAVE7_Blocked (1UL) /*!< Access to slave is blocked */
1883 
1884 /* Bit 6 : Control access to slave 6 of master EXTRAM[n] */
1885 #define DCNF_EXTRAM_PROTECT_SLAVE6_Pos (6UL) /*!< Position of SLAVE6 field. */
1886 #define DCNF_EXTRAM_PROTECT_SLAVE6_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE6_Pos) /*!< Bit mask of SLAVE6 field. */
1887 #define DCNF_EXTRAM_PROTECT_SLAVE6_Allowed (0UL) /*!< Access to slave is allowed */
1888 #define DCNF_EXTRAM_PROTECT_SLAVE6_Blocked (1UL) /*!< Access to slave is blocked */
1889 
1890 /* Bit 5 : Control access to slave 5 of master EXTRAM[n] */
1891 #define DCNF_EXTRAM_PROTECT_SLAVE5_Pos (5UL) /*!< Position of SLAVE5 field. */
1892 #define DCNF_EXTRAM_PROTECT_SLAVE5_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE5_Pos) /*!< Bit mask of SLAVE5 field. */
1893 #define DCNF_EXTRAM_PROTECT_SLAVE5_Allowed (0UL) /*!< Access to slave is allowed */
1894 #define DCNF_EXTRAM_PROTECT_SLAVE5_Blocked (1UL) /*!< Access to slave is blocked */
1895 
1896 /* Bit 4 : Control access to slave 4 of master EXTRAM[n] */
1897 #define DCNF_EXTRAM_PROTECT_SLAVE4_Pos (4UL) /*!< Position of SLAVE4 field. */
1898 #define DCNF_EXTRAM_PROTECT_SLAVE4_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE4_Pos) /*!< Bit mask of SLAVE4 field. */
1899 #define DCNF_EXTRAM_PROTECT_SLAVE4_Allowed (0UL) /*!< Access to slave is allowed */
1900 #define DCNF_EXTRAM_PROTECT_SLAVE4_Blocked (1UL) /*!< Access to slave is blocked */
1901 
1902 /* Bit 3 : Control access to slave 3 of master EXTRAM[n] */
1903 #define DCNF_EXTRAM_PROTECT_SLAVE3_Pos (3UL) /*!< Position of SLAVE3 field. */
1904 #define DCNF_EXTRAM_PROTECT_SLAVE3_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE3_Pos) /*!< Bit mask of SLAVE3 field. */
1905 #define DCNF_EXTRAM_PROTECT_SLAVE3_Allowed (0UL) /*!< Access to slave is allowed */
1906 #define DCNF_EXTRAM_PROTECT_SLAVE3_Blocked (1UL) /*!< Access to slave is blocked */
1907 
1908 /* Bit 2 : Control access to slave 2 of master EXTRAM[n] */
1909 #define DCNF_EXTRAM_PROTECT_SLAVE2_Pos (2UL) /*!< Position of SLAVE2 field. */
1910 #define DCNF_EXTRAM_PROTECT_SLAVE2_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE2_Pos) /*!< Bit mask of SLAVE2 field. */
1911 #define DCNF_EXTRAM_PROTECT_SLAVE2_Allowed (0UL) /*!< Access to slave is allowed */
1912 #define DCNF_EXTRAM_PROTECT_SLAVE2_Blocked (1UL) /*!< Access to slave is blocked */
1913 
1914 /* Bit 1 : Control access to slave 1 of master EXTRAM[n] */
1915 #define DCNF_EXTRAM_PROTECT_SLAVE1_Pos (1UL) /*!< Position of SLAVE1 field. */
1916 #define DCNF_EXTRAM_PROTECT_SLAVE1_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE1_Pos) /*!< Bit mask of SLAVE1 field. */
1917 #define DCNF_EXTRAM_PROTECT_SLAVE1_Allowed (0UL) /*!< Access to slave is allowed */
1918 #define DCNF_EXTRAM_PROTECT_SLAVE1_Blocked (1UL) /*!< Access to slave is blocked */
1919 
1920 /* Bit 0 : Control access to slave 0 of master EXTRAM[n] */
1921 #define DCNF_EXTRAM_PROTECT_SLAVE0_Pos (0UL) /*!< Position of SLAVE0 field. */
1922 #define DCNF_EXTRAM_PROTECT_SLAVE0_Msk (0x1UL << DCNF_EXTRAM_PROTECT_SLAVE0_Pos) /*!< Bit mask of SLAVE0 field. */
1923 #define DCNF_EXTRAM_PROTECT_SLAVE0_Allowed (0UL) /*!< Access to slave is allowed */
1924 #define DCNF_EXTRAM_PROTECT_SLAVE0_Blocked (1UL) /*!< Access to slave is blocked */
1925 
1926 /* Register: DCNF_EXTCODE_PROTECT */
1927 /* Description: Description cluster: Control access from master connected to AMLI master port EXTCODE[n] */
1928 
1929 /* Bit 0 : Control access to slave 0 of master EXTCODE[n] */
1930 #define DCNF_EXTCODE_PROTECT_SLAVE0_Pos (0UL) /*!< Position of SLAVE0 field. */
1931 #define DCNF_EXTCODE_PROTECT_SLAVE0_Msk (0x1UL << DCNF_EXTCODE_PROTECT_SLAVE0_Pos) /*!< Bit mask of SLAVE0 field. */
1932 #define DCNF_EXTCODE_PROTECT_SLAVE0_Allowed (0UL) /*!< Access to slave is allowed */
1933 #define DCNF_EXTCODE_PROTECT_SLAVE0_Blocked (1UL) /*!< Access to slave is blocked */
1934 
1935 
1936 /* Peripheral: DPPIC */
1937 /* Description: Distributed programmable peripheral interconnect controller 0 */
1938 
1939 /* Register: DPPIC_TASKS_CHG_EN */
1940 /* Description: Description cluster: Enable channel group n */
1941 
1942 /* Bit 0 : Enable channel group n */
1943 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
1944 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
1945 #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
1946 
1947 /* Register: DPPIC_TASKS_CHG_DIS */
1948 /* Description: Description cluster: Disable channel group n */
1949 
1950 /* Bit 0 : Disable channel group n */
1951 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
1952 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
1953 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
1954 
1955 /* Register: DPPIC_SUBSCRIBE_CHG_EN */
1956 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */
1957 
1958 /* Bit 31 :   */
1959 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */
1960 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
1961 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */
1962 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */
1963 
1964 /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */
1965 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1966 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1967 
1968 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */
1969 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */
1970 
1971 /* Bit 31 :   */
1972 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */
1973 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */
1974 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */
1975 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */
1976 
1977 /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */
1978 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1979 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1980 
1981 /* Register: DPPIC_CHEN */
1982 /* Description: Channel enable register */
1983 
1984 /* Bit 31 : Enable or disable channel 31 */
1985 #define DPPIC_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
1986 #define DPPIC_CHEN_CH31_Msk (0x1UL << DPPIC_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
1987 #define DPPIC_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
1988 #define DPPIC_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
1989 
1990 /* Bit 30 : Enable or disable channel 30 */
1991 #define DPPIC_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
1992 #define DPPIC_CHEN_CH30_Msk (0x1UL << DPPIC_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
1993 #define DPPIC_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
1994 #define DPPIC_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
1995 
1996 /* Bit 29 : Enable or disable channel 29 */
1997 #define DPPIC_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
1998 #define DPPIC_CHEN_CH29_Msk (0x1UL << DPPIC_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
1999 #define DPPIC_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
2000 #define DPPIC_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
2001 
2002 /* Bit 28 : Enable or disable channel 28 */
2003 #define DPPIC_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
2004 #define DPPIC_CHEN_CH28_Msk (0x1UL << DPPIC_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
2005 #define DPPIC_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
2006 #define DPPIC_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
2007 
2008 /* Bit 27 : Enable or disable channel 27 */
2009 #define DPPIC_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
2010 #define DPPIC_CHEN_CH27_Msk (0x1UL << DPPIC_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
2011 #define DPPIC_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
2012 #define DPPIC_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
2013 
2014 /* Bit 26 : Enable or disable channel 26 */
2015 #define DPPIC_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
2016 #define DPPIC_CHEN_CH26_Msk (0x1UL << DPPIC_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
2017 #define DPPIC_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
2018 #define DPPIC_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
2019 
2020 /* Bit 25 : Enable or disable channel 25 */
2021 #define DPPIC_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
2022 #define DPPIC_CHEN_CH25_Msk (0x1UL << DPPIC_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
2023 #define DPPIC_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
2024 #define DPPIC_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
2025 
2026 /* Bit 24 : Enable or disable channel 24 */
2027 #define DPPIC_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
2028 #define DPPIC_CHEN_CH24_Msk (0x1UL << DPPIC_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
2029 #define DPPIC_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
2030 #define DPPIC_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
2031 
2032 /* Bit 23 : Enable or disable channel 23 */
2033 #define DPPIC_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
2034 #define DPPIC_CHEN_CH23_Msk (0x1UL << DPPIC_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
2035 #define DPPIC_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
2036 #define DPPIC_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
2037 
2038 /* Bit 22 : Enable or disable channel 22 */
2039 #define DPPIC_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
2040 #define DPPIC_CHEN_CH22_Msk (0x1UL << DPPIC_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
2041 #define DPPIC_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
2042 #define DPPIC_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
2043 
2044 /* Bit 21 : Enable or disable channel 21 */
2045 #define DPPIC_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
2046 #define DPPIC_CHEN_CH21_Msk (0x1UL << DPPIC_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
2047 #define DPPIC_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
2048 #define DPPIC_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
2049 
2050 /* Bit 20 : Enable or disable channel 20 */
2051 #define DPPIC_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
2052 #define DPPIC_CHEN_CH20_Msk (0x1UL << DPPIC_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
2053 #define DPPIC_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
2054 #define DPPIC_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
2055 
2056 /* Bit 19 : Enable or disable channel 19 */
2057 #define DPPIC_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
2058 #define DPPIC_CHEN_CH19_Msk (0x1UL << DPPIC_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
2059 #define DPPIC_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
2060 #define DPPIC_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
2061 
2062 /* Bit 18 : Enable or disable channel 18 */
2063 #define DPPIC_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
2064 #define DPPIC_CHEN_CH18_Msk (0x1UL << DPPIC_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
2065 #define DPPIC_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
2066 #define DPPIC_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
2067 
2068 /* Bit 17 : Enable or disable channel 17 */
2069 #define DPPIC_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
2070 #define DPPIC_CHEN_CH17_Msk (0x1UL << DPPIC_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
2071 #define DPPIC_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
2072 #define DPPIC_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
2073 
2074 /* Bit 16 : Enable or disable channel 16 */
2075 #define DPPIC_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
2076 #define DPPIC_CHEN_CH16_Msk (0x1UL << DPPIC_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
2077 #define DPPIC_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
2078 #define DPPIC_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
2079 
2080 /* Bit 15 : Enable or disable channel 15 */
2081 #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
2082 #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
2083 #define DPPIC_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
2084 #define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
2085 
2086 /* Bit 14 : Enable or disable channel 14 */
2087 #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
2088 #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
2089 #define DPPIC_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
2090 #define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
2091 
2092 /* Bit 13 : Enable or disable channel 13 */
2093 #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
2094 #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
2095 #define DPPIC_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
2096 #define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
2097 
2098 /* Bit 12 : Enable or disable channel 12 */
2099 #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
2100 #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
2101 #define DPPIC_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
2102 #define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
2103 
2104 /* Bit 11 : Enable or disable channel 11 */
2105 #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
2106 #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
2107 #define DPPIC_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
2108 #define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
2109 
2110 /* Bit 10 : Enable or disable channel 10 */
2111 #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
2112 #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
2113 #define DPPIC_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
2114 #define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
2115 
2116 /* Bit 9 : Enable or disable channel 9 */
2117 #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
2118 #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
2119 #define DPPIC_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
2120 #define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
2121 
2122 /* Bit 8 : Enable or disable channel 8 */
2123 #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
2124 #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
2125 #define DPPIC_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
2126 #define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
2127 
2128 /* Bit 7 : Enable or disable channel 7 */
2129 #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
2130 #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
2131 #define DPPIC_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
2132 #define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
2133 
2134 /* Bit 6 : Enable or disable channel 6 */
2135 #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
2136 #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
2137 #define DPPIC_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
2138 #define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
2139 
2140 /* Bit 5 : Enable or disable channel 5 */
2141 #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
2142 #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
2143 #define DPPIC_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
2144 #define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
2145 
2146 /* Bit 4 : Enable or disable channel 4 */
2147 #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
2148 #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
2149 #define DPPIC_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
2150 #define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
2151 
2152 /* Bit 3 : Enable or disable channel 3 */
2153 #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
2154 #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
2155 #define DPPIC_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
2156 #define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
2157 
2158 /* Bit 2 : Enable or disable channel 2 */
2159 #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
2160 #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
2161 #define DPPIC_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
2162 #define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
2163 
2164 /* Bit 1 : Enable or disable channel 1 */
2165 #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
2166 #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
2167 #define DPPIC_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
2168 #define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
2169 
2170 /* Bit 0 : Enable or disable channel 0 */
2171 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
2172 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
2173 #define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
2174 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
2175 
2176 /* Register: DPPIC_CHENSET */
2177 /* Description: Channel enable set register */
2178 
2179 /* Bit 31 : Channel 31 enable set register. Writing 0 has no effect. */
2180 #define DPPIC_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
2181 #define DPPIC_CHENSET_CH31_Msk (0x1UL << DPPIC_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
2182 #define DPPIC_CHENSET_CH31_Disabled (0UL) /*!< Read: Channel disabled */
2183 #define DPPIC_CHENSET_CH31_Enabled (1UL) /*!< Read: Channel enabled */
2184 #define DPPIC_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
2185 
2186 /* Bit 30 : Channel 30 enable set register. Writing 0 has no effect. */
2187 #define DPPIC_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
2188 #define DPPIC_CHENSET_CH30_Msk (0x1UL << DPPIC_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
2189 #define DPPIC_CHENSET_CH30_Disabled (0UL) /*!< Read: Channel disabled */
2190 #define DPPIC_CHENSET_CH30_Enabled (1UL) /*!< Read: Channel enabled */
2191 #define DPPIC_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
2192 
2193 /* Bit 29 : Channel 29 enable set register. Writing 0 has no effect. */
2194 #define DPPIC_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
2195 #define DPPIC_CHENSET_CH29_Msk (0x1UL << DPPIC_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
2196 #define DPPIC_CHENSET_CH29_Disabled (0UL) /*!< Read: Channel disabled */
2197 #define DPPIC_CHENSET_CH29_Enabled (1UL) /*!< Read: Channel enabled */
2198 #define DPPIC_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
2199 
2200 /* Bit 28 : Channel 28 enable set register. Writing 0 has no effect. */
2201 #define DPPIC_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
2202 #define DPPIC_CHENSET_CH28_Msk (0x1UL << DPPIC_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
2203 #define DPPIC_CHENSET_CH28_Disabled (0UL) /*!< Read: Channel disabled */
2204 #define DPPIC_CHENSET_CH28_Enabled (1UL) /*!< Read: Channel enabled */
2205 #define DPPIC_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
2206 
2207 /* Bit 27 : Channel 27 enable set register. Writing 0 has no effect. */
2208 #define DPPIC_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
2209 #define DPPIC_CHENSET_CH27_Msk (0x1UL << DPPIC_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
2210 #define DPPIC_CHENSET_CH27_Disabled (0UL) /*!< Read: Channel disabled */
2211 #define DPPIC_CHENSET_CH27_Enabled (1UL) /*!< Read: Channel enabled */
2212 #define DPPIC_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
2213 
2214 /* Bit 26 : Channel 26 enable set register. Writing 0 has no effect. */
2215 #define DPPIC_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
2216 #define DPPIC_CHENSET_CH26_Msk (0x1UL << DPPIC_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
2217 #define DPPIC_CHENSET_CH26_Disabled (0UL) /*!< Read: Channel disabled */
2218 #define DPPIC_CHENSET_CH26_Enabled (1UL) /*!< Read: Channel enabled */
2219 #define DPPIC_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
2220 
2221 /* Bit 25 : Channel 25 enable set register. Writing 0 has no effect. */
2222 #define DPPIC_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
2223 #define DPPIC_CHENSET_CH25_Msk (0x1UL << DPPIC_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
2224 #define DPPIC_CHENSET_CH25_Disabled (0UL) /*!< Read: Channel disabled */
2225 #define DPPIC_CHENSET_CH25_Enabled (1UL) /*!< Read: Channel enabled */
2226 #define DPPIC_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
2227 
2228 /* Bit 24 : Channel 24 enable set register. Writing 0 has no effect. */
2229 #define DPPIC_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
2230 #define DPPIC_CHENSET_CH24_Msk (0x1UL << DPPIC_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
2231 #define DPPIC_CHENSET_CH24_Disabled (0UL) /*!< Read: Channel disabled */
2232 #define DPPIC_CHENSET_CH24_Enabled (1UL) /*!< Read: Channel enabled */
2233 #define DPPIC_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
2234 
2235 /* Bit 23 : Channel 23 enable set register. Writing 0 has no effect. */
2236 #define DPPIC_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
2237 #define DPPIC_CHENSET_CH23_Msk (0x1UL << DPPIC_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
2238 #define DPPIC_CHENSET_CH23_Disabled (0UL) /*!< Read: Channel disabled */
2239 #define DPPIC_CHENSET_CH23_Enabled (1UL) /*!< Read: Channel enabled */
2240 #define DPPIC_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
2241 
2242 /* Bit 22 : Channel 22 enable set register. Writing 0 has no effect. */
2243 #define DPPIC_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
2244 #define DPPIC_CHENSET_CH22_Msk (0x1UL << DPPIC_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
2245 #define DPPIC_CHENSET_CH22_Disabled (0UL) /*!< Read: Channel disabled */
2246 #define DPPIC_CHENSET_CH22_Enabled (1UL) /*!< Read: Channel enabled */
2247 #define DPPIC_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
2248 
2249 /* Bit 21 : Channel 21 enable set register. Writing 0 has no effect. */
2250 #define DPPIC_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
2251 #define DPPIC_CHENSET_CH21_Msk (0x1UL << DPPIC_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
2252 #define DPPIC_CHENSET_CH21_Disabled (0UL) /*!< Read: Channel disabled */
2253 #define DPPIC_CHENSET_CH21_Enabled (1UL) /*!< Read: Channel enabled */
2254 #define DPPIC_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
2255 
2256 /* Bit 20 : Channel 20 enable set register. Writing 0 has no effect. */
2257 #define DPPIC_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
2258 #define DPPIC_CHENSET_CH20_Msk (0x1UL << DPPIC_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
2259 #define DPPIC_CHENSET_CH20_Disabled (0UL) /*!< Read: Channel disabled */
2260 #define DPPIC_CHENSET_CH20_Enabled (1UL) /*!< Read: Channel enabled */
2261 #define DPPIC_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
2262 
2263 /* Bit 19 : Channel 19 enable set register. Writing 0 has no effect. */
2264 #define DPPIC_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
2265 #define DPPIC_CHENSET_CH19_Msk (0x1UL << DPPIC_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
2266 #define DPPIC_CHENSET_CH19_Disabled (0UL) /*!< Read: Channel disabled */
2267 #define DPPIC_CHENSET_CH19_Enabled (1UL) /*!< Read: Channel enabled */
2268 #define DPPIC_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
2269 
2270 /* Bit 18 : Channel 18 enable set register. Writing 0 has no effect. */
2271 #define DPPIC_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
2272 #define DPPIC_CHENSET_CH18_Msk (0x1UL << DPPIC_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
2273 #define DPPIC_CHENSET_CH18_Disabled (0UL) /*!< Read: Channel disabled */
2274 #define DPPIC_CHENSET_CH18_Enabled (1UL) /*!< Read: Channel enabled */
2275 #define DPPIC_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
2276 
2277 /* Bit 17 : Channel 17 enable set register. Writing 0 has no effect. */
2278 #define DPPIC_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
2279 #define DPPIC_CHENSET_CH17_Msk (0x1UL << DPPIC_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
2280 #define DPPIC_CHENSET_CH17_Disabled (0UL) /*!< Read: Channel disabled */
2281 #define DPPIC_CHENSET_CH17_Enabled (1UL) /*!< Read: Channel enabled */
2282 #define DPPIC_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
2283 
2284 /* Bit 16 : Channel 16 enable set register. Writing 0 has no effect. */
2285 #define DPPIC_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
2286 #define DPPIC_CHENSET_CH16_Msk (0x1UL << DPPIC_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
2287 #define DPPIC_CHENSET_CH16_Disabled (0UL) /*!< Read: Channel disabled */
2288 #define DPPIC_CHENSET_CH16_Enabled (1UL) /*!< Read: Channel enabled */
2289 #define DPPIC_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
2290 
2291 /* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */
2292 #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
2293 #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
2294 #define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: Channel disabled */
2295 #define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: Channel enabled */
2296 #define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
2297 
2298 /* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */
2299 #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
2300 #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
2301 #define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: Channel disabled */
2302 #define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: Channel enabled */
2303 #define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
2304 
2305 /* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */
2306 #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
2307 #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
2308 #define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: Channel disabled */
2309 #define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: Channel enabled */
2310 #define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
2311 
2312 /* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */
2313 #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
2314 #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
2315 #define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: Channel disabled */
2316 #define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: Channel enabled */
2317 #define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
2318 
2319 /* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */
2320 #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
2321 #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
2322 #define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: Channel disabled */
2323 #define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: Channel enabled */
2324 #define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
2325 
2326 /* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */
2327 #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
2328 #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
2329 #define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: Channel disabled */
2330 #define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: Channel enabled */
2331 #define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
2332 
2333 /* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */
2334 #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
2335 #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
2336 #define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: Channel disabled */
2337 #define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: Channel enabled */
2338 #define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
2339 
2340 /* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */
2341 #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
2342 #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
2343 #define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: Channel disabled */
2344 #define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: Channel enabled */
2345 #define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
2346 
2347 /* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */
2348 #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
2349 #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
2350 #define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: Channel disabled */
2351 #define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: Channel enabled */
2352 #define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
2353 
2354 /* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */
2355 #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
2356 #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
2357 #define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: Channel disabled */
2358 #define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: Channel enabled */
2359 #define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
2360 
2361 /* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */
2362 #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
2363 #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
2364 #define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: Channel disabled */
2365 #define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: Channel enabled */
2366 #define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
2367 
2368 /* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */
2369 #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
2370 #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
2371 #define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: Channel disabled */
2372 #define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: Channel enabled */
2373 #define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
2374 
2375 /* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */
2376 #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
2377 #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
2378 #define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: Channel disabled */
2379 #define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: Channel enabled */
2380 #define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
2381 
2382 /* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */
2383 #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
2384 #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
2385 #define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: Channel disabled */
2386 #define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: Channel enabled */
2387 #define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
2388 
2389 /* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */
2390 #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
2391 #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
2392 #define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: Channel disabled */
2393 #define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: Channel enabled */
2394 #define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
2395 
2396 /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
2397 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
2398 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
2399 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */
2400 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */
2401 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
2402 
2403 /* Register: DPPIC_CHENCLR */
2404 /* Description: Channel enable clear register */
2405 
2406 /* Bit 31 : Channel 31 enable clear register.  Writing 0 has no effect. */
2407 #define DPPIC_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
2408 #define DPPIC_CHENCLR_CH31_Msk (0x1UL << DPPIC_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
2409 #define DPPIC_CHENCLR_CH31_Disabled (0UL) /*!< Read: Channel disabled */
2410 #define DPPIC_CHENCLR_CH31_Enabled (1UL) /*!< Read: Channel enabled */
2411 #define DPPIC_CHENCLR_CH31_Clear (1UL) /*!< Write: Disable channel */
2412 
2413 /* Bit 30 : Channel 30 enable clear register.  Writing 0 has no effect. */
2414 #define DPPIC_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
2415 #define DPPIC_CHENCLR_CH30_Msk (0x1UL << DPPIC_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
2416 #define DPPIC_CHENCLR_CH30_Disabled (0UL) /*!< Read: Channel disabled */
2417 #define DPPIC_CHENCLR_CH30_Enabled (1UL) /*!< Read: Channel enabled */
2418 #define DPPIC_CHENCLR_CH30_Clear (1UL) /*!< Write: Disable channel */
2419 
2420 /* Bit 29 : Channel 29 enable clear register.  Writing 0 has no effect. */
2421 #define DPPIC_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
2422 #define DPPIC_CHENCLR_CH29_Msk (0x1UL << DPPIC_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
2423 #define DPPIC_CHENCLR_CH29_Disabled (0UL) /*!< Read: Channel disabled */
2424 #define DPPIC_CHENCLR_CH29_Enabled (1UL) /*!< Read: Channel enabled */
2425 #define DPPIC_CHENCLR_CH29_Clear (1UL) /*!< Write: Disable channel */
2426 
2427 /* Bit 28 : Channel 28 enable clear register.  Writing 0 has no effect. */
2428 #define DPPIC_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
2429 #define DPPIC_CHENCLR_CH28_Msk (0x1UL << DPPIC_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
2430 #define DPPIC_CHENCLR_CH28_Disabled (0UL) /*!< Read: Channel disabled */
2431 #define DPPIC_CHENCLR_CH28_Enabled (1UL) /*!< Read: Channel enabled */
2432 #define DPPIC_CHENCLR_CH28_Clear (1UL) /*!< Write: Disable channel */
2433 
2434 /* Bit 27 : Channel 27 enable clear register.  Writing 0 has no effect. */
2435 #define DPPIC_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
2436 #define DPPIC_CHENCLR_CH27_Msk (0x1UL << DPPIC_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
2437 #define DPPIC_CHENCLR_CH27_Disabled (0UL) /*!< Read: Channel disabled */
2438 #define DPPIC_CHENCLR_CH27_Enabled (1UL) /*!< Read: Channel enabled */
2439 #define DPPIC_CHENCLR_CH27_Clear (1UL) /*!< Write: Disable channel */
2440 
2441 /* Bit 26 : Channel 26 enable clear register.  Writing 0 has no effect. */
2442 #define DPPIC_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
2443 #define DPPIC_CHENCLR_CH26_Msk (0x1UL << DPPIC_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
2444 #define DPPIC_CHENCLR_CH26_Disabled (0UL) /*!< Read: Channel disabled */
2445 #define DPPIC_CHENCLR_CH26_Enabled (1UL) /*!< Read: Channel enabled */
2446 #define DPPIC_CHENCLR_CH26_Clear (1UL) /*!< Write: Disable channel */
2447 
2448 /* Bit 25 : Channel 25 enable clear register.  Writing 0 has no effect. */
2449 #define DPPIC_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
2450 #define DPPIC_CHENCLR_CH25_Msk (0x1UL << DPPIC_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
2451 #define DPPIC_CHENCLR_CH25_Disabled (0UL) /*!< Read: Channel disabled */
2452 #define DPPIC_CHENCLR_CH25_Enabled (1UL) /*!< Read: Channel enabled */
2453 #define DPPIC_CHENCLR_CH25_Clear (1UL) /*!< Write: Disable channel */
2454 
2455 /* Bit 24 : Channel 24 enable clear register.  Writing 0 has no effect. */
2456 #define DPPIC_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
2457 #define DPPIC_CHENCLR_CH24_Msk (0x1UL << DPPIC_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
2458 #define DPPIC_CHENCLR_CH24_Disabled (0UL) /*!< Read: Channel disabled */
2459 #define DPPIC_CHENCLR_CH24_Enabled (1UL) /*!< Read: Channel enabled */
2460 #define DPPIC_CHENCLR_CH24_Clear (1UL) /*!< Write: Disable channel */
2461 
2462 /* Bit 23 : Channel 23 enable clear register.  Writing 0 has no effect. */
2463 #define DPPIC_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
2464 #define DPPIC_CHENCLR_CH23_Msk (0x1UL << DPPIC_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
2465 #define DPPIC_CHENCLR_CH23_Disabled (0UL) /*!< Read: Channel disabled */
2466 #define DPPIC_CHENCLR_CH23_Enabled (1UL) /*!< Read: Channel enabled */
2467 #define DPPIC_CHENCLR_CH23_Clear (1UL) /*!< Write: Disable channel */
2468 
2469 /* Bit 22 : Channel 22 enable clear register.  Writing 0 has no effect. */
2470 #define DPPIC_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
2471 #define DPPIC_CHENCLR_CH22_Msk (0x1UL << DPPIC_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
2472 #define DPPIC_CHENCLR_CH22_Disabled (0UL) /*!< Read: Channel disabled */
2473 #define DPPIC_CHENCLR_CH22_Enabled (1UL) /*!< Read: Channel enabled */
2474 #define DPPIC_CHENCLR_CH22_Clear (1UL) /*!< Write: Disable channel */
2475 
2476 /* Bit 21 : Channel 21 enable clear register.  Writing 0 has no effect. */
2477 #define DPPIC_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
2478 #define DPPIC_CHENCLR_CH21_Msk (0x1UL << DPPIC_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
2479 #define DPPIC_CHENCLR_CH21_Disabled (0UL) /*!< Read: Channel disabled */
2480 #define DPPIC_CHENCLR_CH21_Enabled (1UL) /*!< Read: Channel enabled */
2481 #define DPPIC_CHENCLR_CH21_Clear (1UL) /*!< Write: Disable channel */
2482 
2483 /* Bit 20 : Channel 20 enable clear register.  Writing 0 has no effect. */
2484 #define DPPIC_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
2485 #define DPPIC_CHENCLR_CH20_Msk (0x1UL << DPPIC_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
2486 #define DPPIC_CHENCLR_CH20_Disabled (0UL) /*!< Read: Channel disabled */
2487 #define DPPIC_CHENCLR_CH20_Enabled (1UL) /*!< Read: Channel enabled */
2488 #define DPPIC_CHENCLR_CH20_Clear (1UL) /*!< Write: Disable channel */
2489 
2490 /* Bit 19 : Channel 19 enable clear register.  Writing 0 has no effect. */
2491 #define DPPIC_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
2492 #define DPPIC_CHENCLR_CH19_Msk (0x1UL << DPPIC_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
2493 #define DPPIC_CHENCLR_CH19_Disabled (0UL) /*!< Read: Channel disabled */
2494 #define DPPIC_CHENCLR_CH19_Enabled (1UL) /*!< Read: Channel enabled */
2495 #define DPPIC_CHENCLR_CH19_Clear (1UL) /*!< Write: Disable channel */
2496 
2497 /* Bit 18 : Channel 18 enable clear register.  Writing 0 has no effect. */
2498 #define DPPIC_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
2499 #define DPPIC_CHENCLR_CH18_Msk (0x1UL << DPPIC_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
2500 #define DPPIC_CHENCLR_CH18_Disabled (0UL) /*!< Read: Channel disabled */
2501 #define DPPIC_CHENCLR_CH18_Enabled (1UL) /*!< Read: Channel enabled */
2502 #define DPPIC_CHENCLR_CH18_Clear (1UL) /*!< Write: Disable channel */
2503 
2504 /* Bit 17 : Channel 17 enable clear register.  Writing 0 has no effect. */
2505 #define DPPIC_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
2506 #define DPPIC_CHENCLR_CH17_Msk (0x1UL << DPPIC_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
2507 #define DPPIC_CHENCLR_CH17_Disabled (0UL) /*!< Read: Channel disabled */
2508 #define DPPIC_CHENCLR_CH17_Enabled (1UL) /*!< Read: Channel enabled */
2509 #define DPPIC_CHENCLR_CH17_Clear (1UL) /*!< Write: Disable channel */
2510 
2511 /* Bit 16 : Channel 16 enable clear register.  Writing 0 has no effect. */
2512 #define DPPIC_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
2513 #define DPPIC_CHENCLR_CH16_Msk (0x1UL << DPPIC_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
2514 #define DPPIC_CHENCLR_CH16_Disabled (0UL) /*!< Read: Channel disabled */
2515 #define DPPIC_CHENCLR_CH16_Enabled (1UL) /*!< Read: Channel enabled */
2516 #define DPPIC_CHENCLR_CH16_Clear (1UL) /*!< Write: Disable channel */
2517 
2518 /* Bit 15 : Channel 15 enable clear register.  Writing 0 has no effect. */
2519 #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
2520 #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
2521 #define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: Channel disabled */
2522 #define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: Channel enabled */
2523 #define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: Disable channel */
2524 
2525 /* Bit 14 : Channel 14 enable clear register.  Writing 0 has no effect. */
2526 #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
2527 #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
2528 #define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: Channel disabled */
2529 #define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: Channel enabled */
2530 #define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: Disable channel */
2531 
2532 /* Bit 13 : Channel 13 enable clear register.  Writing 0 has no effect. */
2533 #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
2534 #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
2535 #define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: Channel disabled */
2536 #define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: Channel enabled */
2537 #define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: Disable channel */
2538 
2539 /* Bit 12 : Channel 12 enable clear register.  Writing 0 has no effect. */
2540 #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
2541 #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
2542 #define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: Channel disabled */
2543 #define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: Channel enabled */
2544 #define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: Disable channel */
2545 
2546 /* Bit 11 : Channel 11 enable clear register.  Writing 0 has no effect. */
2547 #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
2548 #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
2549 #define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: Channel disabled */
2550 #define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: Channel enabled */
2551 #define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: Disable channel */
2552 
2553 /* Bit 10 : Channel 10 enable clear register.  Writing 0 has no effect. */
2554 #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
2555 #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
2556 #define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: Channel disabled */
2557 #define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: Channel enabled */
2558 #define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: Disable channel */
2559 
2560 /* Bit 9 : Channel 9 enable clear register.  Writing 0 has no effect. */
2561 #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
2562 #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
2563 #define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: Channel disabled */
2564 #define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: Channel enabled */
2565 #define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: Disable channel */
2566 
2567 /* Bit 8 : Channel 8 enable clear register.  Writing 0 has no effect. */
2568 #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
2569 #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
2570 #define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: Channel disabled */
2571 #define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: Channel enabled */
2572 #define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: Disable channel */
2573 
2574 /* Bit 7 : Channel 7 enable clear register.  Writing 0 has no effect. */
2575 #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
2576 #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
2577 #define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: Channel disabled */
2578 #define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: Channel enabled */
2579 #define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: Disable channel */
2580 
2581 /* Bit 6 : Channel 6 enable clear register.  Writing 0 has no effect. */
2582 #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
2583 #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
2584 #define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: Channel disabled */
2585 #define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: Channel enabled */
2586 #define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: Disable channel */
2587 
2588 /* Bit 5 : Channel 5 enable clear register.  Writing 0 has no effect. */
2589 #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
2590 #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
2591 #define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: Channel disabled */
2592 #define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: Channel enabled */
2593 #define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: Disable channel */
2594 
2595 /* Bit 4 : Channel 4 enable clear register.  Writing 0 has no effect. */
2596 #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
2597 #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
2598 #define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: Channel disabled */
2599 #define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: Channel enabled */
2600 #define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: Disable channel */
2601 
2602 /* Bit 3 : Channel 3 enable clear register.  Writing 0 has no effect. */
2603 #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
2604 #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
2605 #define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: Channel disabled */
2606 #define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: Channel enabled */
2607 #define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: Disable channel */
2608 
2609 /* Bit 2 : Channel 2 enable clear register.  Writing 0 has no effect. */
2610 #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
2611 #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
2612 #define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: Channel disabled */
2613 #define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: Channel enabled */
2614 #define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: Disable channel */
2615 
2616 /* Bit 1 : Channel 1 enable clear register.  Writing 0 has no effect. */
2617 #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
2618 #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
2619 #define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: Channel disabled */
2620 #define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: Channel enabled */
2621 #define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: Disable channel */
2622 
2623 /* Bit 0 : Channel 0 enable clear register.  Writing 0 has no effect. */
2624 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
2625 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
2626 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */
2627 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */
2628 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */
2629 
2630 /* Register: DPPIC_CHG */
2631 /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */
2632 
2633 /* Bit 31 : Include or exclude channel 31 */
2634 #define DPPIC_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
2635 #define DPPIC_CHG_CH31_Msk (0x1UL << DPPIC_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
2636 #define DPPIC_CHG_CH31_Excluded (0UL) /*!< Exclude */
2637 #define DPPIC_CHG_CH31_Included (1UL) /*!< Include */
2638 
2639 /* Bit 30 : Include or exclude channel 30 */
2640 #define DPPIC_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
2641 #define DPPIC_CHG_CH30_Msk (0x1UL << DPPIC_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
2642 #define DPPIC_CHG_CH30_Excluded (0UL) /*!< Exclude */
2643 #define DPPIC_CHG_CH30_Included (1UL) /*!< Include */
2644 
2645 /* Bit 29 : Include or exclude channel 29 */
2646 #define DPPIC_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
2647 #define DPPIC_CHG_CH29_Msk (0x1UL << DPPIC_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
2648 #define DPPIC_CHG_CH29_Excluded (0UL) /*!< Exclude */
2649 #define DPPIC_CHG_CH29_Included (1UL) /*!< Include */
2650 
2651 /* Bit 28 : Include or exclude channel 28 */
2652 #define DPPIC_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
2653 #define DPPIC_CHG_CH28_Msk (0x1UL << DPPIC_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
2654 #define DPPIC_CHG_CH28_Excluded (0UL) /*!< Exclude */
2655 #define DPPIC_CHG_CH28_Included (1UL) /*!< Include */
2656 
2657 /* Bit 27 : Include or exclude channel 27 */
2658 #define DPPIC_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
2659 #define DPPIC_CHG_CH27_Msk (0x1UL << DPPIC_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
2660 #define DPPIC_CHG_CH27_Excluded (0UL) /*!< Exclude */
2661 #define DPPIC_CHG_CH27_Included (1UL) /*!< Include */
2662 
2663 /* Bit 26 : Include or exclude channel 26 */
2664 #define DPPIC_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
2665 #define DPPIC_CHG_CH26_Msk (0x1UL << DPPIC_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
2666 #define DPPIC_CHG_CH26_Excluded (0UL) /*!< Exclude */
2667 #define DPPIC_CHG_CH26_Included (1UL) /*!< Include */
2668 
2669 /* Bit 25 : Include or exclude channel 25 */
2670 #define DPPIC_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
2671 #define DPPIC_CHG_CH25_Msk (0x1UL << DPPIC_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
2672 #define DPPIC_CHG_CH25_Excluded (0UL) /*!< Exclude */
2673 #define DPPIC_CHG_CH25_Included (1UL) /*!< Include */
2674 
2675 /* Bit 24 : Include or exclude channel 24 */
2676 #define DPPIC_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
2677 #define DPPIC_CHG_CH24_Msk (0x1UL << DPPIC_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
2678 #define DPPIC_CHG_CH24_Excluded (0UL) /*!< Exclude */
2679 #define DPPIC_CHG_CH24_Included (1UL) /*!< Include */
2680 
2681 /* Bit 23 : Include or exclude channel 23 */
2682 #define DPPIC_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
2683 #define DPPIC_CHG_CH23_Msk (0x1UL << DPPIC_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
2684 #define DPPIC_CHG_CH23_Excluded (0UL) /*!< Exclude */
2685 #define DPPIC_CHG_CH23_Included (1UL) /*!< Include */
2686 
2687 /* Bit 22 : Include or exclude channel 22 */
2688 #define DPPIC_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
2689 #define DPPIC_CHG_CH22_Msk (0x1UL << DPPIC_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
2690 #define DPPIC_CHG_CH22_Excluded (0UL) /*!< Exclude */
2691 #define DPPIC_CHG_CH22_Included (1UL) /*!< Include */
2692 
2693 /* Bit 21 : Include or exclude channel 21 */
2694 #define DPPIC_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
2695 #define DPPIC_CHG_CH21_Msk (0x1UL << DPPIC_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
2696 #define DPPIC_CHG_CH21_Excluded (0UL) /*!< Exclude */
2697 #define DPPIC_CHG_CH21_Included (1UL) /*!< Include */
2698 
2699 /* Bit 20 : Include or exclude channel 20 */
2700 #define DPPIC_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
2701 #define DPPIC_CHG_CH20_Msk (0x1UL << DPPIC_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
2702 #define DPPIC_CHG_CH20_Excluded (0UL) /*!< Exclude */
2703 #define DPPIC_CHG_CH20_Included (1UL) /*!< Include */
2704 
2705 /* Bit 19 : Include or exclude channel 19 */
2706 #define DPPIC_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
2707 #define DPPIC_CHG_CH19_Msk (0x1UL << DPPIC_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
2708 #define DPPIC_CHG_CH19_Excluded (0UL) /*!< Exclude */
2709 #define DPPIC_CHG_CH19_Included (1UL) /*!< Include */
2710 
2711 /* Bit 18 : Include or exclude channel 18 */
2712 #define DPPIC_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
2713 #define DPPIC_CHG_CH18_Msk (0x1UL << DPPIC_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
2714 #define DPPIC_CHG_CH18_Excluded (0UL) /*!< Exclude */
2715 #define DPPIC_CHG_CH18_Included (1UL) /*!< Include */
2716 
2717 /* Bit 17 : Include or exclude channel 17 */
2718 #define DPPIC_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
2719 #define DPPIC_CHG_CH17_Msk (0x1UL << DPPIC_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
2720 #define DPPIC_CHG_CH17_Excluded (0UL) /*!< Exclude */
2721 #define DPPIC_CHG_CH17_Included (1UL) /*!< Include */
2722 
2723 /* Bit 16 : Include or exclude channel 16 */
2724 #define DPPIC_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
2725 #define DPPIC_CHG_CH16_Msk (0x1UL << DPPIC_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
2726 #define DPPIC_CHG_CH16_Excluded (0UL) /*!< Exclude */
2727 #define DPPIC_CHG_CH16_Included (1UL) /*!< Include */
2728 
2729 /* Bit 15 : Include or exclude channel 15 */
2730 #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
2731 #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
2732 #define DPPIC_CHG_CH15_Excluded (0UL) /*!< Exclude */
2733 #define DPPIC_CHG_CH15_Included (1UL) /*!< Include */
2734 
2735 /* Bit 14 : Include or exclude channel 14 */
2736 #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
2737 #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
2738 #define DPPIC_CHG_CH14_Excluded (0UL) /*!< Exclude */
2739 #define DPPIC_CHG_CH14_Included (1UL) /*!< Include */
2740 
2741 /* Bit 13 : Include or exclude channel 13 */
2742 #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
2743 #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
2744 #define DPPIC_CHG_CH13_Excluded (0UL) /*!< Exclude */
2745 #define DPPIC_CHG_CH13_Included (1UL) /*!< Include */
2746 
2747 /* Bit 12 : Include or exclude channel 12 */
2748 #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
2749 #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
2750 #define DPPIC_CHG_CH12_Excluded (0UL) /*!< Exclude */
2751 #define DPPIC_CHG_CH12_Included (1UL) /*!< Include */
2752 
2753 /* Bit 11 : Include or exclude channel 11 */
2754 #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
2755 #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
2756 #define DPPIC_CHG_CH11_Excluded (0UL) /*!< Exclude */
2757 #define DPPIC_CHG_CH11_Included (1UL) /*!< Include */
2758 
2759 /* Bit 10 : Include or exclude channel 10 */
2760 #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
2761 #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
2762 #define DPPIC_CHG_CH10_Excluded (0UL) /*!< Exclude */
2763 #define DPPIC_CHG_CH10_Included (1UL) /*!< Include */
2764 
2765 /* Bit 9 : Include or exclude channel 9 */
2766 #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
2767 #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
2768 #define DPPIC_CHG_CH9_Excluded (0UL) /*!< Exclude */
2769 #define DPPIC_CHG_CH9_Included (1UL) /*!< Include */
2770 
2771 /* Bit 8 : Include or exclude channel 8 */
2772 #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
2773 #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
2774 #define DPPIC_CHG_CH8_Excluded (0UL) /*!< Exclude */
2775 #define DPPIC_CHG_CH8_Included (1UL) /*!< Include */
2776 
2777 /* Bit 7 : Include or exclude channel 7 */
2778 #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
2779 #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
2780 #define DPPIC_CHG_CH7_Excluded (0UL) /*!< Exclude */
2781 #define DPPIC_CHG_CH7_Included (1UL) /*!< Include */
2782 
2783 /* Bit 6 : Include or exclude channel 6 */
2784 #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
2785 #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
2786 #define DPPIC_CHG_CH6_Excluded (0UL) /*!< Exclude */
2787 #define DPPIC_CHG_CH6_Included (1UL) /*!< Include */
2788 
2789 /* Bit 5 : Include or exclude channel 5 */
2790 #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
2791 #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
2792 #define DPPIC_CHG_CH5_Excluded (0UL) /*!< Exclude */
2793 #define DPPIC_CHG_CH5_Included (1UL) /*!< Include */
2794 
2795 /* Bit 4 : Include or exclude channel 4 */
2796 #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
2797 #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
2798 #define DPPIC_CHG_CH4_Excluded (0UL) /*!< Exclude */
2799 #define DPPIC_CHG_CH4_Included (1UL) /*!< Include */
2800 
2801 /* Bit 3 : Include or exclude channel 3 */
2802 #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
2803 #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
2804 #define DPPIC_CHG_CH3_Excluded (0UL) /*!< Exclude */
2805 #define DPPIC_CHG_CH3_Included (1UL) /*!< Include */
2806 
2807 /* Bit 2 : Include or exclude channel 2 */
2808 #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
2809 #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
2810 #define DPPIC_CHG_CH2_Excluded (0UL) /*!< Exclude */
2811 #define DPPIC_CHG_CH2_Included (1UL) /*!< Include */
2812 
2813 /* Bit 1 : Include or exclude channel 1 */
2814 #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
2815 #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
2816 #define DPPIC_CHG_CH1_Excluded (0UL) /*!< Exclude */
2817 #define DPPIC_CHG_CH1_Included (1UL) /*!< Include */
2818 
2819 /* Bit 0 : Include or exclude channel 0 */
2820 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
2821 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
2822 #define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */
2823 #define DPPIC_CHG_CH0_Included (1UL) /*!< Include */
2824 
2825 
2826 /* Peripheral: EGU */
2827 /* Description: Event generator unit 0 */
2828 
2829 /* Register: EGU_TASKS_TRIGGER */
2830 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
2831 
2832 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
2833 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
2834 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
2835 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
2836 
2837 /* Register: EGU_SUBSCRIBE_TRIGGER */
2838 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */
2839 
2840 /* Bit 31 :   */
2841 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */
2842 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */
2843 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */
2844 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */
2845 
2846 /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */
2847 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2848 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2849 
2850 /* Register: EGU_EVENTS_TRIGGERED */
2851 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
2852 
2853 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
2854 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
2855 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
2856 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
2857 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
2858 
2859 /* Register: EGU_PUBLISH_TRIGGERED */
2860 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */
2861 
2862 /* Bit 31 :   */
2863 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */
2864 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */
2865 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */
2866 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */
2867 
2868 /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to. */
2869 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2870 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2871 
2872 /* Register: EGU_INTEN */
2873 /* Description: Enable or disable interrupt */
2874 
2875 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
2876 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
2877 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
2878 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
2879 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
2880 
2881 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
2882 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
2883 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
2884 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
2885 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
2886 
2887 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
2888 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
2889 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
2890 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
2891 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
2892 
2893 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
2894 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
2895 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
2896 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
2897 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
2898 
2899 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
2900 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
2901 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
2902 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
2903 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
2904 
2905 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
2906 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
2907 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
2908 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
2909 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
2910 
2911 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
2912 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
2913 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
2914 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
2915 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
2916 
2917 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
2918 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
2919 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
2920 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
2921 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
2922 
2923 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
2924 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
2925 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
2926 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
2927 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
2928 
2929 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
2930 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
2931 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
2932 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
2933 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
2934 
2935 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
2936 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
2937 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
2938 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
2939 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
2940 
2941 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
2942 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
2943 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
2944 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
2945 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
2946 
2947 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
2948 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
2949 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
2950 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
2951 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
2952 
2953 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
2954 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
2955 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
2956 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
2957 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
2958 
2959 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
2960 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
2961 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
2962 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
2963 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
2964 
2965 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
2966 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
2967 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
2968 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
2969 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
2970 
2971 /* Register: EGU_INTENSET */
2972 /* Description: Enable interrupt */
2973 
2974 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
2975 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
2976 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
2977 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
2978 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
2979 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
2980 
2981 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
2982 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
2983 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
2984 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
2985 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
2986 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
2987 
2988 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
2989 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
2990 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
2991 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
2992 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
2993 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
2994 
2995 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
2996 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
2997 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
2998 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
2999 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
3000 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
3001 
3002 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
3003 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
3004 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
3005 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
3006 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
3007 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
3008 
3009 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
3010 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
3011 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
3012 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
3013 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
3014 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
3015 
3016 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
3017 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
3018 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
3019 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
3020 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
3021 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
3022 
3023 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
3024 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
3025 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
3026 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
3027 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
3028 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
3029 
3030 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
3031 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
3032 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
3033 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
3034 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
3035 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
3036 
3037 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
3038 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
3039 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
3040 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
3041 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
3042 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
3043 
3044 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
3045 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
3046 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
3047 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
3048 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
3049 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
3050 
3051 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
3052 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
3053 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
3054 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
3055 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
3056 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
3057 
3058 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
3059 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
3060 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
3061 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
3062 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
3063 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
3064 
3065 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
3066 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
3067 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
3068 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
3069 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
3070 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
3071 
3072 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
3073 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
3074 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
3075 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
3076 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
3077 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
3078 
3079 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
3080 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
3081 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
3082 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
3083 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
3084 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
3085 
3086 /* Register: EGU_INTENCLR */
3087 /* Description: Disable interrupt */
3088 
3089 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
3090 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
3091 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
3092 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
3093 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
3094 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
3095 
3096 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
3097 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
3098 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
3099 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
3100 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
3101 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
3102 
3103 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
3104 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
3105 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
3106 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
3107 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
3108 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
3109 
3110 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
3111 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
3112 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
3113 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
3114 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
3115 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
3116 
3117 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
3118 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
3119 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
3120 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
3121 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
3122 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
3123 
3124 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
3125 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
3126 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
3127 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
3128 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
3129 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
3130 
3131 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
3132 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
3133 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
3134 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
3135 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
3136 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
3137 
3138 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
3139 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
3140 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
3141 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
3142 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
3143 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
3144 
3145 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
3146 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
3147 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
3148 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
3149 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
3150 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
3151 
3152 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
3153 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
3154 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
3155 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
3156 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
3157 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
3158 
3159 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
3160 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
3161 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
3162 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
3163 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
3164 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
3165 
3166 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
3167 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
3168 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
3169 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
3170 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
3171 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
3172 
3173 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
3174 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
3175 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
3176 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
3177 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
3178 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
3179 
3180 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
3181 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
3182 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
3183 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
3184 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
3185 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
3186 
3187 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
3188 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
3189 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
3190 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
3191 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
3192 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
3193 
3194 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
3195 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
3196 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
3197 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
3198 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
3199 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
3200 
3201 
3202 /* Peripheral: FICR */
3203 /* Description: Factory Information Configuration Registers */
3204 
3205 /* Register: FICR_INFO_CONFIGID */
3206 /* Description: Configuration identifier */
3207 
3208 /* Bits 15..0 : Identification number for the HW */
3209 #define FICR_INFO_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
3210 #define FICR_INFO_CONFIGID_HWID_Msk (0xFFFFUL << FICR_INFO_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
3211 
3212 /* Register: FICR_INFO_DEVICEID */
3213 /* Description: Description collection: Device identifier */
3214 
3215 /* Bits 31..0 : 64 bit unique device identifier */
3216 #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
3217 #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
3218 
3219 /* Register: FICR_INFO_PART */
3220 /* Description: Part code */
3221 
3222 /* Bits 31..0 : Part code */
3223 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
3224 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
3225 #define FICR_INFO_PART_PART_N5340 (0x5340UL) /*!< nRF5340 */
3226 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3227 
3228 /* Register: FICR_INFO_VARIANT */
3229 /* Description: Part Variant, Hardware version and Production configuration */
3230 
3231 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
3232 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
3233 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
3234 #define FICR_INFO_VARIANT_VARIANT_CLAA (0x434C4141UL) /*!< CLAA */
3235 #define FICR_INFO_VARIANT_VARIANT_QKAA (0x514B4141UL) /*!< QKAA */
3236 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3237 
3238 /* Register: FICR_INFO_PACKAGE */
3239 /* Description: Package option */
3240 
3241 /* Bits 31..0 : Package option */
3242 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
3243 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
3244 #define FICR_INFO_PACKAGE_PACKAGE_QK (0x2000UL) /*!< QKxx - 94-pin aQFN */
3245 #define FICR_INFO_PACKAGE_PACKAGE_CL (0x2005UL) /*!< CLxx - WLCSP */
3246 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3247 
3248 /* Register: FICR_INFO_RAM */
3249 /* Description: RAM variant */
3250 
3251 /* Bits 31..0 : RAM variant */
3252 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
3253 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
3254 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
3255 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
3256 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
3257 #define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */
3258 #define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */
3259 #define FICR_INFO_RAM_RAM_K512 (0x200UL) /*!< 512 kByte RAM */
3260 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3261 
3262 /* Register: FICR_INFO_FLASH */
3263 /* Description: Flash variant */
3264 
3265 /* Bits 31..0 : Flash variant */
3266 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
3267 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
3268 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
3269 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
3270 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
3271 #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
3272 #define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */
3273 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
3274 
3275 /* Register: FICR_INFO_CODEPAGESIZE */
3276 /* Description: Code memory page size in bytes */
3277 
3278 /* Bits 31..0 : Code memory page size in bytes */
3279 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
3280 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
3281 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x1000UL) /*!< 4 kByte */
3282 
3283 /* Register: FICR_INFO_CODESIZE */
3284 /* Description: Code memory size */
3285 
3286 /* Bits 31..0 : Code memory size in number of pages */
3287 #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
3288 #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
3289 #define FICR_INFO_CODESIZE_CODESIZE_P256 (256UL) /*!< 256 pages */
3290 
3291 /* Register: FICR_INFO_DEVICETYPE */
3292 /* Description: Device type */
3293 
3294 /* Bits 31..0 : Device type */
3295 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */
3296 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */
3297 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL) /*!< Device is an physical DIE */
3298 #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */
3299 
3300 /* Register: FICR_TRIMCNF_ADDR */
3301 /* Description: Description cluster: Address of the PAR register which will be written */
3302 
3303 /* Bits 31..0 : Address */
3304 #define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */
3305 #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */
3306 
3307 /* Register: FICR_TRIMCNF_DATA */
3308 /* Description: Description cluster: Data */
3309 
3310 /* Bits 31..0 : Data to be written into the PAR register */
3311 #define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */
3312 #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */
3313 
3314 /* Register: FICR_NFC_TAGHEADER0 */
3315 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
3316 
3317 /* Bits 31..24 : Unique identifier byte 3 */
3318 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
3319 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
3320 
3321 /* Bits 23..16 : Unique identifier byte 2 */
3322 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
3323 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
3324 
3325 /* Bits 15..8 : Unique identifier byte 1 */
3326 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
3327 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
3328 
3329 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
3330 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
3331 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
3332 
3333 /* Register: FICR_NFC_TAGHEADER1 */
3334 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
3335 
3336 /* Bits 31..24 : Unique identifier byte 7 */
3337 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
3338 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
3339 
3340 /* Bits 23..16 : Unique identifier byte 6 */
3341 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
3342 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
3343 
3344 /* Bits 15..8 : Unique identifier byte 5 */
3345 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
3346 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
3347 
3348 /* Bits 7..0 : Unique identifier byte 4 */
3349 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
3350 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
3351 
3352 /* Register: FICR_NFC_TAGHEADER2 */
3353 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
3354 
3355 /* Bits 31..24 : Unique identifier byte 11 */
3356 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
3357 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
3358 
3359 /* Bits 23..16 : Unique identifier byte 10 */
3360 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
3361 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
3362 
3363 /* Bits 15..8 : Unique identifier byte 9 */
3364 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
3365 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
3366 
3367 /* Bits 7..0 : Unique identifier byte 8 */
3368 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
3369 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
3370 
3371 /* Register: FICR_NFC_TAGHEADER3 */
3372 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
3373 
3374 /* Bits 31..24 : Unique identifier byte 15 */
3375 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
3376 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
3377 
3378 /* Bits 23..16 : Unique identifier byte 14 */
3379 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
3380 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
3381 
3382 /* Bits 15..8 : Unique identifier byte 13 */
3383 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
3384 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
3385 
3386 /* Bits 7..0 : Unique identifier byte 12 */
3387 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
3388 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
3389 
3390 /* Register: FICR_TRNG90B_BYTES */
3391 /* Description: Amount of bytes for the required entropy bits */
3392 
3393 /* Bits 31..0 : Amount of bytes for the required entropy bits */
3394 #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */
3395 #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */
3396 
3397 /* Register: FICR_TRNG90B_RCCUTOFF */
3398 /* Description: Repetition counter cutoff */
3399 
3400 /* Bits 31..0 : Repetition counter cutoff */
3401 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */
3402 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */
3403 
3404 /* Register: FICR_TRNG90B_APCUTOFF */
3405 /* Description: Adaptive proportion cutoff */
3406 
3407 /* Bits 31..0 : Adaptive proportion cutoff */
3408 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */
3409 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */
3410 
3411 /* Register: FICR_TRNG90B_STARTUP */
3412 /* Description: Amount of bytes for the startup tests */
3413 
3414 /* Bits 31..0 : Amount of bytes for the startup tests */
3415 #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */
3416 #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */
3417 
3418 /* Register: FICR_TRNG90B_ROSC1 */
3419 /* Description: Sample count for ring oscillator 1 */
3420 
3421 /* Bits 31..0 : Sample count for ring oscillator 1 */
3422 #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
3423 #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
3424 
3425 /* Register: FICR_TRNG90B_ROSC2 */
3426 /* Description: Sample count for ring oscillator 2 */
3427 
3428 /* Bits 31..0 : Sample count for ring oscillator 2 */
3429 #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */
3430 #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
3431 
3432 /* Register: FICR_TRNG90B_ROSC3 */
3433 /* Description: Sample count for ring oscillator 3 */
3434 
3435 /* Bits 31..0 : Sample count for ring oscillator 3 */
3436 #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */
3437 #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
3438 
3439 /* Register: FICR_TRNG90B_ROSC4 */
3440 /* Description: Sample count for ring oscillator 4 */
3441 
3442 /* Bits 31..0 : Sample count for ring oscillator 4 */
3443 #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */
3444 #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
3445 
3446 /* Register: FICR_XOSC32MTRIM */
3447 /* Description: XOSC32M capacitor selection trim values */
3448 
3449 /* Bits 9..5 : Offset trim factor on integer form */
3450 #define FICR_XOSC32MTRIM_OFFSET_Pos (5UL) /*!< Position of OFFSET field. */
3451 #define FICR_XOSC32MTRIM_OFFSET_Msk (0x1FUL << FICR_XOSC32MTRIM_OFFSET_Pos) /*!< Bit mask of OFFSET field. */
3452 
3453 /* Bits 4..0 : Slope trim factor on twos complement form */
3454 #define FICR_XOSC32MTRIM_SLOPE_Pos (0UL) /*!< Position of SLOPE field. */
3455 #define FICR_XOSC32MTRIM_SLOPE_Msk (0x1FUL << FICR_XOSC32MTRIM_SLOPE_Pos) /*!< Bit mask of SLOPE field. */
3456 
3457 
3458 /* Peripheral: FPU */
3459 /* Description: FPU control peripheral 0 */
3460 
3461 /* Register: FPU_EVENTS_INVALIDOPERATION */
3462 /* Description: An FPUIOC exception triggered by an invalid operation has occurred in the FPU */
3463 
3464 /* Bit 0 : An FPUIOC exception triggered by an invalid operation has occurred in the FPU */
3465 #define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Pos (0UL) /*!< Position of EVENTS_INVALIDOPERATION field. */
3466 #define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Msk (0x1UL << FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Pos) /*!< Bit mask of EVENTS_INVALIDOPERATION field. */
3467 #define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_NotGenerated (0UL) /*!< Event not generated */
3468 #define FPU_EVENTS_INVALIDOPERATION_EVENTS_INVALIDOPERATION_Generated (1UL) /*!< Event generated */
3469 
3470 /* Register: FPU_EVENTS_DIVIDEBYZERO */
3471 /* Description: An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU */
3472 
3473 /* Bit 0 : An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU */
3474 #define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Pos (0UL) /*!< Position of EVENTS_DIVIDEBYZERO field. */
3475 #define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Msk (0x1UL << FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Pos) /*!< Bit mask of EVENTS_DIVIDEBYZERO field. */
3476 #define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_NotGenerated (0UL) /*!< Event not generated */
3477 #define FPU_EVENTS_DIVIDEBYZERO_EVENTS_DIVIDEBYZERO_Generated (1UL) /*!< Event generated */
3478 
3479 /* Register: FPU_EVENTS_OVERFLOW */
3480 /* Description: An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU */
3481 
3482 /* Bit 0 : An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU */
3483 #define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Pos (0UL) /*!< Position of EVENTS_OVERFLOW field. */
3484 #define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Msk (0x1UL << FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Pos) /*!< Bit mask of EVENTS_OVERFLOW field. */
3485 #define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_NotGenerated (0UL) /*!< Event not generated */
3486 #define FPU_EVENTS_OVERFLOW_EVENTS_OVERFLOW_Generated (1UL) /*!< Event generated */
3487 
3488 /* Register: FPU_EVENTS_UNDERFLOW */
3489 /* Description: An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU */
3490 
3491 /* Bit 0 : An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU */
3492 #define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Pos (0UL) /*!< Position of EVENTS_UNDERFLOW field. */
3493 #define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Msk (0x1UL << FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Pos) /*!< Bit mask of EVENTS_UNDERFLOW field. */
3494 #define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_NotGenerated (0UL) /*!< Event not generated */
3495 #define FPU_EVENTS_UNDERFLOW_EVENTS_UNDERFLOW_Generated (1UL) /*!< Event generated */
3496 
3497 /* Register: FPU_EVENTS_INEXACT */
3498 /* Description: An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU */
3499 
3500 /* Bit 0 : An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU */
3501 #define FPU_EVENTS_INEXACT_EVENTS_INEXACT_Pos (0UL) /*!< Position of EVENTS_INEXACT field. */
3502 #define FPU_EVENTS_INEXACT_EVENTS_INEXACT_Msk (0x1UL << FPU_EVENTS_INEXACT_EVENTS_INEXACT_Pos) /*!< Bit mask of EVENTS_INEXACT field. */
3503 #define FPU_EVENTS_INEXACT_EVENTS_INEXACT_NotGenerated (0UL) /*!< Event not generated */
3504 #define FPU_EVENTS_INEXACT_EVENTS_INEXACT_Generated (1UL) /*!< Event generated */
3505 
3506 /* Register: FPU_EVENTS_DENORMALINPUT */
3507 /* Description: An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU */
3508 
3509 /* Bit 0 : An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU */
3510 #define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Pos (0UL) /*!< Position of EVENTS_DENORMALINPUT field. */
3511 #define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Msk (0x1UL << FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Pos) /*!< Bit mask of EVENTS_DENORMALINPUT field. */
3512 #define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_NotGenerated (0UL) /*!< Event not generated */
3513 #define FPU_EVENTS_DENORMALINPUT_EVENTS_DENORMALINPUT_Generated (1UL) /*!< Event generated */
3514 
3515 /* Register: FPU_INTEN */
3516 /* Description: Enable or disable interrupt */
3517 
3518 /* Bit 5 : Enable or disable interrupt for event DENORMALINPUT */
3519 #define FPU_INTEN_DENORMALINPUT_Pos (5UL) /*!< Position of DENORMALINPUT field. */
3520 #define FPU_INTEN_DENORMALINPUT_Msk (0x1UL << FPU_INTEN_DENORMALINPUT_Pos) /*!< Bit mask of DENORMALINPUT field. */
3521 #define FPU_INTEN_DENORMALINPUT_Disabled (0UL) /*!< Disable */
3522 #define FPU_INTEN_DENORMALINPUT_Enabled (1UL) /*!< Enable */
3523 
3524 /* Bit 4 : Enable or disable interrupt for event INEXACT */
3525 #define FPU_INTEN_INEXACT_Pos (4UL) /*!< Position of INEXACT field. */
3526 #define FPU_INTEN_INEXACT_Msk (0x1UL << FPU_INTEN_INEXACT_Pos) /*!< Bit mask of INEXACT field. */
3527 #define FPU_INTEN_INEXACT_Disabled (0UL) /*!< Disable */
3528 #define FPU_INTEN_INEXACT_Enabled (1UL) /*!< Enable */
3529 
3530 /* Bit 3 : Enable or disable interrupt for event UNDERFLOW */
3531 #define FPU_INTEN_UNDERFLOW_Pos (3UL) /*!< Position of UNDERFLOW field. */
3532 #define FPU_INTEN_UNDERFLOW_Msk (0x1UL << FPU_INTEN_UNDERFLOW_Pos) /*!< Bit mask of UNDERFLOW field. */
3533 #define FPU_INTEN_UNDERFLOW_Disabled (0UL) /*!< Disable */
3534 #define FPU_INTEN_UNDERFLOW_Enabled (1UL) /*!< Enable */
3535 
3536 /* Bit 2 : Enable or disable interrupt for event OVERFLOW */
3537 #define FPU_INTEN_OVERFLOW_Pos (2UL) /*!< Position of OVERFLOW field. */
3538 #define FPU_INTEN_OVERFLOW_Msk (0x1UL << FPU_INTEN_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
3539 #define FPU_INTEN_OVERFLOW_Disabled (0UL) /*!< Disable */
3540 #define FPU_INTEN_OVERFLOW_Enabled (1UL) /*!< Enable */
3541 
3542 /* Bit 1 : Enable or disable interrupt for event DIVIDEBYZERO */
3543 #define FPU_INTEN_DIVIDEBYZERO_Pos (1UL) /*!< Position of DIVIDEBYZERO field. */
3544 #define FPU_INTEN_DIVIDEBYZERO_Msk (0x1UL << FPU_INTEN_DIVIDEBYZERO_Pos) /*!< Bit mask of DIVIDEBYZERO field. */
3545 #define FPU_INTEN_DIVIDEBYZERO_Disabled (0UL) /*!< Disable */
3546 #define FPU_INTEN_DIVIDEBYZERO_Enabled (1UL) /*!< Enable */
3547 
3548 /* Bit 0 : Enable or disable interrupt for event INVALIDOPERATION */
3549 #define FPU_INTEN_INVALIDOPERATION_Pos (0UL) /*!< Position of INVALIDOPERATION field. */
3550 #define FPU_INTEN_INVALIDOPERATION_Msk (0x1UL << FPU_INTEN_INVALIDOPERATION_Pos) /*!< Bit mask of INVALIDOPERATION field. */
3551 #define FPU_INTEN_INVALIDOPERATION_Disabled (0UL) /*!< Disable */
3552 #define FPU_INTEN_INVALIDOPERATION_Enabled (1UL) /*!< Enable */
3553 
3554 /* Register: FPU_INTENSET */
3555 /* Description: Enable interrupt */
3556 
3557 /* Bit 5 : Write '1' to enable interrupt for event DENORMALINPUT */
3558 #define FPU_INTENSET_DENORMALINPUT_Pos (5UL) /*!< Position of DENORMALINPUT field. */
3559 #define FPU_INTENSET_DENORMALINPUT_Msk (0x1UL << FPU_INTENSET_DENORMALINPUT_Pos) /*!< Bit mask of DENORMALINPUT field. */
3560 #define FPU_INTENSET_DENORMALINPUT_Disabled (0UL) /*!< Read: Disabled */
3561 #define FPU_INTENSET_DENORMALINPUT_Enabled (1UL) /*!< Read: Enabled */
3562 #define FPU_INTENSET_DENORMALINPUT_Set (1UL) /*!< Enable */
3563 
3564 /* Bit 4 : Write '1' to enable interrupt for event INEXACT */
3565 #define FPU_INTENSET_INEXACT_Pos (4UL) /*!< Position of INEXACT field. */
3566 #define FPU_INTENSET_INEXACT_Msk (0x1UL << FPU_INTENSET_INEXACT_Pos) /*!< Bit mask of INEXACT field. */
3567 #define FPU_INTENSET_INEXACT_Disabled (0UL) /*!< Read: Disabled */
3568 #define FPU_INTENSET_INEXACT_Enabled (1UL) /*!< Read: Enabled */
3569 #define FPU_INTENSET_INEXACT_Set (1UL) /*!< Enable */
3570 
3571 /* Bit 3 : Write '1' to enable interrupt for event UNDERFLOW */
3572 #define FPU_INTENSET_UNDERFLOW_Pos (3UL) /*!< Position of UNDERFLOW field. */
3573 #define FPU_INTENSET_UNDERFLOW_Msk (0x1UL << FPU_INTENSET_UNDERFLOW_Pos) /*!< Bit mask of UNDERFLOW field. */
3574 #define FPU_INTENSET_UNDERFLOW_Disabled (0UL) /*!< Read: Disabled */
3575 #define FPU_INTENSET_UNDERFLOW_Enabled (1UL) /*!< Read: Enabled */
3576 #define FPU_INTENSET_UNDERFLOW_Set (1UL) /*!< Enable */
3577 
3578 /* Bit 2 : Write '1' to enable interrupt for event OVERFLOW */
3579 #define FPU_INTENSET_OVERFLOW_Pos (2UL) /*!< Position of OVERFLOW field. */
3580 #define FPU_INTENSET_OVERFLOW_Msk (0x1UL << FPU_INTENSET_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
3581 #define FPU_INTENSET_OVERFLOW_Disabled (0UL) /*!< Read: Disabled */
3582 #define FPU_INTENSET_OVERFLOW_Enabled (1UL) /*!< Read: Enabled */
3583 #define FPU_INTENSET_OVERFLOW_Set (1UL) /*!< Enable */
3584 
3585 /* Bit 1 : Write '1' to enable interrupt for event DIVIDEBYZERO */
3586 #define FPU_INTENSET_DIVIDEBYZERO_Pos (1UL) /*!< Position of DIVIDEBYZERO field. */
3587 #define FPU_INTENSET_DIVIDEBYZERO_Msk (0x1UL << FPU_INTENSET_DIVIDEBYZERO_Pos) /*!< Bit mask of DIVIDEBYZERO field. */
3588 #define FPU_INTENSET_DIVIDEBYZERO_Disabled (0UL) /*!< Read: Disabled */
3589 #define FPU_INTENSET_DIVIDEBYZERO_Enabled (1UL) /*!< Read: Enabled */
3590 #define FPU_INTENSET_DIVIDEBYZERO_Set (1UL) /*!< Enable */
3591 
3592 /* Bit 0 : Write '1' to enable interrupt for event INVALIDOPERATION */
3593 #define FPU_INTENSET_INVALIDOPERATION_Pos (0UL) /*!< Position of INVALIDOPERATION field. */
3594 #define FPU_INTENSET_INVALIDOPERATION_Msk (0x1UL << FPU_INTENSET_INVALIDOPERATION_Pos) /*!< Bit mask of INVALIDOPERATION field. */
3595 #define FPU_INTENSET_INVALIDOPERATION_Disabled (0UL) /*!< Read: Disabled */
3596 #define FPU_INTENSET_INVALIDOPERATION_Enabled (1UL) /*!< Read: Enabled */
3597 #define FPU_INTENSET_INVALIDOPERATION_Set (1UL) /*!< Enable */
3598 
3599 /* Register: FPU_INTENCLR */
3600 /* Description: Disable interrupt */
3601 
3602 /* Bit 5 : Write '1' to disable interrupt for event DENORMALINPUT */
3603 #define FPU_INTENCLR_DENORMALINPUT_Pos (5UL) /*!< Position of DENORMALINPUT field. */
3604 #define FPU_INTENCLR_DENORMALINPUT_Msk (0x1UL << FPU_INTENCLR_DENORMALINPUT_Pos) /*!< Bit mask of DENORMALINPUT field. */
3605 #define FPU_INTENCLR_DENORMALINPUT_Disabled (0UL) /*!< Read: Disabled */
3606 #define FPU_INTENCLR_DENORMALINPUT_Enabled (1UL) /*!< Read: Enabled */
3607 #define FPU_INTENCLR_DENORMALINPUT_Clear (1UL) /*!< Disable */
3608 
3609 /* Bit 4 : Write '1' to disable interrupt for event INEXACT */
3610 #define FPU_INTENCLR_INEXACT_Pos (4UL) /*!< Position of INEXACT field. */
3611 #define FPU_INTENCLR_INEXACT_Msk (0x1UL << FPU_INTENCLR_INEXACT_Pos) /*!< Bit mask of INEXACT field. */
3612 #define FPU_INTENCLR_INEXACT_Disabled (0UL) /*!< Read: Disabled */
3613 #define FPU_INTENCLR_INEXACT_Enabled (1UL) /*!< Read: Enabled */
3614 #define FPU_INTENCLR_INEXACT_Clear (1UL) /*!< Disable */
3615 
3616 /* Bit 3 : Write '1' to disable interrupt for event UNDERFLOW */
3617 #define FPU_INTENCLR_UNDERFLOW_Pos (3UL) /*!< Position of UNDERFLOW field. */
3618 #define FPU_INTENCLR_UNDERFLOW_Msk (0x1UL << FPU_INTENCLR_UNDERFLOW_Pos) /*!< Bit mask of UNDERFLOW field. */
3619 #define FPU_INTENCLR_UNDERFLOW_Disabled (0UL) /*!< Read: Disabled */
3620 #define FPU_INTENCLR_UNDERFLOW_Enabled (1UL) /*!< Read: Enabled */
3621 #define FPU_INTENCLR_UNDERFLOW_Clear (1UL) /*!< Disable */
3622 
3623 /* Bit 2 : Write '1' to disable interrupt for event OVERFLOW */
3624 #define FPU_INTENCLR_OVERFLOW_Pos (2UL) /*!< Position of OVERFLOW field. */
3625 #define FPU_INTENCLR_OVERFLOW_Msk (0x1UL << FPU_INTENCLR_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
3626 #define FPU_INTENCLR_OVERFLOW_Disabled (0UL) /*!< Read: Disabled */
3627 #define FPU_INTENCLR_OVERFLOW_Enabled (1UL) /*!< Read: Enabled */
3628 #define FPU_INTENCLR_OVERFLOW_Clear (1UL) /*!< Disable */
3629 
3630 /* Bit 1 : Write '1' to disable interrupt for event DIVIDEBYZERO */
3631 #define FPU_INTENCLR_DIVIDEBYZERO_Pos (1UL) /*!< Position of DIVIDEBYZERO field. */
3632 #define FPU_INTENCLR_DIVIDEBYZERO_Msk (0x1UL << FPU_INTENCLR_DIVIDEBYZERO_Pos) /*!< Bit mask of DIVIDEBYZERO field. */
3633 #define FPU_INTENCLR_DIVIDEBYZERO_Disabled (0UL) /*!< Read: Disabled */
3634 #define FPU_INTENCLR_DIVIDEBYZERO_Enabled (1UL) /*!< Read: Enabled */
3635 #define FPU_INTENCLR_DIVIDEBYZERO_Clear (1UL) /*!< Disable */
3636 
3637 /* Bit 0 : Write '1' to disable interrupt for event INVALIDOPERATION */
3638 #define FPU_INTENCLR_INVALIDOPERATION_Pos (0UL) /*!< Position of INVALIDOPERATION field. */
3639 #define FPU_INTENCLR_INVALIDOPERATION_Msk (0x1UL << FPU_INTENCLR_INVALIDOPERATION_Pos) /*!< Bit mask of INVALIDOPERATION field. */
3640 #define FPU_INTENCLR_INVALIDOPERATION_Disabled (0UL) /*!< Read: Disabled */
3641 #define FPU_INTENCLR_INVALIDOPERATION_Enabled (1UL) /*!< Read: Enabled */
3642 #define FPU_INTENCLR_INVALIDOPERATION_Clear (1UL) /*!< Disable */
3643 
3644 
3645 /* Peripheral: GPIOTE */
3646 /* Description: GPIO Tasks and Events 0 */
3647 
3648 /* Register: GPIOTE_TASKS_OUT */
3649 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
3650 
3651 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
3652 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
3653 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
3654 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
3655 
3656 /* Register: GPIOTE_TASKS_SET */
3657 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
3658 
3659 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
3660 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
3661 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
3662 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
3663 
3664 /* Register: GPIOTE_TASKS_CLR */
3665 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
3666 
3667 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
3668 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
3669 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
3670 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
3671 
3672 /* Register: GPIOTE_SUBSCRIBE_OUT */
3673 /* Description: Description collection: Subscribe configuration for task OUT[n] */
3674 
3675 /* Bit 31 :   */
3676 #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */
3677 #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */
3678 #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */
3679 #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */
3680 
3681 /* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */
3682 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3683 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3684 
3685 /* Register: GPIOTE_SUBSCRIBE_SET */
3686 /* Description: Description collection: Subscribe configuration for task SET[n] */
3687 
3688 /* Bit 31 :   */
3689 #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */
3690 #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */
3691 #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */
3692 #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */
3693 
3694 /* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */
3695 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3696 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3697 
3698 /* Register: GPIOTE_SUBSCRIBE_CLR */
3699 /* Description: Description collection: Subscribe configuration for task CLR[n] */
3700 
3701 /* Bit 31 :   */
3702 #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */
3703 #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */
3704 #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */
3705 #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */
3706 
3707 /* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */
3708 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3709 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3710 
3711 /* Register: GPIOTE_EVENTS_IN */
3712 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
3713 
3714 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
3715 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
3716 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
3717 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
3718 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
3719 
3720 /* Register: GPIOTE_EVENTS_PORT */
3721 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
3722 
3723 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
3724 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
3725 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
3726 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
3727 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
3728 
3729 /* Register: GPIOTE_PUBLISH_IN */
3730 /* Description: Description collection: Publish configuration for event IN[n] */
3731 
3732 /* Bit 31 :   */
3733 #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */
3734 #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */
3735 #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */
3736 #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */
3737 
3738 /* Bits 7..0 : DPPI channel that event IN[n] will publish to. */
3739 #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3740 #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3741 
3742 /* Register: GPIOTE_PUBLISH_PORT */
3743 /* Description: Publish configuration for event PORT */
3744 
3745 /* Bit 31 :   */
3746 #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */
3747 #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */
3748 #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */
3749 #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */
3750 
3751 /* Bits 7..0 : DPPI channel that event PORT will publish to. */
3752 #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3753 #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3754 
3755 /* Register: GPIOTE_INTENSET */
3756 /* Description: Enable interrupt */
3757 
3758 /* Bit 31 : Write '1' to enable interrupt for event PORT */
3759 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
3760 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
3761 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
3762 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
3763 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
3764 
3765 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
3766 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
3767 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
3768 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
3769 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
3770 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
3771 
3772 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
3773 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
3774 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
3775 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
3776 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
3777 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
3778 
3779 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
3780 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
3781 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
3782 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
3783 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
3784 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
3785 
3786 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
3787 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
3788 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
3789 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
3790 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
3791 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
3792 
3793 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
3794 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
3795 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
3796 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
3797 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
3798 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
3799 
3800 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
3801 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
3802 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
3803 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
3804 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
3805 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
3806 
3807 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
3808 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
3809 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
3810 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
3811 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
3812 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
3813 
3814 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
3815 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
3816 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
3817 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
3818 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
3819 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
3820 
3821 /* Register: GPIOTE_INTENCLR */
3822 /* Description: Disable interrupt */
3823 
3824 /* Bit 31 : Write '1' to disable interrupt for event PORT */
3825 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
3826 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
3827 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
3828 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
3829 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
3830 
3831 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
3832 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
3833 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
3834 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
3835 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
3836 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
3837 
3838 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
3839 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
3840 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
3841 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
3842 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
3843 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
3844 
3845 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
3846 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
3847 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
3848 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
3849 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
3850 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
3851 
3852 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
3853 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
3854 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
3855 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
3856 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
3857 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
3858 
3859 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
3860 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
3861 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
3862 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
3863 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
3864 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
3865 
3866 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
3867 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
3868 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
3869 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
3870 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
3871 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
3872 
3873 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
3874 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
3875 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
3876 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
3877 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
3878 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
3879 
3880 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
3881 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
3882 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
3883 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
3884 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
3885 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
3886 
3887 /* Register: GPIOTE_LATENCY */
3888 /* Description: Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. */
3889 
3890 /* Bit 0 : Latency setting */
3891 #define GPIOTE_LATENCY_LATENCY_Pos (0UL) /*!< Position of LATENCY field. */
3892 #define GPIOTE_LATENCY_LATENCY_Msk (0x1UL << GPIOTE_LATENCY_LATENCY_Pos) /*!< Bit mask of LATENCY field. */
3893 #define GPIOTE_LATENCY_LATENCY_LowPower (0UL) /*!< Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section */
3894 #define GPIOTE_LATENCY_LATENCY_LowLatency (1UL) /*!< Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section */
3895 
3896 /* Register: GPIOTE_CONFIG */
3897 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
3898 
3899 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
3900 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
3901 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
3902 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
3903 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
3904 
3905 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
3906 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
3907 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
3908 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
3909 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
3910 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
3911 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
3912 
3913 /* Bit 13 : Port number */
3914 #define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
3915 #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */
3916 
3917 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
3918 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
3919 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
3920 
3921 /* Bits 1..0 : Mode */
3922 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
3923 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
3924 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
3925 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
3926 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
3927 
3928 
3929 /* Peripheral: I2S */
3930 /* Description: Inter-IC Sound 0 */
3931 
3932 /* Register: I2S_TASKS_START */
3933 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled */
3934 
3935 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled */
3936 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
3937 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
3938 #define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
3939 
3940 /* Register: I2S_TASKS_STOP */
3941 /* Description: Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. */
3942 
3943 /* Bit 0 : Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. */
3944 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
3945 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
3946 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
3947 
3948 /* Register: I2S_SUBSCRIBE_START */
3949 /* Description: Subscribe configuration for task START */
3950 
3951 /* Bit 31 :   */
3952 #define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
3953 #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
3954 #define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
3955 #define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
3956 
3957 /* Bits 7..0 : DPPI channel that task START will subscribe to */
3958 #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3959 #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3960 
3961 /* Register: I2S_SUBSCRIBE_STOP */
3962 /* Description: Subscribe configuration for task STOP */
3963 
3964 /* Bit 31 :   */
3965 #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
3966 #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
3967 #define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
3968 #define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
3969 
3970 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
3971 #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3972 #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3973 
3974 /* Register: I2S_EVENTS_RXPTRUPD */
3975 /* Description: The RXD.PTR register has been copied to internal double-buffers.
3976       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */
3977 
3978 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
3979       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */
3980 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
3981 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
3982 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
3983 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
3984 
3985 /* Register: I2S_EVENTS_STOPPED */
3986 /* Description: I2S transfer stopped. */
3987 
3988 /* Bit 0 : I2S transfer stopped. */
3989 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
3990 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
3991 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
3992 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
3993 
3994 /* Register: I2S_EVENTS_TXPTRUPD */
3995 /* Description: The TDX.PTR register has been copied to internal double-buffers.
3996       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
3997 
3998 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
3999       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
4000 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
4001 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
4002 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
4003 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
4004 
4005 /* Register: I2S_EVENTS_FRAMESTART */
4006 /* Description: Frame start event, generated on the active edge of LRCK */
4007 
4008 /* Bit 0 : Frame start event, generated on the active edge of LRCK */
4009 #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */
4010 #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */
4011 #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */
4012 #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */
4013 
4014 /* Register: I2S_PUBLISH_RXPTRUPD */
4015 /* Description: Publish configuration for event RXPTRUPD */
4016 
4017 /* Bit 31 :   */
4018 #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
4019 #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
4020 #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
4021 #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
4022 
4023 /* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to. */
4024 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4025 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4026 
4027 /* Register: I2S_PUBLISH_STOPPED */
4028 /* Description: Publish configuration for event STOPPED */
4029 
4030 /* Bit 31 :   */
4031 #define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
4032 #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
4033 #define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
4034 #define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
4035 
4036 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
4037 #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4038 #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4039 
4040 /* Register: I2S_PUBLISH_TXPTRUPD */
4041 /* Description: Publish configuration for event TXPTRUPD */
4042 
4043 /* Bit 31 :   */
4044 #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
4045 #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
4046 #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
4047 #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
4048 
4049 /* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to. */
4050 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4051 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4052 
4053 /* Register: I2S_PUBLISH_FRAMESTART */
4054 /* Description: Publish configuration for event FRAMESTART */
4055 
4056 /* Bit 31 :   */
4057 #define I2S_PUBLISH_FRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */
4058 #define I2S_PUBLISH_FRAMESTART_EN_Msk (0x1UL << I2S_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field. */
4059 #define I2S_PUBLISH_FRAMESTART_EN_Disabled (0UL) /*!< Disable publishing */
4060 #define I2S_PUBLISH_FRAMESTART_EN_Enabled (1UL) /*!< Enable publishing */
4061 
4062 /* Bits 7..0 : DPPI channel that event FRAMESTART will publish to. */
4063 #define I2S_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4064 #define I2S_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << I2S_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4065 
4066 /* Register: I2S_INTEN */
4067 /* Description: Enable or disable interrupt */
4068 
4069 /* Bit 7 : Enable or disable interrupt for event FRAMESTART */
4070 #define I2S_INTEN_FRAMESTART_Pos (7UL) /*!< Position of FRAMESTART field. */
4071 #define I2S_INTEN_FRAMESTART_Msk (0x1UL << I2S_INTEN_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
4072 #define I2S_INTEN_FRAMESTART_Disabled (0UL) /*!< Disable */
4073 #define I2S_INTEN_FRAMESTART_Enabled (1UL) /*!< Enable */
4074 
4075 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
4076 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
4077 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
4078 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
4079 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
4080 
4081 /* Bit 2 : Enable or disable interrupt for event STOPPED */
4082 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
4083 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4084 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
4085 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
4086 
4087 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
4088 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
4089 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
4090 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
4091 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
4092 
4093 /* Register: I2S_INTENSET */
4094 /* Description: Enable interrupt */
4095 
4096 /* Bit 7 : Write '1' to enable interrupt for event FRAMESTART */
4097 #define I2S_INTENSET_FRAMESTART_Pos (7UL) /*!< Position of FRAMESTART field. */
4098 #define I2S_INTENSET_FRAMESTART_Msk (0x1UL << I2S_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
4099 #define I2S_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4100 #define I2S_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4101 #define I2S_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
4102 
4103 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
4104 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
4105 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
4106 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
4107 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
4108 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
4109 
4110 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
4111 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
4112 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4113 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4114 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4115 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
4116 
4117 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
4118 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
4119 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
4120 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
4121 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
4122 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
4123 
4124 /* Register: I2S_INTENCLR */
4125 /* Description: Disable interrupt */
4126 
4127 /* Bit 7 : Write '1' to disable interrupt for event FRAMESTART */
4128 #define I2S_INTENCLR_FRAMESTART_Pos (7UL) /*!< Position of FRAMESTART field. */
4129 #define I2S_INTENCLR_FRAMESTART_Msk (0x1UL << I2S_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
4130 #define I2S_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4131 #define I2S_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4132 #define I2S_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
4133 
4134 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
4135 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
4136 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
4137 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
4138 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
4139 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
4140 
4141 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
4142 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
4143 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4144 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4145 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4146 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
4147 
4148 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
4149 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
4150 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
4151 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
4152 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
4153 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
4154 
4155 /* Register: I2S_ENABLE */
4156 /* Description: Enable I2S module */
4157 
4158 /* Bit 0 : Enable I2S module */
4159 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
4160 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
4161 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
4162 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
4163 
4164 /* Register: I2S_CONFIG_MODE */
4165 /* Description: I2S mode */
4166 
4167 /* Bit 0 : I2S mode */
4168 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
4169 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
4170 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
4171 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
4172 
4173 /* Register: I2S_CONFIG_RXEN */
4174 /* Description: Reception (RX) enable */
4175 
4176 /* Bit 0 : Reception (RX) enable */
4177 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
4178 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
4179 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
4180 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
4181 
4182 /* Register: I2S_CONFIG_TXEN */
4183 /* Description: Transmission (TX) enable */
4184 
4185 /* Bit 0 : Transmission (TX) enable */
4186 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
4187 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
4188 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
4189 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
4190 
4191 /* Register: I2S_CONFIG_MCKEN */
4192 /* Description: Master clock generator enable */
4193 
4194 /* Bit 0 : Master clock generator enable */
4195 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
4196 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
4197 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
4198 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
4199 
4200 /* Register: I2S_CONFIG_MCKFREQ */
4201 /* Description: I2S clock generator control */
4202 
4203 /* Bits 31..0 : I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. */
4204 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
4205 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
4206 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. */
4207 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. */
4208 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. */
4209 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. */
4210 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. */
4211 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. */
4212 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. */
4213 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. */
4214 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. */
4215 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. */
4216 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. */
4217 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. */
4218 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. */
4219 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. */
4220 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. */
4221 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. */
4222 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. */
4223 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. */
4224 
4225 /* Register: I2S_CONFIG_RATIO */
4226 /* Description: MCK / LRCK ratio */
4227 
4228 /* Bits 3..0 : MCK / LRCK ratio */
4229 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
4230 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
4231 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
4232 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
4233 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
4234 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
4235 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
4236 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
4237 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
4238 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
4239 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
4240 
4241 /* Register: I2S_CONFIG_SWIDTH */
4242 /* Description: Sample width */
4243 
4244 /* Bits 2..0 : Sample and half-frame width */
4245 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
4246 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x7UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
4247 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit sample. */
4248 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit sample. */
4249 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit sample. */
4250 #define I2S_CONFIG_SWIDTH_SWIDTH_32Bit (3UL) /*!< 32 bit sample. */
4251 #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16 (4UL) /*!< 8 bit sample in a 16-bit half-frame. */
4252 #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32 (5UL) /*!< 8 bit sample in a 32-bit half-frame. */
4253 #define I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32 (6UL) /*!< 16 bit sample in a 32-bit half-frame. */
4254 #define I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32 (7UL) /*!< 24 bit sample in a 32-bit half-frame. */
4255 
4256 /* Register: I2S_CONFIG_ALIGN */
4257 /* Description: Alignment of sample within a frame */
4258 
4259 /* Bit 0 : Alignment of sample within a frame */
4260 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
4261 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
4262 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
4263 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
4264 
4265 /* Register: I2S_CONFIG_FORMAT */
4266 /* Description: Frame format */
4267 
4268 /* Bit 0 : Frame format */
4269 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
4270 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
4271 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
4272 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
4273 
4274 /* Register: I2S_CONFIG_CHANNELS */
4275 /* Description: Enable channels */
4276 
4277 /* Bits 1..0 : Enable channels */
4278 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
4279 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
4280 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
4281 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
4282 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
4283 
4284 /* Register: I2S_CONFIG_CLKCONFIG */
4285 /* Description: Clock source selection for the I2S module */
4286 
4287 /* Bit 8 : Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. */
4288 #define I2S_CONFIG_CLKCONFIG_BYPASS_Pos (8UL) /*!< Position of BYPASS field. */
4289 #define I2S_CONFIG_CLKCONFIG_BYPASS_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
4290 #define I2S_CONFIG_CLKCONFIG_BYPASS_Disable (0UL) /*!< Disable bypass */
4291 #define I2S_CONFIG_CLKCONFIG_BYPASS_Enable (1UL) /*!< Enable bypass */
4292 
4293 /* Bit 0 : Clock source selection */
4294 #define I2S_CONFIG_CLKCONFIG_CLKSRC_Pos (0UL) /*!< Position of CLKSRC field. */
4295 #define I2S_CONFIG_CLKCONFIG_CLKSRC_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_CLKSRC_Pos) /*!< Bit mask of CLKSRC field. */
4296 #define I2S_CONFIG_CLKCONFIG_CLKSRC_PCLK32M (0UL) /*!< 32MHz peripheral clock */
4297 #define I2S_CONFIG_CLKCONFIG_CLKSRC_ACLK (1UL) /*!< Audio PLL clock */
4298 
4299 /* Register: I2S_RXD_PTR */
4300 /* Description: Receive buffer RAM start address. */
4301 
4302 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
4303 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4304 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
4305 
4306 /* Register: I2S_TXD_PTR */
4307 /* Description: Transmit buffer RAM start address */
4308 
4309 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
4310 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4311 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
4312 
4313 /* Register: I2S_RXTXD_MAXCNT */
4314 /* Description: Size of RXD and TXD buffers */
4315 
4316 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words */
4317 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
4318 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
4319 
4320 /* Register: I2S_PSEL_MCK */
4321 /* Description: Pin select for MCK signal */
4322 
4323 /* Bit 31 : Connection */
4324 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4325 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4326 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
4327 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
4328 
4329 /* Bit 5 : Port number */
4330 #define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */
4331 #define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */
4332 
4333 /* Bits 4..0 : Pin number */
4334 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
4335 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
4336 
4337 /* Register: I2S_PSEL_SCK */
4338 /* Description: Pin select for SCK signal */
4339 
4340 /* Bit 31 : Connection */
4341 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4342 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4343 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
4344 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
4345 
4346 /* Bit 5 : Port number */
4347 #define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
4348 #define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
4349 
4350 /* Bits 4..0 : Pin number */
4351 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
4352 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
4353 
4354 /* Register: I2S_PSEL_LRCK */
4355 /* Description: Pin select for LRCK signal */
4356 
4357 /* Bit 31 : Connection */
4358 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4359 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4360 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
4361 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
4362 
4363 /* Bit 5 : Port number */
4364 #define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */
4365 #define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */
4366 
4367 /* Bits 4..0 : Pin number */
4368 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
4369 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
4370 
4371 /* Register: I2S_PSEL_SDIN */
4372 /* Description: Pin select for SDIN signal */
4373 
4374 /* Bit 31 : Connection */
4375 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4376 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4377 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
4378 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
4379 
4380 /* Bit 5 : Port number */
4381 #define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */
4382 #define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */
4383 
4384 /* Bits 4..0 : Pin number */
4385 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
4386 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
4387 
4388 /* Register: I2S_PSEL_SDOUT */
4389 /* Description: Pin select for SDOUT signal */
4390 
4391 /* Bit 31 : Connection */
4392 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4393 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4394 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
4395 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
4396 
4397 /* Bit 5 : Port number */
4398 #define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */
4399 #define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */
4400 
4401 /* Bits 4..0 : Pin number */
4402 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
4403 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
4404 
4405 
4406 /* Peripheral: IPC */
4407 /* Description: Interprocessor communication 0 */
4408 
4409 /* Register: IPC_TASKS_SEND */
4410 /* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */
4411 
4412 /* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */
4413 #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */
4414 #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */
4415 #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */
4416 
4417 /* Register: IPC_SUBSCRIBE_SEND */
4418 /* Description: Description collection: Subscribe configuration for task SEND[n] */
4419 
4420 /* Bit 31 :   */
4421 #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */
4422 #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */
4423 #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */
4424 #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */
4425 
4426 /* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */
4427 #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4428 #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4429 
4430 /* Register: IPC_EVENTS_RECEIVE */
4431 /* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
4432 
4433 /* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
4434 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */
4435 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */
4436 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */
4437 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL) /*!< Event generated */
4438 
4439 /* Register: IPC_PUBLISH_RECEIVE */
4440 /* Description: Description collection: Publish configuration for event RECEIVE[n] */
4441 
4442 /* Bit 31 :   */
4443 #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */
4444 #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */
4445 #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */
4446 #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */
4447 
4448 /* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to. */
4449 #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4450 #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4451 
4452 /* Register: IPC_INTEN */
4453 /* Description: Enable or disable interrupt */
4454 
4455 /* Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
4456 #define IPC_INTEN_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
4457 #define IPC_INTEN_RECEIVE15_Msk (0x1UL << IPC_INTEN_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
4458 #define IPC_INTEN_RECEIVE15_Disabled (0UL) /*!< Disable */
4459 #define IPC_INTEN_RECEIVE15_Enabled (1UL) /*!< Enable */
4460 
4461 /* Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
4462 #define IPC_INTEN_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
4463 #define IPC_INTEN_RECEIVE14_Msk (0x1UL << IPC_INTEN_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
4464 #define IPC_INTEN_RECEIVE14_Disabled (0UL) /*!< Disable */
4465 #define IPC_INTEN_RECEIVE14_Enabled (1UL) /*!< Enable */
4466 
4467 /* Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
4468 #define IPC_INTEN_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
4469 #define IPC_INTEN_RECEIVE13_Msk (0x1UL << IPC_INTEN_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
4470 #define IPC_INTEN_RECEIVE13_Disabled (0UL) /*!< Disable */
4471 #define IPC_INTEN_RECEIVE13_Enabled (1UL) /*!< Enable */
4472 
4473 /* Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
4474 #define IPC_INTEN_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
4475 #define IPC_INTEN_RECEIVE12_Msk (0x1UL << IPC_INTEN_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
4476 #define IPC_INTEN_RECEIVE12_Disabled (0UL) /*!< Disable */
4477 #define IPC_INTEN_RECEIVE12_Enabled (1UL) /*!< Enable */
4478 
4479 /* Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
4480 #define IPC_INTEN_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
4481 #define IPC_INTEN_RECEIVE11_Msk (0x1UL << IPC_INTEN_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
4482 #define IPC_INTEN_RECEIVE11_Disabled (0UL) /*!< Disable */
4483 #define IPC_INTEN_RECEIVE11_Enabled (1UL) /*!< Enable */
4484 
4485 /* Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
4486 #define IPC_INTEN_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
4487 #define IPC_INTEN_RECEIVE10_Msk (0x1UL << IPC_INTEN_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
4488 #define IPC_INTEN_RECEIVE10_Disabled (0UL) /*!< Disable */
4489 #define IPC_INTEN_RECEIVE10_Enabled (1UL) /*!< Enable */
4490 
4491 /* Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
4492 #define IPC_INTEN_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
4493 #define IPC_INTEN_RECEIVE9_Msk (0x1UL << IPC_INTEN_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
4494 #define IPC_INTEN_RECEIVE9_Disabled (0UL) /*!< Disable */
4495 #define IPC_INTEN_RECEIVE9_Enabled (1UL) /*!< Enable */
4496 
4497 /* Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
4498 #define IPC_INTEN_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
4499 #define IPC_INTEN_RECEIVE8_Msk (0x1UL << IPC_INTEN_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
4500 #define IPC_INTEN_RECEIVE8_Disabled (0UL) /*!< Disable */
4501 #define IPC_INTEN_RECEIVE8_Enabled (1UL) /*!< Enable */
4502 
4503 /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
4504 #define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
4505 #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
4506 #define IPC_INTEN_RECEIVE7_Disabled (0UL) /*!< Disable */
4507 #define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */
4508 
4509 /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
4510 #define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
4511 #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
4512 #define IPC_INTEN_RECEIVE6_Disabled (0UL) /*!< Disable */
4513 #define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */
4514 
4515 /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
4516 #define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
4517 #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
4518 #define IPC_INTEN_RECEIVE5_Disabled (0UL) /*!< Disable */
4519 #define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */
4520 
4521 /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
4522 #define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
4523 #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
4524 #define IPC_INTEN_RECEIVE4_Disabled (0UL) /*!< Disable */
4525 #define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */
4526 
4527 /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
4528 #define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
4529 #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
4530 #define IPC_INTEN_RECEIVE3_Disabled (0UL) /*!< Disable */
4531 #define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */
4532 
4533 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
4534 #define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
4535 #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
4536 #define IPC_INTEN_RECEIVE2_Disabled (0UL) /*!< Disable */
4537 #define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */
4538 
4539 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
4540 #define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
4541 #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
4542 #define IPC_INTEN_RECEIVE1_Disabled (0UL) /*!< Disable */
4543 #define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */
4544 
4545 /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
4546 #define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
4547 #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
4548 #define IPC_INTEN_RECEIVE0_Disabled (0UL) /*!< Disable */
4549 #define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */
4550 
4551 /* Register: IPC_INTENSET */
4552 /* Description: Enable interrupt */
4553 
4554 /* Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
4555 #define IPC_INTENSET_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
4556 #define IPC_INTENSET_RECEIVE15_Msk (0x1UL << IPC_INTENSET_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
4557 #define IPC_INTENSET_RECEIVE15_Disabled (0UL) /*!< Read: Disabled */
4558 #define IPC_INTENSET_RECEIVE15_Enabled (1UL) /*!< Read: Enabled */
4559 #define IPC_INTENSET_RECEIVE15_Set (1UL) /*!< Enable */
4560 
4561 /* Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
4562 #define IPC_INTENSET_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
4563 #define IPC_INTENSET_RECEIVE14_Msk (0x1UL << IPC_INTENSET_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
4564 #define IPC_INTENSET_RECEIVE14_Disabled (0UL) /*!< Read: Disabled */
4565 #define IPC_INTENSET_RECEIVE14_Enabled (1UL) /*!< Read: Enabled */
4566 #define IPC_INTENSET_RECEIVE14_Set (1UL) /*!< Enable */
4567 
4568 /* Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
4569 #define IPC_INTENSET_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
4570 #define IPC_INTENSET_RECEIVE13_Msk (0x1UL << IPC_INTENSET_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
4571 #define IPC_INTENSET_RECEIVE13_Disabled (0UL) /*!< Read: Disabled */
4572 #define IPC_INTENSET_RECEIVE13_Enabled (1UL) /*!< Read: Enabled */
4573 #define IPC_INTENSET_RECEIVE13_Set (1UL) /*!< Enable */
4574 
4575 /* Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
4576 #define IPC_INTENSET_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
4577 #define IPC_INTENSET_RECEIVE12_Msk (0x1UL << IPC_INTENSET_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
4578 #define IPC_INTENSET_RECEIVE12_Disabled (0UL) /*!< Read: Disabled */
4579 #define IPC_INTENSET_RECEIVE12_Enabled (1UL) /*!< Read: Enabled */
4580 #define IPC_INTENSET_RECEIVE12_Set (1UL) /*!< Enable */
4581 
4582 /* Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
4583 #define IPC_INTENSET_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
4584 #define IPC_INTENSET_RECEIVE11_Msk (0x1UL << IPC_INTENSET_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
4585 #define IPC_INTENSET_RECEIVE11_Disabled (0UL) /*!< Read: Disabled */
4586 #define IPC_INTENSET_RECEIVE11_Enabled (1UL) /*!< Read: Enabled */
4587 #define IPC_INTENSET_RECEIVE11_Set (1UL) /*!< Enable */
4588 
4589 /* Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
4590 #define IPC_INTENSET_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
4591 #define IPC_INTENSET_RECEIVE10_Msk (0x1UL << IPC_INTENSET_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
4592 #define IPC_INTENSET_RECEIVE10_Disabled (0UL) /*!< Read: Disabled */
4593 #define IPC_INTENSET_RECEIVE10_Enabled (1UL) /*!< Read: Enabled */
4594 #define IPC_INTENSET_RECEIVE10_Set (1UL) /*!< Enable */
4595 
4596 /* Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
4597 #define IPC_INTENSET_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
4598 #define IPC_INTENSET_RECEIVE9_Msk (0x1UL << IPC_INTENSET_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
4599 #define IPC_INTENSET_RECEIVE9_Disabled (0UL) /*!< Read: Disabled */
4600 #define IPC_INTENSET_RECEIVE9_Enabled (1UL) /*!< Read: Enabled */
4601 #define IPC_INTENSET_RECEIVE9_Set (1UL) /*!< Enable */
4602 
4603 /* Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
4604 #define IPC_INTENSET_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
4605 #define IPC_INTENSET_RECEIVE8_Msk (0x1UL << IPC_INTENSET_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
4606 #define IPC_INTENSET_RECEIVE8_Disabled (0UL) /*!< Read: Disabled */
4607 #define IPC_INTENSET_RECEIVE8_Enabled (1UL) /*!< Read: Enabled */
4608 #define IPC_INTENSET_RECEIVE8_Set (1UL) /*!< Enable */
4609 
4610 /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
4611 #define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
4612 #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
4613 #define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
4614 #define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
4615 #define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */
4616 
4617 /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
4618 #define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
4619 #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
4620 #define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
4621 #define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
4622 #define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */
4623 
4624 /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
4625 #define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
4626 #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
4627 #define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
4628 #define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
4629 #define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */
4630 
4631 /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
4632 #define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
4633 #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
4634 #define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
4635 #define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
4636 #define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */
4637 
4638 /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
4639 #define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
4640 #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
4641 #define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
4642 #define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
4643 #define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */
4644 
4645 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
4646 #define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
4647 #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
4648 #define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
4649 #define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
4650 #define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */
4651 
4652 /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
4653 #define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
4654 #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
4655 #define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
4656 #define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
4657 #define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */
4658 
4659 /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
4660 #define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
4661 #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
4662 #define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
4663 #define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
4664 #define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */
4665 
4666 /* Register: IPC_INTENCLR */
4667 /* Description: Disable interrupt */
4668 
4669 /* Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
4670 #define IPC_INTENCLR_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
4671 #define IPC_INTENCLR_RECEIVE15_Msk (0x1UL << IPC_INTENCLR_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
4672 #define IPC_INTENCLR_RECEIVE15_Disabled (0UL) /*!< Read: Disabled */
4673 #define IPC_INTENCLR_RECEIVE15_Enabled (1UL) /*!< Read: Enabled */
4674 #define IPC_INTENCLR_RECEIVE15_Clear (1UL) /*!< Disable */
4675 
4676 /* Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
4677 #define IPC_INTENCLR_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
4678 #define IPC_INTENCLR_RECEIVE14_Msk (0x1UL << IPC_INTENCLR_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
4679 #define IPC_INTENCLR_RECEIVE14_Disabled (0UL) /*!< Read: Disabled */
4680 #define IPC_INTENCLR_RECEIVE14_Enabled (1UL) /*!< Read: Enabled */
4681 #define IPC_INTENCLR_RECEIVE14_Clear (1UL) /*!< Disable */
4682 
4683 /* Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
4684 #define IPC_INTENCLR_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
4685 #define IPC_INTENCLR_RECEIVE13_Msk (0x1UL << IPC_INTENCLR_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
4686 #define IPC_INTENCLR_RECEIVE13_Disabled (0UL) /*!< Read: Disabled */
4687 #define IPC_INTENCLR_RECEIVE13_Enabled (1UL) /*!< Read: Enabled */
4688 #define IPC_INTENCLR_RECEIVE13_Clear (1UL) /*!< Disable */
4689 
4690 /* Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
4691 #define IPC_INTENCLR_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
4692 #define IPC_INTENCLR_RECEIVE12_Msk (0x1UL << IPC_INTENCLR_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
4693 #define IPC_INTENCLR_RECEIVE12_Disabled (0UL) /*!< Read: Disabled */
4694 #define IPC_INTENCLR_RECEIVE12_Enabled (1UL) /*!< Read: Enabled */
4695 #define IPC_INTENCLR_RECEIVE12_Clear (1UL) /*!< Disable */
4696 
4697 /* Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
4698 #define IPC_INTENCLR_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
4699 #define IPC_INTENCLR_RECEIVE11_Msk (0x1UL << IPC_INTENCLR_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
4700 #define IPC_INTENCLR_RECEIVE11_Disabled (0UL) /*!< Read: Disabled */
4701 #define IPC_INTENCLR_RECEIVE11_Enabled (1UL) /*!< Read: Enabled */
4702 #define IPC_INTENCLR_RECEIVE11_Clear (1UL) /*!< Disable */
4703 
4704 /* Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
4705 #define IPC_INTENCLR_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
4706 #define IPC_INTENCLR_RECEIVE10_Msk (0x1UL << IPC_INTENCLR_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
4707 #define IPC_INTENCLR_RECEIVE10_Disabled (0UL) /*!< Read: Disabled */
4708 #define IPC_INTENCLR_RECEIVE10_Enabled (1UL) /*!< Read: Enabled */
4709 #define IPC_INTENCLR_RECEIVE10_Clear (1UL) /*!< Disable */
4710 
4711 /* Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
4712 #define IPC_INTENCLR_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
4713 #define IPC_INTENCLR_RECEIVE9_Msk (0x1UL << IPC_INTENCLR_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
4714 #define IPC_INTENCLR_RECEIVE9_Disabled (0UL) /*!< Read: Disabled */
4715 #define IPC_INTENCLR_RECEIVE9_Enabled (1UL) /*!< Read: Enabled */
4716 #define IPC_INTENCLR_RECEIVE9_Clear (1UL) /*!< Disable */
4717 
4718 /* Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
4719 #define IPC_INTENCLR_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
4720 #define IPC_INTENCLR_RECEIVE8_Msk (0x1UL << IPC_INTENCLR_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
4721 #define IPC_INTENCLR_RECEIVE8_Disabled (0UL) /*!< Read: Disabled */
4722 #define IPC_INTENCLR_RECEIVE8_Enabled (1UL) /*!< Read: Enabled */
4723 #define IPC_INTENCLR_RECEIVE8_Clear (1UL) /*!< Disable */
4724 
4725 /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
4726 #define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
4727 #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
4728 #define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
4729 #define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
4730 #define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */
4731 
4732 /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
4733 #define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
4734 #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
4735 #define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
4736 #define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
4737 #define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */
4738 
4739 /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
4740 #define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
4741 #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
4742 #define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
4743 #define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
4744 #define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */
4745 
4746 /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
4747 #define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
4748 #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
4749 #define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
4750 #define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
4751 #define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */
4752 
4753 /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
4754 #define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
4755 #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
4756 #define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
4757 #define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
4758 #define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */
4759 
4760 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
4761 #define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
4762 #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
4763 #define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
4764 #define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
4765 #define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */
4766 
4767 /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
4768 #define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
4769 #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
4770 #define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
4771 #define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
4772 #define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */
4773 
4774 /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
4775 #define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
4776 #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
4777 #define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
4778 #define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
4779 #define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */
4780 
4781 /* Register: IPC_INTPEND */
4782 /* Description: Pending interrupts */
4783 
4784 /* Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
4785 #define IPC_INTPEND_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */
4786 #define IPC_INTPEND_RECEIVE15_Msk (0x1UL << IPC_INTPEND_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */
4787 #define IPC_INTPEND_RECEIVE15_NotPending (0UL) /*!< Read: Not pending */
4788 #define IPC_INTPEND_RECEIVE15_Pending (1UL) /*!< Read: Pending */
4789 
4790 /* Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
4791 #define IPC_INTPEND_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */
4792 #define IPC_INTPEND_RECEIVE14_Msk (0x1UL << IPC_INTPEND_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */
4793 #define IPC_INTPEND_RECEIVE14_NotPending (0UL) /*!< Read: Not pending */
4794 #define IPC_INTPEND_RECEIVE14_Pending (1UL) /*!< Read: Pending */
4795 
4796 /* Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
4797 #define IPC_INTPEND_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */
4798 #define IPC_INTPEND_RECEIVE13_Msk (0x1UL << IPC_INTPEND_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */
4799 #define IPC_INTPEND_RECEIVE13_NotPending (0UL) /*!< Read: Not pending */
4800 #define IPC_INTPEND_RECEIVE13_Pending (1UL) /*!< Read: Pending */
4801 
4802 /* Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
4803 #define IPC_INTPEND_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */
4804 #define IPC_INTPEND_RECEIVE12_Msk (0x1UL << IPC_INTPEND_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */
4805 #define IPC_INTPEND_RECEIVE12_NotPending (0UL) /*!< Read: Not pending */
4806 #define IPC_INTPEND_RECEIVE12_Pending (1UL) /*!< Read: Pending */
4807 
4808 /* Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
4809 #define IPC_INTPEND_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */
4810 #define IPC_INTPEND_RECEIVE11_Msk (0x1UL << IPC_INTPEND_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */
4811 #define IPC_INTPEND_RECEIVE11_NotPending (0UL) /*!< Read: Not pending */
4812 #define IPC_INTPEND_RECEIVE11_Pending (1UL) /*!< Read: Pending */
4813 
4814 /* Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
4815 #define IPC_INTPEND_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */
4816 #define IPC_INTPEND_RECEIVE10_Msk (0x1UL << IPC_INTPEND_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */
4817 #define IPC_INTPEND_RECEIVE10_NotPending (0UL) /*!< Read: Not pending */
4818 #define IPC_INTPEND_RECEIVE10_Pending (1UL) /*!< Read: Pending */
4819 
4820 /* Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
4821 #define IPC_INTPEND_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */
4822 #define IPC_INTPEND_RECEIVE9_Msk (0x1UL << IPC_INTPEND_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */
4823 #define IPC_INTPEND_RECEIVE9_NotPending (0UL) /*!< Read: Not pending */
4824 #define IPC_INTPEND_RECEIVE9_Pending (1UL) /*!< Read: Pending */
4825 
4826 /* Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
4827 #define IPC_INTPEND_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */
4828 #define IPC_INTPEND_RECEIVE8_Msk (0x1UL << IPC_INTPEND_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */
4829 #define IPC_INTPEND_RECEIVE8_NotPending (0UL) /*!< Read: Not pending */
4830 #define IPC_INTPEND_RECEIVE8_Pending (1UL) /*!< Read: Pending */
4831 
4832 /* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
4833 #define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
4834 #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
4835 #define IPC_INTPEND_RECEIVE7_NotPending (0UL) /*!< Read: Not pending */
4836 #define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */
4837 
4838 /* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
4839 #define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
4840 #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
4841 #define IPC_INTPEND_RECEIVE6_NotPending (0UL) /*!< Read: Not pending */
4842 #define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */
4843 
4844 /* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
4845 #define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
4846 #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
4847 #define IPC_INTPEND_RECEIVE5_NotPending (0UL) /*!< Read: Not pending */
4848 #define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */
4849 
4850 /* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
4851 #define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
4852 #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
4853 #define IPC_INTPEND_RECEIVE4_NotPending (0UL) /*!< Read: Not pending */
4854 #define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */
4855 
4856 /* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
4857 #define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
4858 #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
4859 #define IPC_INTPEND_RECEIVE3_NotPending (0UL) /*!< Read: Not pending */
4860 #define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */
4861 
4862 /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
4863 #define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
4864 #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
4865 #define IPC_INTPEND_RECEIVE2_NotPending (0UL) /*!< Read: Not pending */
4866 #define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */
4867 
4868 /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
4869 #define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
4870 #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
4871 #define IPC_INTPEND_RECEIVE1_NotPending (0UL) /*!< Read: Not pending */
4872 #define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */
4873 
4874 /* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
4875 #define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
4876 #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
4877 #define IPC_INTPEND_RECEIVE0_NotPending (0UL) /*!< Read: Not pending */
4878 #define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */
4879 
4880 /* Register: IPC_SEND_CNF */
4881 /* Description: Description collection: Send event configuration for TASKS_SEND[n] */
4882 
4883 /* Bit 15 : Enable broadcasting on IPC channel 15 */
4884 #define IPC_SEND_CNF_CHEN15_Pos (15UL) /*!< Position of CHEN15 field. */
4885 #define IPC_SEND_CNF_CHEN15_Msk (0x1UL << IPC_SEND_CNF_CHEN15_Pos) /*!< Bit mask of CHEN15 field. */
4886 #define IPC_SEND_CNF_CHEN15_Disable (0UL) /*!< Disable broadcast */
4887 #define IPC_SEND_CNF_CHEN15_Enable (1UL) /*!< Enable broadcast */
4888 
4889 /* Bit 14 : Enable broadcasting on IPC channel 14 */
4890 #define IPC_SEND_CNF_CHEN14_Pos (14UL) /*!< Position of CHEN14 field. */
4891 #define IPC_SEND_CNF_CHEN14_Msk (0x1UL << IPC_SEND_CNF_CHEN14_Pos) /*!< Bit mask of CHEN14 field. */
4892 #define IPC_SEND_CNF_CHEN14_Disable (0UL) /*!< Disable broadcast */
4893 #define IPC_SEND_CNF_CHEN14_Enable (1UL) /*!< Enable broadcast */
4894 
4895 /* Bit 13 : Enable broadcasting on IPC channel 13 */
4896 #define IPC_SEND_CNF_CHEN13_Pos (13UL) /*!< Position of CHEN13 field. */
4897 #define IPC_SEND_CNF_CHEN13_Msk (0x1UL << IPC_SEND_CNF_CHEN13_Pos) /*!< Bit mask of CHEN13 field. */
4898 #define IPC_SEND_CNF_CHEN13_Disable (0UL) /*!< Disable broadcast */
4899 #define IPC_SEND_CNF_CHEN13_Enable (1UL) /*!< Enable broadcast */
4900 
4901 /* Bit 12 : Enable broadcasting on IPC channel 12 */
4902 #define IPC_SEND_CNF_CHEN12_Pos (12UL) /*!< Position of CHEN12 field. */
4903 #define IPC_SEND_CNF_CHEN12_Msk (0x1UL << IPC_SEND_CNF_CHEN12_Pos) /*!< Bit mask of CHEN12 field. */
4904 #define IPC_SEND_CNF_CHEN12_Disable (0UL) /*!< Disable broadcast */
4905 #define IPC_SEND_CNF_CHEN12_Enable (1UL) /*!< Enable broadcast */
4906 
4907 /* Bit 11 : Enable broadcasting on IPC channel 11 */
4908 #define IPC_SEND_CNF_CHEN11_Pos (11UL) /*!< Position of CHEN11 field. */
4909 #define IPC_SEND_CNF_CHEN11_Msk (0x1UL << IPC_SEND_CNF_CHEN11_Pos) /*!< Bit mask of CHEN11 field. */
4910 #define IPC_SEND_CNF_CHEN11_Disable (0UL) /*!< Disable broadcast */
4911 #define IPC_SEND_CNF_CHEN11_Enable (1UL) /*!< Enable broadcast */
4912 
4913 /* Bit 10 : Enable broadcasting on IPC channel 10 */
4914 #define IPC_SEND_CNF_CHEN10_Pos (10UL) /*!< Position of CHEN10 field. */
4915 #define IPC_SEND_CNF_CHEN10_Msk (0x1UL << IPC_SEND_CNF_CHEN10_Pos) /*!< Bit mask of CHEN10 field. */
4916 #define IPC_SEND_CNF_CHEN10_Disable (0UL) /*!< Disable broadcast */
4917 #define IPC_SEND_CNF_CHEN10_Enable (1UL) /*!< Enable broadcast */
4918 
4919 /* Bit 9 : Enable broadcasting on IPC channel 9 */
4920 #define IPC_SEND_CNF_CHEN9_Pos (9UL) /*!< Position of CHEN9 field. */
4921 #define IPC_SEND_CNF_CHEN9_Msk (0x1UL << IPC_SEND_CNF_CHEN9_Pos) /*!< Bit mask of CHEN9 field. */
4922 #define IPC_SEND_CNF_CHEN9_Disable (0UL) /*!< Disable broadcast */
4923 #define IPC_SEND_CNF_CHEN9_Enable (1UL) /*!< Enable broadcast */
4924 
4925 /* Bit 8 : Enable broadcasting on IPC channel 8 */
4926 #define IPC_SEND_CNF_CHEN8_Pos (8UL) /*!< Position of CHEN8 field. */
4927 #define IPC_SEND_CNF_CHEN8_Msk (0x1UL << IPC_SEND_CNF_CHEN8_Pos) /*!< Bit mask of CHEN8 field. */
4928 #define IPC_SEND_CNF_CHEN8_Disable (0UL) /*!< Disable broadcast */
4929 #define IPC_SEND_CNF_CHEN8_Enable (1UL) /*!< Enable broadcast */
4930 
4931 /* Bit 7 : Enable broadcasting on IPC channel 7 */
4932 #define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
4933 #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
4934 #define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast */
4935 #define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast */
4936 
4937 /* Bit 6 : Enable broadcasting on IPC channel 6 */
4938 #define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
4939 #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
4940 #define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast */
4941 #define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast */
4942 
4943 /* Bit 5 : Enable broadcasting on IPC channel 5 */
4944 #define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
4945 #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
4946 #define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast */
4947 #define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast */
4948 
4949 /* Bit 4 : Enable broadcasting on IPC channel 4 */
4950 #define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
4951 #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
4952 #define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast */
4953 #define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast */
4954 
4955 /* Bit 3 : Enable broadcasting on IPC channel 3 */
4956 #define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
4957 #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
4958 #define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast */
4959 #define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast */
4960 
4961 /* Bit 2 : Enable broadcasting on IPC channel 2 */
4962 #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
4963 #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
4964 #define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast */
4965 #define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast */
4966 
4967 /* Bit 1 : Enable broadcasting on IPC channel 1 */
4968 #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
4969 #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
4970 #define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast */
4971 #define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast */
4972 
4973 /* Bit 0 : Enable broadcasting on IPC channel 0 */
4974 #define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
4975 #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
4976 #define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast */
4977 #define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast */
4978 
4979 /* Register: IPC_RECEIVE_CNF */
4980 /* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */
4981 
4982 /* Bit 15 : Enable subscription to IPC channel 15 */
4983 #define IPC_RECEIVE_CNF_CHEN15_Pos (15UL) /*!< Position of CHEN15 field. */
4984 #define IPC_RECEIVE_CNF_CHEN15_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN15_Pos) /*!< Bit mask of CHEN15 field. */
4985 #define IPC_RECEIVE_CNF_CHEN15_Disable (0UL) /*!< Disable events */
4986 #define IPC_RECEIVE_CNF_CHEN15_Enable (1UL) /*!< Enable events */
4987 
4988 /* Bit 14 : Enable subscription to IPC channel 14 */
4989 #define IPC_RECEIVE_CNF_CHEN14_Pos (14UL) /*!< Position of CHEN14 field. */
4990 #define IPC_RECEIVE_CNF_CHEN14_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN14_Pos) /*!< Bit mask of CHEN14 field. */
4991 #define IPC_RECEIVE_CNF_CHEN14_Disable (0UL) /*!< Disable events */
4992 #define IPC_RECEIVE_CNF_CHEN14_Enable (1UL) /*!< Enable events */
4993 
4994 /* Bit 13 : Enable subscription to IPC channel 13 */
4995 #define IPC_RECEIVE_CNF_CHEN13_Pos (13UL) /*!< Position of CHEN13 field. */
4996 #define IPC_RECEIVE_CNF_CHEN13_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN13_Pos) /*!< Bit mask of CHEN13 field. */
4997 #define IPC_RECEIVE_CNF_CHEN13_Disable (0UL) /*!< Disable events */
4998 #define IPC_RECEIVE_CNF_CHEN13_Enable (1UL) /*!< Enable events */
4999 
5000 /* Bit 12 : Enable subscription to IPC channel 12 */
5001 #define IPC_RECEIVE_CNF_CHEN12_Pos (12UL) /*!< Position of CHEN12 field. */
5002 #define IPC_RECEIVE_CNF_CHEN12_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN12_Pos) /*!< Bit mask of CHEN12 field. */
5003 #define IPC_RECEIVE_CNF_CHEN12_Disable (0UL) /*!< Disable events */
5004 #define IPC_RECEIVE_CNF_CHEN12_Enable (1UL) /*!< Enable events */
5005 
5006 /* Bit 11 : Enable subscription to IPC channel 11 */
5007 #define IPC_RECEIVE_CNF_CHEN11_Pos (11UL) /*!< Position of CHEN11 field. */
5008 #define IPC_RECEIVE_CNF_CHEN11_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN11_Pos) /*!< Bit mask of CHEN11 field. */
5009 #define IPC_RECEIVE_CNF_CHEN11_Disable (0UL) /*!< Disable events */
5010 #define IPC_RECEIVE_CNF_CHEN11_Enable (1UL) /*!< Enable events */
5011 
5012 /* Bit 10 : Enable subscription to IPC channel 10 */
5013 #define IPC_RECEIVE_CNF_CHEN10_Pos (10UL) /*!< Position of CHEN10 field. */
5014 #define IPC_RECEIVE_CNF_CHEN10_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN10_Pos) /*!< Bit mask of CHEN10 field. */
5015 #define IPC_RECEIVE_CNF_CHEN10_Disable (0UL) /*!< Disable events */
5016 #define IPC_RECEIVE_CNF_CHEN10_Enable (1UL) /*!< Enable events */
5017 
5018 /* Bit 9 : Enable subscription to IPC channel 9 */
5019 #define IPC_RECEIVE_CNF_CHEN9_Pos (9UL) /*!< Position of CHEN9 field. */
5020 #define IPC_RECEIVE_CNF_CHEN9_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN9_Pos) /*!< Bit mask of CHEN9 field. */
5021 #define IPC_RECEIVE_CNF_CHEN9_Disable (0UL) /*!< Disable events */
5022 #define IPC_RECEIVE_CNF_CHEN9_Enable (1UL) /*!< Enable events */
5023 
5024 /* Bit 8 : Enable subscription to IPC channel 8 */
5025 #define IPC_RECEIVE_CNF_CHEN8_Pos (8UL) /*!< Position of CHEN8 field. */
5026 #define IPC_RECEIVE_CNF_CHEN8_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN8_Pos) /*!< Bit mask of CHEN8 field. */
5027 #define IPC_RECEIVE_CNF_CHEN8_Disable (0UL) /*!< Disable events */
5028 #define IPC_RECEIVE_CNF_CHEN8_Enable (1UL) /*!< Enable events */
5029 
5030 /* Bit 7 : Enable subscription to IPC channel 7 */
5031 #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
5032 #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
5033 #define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events */
5034 #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events */
5035 
5036 /* Bit 6 : Enable subscription to IPC channel 6 */
5037 #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
5038 #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
5039 #define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events */
5040 #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events */
5041 
5042 /* Bit 5 : Enable subscription to IPC channel 5 */
5043 #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
5044 #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
5045 #define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events */
5046 #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events */
5047 
5048 /* Bit 4 : Enable subscription to IPC channel 4 */
5049 #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
5050 #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
5051 #define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events */
5052 #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events */
5053 
5054 /* Bit 3 : Enable subscription to IPC channel 3 */
5055 #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
5056 #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
5057 #define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events */
5058 #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events */
5059 
5060 /* Bit 2 : Enable subscription to IPC channel 2 */
5061 #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
5062 #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
5063 #define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events */
5064 #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events */
5065 
5066 /* Bit 1 : Enable subscription to IPC channel 1 */
5067 #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
5068 #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
5069 #define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events */
5070 #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events */
5071 
5072 /* Bit 0 : Enable subscription to IPC channel 0 */
5073 #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
5074 #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
5075 #define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events */
5076 #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events */
5077 
5078 /* Register: IPC_GPMEM */
5079 /* Description: Description collection: General purpose memory */
5080 
5081 /* Bits 31..0 : General purpose memory */
5082 #define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */
5083 #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */
5084 
5085 
5086 /* Peripheral: KMU */
5087 /* Description: Key management unit 0 */
5088 
5089 /* Register: KMU_TASKS_PUSH_KEYSLOT */
5090 /* Description: Push a key slot over secure APB */
5091 
5092 /* Bit 0 : Push a key slot over secure APB */
5093 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */
5094 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */
5095 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL) /*!< Trigger task */
5096 
5097 /* Register: KMU_EVENTS_KEYSLOT_PUSHED */
5098 /* Description: Key slot successfully pushed over secure APB */
5099 
5100 /* Bit 0 : Key slot successfully pushed over secure APB */
5101 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */
5102 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */
5103 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL) /*!< Event not generated */
5104 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL) /*!< Event generated */
5105 
5106 /* Register: KMU_EVENTS_KEYSLOT_REVOKED */
5107 /* Description: Key slot has been revoked and cannot be tasked for selection */
5108 
5109 /* Bit 0 : Key slot has been revoked and cannot be tasked for selection */
5110 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */
5111 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */
5112 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL) /*!< Event not generated */
5113 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL) /*!< Event generated */
5114 
5115 /* Register: KMU_EVENTS_KEYSLOT_ERROR */
5116 /* Description: No key slot selected, no destination address defined, or error during push operation */
5117 
5118 /* Bit 0 : No key slot selected, no destination address defined, or error during push operation */
5119 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */
5120 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */
5121 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0UL) /*!< Event not generated */
5122 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL) /*!< Event generated */
5123 
5124 /* Register: KMU_INTEN */
5125 /* Description: Enable or disable interrupt */
5126 
5127 /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */
5128 #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
5129 #define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
5130 #define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL) /*!< Disable */
5131 #define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL) /*!< Enable */
5132 
5133 /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */
5134 #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
5135 #define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
5136 #define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL) /*!< Disable */
5137 #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL) /*!< Enable */
5138 
5139 /* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */
5140 #define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
5141 #define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
5142 #define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL) /*!< Disable */
5143 #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL) /*!< Enable */
5144 
5145 /* Register: KMU_INTENSET */
5146 /* Description: Enable interrupt */
5147 
5148 /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */
5149 #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
5150 #define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
5151 #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
5152 #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
5153 #define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL) /*!< Enable */
5154 
5155 /* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */
5156 #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
5157 #define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
5158 #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
5159 #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
5160 #define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL) /*!< Enable */
5161 
5162 /* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */
5163 #define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
5164 #define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
5165 #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
5166 #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
5167 #define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL) /*!< Enable */
5168 
5169 /* Register: KMU_INTENCLR */
5170 /* Description: Disable interrupt */
5171 
5172 /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */
5173 #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
5174 #define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
5175 #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
5176 #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
5177 #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL) /*!< Disable */
5178 
5179 /* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */
5180 #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
5181 #define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
5182 #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
5183 #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
5184 #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL) /*!< Disable */
5185 
5186 /* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */
5187 #define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
5188 #define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
5189 #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
5190 #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
5191 #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL) /*!< Disable */
5192 
5193 /* Register: KMU_INTPEND */
5194 /* Description: Pending interrupts */
5195 
5196 /* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */
5197 #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
5198 #define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
5199 #define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL) /*!< Read: Not pending */
5200 #define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL) /*!< Read: Pending */
5201 
5202 /* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */
5203 #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
5204 #define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
5205 #define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL) /*!< Read: Not pending */
5206 #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL) /*!< Read: Pending */
5207 
5208 /* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */
5209 #define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
5210 #define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
5211 #define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL) /*!< Read: Not pending */
5212 #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL) /*!< Read: Pending */
5213 
5214 /* Register: KMU_STATUS */
5215 /* Description: Status bits for KMU operation */
5216 
5217 /* Bit 1 : Violation status */
5218 #define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */
5219 #define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */
5220 #define KMU_STATUS_BLOCKED_Disabled (0UL) /*!< No access violation detected */
5221 #define KMU_STATUS_BLOCKED_Enabled (1UL) /*!< Access violation detected and blocked */
5222 
5223 /* Bit 0 : Key slot ID successfully selected by the KMU */
5224 #define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */
5225 #define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
5226 #define KMU_STATUS_SELECTED_Disabled (0UL) /*!< No key slot ID selected by KMU */
5227 #define KMU_STATUS_SELECTED_Enabled (1UL) /*!< Key slot ID successfully selected by KMU */
5228 
5229 /* Register: KMU_SELECTKEYSLOT */
5230 /* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */
5231 
5232 /* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */
5233 #define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */
5234 #define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */
5235 
5236 
5237 /* Peripheral: LPCOMP */
5238 /* Description: Low-power comparator 0 */
5239 
5240 /* Register: LPCOMP_TASKS_START */
5241 /* Description: Start comparator */
5242 
5243 /* Bit 0 : Start comparator */
5244 #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5245 #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5246 #define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5247 
5248 /* Register: LPCOMP_TASKS_STOP */
5249 /* Description: Stop comparator */
5250 
5251 /* Bit 0 : Stop comparator */
5252 #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5253 #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5254 #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5255 
5256 /* Register: LPCOMP_TASKS_SAMPLE */
5257 /* Description: Sample comparator value */
5258 
5259 /* Bit 0 : Sample comparator value */
5260 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
5261 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
5262 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
5263 
5264 /* Register: LPCOMP_SUBSCRIBE_START */
5265 /* Description: Subscribe configuration for task START */
5266 
5267 /* Bit 31 :   */
5268 #define LPCOMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
5269 #define LPCOMP_SUBSCRIBE_START_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
5270 #define LPCOMP_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5271 #define LPCOMP_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5272 
5273 /* Bits 7..0 : DPPI channel that task START will subscribe to */
5274 #define LPCOMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5275 #define LPCOMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5276 
5277 /* Register: LPCOMP_SUBSCRIBE_STOP */
5278 /* Description: Subscribe configuration for task STOP */
5279 
5280 /* Bit 31 :   */
5281 #define LPCOMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
5282 #define LPCOMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
5283 #define LPCOMP_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5284 #define LPCOMP_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5285 
5286 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
5287 #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5288 #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5289 
5290 /* Register: LPCOMP_SUBSCRIBE_SAMPLE */
5291 /* Description: Subscribe configuration for task SAMPLE */
5292 
5293 /* Bit 31 :   */
5294 #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
5295 #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
5296 #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */
5297 #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */
5298 
5299 /* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
5300 #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5301 #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5302 
5303 /* Register: LPCOMP_EVENTS_READY */
5304 /* Description: LPCOMP is ready and output is valid */
5305 
5306 /* Bit 0 : LPCOMP is ready and output is valid */
5307 #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
5308 #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
5309 #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
5310 #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
5311 
5312 /* Register: LPCOMP_EVENTS_DOWN */
5313 /* Description: Downward crossing */
5314 
5315 /* Bit 0 : Downward crossing */
5316 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
5317 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
5318 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
5319 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
5320 
5321 /* Register: LPCOMP_EVENTS_UP */
5322 /* Description: Upward crossing */
5323 
5324 /* Bit 0 : Upward crossing */
5325 #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
5326 #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
5327 #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
5328 #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
5329 
5330 /* Register: LPCOMP_EVENTS_CROSS */
5331 /* Description: Downward or upward crossing */
5332 
5333 /* Bit 0 : Downward or upward crossing */
5334 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
5335 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
5336 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
5337 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
5338 
5339 /* Register: LPCOMP_PUBLISH_READY */
5340 /* Description: Publish configuration for event READY */
5341 
5342 /* Bit 31 :   */
5343 #define LPCOMP_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
5344 #define LPCOMP_PUBLISH_READY_EN_Msk (0x1UL << LPCOMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
5345 #define LPCOMP_PUBLISH_READY_EN_Disabled (0UL) /*!< Disable publishing */
5346 #define LPCOMP_PUBLISH_READY_EN_Enabled (1UL) /*!< Enable publishing */
5347 
5348 /* Bits 7..0 : DPPI channel that event READY will publish to. */
5349 #define LPCOMP_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5350 #define LPCOMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5351 
5352 /* Register: LPCOMP_PUBLISH_DOWN */
5353 /* Description: Publish configuration for event DOWN */
5354 
5355 /* Bit 31 :   */
5356 #define LPCOMP_PUBLISH_DOWN_EN_Pos (31UL) /*!< Position of EN field. */
5357 #define LPCOMP_PUBLISH_DOWN_EN_Msk (0x1UL << LPCOMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field. */
5358 #define LPCOMP_PUBLISH_DOWN_EN_Disabled (0UL) /*!< Disable publishing */
5359 #define LPCOMP_PUBLISH_DOWN_EN_Enabled (1UL) /*!< Enable publishing */
5360 
5361 /* Bits 7..0 : DPPI channel that event DOWN will publish to. */
5362 #define LPCOMP_PUBLISH_DOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5363 #define LPCOMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5364 
5365 /* Register: LPCOMP_PUBLISH_UP */
5366 /* Description: Publish configuration for event UP */
5367 
5368 /* Bit 31 :   */
5369 #define LPCOMP_PUBLISH_UP_EN_Pos (31UL) /*!< Position of EN field. */
5370 #define LPCOMP_PUBLISH_UP_EN_Msk (0x1UL << LPCOMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field. */
5371 #define LPCOMP_PUBLISH_UP_EN_Disabled (0UL) /*!< Disable publishing */
5372 #define LPCOMP_PUBLISH_UP_EN_Enabled (1UL) /*!< Enable publishing */
5373 
5374 /* Bits 7..0 : DPPI channel that event UP will publish to. */
5375 #define LPCOMP_PUBLISH_UP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5376 #define LPCOMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5377 
5378 /* Register: LPCOMP_PUBLISH_CROSS */
5379 /* Description: Publish configuration for event CROSS */
5380 
5381 /* Bit 31 :   */
5382 #define LPCOMP_PUBLISH_CROSS_EN_Pos (31UL) /*!< Position of EN field. */
5383 #define LPCOMP_PUBLISH_CROSS_EN_Msk (0x1UL << LPCOMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field. */
5384 #define LPCOMP_PUBLISH_CROSS_EN_Disabled (0UL) /*!< Disable publishing */
5385 #define LPCOMP_PUBLISH_CROSS_EN_Enabled (1UL) /*!< Enable publishing */
5386 
5387 /* Bits 7..0 : DPPI channel that event CROSS will publish to. */
5388 #define LPCOMP_PUBLISH_CROSS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5389 #define LPCOMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5390 
5391 /* Register: LPCOMP_SHORTS */
5392 /* Description: Shortcuts between local events and tasks */
5393 
5394 /* Bit 4 : Shortcut between event CROSS and task STOP */
5395 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
5396 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
5397 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
5398 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
5399 
5400 /* Bit 3 : Shortcut between event UP and task STOP */
5401 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
5402 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
5403 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
5404 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
5405 
5406 /* Bit 2 : Shortcut between event DOWN and task STOP */
5407 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
5408 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
5409 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
5410 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
5411 
5412 /* Bit 1 : Shortcut between event READY and task STOP */
5413 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
5414 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
5415 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
5416 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
5417 
5418 /* Bit 0 : Shortcut between event READY and task SAMPLE */
5419 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
5420 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
5421 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
5422 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
5423 
5424 /* Register: LPCOMP_INTENSET */
5425 /* Description: Enable interrupt */
5426 
5427 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
5428 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
5429 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
5430 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
5431 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
5432 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
5433 
5434 /* Bit 2 : Write '1' to enable interrupt for event UP */
5435 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
5436 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
5437 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
5438 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
5439 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
5440 
5441 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
5442 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
5443 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
5444 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
5445 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
5446 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
5447 
5448 /* Bit 0 : Write '1' to enable interrupt for event READY */
5449 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
5450 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
5451 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
5452 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
5453 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
5454 
5455 /* Register: LPCOMP_INTENCLR */
5456 /* Description: Disable interrupt */
5457 
5458 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
5459 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
5460 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
5461 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
5462 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
5463 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
5464 
5465 /* Bit 2 : Write '1' to disable interrupt for event UP */
5466 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
5467 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
5468 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
5469 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
5470 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
5471 
5472 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
5473 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
5474 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
5475 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
5476 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
5477 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
5478 
5479 /* Bit 0 : Write '1' to disable interrupt for event READY */
5480 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
5481 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
5482 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
5483 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
5484 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
5485 
5486 /* Register: LPCOMP_RESULT */
5487 /* Description: Compare result */
5488 
5489 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
5490 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
5491 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
5492 #define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-) */
5493 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-) */
5494 
5495 /* Register: LPCOMP_ENABLE */
5496 /* Description: Enable LPCOMP */
5497 
5498 /* Bits 1..0 : Enable or disable LPCOMP */
5499 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5500 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5501 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
5502 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5503 
5504 /* Register: LPCOMP_PSEL */
5505 /* Description: Input pin select */
5506 
5507 /* Bits 2..0 : Analog pin select */
5508 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
5509 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
5510 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
5511 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
5512 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
5513 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
5514 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
5515 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
5516 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
5517 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
5518 
5519 /* Register: LPCOMP_REFSEL */
5520 /* Description: Reference select */
5521 
5522 /* Bits 3..0 : Reference select */
5523 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
5524 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
5525 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
5526 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
5527 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
5528 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
5529 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
5530 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
5531 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
5532 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
5533 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
5534 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
5535 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
5536 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
5537 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
5538 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
5539 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
5540 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
5541 
5542 /* Register: LPCOMP_EXTREFSEL */
5543 /* Description: External reference select */
5544 
5545 /* Bit 0 : External analog reference select */
5546 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
5547 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
5548 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
5549 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
5550 
5551 /* Register: LPCOMP_ANADETECT */
5552 /* Description: Analog detect configuration */
5553 
5554 /* Bits 1..0 : Analog detect configuration */
5555 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
5556 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
5557 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
5558 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
5559 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
5560 
5561 /* Register: LPCOMP_HYST */
5562 /* Description: Comparator hysteresis enable */
5563 
5564 /* Bit 0 : Comparator hysteresis enable */
5565 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
5566 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
5567 #define LPCOMP_HYST_HYST_Disabled (0UL) /*!< Comparator hysteresis disabled */
5568 #define LPCOMP_HYST_HYST_Enabled (1UL) /*!< Comparator hysteresis enabled */
5569 
5570 
5571 /* Peripheral: MUTEX */
5572 /* Description: MUTEX 0 */
5573 
5574 /* Register: MUTEX_MUTEX */
5575 /* Description: Description collection: Mutex register */
5576 
5577 /* Bit 0 : Mutex register n */
5578 #define MUTEX_MUTEX_MUTEX_Pos (0UL) /*!< Position of MUTEX field. */
5579 #define MUTEX_MUTEX_MUTEX_Msk (0x1UL << MUTEX_MUTEX_MUTEX_Pos) /*!< Bit mask of MUTEX field. */
5580 #define MUTEX_MUTEX_MUTEX_Unlocked (0UL) /*!< Mutex n is in unlocked state */
5581 #define MUTEX_MUTEX_MUTEX_Locked (1UL) /*!< Mutex n is in locked state */
5582 
5583 
5584 /* Peripheral: NFCT */
5585 /* Description: NFC-A compatible radio 0 */
5586 
5587 /* Register: NFCT_TASKS_ACTIVATE */
5588 /* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
5589 
5590 /* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
5591 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
5592 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
5593 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */
5594 
5595 /* Register: NFCT_TASKS_DISABLE */
5596 /* Description: Disable NFCT peripheral */
5597 
5598 /* Bit 0 : Disable NFCT peripheral */
5599 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
5600 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
5601 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
5602 
5603 /* Register: NFCT_TASKS_SENSE */
5604 /* Description: Enable NFC sense field mode, change state to sense mode */
5605 
5606 /* Bit 0 : Enable NFC sense field mode, change state to sense mode */
5607 #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */
5608 #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */
5609 #define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */
5610 
5611 /* Register: NFCT_TASKS_STARTTX */
5612 /* Description: Start transmission of an outgoing frame, change state to transmit */
5613 
5614 /* Bit 0 : Start transmission of an outgoing frame, change state to transmit */
5615 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
5616 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
5617 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
5618 
5619 /* Register: NFCT_TASKS_ENABLERXDATA */
5620 /* Description: Initializes the EasyDMA for receive. */
5621 
5622 /* Bit 0 : Initializes the EasyDMA for receive. */
5623 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */
5624 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */
5625 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */
5626 
5627 /* Register: NFCT_TASKS_GOIDLE */
5628 /* Description: Force state machine to IDLE state */
5629 
5630 /* Bit 0 : Force state machine to IDLE state */
5631 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */
5632 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */
5633 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */
5634 
5635 /* Register: NFCT_TASKS_GOSLEEP */
5636 /* Description: Force state machine to SLEEP_A state */
5637 
5638 /* Bit 0 : Force state machine to SLEEP_A state */
5639 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */
5640 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */
5641 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */
5642 
5643 /* Register: NFCT_SUBSCRIBE_ACTIVATE */
5644 /* Description: Subscribe configuration for task ACTIVATE */
5645 
5646 /* Bit 31 :   */
5647 #define NFCT_SUBSCRIBE_ACTIVATE_EN_Pos (31UL) /*!< Position of EN field. */
5648 #define NFCT_SUBSCRIBE_ACTIVATE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ACTIVATE_EN_Pos) /*!< Bit mask of EN field. */
5649 #define NFCT_SUBSCRIBE_ACTIVATE_EN_Disabled (0UL) /*!< Disable subscription */
5650 #define NFCT_SUBSCRIBE_ACTIVATE_EN_Enabled (1UL) /*!< Enable subscription */
5651 
5652 /* Bits 7..0 : DPPI channel that task ACTIVATE will subscribe to */
5653 #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5654 #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5655 
5656 /* Register: NFCT_SUBSCRIBE_DISABLE */
5657 /* Description: Subscribe configuration for task DISABLE */
5658 
5659 /* Bit 31 :   */
5660 #define NFCT_SUBSCRIBE_DISABLE_EN_Pos (31UL) /*!< Position of EN field. */
5661 #define NFCT_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field. */
5662 #define NFCT_SUBSCRIBE_DISABLE_EN_Disabled (0UL) /*!< Disable subscription */
5663 #define NFCT_SUBSCRIBE_DISABLE_EN_Enabled (1UL) /*!< Enable subscription */
5664 
5665 /* Bits 7..0 : DPPI channel that task DISABLE will subscribe to */
5666 #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5667 #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5668 
5669 /* Register: NFCT_SUBSCRIBE_SENSE */
5670 /* Description: Subscribe configuration for task SENSE */
5671 
5672 /* Bit 31 :   */
5673 #define NFCT_SUBSCRIBE_SENSE_EN_Pos (31UL) /*!< Position of EN field. */
5674 #define NFCT_SUBSCRIBE_SENSE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_SENSE_EN_Pos) /*!< Bit mask of EN field. */
5675 #define NFCT_SUBSCRIBE_SENSE_EN_Disabled (0UL) /*!< Disable subscription */
5676 #define NFCT_SUBSCRIBE_SENSE_EN_Enabled (1UL) /*!< Enable subscription */
5677 
5678 /* Bits 7..0 : DPPI channel that task SENSE will subscribe to */
5679 #define NFCT_SUBSCRIBE_SENSE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5680 #define NFCT_SUBSCRIBE_SENSE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_SENSE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5681 
5682 /* Register: NFCT_SUBSCRIBE_STARTTX */
5683 /* Description: Subscribe configuration for task STARTTX */
5684 
5685 /* Bit 31 :   */
5686 #define NFCT_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
5687 #define NFCT_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << NFCT_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
5688 #define NFCT_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
5689 #define NFCT_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
5690 
5691 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
5692 #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5693 #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5694 
5695 /* Register: NFCT_SUBSCRIBE_ENABLERXDATA */
5696 /* Description: Subscribe configuration for task ENABLERXDATA */
5697 
5698 /* Bit 31 :   */
5699 #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos (31UL) /*!< Position of EN field. */
5700 #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos) /*!< Bit mask of EN field. */
5701 #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Disabled (0UL) /*!< Disable subscription */
5702 #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Enabled (1UL) /*!< Enable subscription */
5703 
5704 /* Bits 7..0 : DPPI channel that task ENABLERXDATA will subscribe to */
5705 #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5706 #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5707 
5708 /* Register: NFCT_SUBSCRIBE_GOIDLE */
5709 /* Description: Subscribe configuration for task GOIDLE */
5710 
5711 /* Bit 31 :   */
5712 #define NFCT_SUBSCRIBE_GOIDLE_EN_Pos (31UL) /*!< Position of EN field. */
5713 #define NFCT_SUBSCRIBE_GOIDLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOIDLE_EN_Pos) /*!< Bit mask of EN field. */
5714 #define NFCT_SUBSCRIBE_GOIDLE_EN_Disabled (0UL) /*!< Disable subscription */
5715 #define NFCT_SUBSCRIBE_GOIDLE_EN_Enabled (1UL) /*!< Enable subscription */
5716 
5717 /* Bits 7..0 : DPPI channel that task GOIDLE will subscribe to */
5718 #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5719 #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5720 
5721 /* Register: NFCT_SUBSCRIBE_GOSLEEP */
5722 /* Description: Subscribe configuration for task GOSLEEP */
5723 
5724 /* Bit 31 :   */
5725 #define NFCT_SUBSCRIBE_GOSLEEP_EN_Pos (31UL) /*!< Position of EN field. */
5726 #define NFCT_SUBSCRIBE_GOSLEEP_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOSLEEP_EN_Pos) /*!< Bit mask of EN field. */
5727 #define NFCT_SUBSCRIBE_GOSLEEP_EN_Disabled (0UL) /*!< Disable subscription */
5728 #define NFCT_SUBSCRIBE_GOSLEEP_EN_Enabled (1UL) /*!< Enable subscription */
5729 
5730 /* Bits 7..0 : DPPI channel that task GOSLEEP will subscribe to */
5731 #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5732 #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5733 
5734 /* Register: NFCT_EVENTS_READY */
5735 /* Description: The NFCT peripheral is ready to receive and send frames */
5736 
5737 /* Bit 0 : The NFCT peripheral is ready to receive and send frames */
5738 #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
5739 #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
5740 #define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
5741 #define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
5742 
5743 /* Register: NFCT_EVENTS_FIELDDETECTED */
5744 /* Description: Remote NFC field detected */
5745 
5746 /* Bit 0 : Remote NFC field detected */
5747 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */
5748 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */
5749 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */
5750 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */
5751 
5752 /* Register: NFCT_EVENTS_FIELDLOST */
5753 /* Description: Remote NFC field lost */
5754 
5755 /* Bit 0 : Remote NFC field lost */
5756 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */
5757 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */
5758 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */
5759 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */
5760 
5761 /* Register: NFCT_EVENTS_TXFRAMESTART */
5762 /* Description: Marks the start of the first symbol of a transmitted frame */
5763 
5764 /* Bit 0 : Marks the start of the first symbol of a transmitted frame */
5765 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */
5766 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */
5767 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
5768 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */
5769 
5770 /* Register: NFCT_EVENTS_TXFRAMEEND */
5771 /* Description: Marks the end of the last transmitted on-air symbol of a frame */
5772 
5773 /* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
5774 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */
5775 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */
5776 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
5777 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */
5778 
5779 /* Register: NFCT_EVENTS_RXFRAMESTART */
5780 /* Description: Marks the end of the first symbol of a received frame */
5781 
5782 /* Bit 0 : Marks the end of the first symbol of a received frame */
5783 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */
5784 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */
5785 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
5786 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */
5787 
5788 /* Register: NFCT_EVENTS_RXFRAMEEND */
5789 /* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
5790 
5791 /* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
5792 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */
5793 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */
5794 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
5795 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */
5796 
5797 /* Register: NFCT_EVENTS_ERROR */
5798 /* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
5799 
5800 /* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
5801 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
5802 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
5803 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
5804 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
5805 
5806 /* Register: NFCT_EVENTS_RXERROR */
5807 /* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
5808 
5809 /* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
5810 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */
5811 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */
5812 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */
5813 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */
5814 
5815 /* Register: NFCT_EVENTS_ENDRX */
5816 /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
5817 
5818 /* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
5819 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
5820 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
5821 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
5822 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
5823 
5824 /* Register: NFCT_EVENTS_ENDTX */
5825 /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
5826 
5827 /* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
5828 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
5829 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
5830 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
5831 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
5832 
5833 /* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */
5834 /* Description: Auto collision resolution process has started */
5835 
5836 /* Bit 0 : Auto collision resolution process has started */
5837 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */
5838 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */
5839 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */
5840 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */
5841 
5842 /* Register: NFCT_EVENTS_COLLISION */
5843 /* Description: NFC auto collision resolution error reported. */
5844 
5845 /* Bit 0 : NFC auto collision resolution error reported. */
5846 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */
5847 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */
5848 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */
5849 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */
5850 
5851 /* Register: NFCT_EVENTS_SELECTED */
5852 /* Description: NFC auto collision resolution successfully completed */
5853 
5854 /* Bit 0 : NFC auto collision resolution successfully completed */
5855 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */
5856 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */
5857 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */
5858 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */
5859 
5860 /* Register: NFCT_EVENTS_STARTED */
5861 /* Description: EasyDMA is ready to receive or send frames. */
5862 
5863 /* Bit 0 : EasyDMA is ready to receive or send frames. */
5864 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
5865 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
5866 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
5867 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
5868 
5869 /* Register: NFCT_PUBLISH_READY */
5870 /* Description: Publish configuration for event READY */
5871 
5872 /* Bit 31 :   */
5873 #define NFCT_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
5874 #define NFCT_PUBLISH_READY_EN_Msk (0x1UL << NFCT_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
5875 #define NFCT_PUBLISH_READY_EN_Disabled (0UL) /*!< Disable publishing */
5876 #define NFCT_PUBLISH_READY_EN_Enabled (1UL) /*!< Enable publishing */
5877 
5878 /* Bits 7..0 : DPPI channel that event READY will publish to. */
5879 #define NFCT_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5880 #define NFCT_PUBLISH_READY_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5881 
5882 /* Register: NFCT_PUBLISH_FIELDDETECTED */
5883 /* Description: Publish configuration for event FIELDDETECTED */
5884 
5885 /* Bit 31 :   */
5886 #define NFCT_PUBLISH_FIELDDETECTED_EN_Pos (31UL) /*!< Position of EN field. */
5887 #define NFCT_PUBLISH_FIELDDETECTED_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDDETECTED_EN_Pos) /*!< Bit mask of EN field. */
5888 #define NFCT_PUBLISH_FIELDDETECTED_EN_Disabled (0UL) /*!< Disable publishing */
5889 #define NFCT_PUBLISH_FIELDDETECTED_EN_Enabled (1UL) /*!< Enable publishing */
5890 
5891 /* Bits 7..0 : DPPI channel that event FIELDDETECTED will publish to. */
5892 #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5893 #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5894 
5895 /* Register: NFCT_PUBLISH_FIELDLOST */
5896 /* Description: Publish configuration for event FIELDLOST */
5897 
5898 /* Bit 31 :   */
5899 #define NFCT_PUBLISH_FIELDLOST_EN_Pos (31UL) /*!< Position of EN field. */
5900 #define NFCT_PUBLISH_FIELDLOST_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDLOST_EN_Pos) /*!< Bit mask of EN field. */
5901 #define NFCT_PUBLISH_FIELDLOST_EN_Disabled (0UL) /*!< Disable publishing */
5902 #define NFCT_PUBLISH_FIELDLOST_EN_Enabled (1UL) /*!< Enable publishing */
5903 
5904 /* Bits 7..0 : DPPI channel that event FIELDLOST will publish to. */
5905 #define NFCT_PUBLISH_FIELDLOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5906 #define NFCT_PUBLISH_FIELDLOST_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDLOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5907 
5908 /* Register: NFCT_PUBLISH_TXFRAMESTART */
5909 /* Description: Publish configuration for event TXFRAMESTART */
5910 
5911 /* Bit 31 :   */
5912 #define NFCT_PUBLISH_TXFRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */
5913 #define NFCT_PUBLISH_TXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMESTART_EN_Pos) /*!< Bit mask of EN field. */
5914 #define NFCT_PUBLISH_TXFRAMESTART_EN_Disabled (0UL) /*!< Disable publishing */
5915 #define NFCT_PUBLISH_TXFRAMESTART_EN_Enabled (1UL) /*!< Enable publishing */
5916 
5917 /* Bits 7..0 : DPPI channel that event TXFRAMESTART will publish to. */
5918 #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5919 #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5920 
5921 /* Register: NFCT_PUBLISH_TXFRAMEEND */
5922 /* Description: Publish configuration for event TXFRAMEEND */
5923 
5924 /* Bit 31 :   */
5925 #define NFCT_PUBLISH_TXFRAMEEND_EN_Pos (31UL) /*!< Position of EN field. */
5926 #define NFCT_PUBLISH_TXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMEEND_EN_Pos) /*!< Bit mask of EN field. */
5927 #define NFCT_PUBLISH_TXFRAMEEND_EN_Disabled (0UL) /*!< Disable publishing */
5928 #define NFCT_PUBLISH_TXFRAMEEND_EN_Enabled (1UL) /*!< Enable publishing */
5929 
5930 /* Bits 7..0 : DPPI channel that event TXFRAMEEND will publish to. */
5931 #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5932 #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5933 
5934 /* Register: NFCT_PUBLISH_RXFRAMESTART */
5935 /* Description: Publish configuration for event RXFRAMESTART */
5936 
5937 /* Bit 31 :   */
5938 #define NFCT_PUBLISH_RXFRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */
5939 #define NFCT_PUBLISH_RXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMESTART_EN_Pos) /*!< Bit mask of EN field. */
5940 #define NFCT_PUBLISH_RXFRAMESTART_EN_Disabled (0UL) /*!< Disable publishing */
5941 #define NFCT_PUBLISH_RXFRAMESTART_EN_Enabled (1UL) /*!< Enable publishing */
5942 
5943 /* Bits 7..0 : DPPI channel that event RXFRAMESTART will publish to. */
5944 #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5945 #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5946 
5947 /* Register: NFCT_PUBLISH_RXFRAMEEND */
5948 /* Description: Publish configuration for event RXFRAMEEND */
5949 
5950 /* Bit 31 :   */
5951 #define NFCT_PUBLISH_RXFRAMEEND_EN_Pos (31UL) /*!< Position of EN field. */
5952 #define NFCT_PUBLISH_RXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMEEND_EN_Pos) /*!< Bit mask of EN field. */
5953 #define NFCT_PUBLISH_RXFRAMEEND_EN_Disabled (0UL) /*!< Disable publishing */
5954 #define NFCT_PUBLISH_RXFRAMEEND_EN_Enabled (1UL) /*!< Enable publishing */
5955 
5956 /* Bits 7..0 : DPPI channel that event RXFRAMEEND will publish to. */
5957 #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5958 #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5959 
5960 /* Register: NFCT_PUBLISH_ERROR */
5961 /* Description: Publish configuration for event ERROR */
5962 
5963 /* Bit 31 :   */
5964 #define NFCT_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
5965 #define NFCT_PUBLISH_ERROR_EN_Msk (0x1UL << NFCT_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
5966 #define NFCT_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
5967 #define NFCT_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
5968 
5969 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */
5970 #define NFCT_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5971 #define NFCT_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5972 
5973 /* Register: NFCT_PUBLISH_RXERROR */
5974 /* Description: Publish configuration for event RXERROR */
5975 
5976 /* Bit 31 :   */
5977 #define NFCT_PUBLISH_RXERROR_EN_Pos (31UL) /*!< Position of EN field. */
5978 #define NFCT_PUBLISH_RXERROR_EN_Msk (0x1UL << NFCT_PUBLISH_RXERROR_EN_Pos) /*!< Bit mask of EN field. */
5979 #define NFCT_PUBLISH_RXERROR_EN_Disabled (0UL) /*!< Disable publishing */
5980 #define NFCT_PUBLISH_RXERROR_EN_Enabled (1UL) /*!< Enable publishing */
5981 
5982 /* Bits 7..0 : DPPI channel that event RXERROR will publish to. */
5983 #define NFCT_PUBLISH_RXERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5984 #define NFCT_PUBLISH_RXERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5985 
5986 /* Register: NFCT_PUBLISH_ENDRX */
5987 /* Description: Publish configuration for event ENDRX */
5988 
5989 /* Bit 31 :   */
5990 #define NFCT_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
5991 #define NFCT_PUBLISH_ENDRX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
5992 #define NFCT_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
5993 #define NFCT_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
5994 
5995 /* Bits 7..0 : DPPI channel that event ENDRX will publish to. */
5996 #define NFCT_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5997 #define NFCT_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5998 
5999 /* Register: NFCT_PUBLISH_ENDTX */
6000 /* Description: Publish configuration for event ENDTX */
6001 
6002 /* Bit 31 :   */
6003 #define NFCT_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
6004 #define NFCT_PUBLISH_ENDTX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
6005 #define NFCT_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
6006 #define NFCT_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
6007 
6008 /* Bits 7..0 : DPPI channel that event ENDTX will publish to. */
6009 #define NFCT_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6010 #define NFCT_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6011 
6012 /* Register: NFCT_PUBLISH_AUTOCOLRESSTARTED */
6013 /* Description: Publish configuration for event AUTOCOLRESSTARTED */
6014 
6015 /* Bit 31 :   */
6016 #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
6017 #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Msk (0x1UL << NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos) /*!< Bit mask of EN field. */
6018 #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
6019 #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
6020 
6021 /* Bits 7..0 : DPPI channel that event AUTOCOLRESSTARTED will publish to. */
6022 #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6023 #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6024 
6025 /* Register: NFCT_PUBLISH_COLLISION */
6026 /* Description: Publish configuration for event COLLISION */
6027 
6028 /* Bit 31 :   */
6029 #define NFCT_PUBLISH_COLLISION_EN_Pos (31UL) /*!< Position of EN field. */
6030 #define NFCT_PUBLISH_COLLISION_EN_Msk (0x1UL << NFCT_PUBLISH_COLLISION_EN_Pos) /*!< Bit mask of EN field. */
6031 #define NFCT_PUBLISH_COLLISION_EN_Disabled (0UL) /*!< Disable publishing */
6032 #define NFCT_PUBLISH_COLLISION_EN_Enabled (1UL) /*!< Enable publishing */
6033 
6034 /* Bits 7..0 : DPPI channel that event COLLISION will publish to. */
6035 #define NFCT_PUBLISH_COLLISION_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6036 #define NFCT_PUBLISH_COLLISION_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_COLLISION_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6037 
6038 /* Register: NFCT_PUBLISH_SELECTED */
6039 /* Description: Publish configuration for event SELECTED */
6040 
6041 /* Bit 31 :   */
6042 #define NFCT_PUBLISH_SELECTED_EN_Pos (31UL) /*!< Position of EN field. */
6043 #define NFCT_PUBLISH_SELECTED_EN_Msk (0x1UL << NFCT_PUBLISH_SELECTED_EN_Pos) /*!< Bit mask of EN field. */
6044 #define NFCT_PUBLISH_SELECTED_EN_Disabled (0UL) /*!< Disable publishing */
6045 #define NFCT_PUBLISH_SELECTED_EN_Enabled (1UL) /*!< Enable publishing */
6046 
6047 /* Bits 7..0 : DPPI channel that event SELECTED will publish to. */
6048 #define NFCT_PUBLISH_SELECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6049 #define NFCT_PUBLISH_SELECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_SELECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6050 
6051 /* Register: NFCT_PUBLISH_STARTED */
6052 /* Description: Publish configuration for event STARTED */
6053 
6054 /* Bit 31 :   */
6055 #define NFCT_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
6056 #define NFCT_PUBLISH_STARTED_EN_Msk (0x1UL << NFCT_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
6057 #define NFCT_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
6058 #define NFCT_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
6059 
6060 /* Bits 7..0 : DPPI channel that event STARTED will publish to. */
6061 #define NFCT_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6062 #define NFCT_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6063 
6064 /* Register: NFCT_SHORTS */
6065 /* Description: Shortcuts between local events and tasks */
6066 
6067 /* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */
6068 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */
6069 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */
6070 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */
6071 #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */
6072 
6073 /* Bit 1 : Shortcut between event FIELDLOST and task SENSE */
6074 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
6075 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
6076 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
6077 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
6078 
6079 /* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
6080 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
6081 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
6082 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
6083 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
6084 
6085 /* Register: NFCT_INTEN */
6086 /* Description: Enable or disable interrupt */
6087 
6088 /* Bit 20 : Enable or disable interrupt for event STARTED */
6089 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
6090 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
6091 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6092 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6093 
6094 /* Bit 19 : Enable or disable interrupt for event SELECTED */
6095 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
6096 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
6097 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
6098 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
6099 
6100 /* Bit 18 : Enable or disable interrupt for event COLLISION */
6101 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
6102 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
6103 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
6104 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
6105 
6106 /* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
6107 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
6108 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
6109 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
6110 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
6111 
6112 /* Bit 12 : Enable or disable interrupt for event ENDTX */
6113 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
6114 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
6115 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
6116 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
6117 
6118 /* Bit 11 : Enable or disable interrupt for event ENDRX */
6119 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
6120 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
6121 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
6122 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
6123 
6124 /* Bit 10 : Enable or disable interrupt for event RXERROR */
6125 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
6126 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
6127 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
6128 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
6129 
6130 /* Bit 7 : Enable or disable interrupt for event ERROR */
6131 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
6132 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
6133 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
6134 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
6135 
6136 /* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
6137 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
6138 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
6139 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
6140 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
6141 
6142 /* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
6143 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
6144 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
6145 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
6146 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
6147 
6148 /* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
6149 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
6150 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
6151 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
6152 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
6153 
6154 /* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
6155 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
6156 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
6157 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
6158 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
6159 
6160 /* Bit 2 : Enable or disable interrupt for event FIELDLOST */
6161 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
6162 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
6163 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
6164 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
6165 
6166 /* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
6167 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
6168 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
6169 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
6170 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
6171 
6172 /* Bit 0 : Enable or disable interrupt for event READY */
6173 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
6174 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
6175 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
6176 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
6177 
6178 /* Register: NFCT_INTENSET */
6179 /* Description: Enable interrupt */
6180 
6181 /* Bit 20 : Write '1' to enable interrupt for event STARTED */
6182 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
6183 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6184 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6185 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6186 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
6187 
6188 /* Bit 19 : Write '1' to enable interrupt for event SELECTED */
6189 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
6190 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
6191 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
6192 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
6193 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
6194 
6195 /* Bit 18 : Write '1' to enable interrupt for event COLLISION */
6196 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
6197 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
6198 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
6199 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
6200 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
6201 
6202 /* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
6203 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
6204 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
6205 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
6206 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
6207 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
6208 
6209 /* Bit 12 : Write '1' to enable interrupt for event ENDTX */
6210 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
6211 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
6212 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
6213 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
6214 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
6215 
6216 /* Bit 11 : Write '1' to enable interrupt for event ENDRX */
6217 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
6218 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
6219 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
6220 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
6221 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
6222 
6223 /* Bit 10 : Write '1' to enable interrupt for event RXERROR */
6224 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
6225 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
6226 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
6227 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
6228 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
6229 
6230 /* Bit 7 : Write '1' to enable interrupt for event ERROR */
6231 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
6232 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
6233 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
6234 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
6235 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
6236 
6237 /* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
6238 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
6239 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
6240 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
6241 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
6242 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
6243 
6244 /* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
6245 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
6246 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
6247 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
6248 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
6249 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
6250 
6251 /* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
6252 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
6253 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
6254 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
6255 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
6256 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
6257 
6258 /* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
6259 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
6260 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
6261 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
6262 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
6263 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
6264 
6265 /* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
6266 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
6267 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
6268 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
6269 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
6270 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
6271 
6272 /* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
6273 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
6274 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
6275 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
6276 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
6277 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
6278 
6279 /* Bit 0 : Write '1' to enable interrupt for event READY */
6280 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
6281 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
6282 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
6283 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
6284 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
6285 
6286 /* Register: NFCT_INTENCLR */
6287 /* Description: Disable interrupt */
6288 
6289 /* Bit 20 : Write '1' to disable interrupt for event STARTED */
6290 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
6291 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
6292 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6293 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6294 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6295 
6296 /* Bit 19 : Write '1' to disable interrupt for event SELECTED */
6297 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
6298 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
6299 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
6300 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
6301 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
6302 
6303 /* Bit 18 : Write '1' to disable interrupt for event COLLISION */
6304 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
6305 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
6306 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
6307 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
6308 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
6309 
6310 /* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
6311 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
6312 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
6313 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
6314 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
6315 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
6316 
6317 /* Bit 12 : Write '1' to disable interrupt for event ENDTX */
6318 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
6319 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
6320 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
6321 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
6322 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
6323 
6324 /* Bit 11 : Write '1' to disable interrupt for event ENDRX */
6325 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
6326 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
6327 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
6328 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
6329 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
6330 
6331 /* Bit 10 : Write '1' to disable interrupt for event RXERROR */
6332 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
6333 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
6334 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
6335 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
6336 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
6337 
6338 /* Bit 7 : Write '1' to disable interrupt for event ERROR */
6339 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
6340 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
6341 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
6342 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
6343 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
6344 
6345 /* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
6346 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
6347 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
6348 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
6349 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
6350 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
6351 
6352 /* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
6353 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
6354 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
6355 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
6356 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
6357 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
6358 
6359 /* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
6360 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
6361 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
6362 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
6363 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
6364 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
6365 
6366 /* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
6367 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
6368 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
6369 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
6370 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
6371 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
6372 
6373 /* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
6374 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
6375 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
6376 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
6377 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
6378 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
6379 
6380 /* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
6381 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
6382 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
6383 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
6384 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
6385 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
6386 
6387 /* Bit 0 : Write '1' to disable interrupt for event READY */
6388 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
6389 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
6390 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
6391 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
6392 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
6393 
6394 /* Register: NFCT_ERRORSTATUS */
6395 /* Description: NFC Error Status register */
6396 
6397 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
6398 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
6399 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
6400 
6401 /* Register: NFCT_FRAMESTATUS_RX */
6402 /* Description: Result of last incoming frame */
6403 
6404 /* Bit 3 : Overrun detected */
6405 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
6406 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
6407 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
6408 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
6409 
6410 /* Bit 2 : Parity status of received frame */
6411 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
6412 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
6413 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
6414 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
6415 
6416 /* Bit 0 : No valid end of frame (EoF) detected */
6417 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
6418 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
6419 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
6420 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
6421 
6422 /* Register: NFCT_NFCTAGSTATE */
6423 /* Description: Current operating state of NFC tag */
6424 
6425 /* Bits 2..0 : NfcTag state */
6426 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */
6427 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */
6428 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */
6429 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */
6430 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL) /*!< Idle */
6431 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL) /*!< Receive */
6432 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */
6433 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */
6434 
6435 /* Register: NFCT_SLEEPSTATE */
6436 /* Description: Sleep state during automatic collision resolution */
6437 
6438 /* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE
6439         by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a
6440         GOSLEEP task. */
6441 #define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */
6442 #define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */
6443 #define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0UL) /*!< State is IDLE. */
6444 #define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (1UL) /*!< State is SLEEP_A. */
6445 
6446 /* Register: NFCT_FIELDPRESENT */
6447 /* Description: Indicates the presence or not of a valid field */
6448 
6449 /* Bit 1 : Indicates if the low level has locked to the field */
6450 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
6451 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
6452 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
6453 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
6454 
6455 /* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
6456 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
6457 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
6458 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
6459 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
6460 
6461 /* Register: NFCT_FRAMEDELAYMIN */
6462 /* Description: Minimum frame delay */
6463 
6464 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clock cycles */
6465 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
6466 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
6467 
6468 /* Register: NFCT_FRAMEDELAYMAX */
6469 /* Description: Maximum frame delay */
6470 
6471 /* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clock cycles */
6472 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
6473 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
6474 
6475 /* Register: NFCT_FRAMEDELAYMODE */
6476 /* Description: Configuration register for the Frame Delay Timer */
6477 
6478 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
6479 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
6480 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
6481 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
6482 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
6483 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
6484 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
6485 
6486 /* Register: NFCT_PACKETPTR */
6487 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
6488 
6489 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
6490 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
6491 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
6492 
6493 /* Register: NFCT_MAXLEN */
6494 /* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */
6495 
6496 /* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */
6497 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
6498 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
6499 
6500 /* Register: NFCT_TXD_FRAMECONFIG */
6501 /* Description: Configuration of outgoing frames */
6502 
6503 /* Bit 4 : CRC mode for outgoing frames */
6504 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
6505 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
6506 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
6507 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
6508 
6509 /* Bit 2 : Adding SoF or not in TX frames */
6510 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
6511 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
6512 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol not added */
6513 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol added */
6514 
6515 /* Bit 1 : Discarding unused bits at start or end of a frame */
6516 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
6517 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
6518 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits are discarded at end of frame (EoF) */
6519 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits are discarded at start of frame (SoF) */
6520 
6521 /* Bit 0 : Indicates if parity is added to the frame */
6522 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
6523 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
6524 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added to TX frames */
6525 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added to TX frames */
6526 
6527 /* Register: NFCT_TXD_AMOUNT */
6528 /* Description: Size of outgoing frame */
6529 
6530 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. */
6531 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
6532 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
6533 
6534 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
6535 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
6536 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
6537 
6538 /* Register: NFCT_RXD_FRAMECONFIG */
6539 /* Description: Configuration of incoming frames */
6540 
6541 /* Bit 4 : CRC mode for incoming frames */
6542 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
6543 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
6544 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
6545 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
6546 
6547 /* Bit 2 : SoF expected or not in RX frames */
6548 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
6549 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
6550 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol is not expected in RX frames */
6551 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol is expected in RX frames */
6552 
6553 /* Bit 0 : Indicates if parity expected in RX frame */
6554 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
6555 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
6556 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
6557 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
6558 
6559 /* Register: NFCT_RXD_AMOUNT */
6560 /* Description: Size of last incoming frame */
6561 
6562 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
6563 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
6564 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
6565 
6566 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
6567 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
6568 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
6569 
6570 /* Register: NFCT_MODULATIONCTRL */
6571 /* Description: Enables the modulation output to a GPIO pin which can be connected to a second external antenna. */
6572 
6573 /* Bits 1..0 : Configuration of modulation control. */
6574 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos (0UL) /*!< Position of MODULATIONCTRL field. */
6575 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk (0x3UL << NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos) /*!< Bit mask of MODULATIONCTRL field. */
6576 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Invalid (0x0UL) /*!< Invalid, defaults to same behaviour as for Internal */
6577 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Internal (0x1UL) /*!< Use internal modulator only */
6578 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_ModToGpio (0x2UL) /*!< Output digital modulation signal to a GPIO pin. */
6579 #define NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio (0x3UL) /*!< Use internal modulator and output digital modulation signal to a GPIO pin. */
6580 
6581 /* Register: NFCT_MODULATIONPSEL */
6582 /* Description: Pin select for Modulation control */
6583 
6584 /* Bit 31 : Connection */
6585 #define NFCT_MODULATIONPSEL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6586 #define NFCT_MODULATIONPSEL_CONNECT_Msk (0x1UL << NFCT_MODULATIONPSEL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6587 #define NFCT_MODULATIONPSEL_CONNECT_Connected (0UL) /*!< Connect */
6588 #define NFCT_MODULATIONPSEL_CONNECT_Disconnected (1UL) /*!< Disconnect */
6589 
6590 /* Bit 5 : Port number */
6591 #define NFCT_MODULATIONPSEL_PORT_Pos (5UL) /*!< Position of PORT field. */
6592 #define NFCT_MODULATIONPSEL_PORT_Msk (0x1UL << NFCT_MODULATIONPSEL_PORT_Pos) /*!< Bit mask of PORT field. */
6593 
6594 /* Bits 4..0 : Pin number */
6595 #define NFCT_MODULATIONPSEL_PIN_Pos (0UL) /*!< Position of PIN field. */
6596 #define NFCT_MODULATIONPSEL_PIN_Msk (0x1FUL << NFCT_MODULATIONPSEL_PIN_Pos) /*!< Bit mask of PIN field. */
6597 
6598 /* Register: NFCT_NFCID1_LAST */
6599 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
6600 
6601 /* Bits 31..24 : NFCID1 byte W */
6602 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
6603 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
6604 
6605 /* Bits 23..16 : NFCID1 byte X */
6606 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
6607 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
6608 
6609 /* Bits 15..8 : NFCID1 byte Y */
6610 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
6611 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
6612 
6613 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
6614 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
6615 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
6616 
6617 /* Register: NFCT_NFCID1_2ND_LAST */
6618 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
6619 
6620 /* Bits 23..16 : NFCID1 byte T */
6621 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
6622 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
6623 
6624 /* Bits 15..8 : NFCID1 byte U */
6625 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
6626 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
6627 
6628 /* Bits 7..0 : NFCID1 byte V */
6629 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
6630 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
6631 
6632 /* Register: NFCT_NFCID1_3RD_LAST */
6633 /* Description: Third last NFCID1 part (10 bytes ID) */
6634 
6635 /* Bits 23..16 : NFCID1 byte Q */
6636 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
6637 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
6638 
6639 /* Bits 15..8 : NFCID1 byte R */
6640 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
6641 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
6642 
6643 /* Bits 7..0 : NFCID1 byte S */
6644 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
6645 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
6646 
6647 /* Register: NFCT_AUTOCOLRESCONFIG */
6648 /* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. */
6649 
6650 /* Bit 0 : Enables/disables auto collision resolution */
6651 #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
6652 #define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
6653 #define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */
6654 #define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */
6655 
6656 /* Register: NFCT_SENSRES */
6657 /* Description: NFC-A SENS_RES auto-response settings */
6658 
6659 /* Bits 15..12 : Reserved for future use. Shall be 0. */
6660 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
6661 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
6662 
6663 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
6664 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
6665 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
6666 
6667 /* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */
6668 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
6669 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
6670 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
6671 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
6672 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
6673 
6674 /* Bit 5 : Reserved for future use. Shall be 0. */
6675 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
6676 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
6677 
6678 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
6679 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
6680 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
6681 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
6682 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
6683 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
6684 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
6685 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
6686 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
6687 
6688 /* Register: NFCT_SELRES */
6689 /* Description: NFC-A SEL_RES auto-response settings */
6690 
6691 /* Bit 7 : Reserved for future use. Shall be 0. */
6692 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
6693 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
6694 
6695 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
6696 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
6697 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
6698 
6699 /* Bits 4..3 : Reserved for future use. Shall be 0. */
6700 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
6701 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
6702 
6703 /* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */
6704 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
6705 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
6706 
6707 /* Bits 1..0 : Reserved for future use. Shall be 0. */
6708 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
6709 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
6710 
6711 
6712 /* Peripheral: NVMC */
6713 /* Description: Non-volatile memory controller 0 */
6714 
6715 /* Register: NVMC_READY */
6716 /* Description: Ready flag */
6717 
6718 /* Bit 0 : NVMC is ready or busy */
6719 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
6720 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
6721 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */
6722 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
6723 
6724 /* Register: NVMC_READYNEXT */
6725 /* Description: Ready flag */
6726 
6727 /* Bit 0 : NVMC can accept a new write operation */
6728 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
6729 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
6730 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
6731 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
6732 
6733 /* Register: NVMC_CONFIG */
6734 /* Description: Configuration register */
6735 
6736 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */
6737 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
6738 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
6739 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
6740 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
6741 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
6742 #define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */
6743 
6744 /* Register: NVMC_ERASEALL */
6745 /* Description: Register for erasing all non-volatile user memory */
6746 
6747 /* Bit 0 : Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. */
6748 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
6749 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
6750 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
6751 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
6752 
6753 /* Register: NVMC_ERASEPAGEPARTIALCFG */
6754 /* Description: Register for partial erase configuration */
6755 
6756 /* Bits 6..0 : Duration of the partial erase in milliseconds */
6757 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
6758 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
6759 
6760 /* Register: NVMC_CONFIGNS */
6761 /* Description: Non-secure configuration register */
6762 
6763 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */
6764 #define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */
6765 #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */
6766 #define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */
6767 #define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */
6768 #define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */
6769 
6770 /* Register: NVMC_WRITEUICRNS */
6771 /* Description: Non-secure APPROTECT enable register */
6772 
6773 /* Bits 31..4 : Key to write in order to validate the write operation */
6774 #define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */
6775 #define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */
6776 #define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */
6777 
6778 /* Bit 0 : Allow non-secure code to set APPROTECT */
6779 #define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */
6780 #define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */
6781 #define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */
6782 
6783 
6784 /* Peripheral: OSCILLATORS */
6785 /* Description: Oscillator control 0 */
6786 
6787 /* Register: OSCILLATORS_XOSC32MCAPS */
6788 /* Description: Programmable capacitance of XC1 and XC2 */
6789 
6790 /* Bit 8 : Enable on-chip capacitors on XC1 and XC2 */
6791 #define OSCILLATORS_XOSC32MCAPS_ENABLE_Pos (8UL) /*!< Position of ENABLE field. */
6792 #define OSCILLATORS_XOSC32MCAPS_ENABLE_Msk (0x1UL << OSCILLATORS_XOSC32MCAPS_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6793 #define OSCILLATORS_XOSC32MCAPS_ENABLE_Disabled (0UL) /*!< Capacitor disabled (use external caps) */
6794 #define OSCILLATORS_XOSC32MCAPS_ENABLE_Enabled (1UL) /*!< Capacitor enabled */
6795 
6796 /* Bits 4..0 : Value representing capacitance, calculated using provided equation */
6797 #define OSCILLATORS_XOSC32MCAPS_CAPVALUE_Pos (0UL) /*!< Position of CAPVALUE field. */
6798 #define OSCILLATORS_XOSC32MCAPS_CAPVALUE_Msk (0x1FUL << OSCILLATORS_XOSC32MCAPS_CAPVALUE_Pos) /*!< Bit mask of CAPVALUE field. */
6799 
6800 /* Register: OSCILLATORS_XOSC32KI_BYPASS */
6801 /* Description: Enable or disable bypass of LFCLK crystal oscillator with external clock source */
6802 
6803 /* Bit 0 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
6804 #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos (0UL) /*!< Position of BYPASS field. */
6805 #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Msk (0x1UL << OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
6806 #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Disabled (0UL) /*!< Disable (use with crystal or low-swing external source) */
6807 #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
6808 
6809 /* Register: OSCILLATORS_XOSC32KI_INTCAP */
6810 /* Description: Control usage of internal load capacitors */
6811 
6812 /* Bits 1..0 : Control usage of internal load capacitors */
6813 #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Pos (0UL) /*!< Position of INTCAP field. */
6814 #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Msk (0x3UL << OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Pos) /*!< Bit mask of INTCAP field. */
6815 #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_External (0UL) /*!< Use external load capacitors */
6816 #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C6PF (1UL) /*!< 6 pF internal load capacitance */
6817 #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C7PF (2UL) /*!< 7 pF internal load capacitance */
6818 #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C9PF (3UL) /*!< 9 pF internal load capacitance */
6819 
6820 
6821 /* Peripheral: GPIO */
6822 /* Description: GPIO Port 0 */
6823 
6824 /* Register: GPIO_OUT */
6825 /* Description: Write GPIO port */
6826 
6827 /* Bit 31 : Pin 31 */
6828 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6829 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6830 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
6831 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
6832 
6833 /* Bit 30 : Pin 30 */
6834 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6835 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6836 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
6837 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
6838 
6839 /* Bit 29 : Pin 29 */
6840 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6841 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6842 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
6843 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
6844 
6845 /* Bit 28 : Pin 28 */
6846 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6847 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6848 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
6849 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
6850 
6851 /* Bit 27 : Pin 27 */
6852 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6853 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6854 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
6855 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
6856 
6857 /* Bit 26 : Pin 26 */
6858 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6859 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6860 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
6861 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
6862 
6863 /* Bit 25 : Pin 25 */
6864 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6865 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6866 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
6867 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
6868 
6869 /* Bit 24 : Pin 24 */
6870 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6871 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6872 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
6873 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
6874 
6875 /* Bit 23 : Pin 23 */
6876 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6877 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6878 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
6879 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
6880 
6881 /* Bit 22 : Pin 22 */
6882 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6883 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6884 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
6885 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
6886 
6887 /* Bit 21 : Pin 21 */
6888 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6889 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6890 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
6891 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
6892 
6893 /* Bit 20 : Pin 20 */
6894 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6895 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6896 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
6897 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
6898 
6899 /* Bit 19 : Pin 19 */
6900 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6901 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6902 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
6903 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
6904 
6905 /* Bit 18 : Pin 18 */
6906 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6907 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6908 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
6909 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
6910 
6911 /* Bit 17 : Pin 17 */
6912 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6913 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6914 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
6915 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
6916 
6917 /* Bit 16 : Pin 16 */
6918 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6919 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6920 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
6921 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
6922 
6923 /* Bit 15 : Pin 15 */
6924 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6925 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6926 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
6927 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
6928 
6929 /* Bit 14 : Pin 14 */
6930 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6931 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6932 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
6933 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
6934 
6935 /* Bit 13 : Pin 13 */
6936 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6937 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6938 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
6939 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
6940 
6941 /* Bit 12 : Pin 12 */
6942 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6943 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6944 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
6945 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
6946 
6947 /* Bit 11 : Pin 11 */
6948 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6949 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6950 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
6951 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
6952 
6953 /* Bit 10 : Pin 10 */
6954 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6955 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6956 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
6957 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
6958 
6959 /* Bit 9 : Pin 9 */
6960 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6961 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6962 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
6963 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
6964 
6965 /* Bit 8 : Pin 8 */
6966 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6967 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6968 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
6969 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
6970 
6971 /* Bit 7 : Pin 7 */
6972 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6973 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6974 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
6975 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
6976 
6977 /* Bit 6 : Pin 6 */
6978 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6979 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6980 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
6981 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
6982 
6983 /* Bit 5 : Pin 5 */
6984 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6985 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6986 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
6987 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
6988 
6989 /* Bit 4 : Pin 4 */
6990 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6991 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6992 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
6993 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
6994 
6995 /* Bit 3 : Pin 3 */
6996 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6997 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6998 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
6999 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
7000 
7001 /* Bit 2 : Pin 2 */
7002 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7003 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7004 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
7005 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
7006 
7007 /* Bit 1 : Pin 1 */
7008 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7009 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7010 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
7011 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
7012 
7013 /* Bit 0 : Pin 0 */
7014 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7015 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7016 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
7017 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
7018 
7019 /* Register: GPIO_OUTSET */
7020 /* Description: Set individual bits in GPIO port */
7021 
7022 /* Bit 31 : Pin 31 */
7023 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7024 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7025 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
7026 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
7027 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7028 
7029 /* Bit 30 : Pin 30 */
7030 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7031 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7032 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
7033 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
7034 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7035 
7036 /* Bit 29 : Pin 29 */
7037 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7038 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7039 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
7040 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
7041 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7042 
7043 /* Bit 28 : Pin 28 */
7044 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7045 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7046 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
7047 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
7048 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7049 
7050 /* Bit 27 : Pin 27 */
7051 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7052 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7053 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
7054 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
7055 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7056 
7057 /* Bit 26 : Pin 26 */
7058 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7059 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7060 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
7061 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
7062 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7063 
7064 /* Bit 25 : Pin 25 */
7065 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7066 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7067 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
7068 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
7069 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7070 
7071 /* Bit 24 : Pin 24 */
7072 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7073 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7074 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
7075 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
7076 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7077 
7078 /* Bit 23 : Pin 23 */
7079 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7080 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7081 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
7082 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
7083 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7084 
7085 /* Bit 22 : Pin 22 */
7086 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7087 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7088 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
7089 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
7090 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7091 
7092 /* Bit 21 : Pin 21 */
7093 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7094 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7095 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
7096 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
7097 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7098 
7099 /* Bit 20 : Pin 20 */
7100 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7101 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7102 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
7103 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
7104 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7105 
7106 /* Bit 19 : Pin 19 */
7107 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7108 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7109 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
7110 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
7111 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7112 
7113 /* Bit 18 : Pin 18 */
7114 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7115 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7116 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
7117 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
7118 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7119 
7120 /* Bit 17 : Pin 17 */
7121 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7122 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7123 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
7124 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
7125 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7126 
7127 /* Bit 16 : Pin 16 */
7128 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7129 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7130 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
7131 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
7132 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7133 
7134 /* Bit 15 : Pin 15 */
7135 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7136 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7137 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
7138 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
7139 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7140 
7141 /* Bit 14 : Pin 14 */
7142 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7143 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7144 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
7145 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
7146 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7147 
7148 /* Bit 13 : Pin 13 */
7149 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7150 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7151 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
7152 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
7153 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7154 
7155 /* Bit 12 : Pin 12 */
7156 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7157 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7158 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
7159 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
7160 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7161 
7162 /* Bit 11 : Pin 11 */
7163 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7164 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7165 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
7166 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
7167 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7168 
7169 /* Bit 10 : Pin 10 */
7170 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7171 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7172 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
7173 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
7174 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7175 
7176 /* Bit 9 : Pin 9 */
7177 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7178 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7179 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
7180 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
7181 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7182 
7183 /* Bit 8 : Pin 8 */
7184 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7185 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7186 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
7187 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
7188 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7189 
7190 /* Bit 7 : Pin 7 */
7191 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7192 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7193 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
7194 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
7195 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7196 
7197 /* Bit 6 : Pin 6 */
7198 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7199 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7200 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
7201 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
7202 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7203 
7204 /* Bit 5 : Pin 5 */
7205 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7206 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7207 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
7208 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
7209 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7210 
7211 /* Bit 4 : Pin 4 */
7212 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7213 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7214 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
7215 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
7216 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7217 
7218 /* Bit 3 : Pin 3 */
7219 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7220 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7221 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
7222 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
7223 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7224 
7225 /* Bit 2 : Pin 2 */
7226 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7227 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7228 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
7229 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
7230 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7231 
7232 /* Bit 1 : Pin 1 */
7233 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7234 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7235 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
7236 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
7237 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7238 
7239 /* Bit 0 : Pin 0 */
7240 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7241 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7242 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
7243 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
7244 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
7245 
7246 /* Register: GPIO_OUTCLR */
7247 /* Description: Clear individual bits in GPIO port */
7248 
7249 /* Bit 31 : Pin 31 */
7250 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7251 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7252 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
7253 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
7254 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7255 
7256 /* Bit 30 : Pin 30 */
7257 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7258 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7259 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
7260 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
7261 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7262 
7263 /* Bit 29 : Pin 29 */
7264 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7265 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7266 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
7267 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
7268 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7269 
7270 /* Bit 28 : Pin 28 */
7271 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7272 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7273 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
7274 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
7275 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7276 
7277 /* Bit 27 : Pin 27 */
7278 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7279 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7280 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
7281 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
7282 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7283 
7284 /* Bit 26 : Pin 26 */
7285 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7286 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7287 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
7288 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
7289 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7290 
7291 /* Bit 25 : Pin 25 */
7292 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7293 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7294 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
7295 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
7296 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7297 
7298 /* Bit 24 : Pin 24 */
7299 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7300 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7301 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
7302 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
7303 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7304 
7305 /* Bit 23 : Pin 23 */
7306 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7307 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7308 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
7309 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
7310 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7311 
7312 /* Bit 22 : Pin 22 */
7313 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7314 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7315 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
7316 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
7317 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7318 
7319 /* Bit 21 : Pin 21 */
7320 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7321 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7322 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
7323 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
7324 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7325 
7326 /* Bit 20 : Pin 20 */
7327 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7328 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7329 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
7330 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
7331 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7332 
7333 /* Bit 19 : Pin 19 */
7334 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7335 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7336 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
7337 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
7338 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7339 
7340 /* Bit 18 : Pin 18 */
7341 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7342 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7343 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
7344 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
7345 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7346 
7347 /* Bit 17 : Pin 17 */
7348 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7349 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7350 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
7351 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
7352 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7353 
7354 /* Bit 16 : Pin 16 */
7355 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7356 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7357 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
7358 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
7359 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7360 
7361 /* Bit 15 : Pin 15 */
7362 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7363 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7364 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
7365 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
7366 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7367 
7368 /* Bit 14 : Pin 14 */
7369 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7370 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7371 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
7372 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
7373 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7374 
7375 /* Bit 13 : Pin 13 */
7376 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7377 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7378 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
7379 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
7380 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7381 
7382 /* Bit 12 : Pin 12 */
7383 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7384 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7385 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
7386 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
7387 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7388 
7389 /* Bit 11 : Pin 11 */
7390 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7391 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7392 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
7393 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
7394 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7395 
7396 /* Bit 10 : Pin 10 */
7397 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7398 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7399 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
7400 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
7401 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7402 
7403 /* Bit 9 : Pin 9 */
7404 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7405 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7406 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
7407 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
7408 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7409 
7410 /* Bit 8 : Pin 8 */
7411 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7412 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7413 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
7414 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
7415 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7416 
7417 /* Bit 7 : Pin 7 */
7418 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7419 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7420 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
7421 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
7422 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7423 
7424 /* Bit 6 : Pin 6 */
7425 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7426 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7427 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
7428 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
7429 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7430 
7431 /* Bit 5 : Pin 5 */
7432 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7433 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7434 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
7435 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
7436 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7437 
7438 /* Bit 4 : Pin 4 */
7439 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7440 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7441 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
7442 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
7443 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7444 
7445 /* Bit 3 : Pin 3 */
7446 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7447 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7448 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
7449 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
7450 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7451 
7452 /* Bit 2 : Pin 2 */
7453 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7454 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7455 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
7456 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
7457 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7458 
7459 /* Bit 1 : Pin 1 */
7460 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7461 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7462 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
7463 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
7464 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7465 
7466 /* Bit 0 : Pin 0 */
7467 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7468 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7469 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
7470 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
7471 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
7472 
7473 /* Register: GPIO_IN */
7474 /* Description: Read GPIO port */
7475 
7476 /* Bit 31 : Pin 31 */
7477 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7478 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7479 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
7480 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
7481 
7482 /* Bit 30 : Pin 30 */
7483 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7484 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7485 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
7486 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
7487 
7488 /* Bit 29 : Pin 29 */
7489 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7490 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7491 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
7492 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
7493 
7494 /* Bit 28 : Pin 28 */
7495 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7496 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7497 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
7498 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
7499 
7500 /* Bit 27 : Pin 27 */
7501 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7502 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7503 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
7504 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
7505 
7506 /* Bit 26 : Pin 26 */
7507 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7508 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7509 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
7510 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
7511 
7512 /* Bit 25 : Pin 25 */
7513 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7514 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7515 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
7516 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
7517 
7518 /* Bit 24 : Pin 24 */
7519 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7520 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7521 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
7522 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
7523 
7524 /* Bit 23 : Pin 23 */
7525 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7526 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7527 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
7528 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
7529 
7530 /* Bit 22 : Pin 22 */
7531 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7532 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7533 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
7534 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
7535 
7536 /* Bit 21 : Pin 21 */
7537 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7538 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7539 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
7540 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
7541 
7542 /* Bit 20 : Pin 20 */
7543 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7544 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7545 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
7546 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
7547 
7548 /* Bit 19 : Pin 19 */
7549 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7550 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7551 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
7552 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
7553 
7554 /* Bit 18 : Pin 18 */
7555 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7556 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7557 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
7558 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
7559 
7560 /* Bit 17 : Pin 17 */
7561 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7562 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7563 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
7564 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
7565 
7566 /* Bit 16 : Pin 16 */
7567 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7568 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7569 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
7570 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
7571 
7572 /* Bit 15 : Pin 15 */
7573 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7574 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7575 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
7576 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
7577 
7578 /* Bit 14 : Pin 14 */
7579 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7580 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7581 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
7582 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
7583 
7584 /* Bit 13 : Pin 13 */
7585 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7586 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7587 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
7588 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
7589 
7590 /* Bit 12 : Pin 12 */
7591 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7592 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7593 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
7594 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
7595 
7596 /* Bit 11 : Pin 11 */
7597 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7598 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7599 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
7600 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
7601 
7602 /* Bit 10 : Pin 10 */
7603 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7604 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7605 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
7606 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
7607 
7608 /* Bit 9 : Pin 9 */
7609 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7610 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7611 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
7612 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
7613 
7614 /* Bit 8 : Pin 8 */
7615 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7616 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7617 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
7618 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
7619 
7620 /* Bit 7 : Pin 7 */
7621 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7622 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7623 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
7624 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
7625 
7626 /* Bit 6 : Pin 6 */
7627 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7628 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7629 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
7630 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
7631 
7632 /* Bit 5 : Pin 5 */
7633 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7634 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7635 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
7636 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
7637 
7638 /* Bit 4 : Pin 4 */
7639 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7640 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7641 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
7642 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
7643 
7644 /* Bit 3 : Pin 3 */
7645 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7646 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7647 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
7648 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
7649 
7650 /* Bit 2 : Pin 2 */
7651 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7652 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7653 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
7654 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
7655 
7656 /* Bit 1 : Pin 1 */
7657 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7658 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7659 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
7660 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
7661 
7662 /* Bit 0 : Pin 0 */
7663 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7664 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7665 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
7666 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
7667 
7668 /* Register: GPIO_DIR */
7669 /* Description: Direction of GPIO pins */
7670 
7671 /* Bit 31 : Pin 31 */
7672 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7673 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7674 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
7675 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
7676 
7677 /* Bit 30 : Pin 30 */
7678 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7679 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7680 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
7681 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
7682 
7683 /* Bit 29 : Pin 29 */
7684 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7685 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7686 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
7687 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
7688 
7689 /* Bit 28 : Pin 28 */
7690 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7691 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7692 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
7693 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
7694 
7695 /* Bit 27 : Pin 27 */
7696 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7697 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7698 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
7699 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
7700 
7701 /* Bit 26 : Pin 26 */
7702 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7703 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7704 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
7705 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
7706 
7707 /* Bit 25 : Pin 25 */
7708 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7709 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7710 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
7711 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
7712 
7713 /* Bit 24 : Pin 24 */
7714 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7715 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7716 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
7717 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
7718 
7719 /* Bit 23 : Pin 23 */
7720 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7721 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7722 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
7723 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
7724 
7725 /* Bit 22 : Pin 22 */
7726 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7727 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7728 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
7729 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
7730 
7731 /* Bit 21 : Pin 21 */
7732 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7733 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7734 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
7735 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
7736 
7737 /* Bit 20 : Pin 20 */
7738 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7739 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7740 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
7741 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
7742 
7743 /* Bit 19 : Pin 19 */
7744 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7745 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7746 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
7747 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
7748 
7749 /* Bit 18 : Pin 18 */
7750 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7751 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7752 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
7753 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
7754 
7755 /* Bit 17 : Pin 17 */
7756 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7757 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7758 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
7759 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
7760 
7761 /* Bit 16 : Pin 16 */
7762 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7763 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7764 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
7765 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
7766 
7767 /* Bit 15 : Pin 15 */
7768 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7769 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7770 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
7771 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
7772 
7773 /* Bit 14 : Pin 14 */
7774 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7775 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7776 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
7777 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
7778 
7779 /* Bit 13 : Pin 13 */
7780 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7781 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7782 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
7783 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
7784 
7785 /* Bit 12 : Pin 12 */
7786 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7787 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7788 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
7789 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
7790 
7791 /* Bit 11 : Pin 11 */
7792 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7793 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7794 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
7795 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
7796 
7797 /* Bit 10 : Pin 10 */
7798 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7799 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7800 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
7801 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
7802 
7803 /* Bit 9 : Pin 9 */
7804 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7805 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7806 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
7807 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
7808 
7809 /* Bit 8 : Pin 8 */
7810 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7811 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7812 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
7813 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
7814 
7815 /* Bit 7 : Pin 7 */
7816 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7817 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7818 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
7819 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
7820 
7821 /* Bit 6 : Pin 6 */
7822 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7823 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7824 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
7825 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
7826 
7827 /* Bit 5 : Pin 5 */
7828 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7829 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7830 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
7831 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
7832 
7833 /* Bit 4 : Pin 4 */
7834 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7835 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7836 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
7837 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
7838 
7839 /* Bit 3 : Pin 3 */
7840 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7841 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7842 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
7843 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
7844 
7845 /* Bit 2 : Pin 2 */
7846 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7847 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7848 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
7849 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
7850 
7851 /* Bit 1 : Pin 1 */
7852 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7853 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7854 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
7855 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
7856 
7857 /* Bit 0 : Pin 0 */
7858 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7859 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7860 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
7861 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
7862 
7863 /* Register: GPIO_DIRSET */
7864 /* Description: DIR set register */
7865 
7866 /* Bit 31 : Set as output pin 31 */
7867 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7868 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7869 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
7870 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
7871 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7872 
7873 /* Bit 30 : Set as output pin 30 */
7874 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7875 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7876 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
7877 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
7878 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7879 
7880 /* Bit 29 : Set as output pin 29 */
7881 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7882 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7883 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
7884 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
7885 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7886 
7887 /* Bit 28 : Set as output pin 28 */
7888 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7889 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7890 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
7891 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
7892 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7893 
7894 /* Bit 27 : Set as output pin 27 */
7895 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7896 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7897 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
7898 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
7899 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7900 
7901 /* Bit 26 : Set as output pin 26 */
7902 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7903 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7904 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
7905 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
7906 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7907 
7908 /* Bit 25 : Set as output pin 25 */
7909 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7910 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7911 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
7912 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
7913 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7914 
7915 /* Bit 24 : Set as output pin 24 */
7916 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7917 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7918 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
7919 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
7920 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7921 
7922 /* Bit 23 : Set as output pin 23 */
7923 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7924 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7925 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
7926 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
7927 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7928 
7929 /* Bit 22 : Set as output pin 22 */
7930 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7931 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7932 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
7933 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
7934 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7935 
7936 /* Bit 21 : Set as output pin 21 */
7937 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7938 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7939 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
7940 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
7941 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7942 
7943 /* Bit 20 : Set as output pin 20 */
7944 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7945 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7946 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
7947 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
7948 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7949 
7950 /* Bit 19 : Set as output pin 19 */
7951 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7952 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7953 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
7954 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
7955 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7956 
7957 /* Bit 18 : Set as output pin 18 */
7958 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7959 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7960 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
7961 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
7962 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7963 
7964 /* Bit 17 : Set as output pin 17 */
7965 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7966 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7967 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
7968 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
7969 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7970 
7971 /* Bit 16 : Set as output pin 16 */
7972 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7973 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7974 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
7975 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
7976 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7977 
7978 /* Bit 15 : Set as output pin 15 */
7979 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7980 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7981 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
7982 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
7983 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7984 
7985 /* Bit 14 : Set as output pin 14 */
7986 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7987 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7988 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
7989 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
7990 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7991 
7992 /* Bit 13 : Set as output pin 13 */
7993 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7994 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7995 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
7996 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
7997 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
7998 
7999 /* Bit 12 : Set as output pin 12 */
8000 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8001 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8002 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
8003 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
8004 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8005 
8006 /* Bit 11 : Set as output pin 11 */
8007 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8008 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8009 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
8010 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
8011 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8012 
8013 /* Bit 10 : Set as output pin 10 */
8014 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8015 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8016 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
8017 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
8018 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8019 
8020 /* Bit 9 : Set as output pin 9 */
8021 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8022 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8023 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
8024 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
8025 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8026 
8027 /* Bit 8 : Set as output pin 8 */
8028 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8029 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8030 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
8031 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
8032 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8033 
8034 /* Bit 7 : Set as output pin 7 */
8035 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8036 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8037 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
8038 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
8039 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8040 
8041 /* Bit 6 : Set as output pin 6 */
8042 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8043 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8044 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
8045 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
8046 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8047 
8048 /* Bit 5 : Set as output pin 5 */
8049 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8050 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8051 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
8052 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
8053 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8054 
8055 /* Bit 4 : Set as output pin 4 */
8056 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8057 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8058 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
8059 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
8060 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8061 
8062 /* Bit 3 : Set as output pin 3 */
8063 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8064 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8065 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
8066 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
8067 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8068 
8069 /* Bit 2 : Set as output pin 2 */
8070 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8071 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8072 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
8073 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
8074 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8075 
8076 /* Bit 1 : Set as output pin 1 */
8077 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8078 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8079 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
8080 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
8081 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8082 
8083 /* Bit 0 : Set as output pin 0 */
8084 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8085 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8086 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
8087 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
8088 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
8089 
8090 /* Register: GPIO_DIRCLR */
8091 /* Description: DIR clear register */
8092 
8093 /* Bit 31 : Set as input pin 31 */
8094 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
8095 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
8096 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
8097 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
8098 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8099 
8100 /* Bit 30 : Set as input pin 30 */
8101 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
8102 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
8103 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
8104 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
8105 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8106 
8107 /* Bit 29 : Set as input pin 29 */
8108 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
8109 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
8110 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
8111 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
8112 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8113 
8114 /* Bit 28 : Set as input pin 28 */
8115 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
8116 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
8117 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
8118 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
8119 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8120 
8121 /* Bit 27 : Set as input pin 27 */
8122 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
8123 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
8124 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
8125 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
8126 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8127 
8128 /* Bit 26 : Set as input pin 26 */
8129 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
8130 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
8131 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
8132 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
8133 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8134 
8135 /* Bit 25 : Set as input pin 25 */
8136 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
8137 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
8138 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
8139 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
8140 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8141 
8142 /* Bit 24 : Set as input pin 24 */
8143 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
8144 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
8145 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
8146 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
8147 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8148 
8149 /* Bit 23 : Set as input pin 23 */
8150 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
8151 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
8152 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
8153 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
8154 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8155 
8156 /* Bit 22 : Set as input pin 22 */
8157 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
8158 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
8159 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
8160 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
8161 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8162 
8163 /* Bit 21 : Set as input pin 21 */
8164 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
8165 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
8166 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
8167 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
8168 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8169 
8170 /* Bit 20 : Set as input pin 20 */
8171 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
8172 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
8173 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
8174 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
8175 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8176 
8177 /* Bit 19 : Set as input pin 19 */
8178 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
8179 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
8180 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
8181 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
8182 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8183 
8184 /* Bit 18 : Set as input pin 18 */
8185 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
8186 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
8187 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
8188 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
8189 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8190 
8191 /* Bit 17 : Set as input pin 17 */
8192 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
8193 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
8194 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
8195 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
8196 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8197 
8198 /* Bit 16 : Set as input pin 16 */
8199 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
8200 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
8201 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
8202 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
8203 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8204 
8205 /* Bit 15 : Set as input pin 15 */
8206 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
8207 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
8208 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
8209 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
8210 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8211 
8212 /* Bit 14 : Set as input pin 14 */
8213 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
8214 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
8215 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
8216 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
8217 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8218 
8219 /* Bit 13 : Set as input pin 13 */
8220 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
8221 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
8222 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
8223 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
8224 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8225 
8226 /* Bit 12 : Set as input pin 12 */
8227 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8228 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8229 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
8230 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
8231 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8232 
8233 /* Bit 11 : Set as input pin 11 */
8234 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8235 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8236 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
8237 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
8238 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8239 
8240 /* Bit 10 : Set as input pin 10 */
8241 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8242 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8243 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
8244 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
8245 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8246 
8247 /* Bit 9 : Set as input pin 9 */
8248 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8249 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8250 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
8251 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
8252 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8253 
8254 /* Bit 8 : Set as input pin 8 */
8255 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8256 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8257 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
8258 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
8259 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8260 
8261 /* Bit 7 : Set as input pin 7 */
8262 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8263 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8264 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
8265 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
8266 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8267 
8268 /* Bit 6 : Set as input pin 6 */
8269 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8270 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8271 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
8272 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
8273 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8274 
8275 /* Bit 5 : Set as input pin 5 */
8276 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8277 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8278 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
8279 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
8280 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8281 
8282 /* Bit 4 : Set as input pin 4 */
8283 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8284 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8285 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
8286 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
8287 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8288 
8289 /* Bit 3 : Set as input pin 3 */
8290 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8291 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8292 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
8293 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
8294 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8295 
8296 /* Bit 2 : Set as input pin 2 */
8297 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8298 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8299 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
8300 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
8301 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8302 
8303 /* Bit 1 : Set as input pin 1 */
8304 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8305 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8306 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
8307 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
8308 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8309 
8310 /* Bit 0 : Set as input pin 0 */
8311 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8312 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8313 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
8314 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
8315 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
8316 
8317 /* Register: GPIO_LATCH */
8318 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
8319 
8320 /* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */
8321 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
8322 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
8323 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
8324 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
8325 
8326 /* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */
8327 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
8328 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
8329 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
8330 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
8331 
8332 /* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */
8333 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
8334 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
8335 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
8336 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
8337 
8338 /* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */
8339 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
8340 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
8341 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
8342 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
8343 
8344 /* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */
8345 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
8346 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
8347 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
8348 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
8349 
8350 /* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */
8351 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
8352 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
8353 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
8354 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
8355 
8356 /* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */
8357 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
8358 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
8359 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
8360 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
8361 
8362 /* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */
8363 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
8364 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
8365 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
8366 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
8367 
8368 /* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */
8369 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
8370 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
8371 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
8372 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
8373 
8374 /* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */
8375 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
8376 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
8377 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
8378 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
8379 
8380 /* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */
8381 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
8382 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
8383 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
8384 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
8385 
8386 /* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */
8387 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
8388 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
8389 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
8390 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
8391 
8392 /* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */
8393 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
8394 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
8395 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
8396 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
8397 
8398 /* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */
8399 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
8400 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
8401 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
8402 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
8403 
8404 /* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */
8405 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
8406 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
8407 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
8408 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
8409 
8410 /* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */
8411 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
8412 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
8413 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
8414 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
8415 
8416 /* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */
8417 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
8418 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
8419 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
8420 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
8421 
8422 /* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */
8423 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
8424 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
8425 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
8426 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
8427 
8428 /* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */
8429 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
8430 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
8431 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
8432 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
8433 
8434 /* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */
8435 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
8436 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
8437 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
8438 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
8439 
8440 /* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */
8441 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
8442 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
8443 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
8444 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
8445 
8446 /* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */
8447 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
8448 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
8449 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
8450 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
8451 
8452 /* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */
8453 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
8454 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
8455 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
8456 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
8457 
8458 /* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */
8459 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
8460 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
8461 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
8462 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
8463 
8464 /* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */
8465 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
8466 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
8467 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
8468 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
8469 
8470 /* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */
8471 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
8472 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
8473 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
8474 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
8475 
8476 /* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */
8477 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
8478 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
8479 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
8480 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
8481 
8482 /* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */
8483 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
8484 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
8485 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
8486 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
8487 
8488 /* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */
8489 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
8490 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
8491 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
8492 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
8493 
8494 /* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */
8495 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
8496 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
8497 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
8498 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
8499 
8500 /* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */
8501 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
8502 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
8503 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
8504 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
8505 
8506 /* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */
8507 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
8508 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
8509 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
8510 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
8511 
8512 /* Register: GPIO_DETECTMODE */
8513 /* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */
8514 
8515 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
8516 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
8517 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
8518 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
8519 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
8520 
8521 /* Register: GPIO_DETECTMODE_SEC */
8522 /* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */
8523 
8524 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
8525 #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
8526 #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
8527 #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
8528 #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */
8529 
8530 /* Register: GPIO_PIN_CNF */
8531 /* Description: Description collection: Configuration of GPIO pins */
8532 
8533 /* Bits 30..28 : Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code. */
8534 #define GPIO_PIN_CNF_MCUSEL_Pos (28UL) /*!< Position of MCUSEL field. */
8535 #define GPIO_PIN_CNF_MCUSEL_Msk (0x7UL << GPIO_PIN_CNF_MCUSEL_Pos) /*!< Bit mask of MCUSEL field. */
8536 #define GPIO_PIN_CNF_MCUSEL_AppMCU (0x0UL) /*!< Application MCU */
8537 #define GPIO_PIN_CNF_MCUSEL_NetworkMCU (0x1UL) /*!< Network MCU */
8538 #define GPIO_PIN_CNF_MCUSEL_Peripheral (0x3UL) /*!< Peripheral with dedicated pins */
8539 #define GPIO_PIN_CNF_MCUSEL_TND (0x7UL) /*!< Trace and Debug Subsystem */
8540 
8541 /* Bits 17..16 : Pin sensing mechanism */
8542 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
8543 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
8544 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
8545 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
8546 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
8547 
8548 /* Bits 11..8 : Drive configuration */
8549 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
8550 #define GPIO_PIN_CNF_DRIVE_Msk (0xFUL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
8551 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
8552 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
8553 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
8554 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
8555 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */
8556 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
8557 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */
8558 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
8559 #define GPIO_PIN_CNF_DRIVE_E0E1 (11UL) /*!< Extra high drive '0', extra high drive '1' */
8560 
8561 /* Bits 3..2 : Pull configuration */
8562 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
8563 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
8564 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
8565 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
8566 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
8567 
8568 /* Bit 1 : Connect or disconnect input buffer */
8569 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
8570 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
8571 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
8572 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
8573 
8574 /* Bit 0 : Pin direction. Same physical register as DIR register */
8575 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
8576 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
8577 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
8578 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
8579 
8580 
8581 /* Peripheral: PDM */
8582 /* Description: Pulse Density Modulation (Digital Microphone) Interface 0 */
8583 
8584 /* Register: PDM_TASKS_START */
8585 /* Description: Starts continuous PDM transfer */
8586 
8587 /* Bit 0 : Starts continuous PDM transfer */
8588 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8589 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8590 #define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8591 
8592 /* Register: PDM_TASKS_STOP */
8593 /* Description: Stops PDM transfer */
8594 
8595 /* Bit 0 : Stops PDM transfer */
8596 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8597 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8598 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8599 
8600 /* Register: PDM_SUBSCRIBE_START */
8601 /* Description: Subscribe configuration for task START */
8602 
8603 /* Bit 31 :   */
8604 #define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
8605 #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
8606 #define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
8607 #define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
8608 
8609 /* Bits 7..0 : DPPI channel that task START will subscribe to */
8610 #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8611 #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8612 
8613 /* Register: PDM_SUBSCRIBE_STOP */
8614 /* Description: Subscribe configuration for task STOP */
8615 
8616 /* Bit 31 :   */
8617 #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
8618 #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
8619 #define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8620 #define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8621 
8622 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
8623 #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8624 #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8625 
8626 /* Register: PDM_EVENTS_STARTED */
8627 /* Description: PDM transfer has started */
8628 
8629 /* Bit 0 : PDM transfer has started */
8630 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
8631 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
8632 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
8633 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
8634 
8635 /* Register: PDM_EVENTS_STOPPED */
8636 /* Description: PDM transfer has finished */
8637 
8638 /* Bit 0 : PDM transfer has finished */
8639 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8640 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8641 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8642 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8643 
8644 /* Register: PDM_EVENTS_END */
8645 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
8646 
8647 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
8648 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
8649 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
8650 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
8651 #define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
8652 
8653 /* Register: PDM_PUBLISH_STARTED */
8654 /* Description: Publish configuration for event STARTED */
8655 
8656 /* Bit 31 :   */
8657 #define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
8658 #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
8659 #define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
8660 #define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
8661 
8662 /* Bits 7..0 : DPPI channel that event STARTED will publish to. */
8663 #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8664 #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8665 
8666 /* Register: PDM_PUBLISH_STOPPED */
8667 /* Description: Publish configuration for event STOPPED */
8668 
8669 /* Bit 31 :   */
8670 #define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
8671 #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
8672 #define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
8673 #define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
8674 
8675 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
8676 #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8677 #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8678 
8679 /* Register: PDM_PUBLISH_END */
8680 /* Description: Publish configuration for event END */
8681 
8682 /* Bit 31 :   */
8683 #define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
8684 #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
8685 #define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
8686 #define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
8687 
8688 /* Bits 7..0 : DPPI channel that event END will publish to. */
8689 #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8690 #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8691 
8692 /* Register: PDM_INTEN */
8693 /* Description: Enable or disable interrupt */
8694 
8695 /* Bit 2 : Enable or disable interrupt for event END */
8696 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
8697 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
8698 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
8699 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
8700 
8701 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8702 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8703 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8704 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8705 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8706 
8707 /* Bit 0 : Enable or disable interrupt for event STARTED */
8708 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
8709 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
8710 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
8711 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
8712 
8713 /* Register: PDM_INTENSET */
8714 /* Description: Enable interrupt */
8715 
8716 /* Bit 2 : Write '1' to enable interrupt for event END */
8717 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
8718 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
8719 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8720 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8721 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
8722 
8723 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
8724 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8725 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8726 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8727 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8728 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8729 
8730 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
8731 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
8732 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
8733 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
8734 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
8735 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
8736 
8737 /* Register: PDM_INTENCLR */
8738 /* Description: Disable interrupt */
8739 
8740 /* Bit 2 : Write '1' to disable interrupt for event END */
8741 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
8742 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
8743 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
8744 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8745 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
8746 
8747 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
8748 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8749 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8750 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8751 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8752 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8753 
8754 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
8755 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
8756 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
8757 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
8758 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
8759 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
8760 
8761 /* Register: PDM_ENABLE */
8762 /* Description: PDM module enable register */
8763 
8764 /* Bit 0 : Enable or disable PDM module */
8765 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8766 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8767 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
8768 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8769 
8770 /* Register: PDM_PDMCLKCTRL */
8771 /* Description: PDM clock generator control */
8772 
8773 /* Bits 31..0 : PDM_CLK frequency configuration. Enumerations are deprecated, use
8774         PDMCLKCTRL equation to find the register value. The 12 least significant bits of the
8775         register are ignored and shall be set to zero. */
8776 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
8777 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
8778 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
8779 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
8780 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
8781 #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
8782 #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
8783 #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
8784 
8785 /* Register: PDM_MODE */
8786 /* Description: Defines the routing of the connected PDM microphones' signals */
8787 
8788 /* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
8789 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
8790 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
8791 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
8792 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
8793 
8794 /* Bit 0 : Mono or stereo operation */
8795 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
8796 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
8797 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */
8798 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */
8799 
8800 /* Register: PDM_GAINL */
8801 /* Description: Left output gain adjustment */
8802 
8803 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
8804 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
8805 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
8806 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
8807 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
8808 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
8809 
8810 /* Register: PDM_GAINR */
8811 /* Description: Right output gain adjustment */
8812 
8813 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
8814 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
8815 #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
8816 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */
8817 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */
8818 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */
8819 
8820 /* Register: PDM_RATIO */
8821 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
8822 
8823 /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
8824 #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
8825 #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
8826 #define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */
8827 #define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
8828 
8829 /* Register: PDM_PSEL_CLK */
8830 /* Description: Pin number configuration for PDM CLK signal */
8831 
8832 /* Bit 31 : Connection */
8833 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8834 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8835 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
8836 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
8837 
8838 /* Bit 5 : Port number */
8839 #define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */
8840 #define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */
8841 
8842 /* Bits 4..0 : Pin number */
8843 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
8844 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
8845 
8846 /* Register: PDM_PSEL_DIN */
8847 /* Description: Pin number configuration for PDM DIN signal */
8848 
8849 /* Bit 31 : Connection */
8850 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8851 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8852 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
8853 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
8854 
8855 /* Bit 5 : Port number */
8856 #define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */
8857 #define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */
8858 
8859 /* Bits 4..0 : Pin number */
8860 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
8861 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
8862 
8863 /* Register: PDM_MCLKCONFIG */
8864 /* Description: Master clock generator configuration */
8865 
8866 /* Bit 0 : Master clock source selection */
8867 #define PDM_MCLKCONFIG_SRC_Pos (0UL) /*!< Position of SRC field. */
8868 #define PDM_MCLKCONFIG_SRC_Msk (0x1UL << PDM_MCLKCONFIG_SRC_Pos) /*!< Bit mask of SRC field. */
8869 #define PDM_MCLKCONFIG_SRC_PCLK32M (0UL) /*!< 32 MHz peripheral clock */
8870 #define PDM_MCLKCONFIG_SRC_ACLK (1UL) /*!< Audio PLL clock */
8871 
8872 /* Register: PDM_SAMPLE_PTR */
8873 /* Description: RAM address pointer to write samples to with EasyDMA */
8874 
8875 /* Bits 31..0 : Address to write PDM samples to over DMA */
8876 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
8877 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
8878 
8879 /* Register: PDM_SAMPLE_MAXCNT */
8880 /* Description: Number of samples to allocate memory for in EasyDMA mode */
8881 
8882 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
8883 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
8884 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
8885 
8886 
8887 /* Peripheral: POWER */
8888 /* Description: Power control 0 */
8889 
8890 /* Register: POWER_TASKS_CONSTLAT */
8891 /* Description: Enable Constant Latency mode */
8892 
8893 /* Bit 0 : Enable Constant Latency mode */
8894 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
8895 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
8896 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
8897 
8898 /* Register: POWER_TASKS_LOWPWR */
8899 /* Description: Enable Low-Power mode (variable latency) */
8900 
8901 /* Bit 0 : Enable Low-Power mode (variable latency) */
8902 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
8903 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
8904 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
8905 
8906 /* Register: POWER_SUBSCRIBE_CONSTLAT */
8907 /* Description: Subscribe configuration for task CONSTLAT */
8908 
8909 /* Bit 31 :   */
8910 #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */
8911 #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */
8912 #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */
8913 #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */
8914 
8915 /* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */
8916 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8917 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8918 
8919 /* Register: POWER_SUBSCRIBE_LOWPWR */
8920 /* Description: Subscribe configuration for task LOWPWR */
8921 
8922 /* Bit 31 :   */
8923 #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */
8924 #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */
8925 #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */
8926 #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */
8927 
8928 /* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */
8929 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8930 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8931 
8932 /* Register: POWER_EVENTS_POFWARN */
8933 /* Description: Power failure warning */
8934 
8935 /* Bit 0 : Power failure warning */
8936 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
8937 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
8938 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
8939 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
8940 
8941 /* Register: POWER_EVENTS_SLEEPENTER */
8942 /* Description: CPU entered WFI/WFE sleep */
8943 
8944 /* Bit 0 : CPU entered WFI/WFE sleep */
8945 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
8946 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
8947 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
8948 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
8949 
8950 /* Register: POWER_EVENTS_SLEEPEXIT */
8951 /* Description: CPU exited WFI/WFE sleep */
8952 
8953 /* Bit 0 : CPU exited WFI/WFE sleep */
8954 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
8955 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
8956 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
8957 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
8958 
8959 /* Register: POWER_PUBLISH_POFWARN */
8960 /* Description: Publish configuration for event POFWARN */
8961 
8962 /* Bit 31 :   */
8963 #define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */
8964 #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */
8965 #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */
8966 #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */
8967 
8968 /* Bits 7..0 : DPPI channel that event POFWARN will publish to. */
8969 #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8970 #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8971 
8972 /* Register: POWER_PUBLISH_SLEEPENTER */
8973 /* Description: Publish configuration for event SLEEPENTER */
8974 
8975 /* Bit 31 :   */
8976 #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */
8977 #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */
8978 #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */
8979 #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */
8980 
8981 /* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to. */
8982 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8983 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8984 
8985 /* Register: POWER_PUBLISH_SLEEPEXIT */
8986 /* Description: Publish configuration for event SLEEPEXIT */
8987 
8988 /* Bit 31 :   */
8989 #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */
8990 #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */
8991 #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */
8992 #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */
8993 
8994 /* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to. */
8995 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8996 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8997 
8998 /* Register: POWER_INTEN */
8999 /* Description: Enable or disable interrupt */
9000 
9001 /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */
9002 #define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
9003 #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
9004 #define POWER_INTEN_SLEEPEXIT_Disabled (0UL) /*!< Disable */
9005 #define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */
9006 
9007 /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */
9008 #define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
9009 #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
9010 #define POWER_INTEN_SLEEPENTER_Disabled (0UL) /*!< Disable */
9011 #define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */
9012 
9013 /* Bit 2 : Enable or disable interrupt for event POFWARN */
9014 #define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
9015 #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
9016 #define POWER_INTEN_POFWARN_Disabled (0UL) /*!< Disable */
9017 #define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */
9018 
9019 /* Register: POWER_INTENSET */
9020 /* Description: Enable interrupt */
9021 
9022 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
9023 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
9024 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
9025 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
9026 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
9027 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
9028 
9029 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
9030 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
9031 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
9032 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
9033 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
9034 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
9035 
9036 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
9037 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
9038 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
9039 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
9040 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
9041 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
9042 
9043 /* Register: POWER_INTENCLR */
9044 /* Description: Disable interrupt */
9045 
9046 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
9047 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
9048 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
9049 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
9050 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
9051 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
9052 
9053 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
9054 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
9055 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
9056 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
9057 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
9058 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
9059 
9060 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
9061 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
9062 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
9063 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
9064 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
9065 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
9066 
9067 /* Register: POWER_GPREGRET */
9068 /* Description: Description collection: General purpose retention register */
9069 
9070 /* Bits 7..0 : General purpose retention register */
9071 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
9072 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
9073 
9074 
9075 /* Peripheral: PWM */
9076 /* Description: Pulse width modulation unit 0 */
9077 
9078 /* Register: PWM_TASKS_STOP */
9079 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
9080 
9081 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
9082 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9083 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9084 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9085 
9086 /* Register: PWM_TASKS_SEQSTART */
9087 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
9088 
9089 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
9090 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
9091 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
9092 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
9093 
9094 /* Register: PWM_TASKS_NEXTSTEP */
9095 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
9096 
9097 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
9098 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
9099 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
9100 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
9101 
9102 /* Register: PWM_SUBSCRIBE_STOP */
9103 /* Description: Subscribe configuration for task STOP */
9104 
9105 /* Bit 31 :   */
9106 #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
9107 #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
9108 #define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
9109 #define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
9110 
9111 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
9112 #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9113 #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9114 
9115 /* Register: PWM_SUBSCRIBE_SEQSTART */
9116 /* Description: Description collection: Subscribe configuration for task SEQSTART[n] */
9117 
9118 /* Bit 31 :   */
9119 #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */
9120 #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */
9121 #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */
9122 #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */
9123 
9124 /* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */
9125 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9126 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9127 
9128 /* Register: PWM_SUBSCRIBE_NEXTSTEP */
9129 /* Description: Subscribe configuration for task NEXTSTEP */
9130 
9131 /* Bit 31 :   */
9132 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */
9133 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */
9134 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */
9135 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */
9136 
9137 /* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */
9138 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9139 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9140 
9141 /* Register: PWM_EVENTS_STOPPED */
9142 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
9143 
9144 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
9145 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9146 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9147 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9148 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9149 
9150 /* Register: PWM_EVENTS_SEQSTARTED */
9151 /* Description: Description collection: First PWM period started on sequence n */
9152 
9153 /* Bit 0 : First PWM period started on sequence n */
9154 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
9155 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
9156 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
9157 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
9158 
9159 /* Register: PWM_EVENTS_SEQEND */
9160 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
9161 
9162 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
9163 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
9164 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
9165 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
9166 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
9167 
9168 /* Register: PWM_EVENTS_PWMPERIODEND */
9169 /* Description: Emitted at the end of each PWM period */
9170 
9171 /* Bit 0 : Emitted at the end of each PWM period */
9172 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
9173 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
9174 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
9175 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
9176 
9177 /* Register: PWM_EVENTS_LOOPSDONE */
9178 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
9179 
9180 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
9181 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
9182 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
9183 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
9184 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
9185 
9186 /* Register: PWM_PUBLISH_STOPPED */
9187 /* Description: Publish configuration for event STOPPED */
9188 
9189 /* Bit 31 :   */
9190 #define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
9191 #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
9192 #define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
9193 #define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
9194 
9195 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
9196 #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9197 #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9198 
9199 /* Register: PWM_PUBLISH_SEQSTARTED */
9200 /* Description: Description collection: Publish configuration for event SEQSTARTED[n] */
9201 
9202 /* Bit 31 :   */
9203 #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
9204 #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */
9205 #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
9206 #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
9207 
9208 /* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to. */
9209 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9210 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9211 
9212 /* Register: PWM_PUBLISH_SEQEND */
9213 /* Description: Description collection: Publish configuration for event SEQEND[n] */
9214 
9215 /* Bit 31 :   */
9216 #define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */
9217 #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */
9218 #define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */
9219 #define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */
9220 
9221 /* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to. */
9222 #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9223 #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9224 
9225 /* Register: PWM_PUBLISH_PWMPERIODEND */
9226 /* Description: Publish configuration for event PWMPERIODEND */
9227 
9228 /* Bit 31 :   */
9229 #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */
9230 #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */
9231 #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */
9232 #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */
9233 
9234 /* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to. */
9235 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9236 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9237 
9238 /* Register: PWM_PUBLISH_LOOPSDONE */
9239 /* Description: Publish configuration for event LOOPSDONE */
9240 
9241 /* Bit 31 :   */
9242 #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */
9243 #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */
9244 #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */
9245 #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */
9246 
9247 /* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to. */
9248 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9249 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9250 
9251 /* Register: PWM_SHORTS */
9252 /* Description: Shortcuts between local events and tasks */
9253 
9254 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
9255 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
9256 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
9257 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
9258 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
9259 
9260 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
9261 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
9262 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
9263 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
9264 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
9265 
9266 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
9267 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
9268 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
9269 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
9270 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
9271 
9272 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
9273 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
9274 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
9275 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
9276 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
9277 
9278 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
9279 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
9280 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
9281 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
9282 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
9283 
9284 /* Register: PWM_INTEN */
9285 /* Description: Enable or disable interrupt */
9286 
9287 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
9288 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
9289 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
9290 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
9291 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
9292 
9293 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
9294 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
9295 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
9296 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
9297 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
9298 
9299 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
9300 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
9301 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
9302 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
9303 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
9304 
9305 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
9306 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
9307 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
9308 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
9309 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
9310 
9311 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
9312 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
9313 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
9314 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
9315 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
9316 
9317 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
9318 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
9319 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
9320 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
9321 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
9322 
9323 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9324 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9325 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9326 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9327 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9328 
9329 /* Register: PWM_INTENSET */
9330 /* Description: Enable interrupt */
9331 
9332 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
9333 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
9334 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
9335 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
9336 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
9337 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
9338 
9339 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
9340 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
9341 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
9342 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
9343 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
9344 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
9345 
9346 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
9347 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
9348 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
9349 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
9350 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
9351 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
9352 
9353 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
9354 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
9355 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
9356 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
9357 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
9358 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
9359 
9360 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
9361 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
9362 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
9363 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
9364 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
9365 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
9366 
9367 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
9368 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
9369 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
9370 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
9371 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
9372 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
9373 
9374 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9375 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9376 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9377 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9378 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9379 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9380 
9381 /* Register: PWM_INTENCLR */
9382 /* Description: Disable interrupt */
9383 
9384 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
9385 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
9386 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
9387 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
9388 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
9389 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
9390 
9391 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
9392 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
9393 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
9394 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
9395 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
9396 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
9397 
9398 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
9399 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
9400 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
9401 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
9402 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
9403 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
9404 
9405 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
9406 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
9407 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
9408 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
9409 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
9410 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
9411 
9412 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
9413 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
9414 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
9415 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
9416 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
9417 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
9418 
9419 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
9420 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
9421 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
9422 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
9423 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
9424 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
9425 
9426 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9427 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9428 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9429 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9430 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9431 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9432 
9433 /* Register: PWM_ENABLE */
9434 /* Description: PWM module enable register */
9435 
9436 /* Bit 0 : Enable or disable PWM module */
9437 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9438 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9439 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
9440 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
9441 
9442 /* Register: PWM_MODE */
9443 /* Description: Selects operating mode of the wave counter */
9444 
9445 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
9446 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
9447 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
9448 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
9449 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
9450 
9451 /* Register: PWM_COUNTERTOP */
9452 /* Description: Value up to which the pulse generator counter counts */
9453 
9454 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
9455 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
9456 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
9457 
9458 /* Register: PWM_PRESCALER */
9459 /* Description: Configuration for PWM_CLK */
9460 
9461 /* Bits 2..0 : Prescaler of PWM_CLK */
9462 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
9463 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
9464 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */
9465 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
9466 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
9467 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
9468 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */
9469 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */
9470 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */
9471 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */
9472 
9473 /* Register: PWM_DECODER */
9474 /* Description: Configuration of the decoder */
9475 
9476 /* Bit 8 : Selects source for advancing the active sequence */
9477 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
9478 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
9479 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
9480 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
9481 
9482 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
9483 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
9484 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
9485 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
9486 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
9487 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
9488 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
9489 
9490 /* Register: PWM_LOOP */
9491 /* Description: Number of playbacks of a loop */
9492 
9493 /* Bits 15..0 : Number of playbacks of pattern cycles */
9494 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
9495 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
9496 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
9497 
9498 /* Register: PWM_SEQ_PTR */
9499 /* Description: Description cluster: Beginning address in RAM of this sequence */
9500 
9501 /* Bits 31..0 : Beginning address in RAM of this sequence */
9502 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9503 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9504 
9505 /* Register: PWM_SEQ_CNT */
9506 /* Description: Description cluster: Number of values (duty cycles) in this sequence */
9507 
9508 /* Bits 14..0 : Number of values (duty cycles) in this sequence */
9509 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
9510 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
9511 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
9512 
9513 /* Register: PWM_SEQ_REFRESH */
9514 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
9515 
9516 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
9517 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
9518 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
9519 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
9520 
9521 /* Register: PWM_SEQ_ENDDELAY */
9522 /* Description: Description cluster: Time added after the sequence */
9523 
9524 /* Bits 23..0 : Time added after the sequence in PWM periods */
9525 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
9526 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
9527 
9528 /* Register: PWM_PSEL_OUT */
9529 /* Description: Description collection: Output pin select for PWM channel n */
9530 
9531 /* Bit 31 : Connection */
9532 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9533 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9534 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
9535 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
9536 
9537 /* Bit 5 : Port number */
9538 #define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */
9539 #define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */
9540 
9541 /* Bits 4..0 : Pin number */
9542 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
9543 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
9544 
9545 
9546 /* Peripheral: QDEC */
9547 /* Description: Quadrature Decoder 0 */
9548 
9549 /* Register: QDEC_TASKS_START */
9550 /* Description: Task starting the quadrature decoder */
9551 
9552 /* Bit 0 : Task starting the quadrature decoder */
9553 #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
9554 #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
9555 #define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
9556 
9557 /* Register: QDEC_TASKS_STOP */
9558 /* Description: Task stopping the quadrature decoder */
9559 
9560 /* Bit 0 : Task stopping the quadrature decoder */
9561 #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9562 #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9563 #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9564 
9565 /* Register: QDEC_TASKS_READCLRACC */
9566 /* Description: Read and clear ACC and ACCDBL */
9567 
9568 /* Bit 0 : Read and clear ACC and ACCDBL */
9569 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
9570 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
9571 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */
9572 
9573 /* Register: QDEC_TASKS_RDCLRACC */
9574 /* Description: Read and clear ACC */
9575 
9576 /* Bit 0 : Read and clear ACC */
9577 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
9578 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
9579 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */
9580 
9581 /* Register: QDEC_TASKS_RDCLRDBL */
9582 /* Description: Read and clear ACCDBL */
9583 
9584 /* Bit 0 : Read and clear ACCDBL */
9585 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
9586 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
9587 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */
9588 
9589 /* Register: QDEC_SUBSCRIBE_START */
9590 /* Description: Subscribe configuration for task START */
9591 
9592 /* Bit 31 :   */
9593 #define QDEC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
9594 #define QDEC_SUBSCRIBE_START_EN_Msk (0x1UL << QDEC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
9595 #define QDEC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
9596 #define QDEC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
9597 
9598 /* Bits 7..0 : DPPI channel that task START will subscribe to */
9599 #define QDEC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9600 #define QDEC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9601 
9602 /* Register: QDEC_SUBSCRIBE_STOP */
9603 /* Description: Subscribe configuration for task STOP */
9604 
9605 /* Bit 31 :   */
9606 #define QDEC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
9607 #define QDEC_SUBSCRIBE_STOP_EN_Msk (0x1UL << QDEC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
9608 #define QDEC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
9609 #define QDEC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
9610 
9611 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
9612 #define QDEC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9613 #define QDEC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9614 
9615 /* Register: QDEC_SUBSCRIBE_READCLRACC */
9616 /* Description: Subscribe configuration for task READCLRACC */
9617 
9618 /* Bit 31 :   */
9619 #define QDEC_SUBSCRIBE_READCLRACC_EN_Pos (31UL) /*!< Position of EN field. */
9620 #define QDEC_SUBSCRIBE_READCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_READCLRACC_EN_Pos) /*!< Bit mask of EN field. */
9621 #define QDEC_SUBSCRIBE_READCLRACC_EN_Disabled (0UL) /*!< Disable subscription */
9622 #define QDEC_SUBSCRIBE_READCLRACC_EN_Enabled (1UL) /*!< Enable subscription */
9623 
9624 /* Bits 7..0 : DPPI channel that task READCLRACC will subscribe to */
9625 #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9626 #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9627 
9628 /* Register: QDEC_SUBSCRIBE_RDCLRACC */
9629 /* Description: Subscribe configuration for task RDCLRACC */
9630 
9631 /* Bit 31 :   */
9632 #define QDEC_SUBSCRIBE_RDCLRACC_EN_Pos (31UL) /*!< Position of EN field. */
9633 #define QDEC_SUBSCRIBE_RDCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRACC_EN_Pos) /*!< Bit mask of EN field. */
9634 #define QDEC_SUBSCRIBE_RDCLRACC_EN_Disabled (0UL) /*!< Disable subscription */
9635 #define QDEC_SUBSCRIBE_RDCLRACC_EN_Enabled (1UL) /*!< Enable subscription */
9636 
9637 /* Bits 7..0 : DPPI channel that task RDCLRACC will subscribe to */
9638 #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9639 #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9640 
9641 /* Register: QDEC_SUBSCRIBE_RDCLRDBL */
9642 /* Description: Subscribe configuration for task RDCLRDBL */
9643 
9644 /* Bit 31 :   */
9645 #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos (31UL) /*!< Position of EN field. */
9646 #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos) /*!< Bit mask of EN field. */
9647 #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Disabled (0UL) /*!< Disable subscription */
9648 #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Enabled (1UL) /*!< Enable subscription */
9649 
9650 /* Bits 7..0 : DPPI channel that task RDCLRDBL will subscribe to */
9651 #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9652 #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9653 
9654 /* Register: QDEC_EVENTS_SAMPLERDY */
9655 /* Description: Event being generated for every new sample value written to the SAMPLE register */
9656 
9657 /* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
9658 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
9659 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
9660 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */
9661 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */
9662 
9663 /* Register: QDEC_EVENTS_REPORTRDY */
9664 /* Description: Non-null report ready */
9665 
9666 /* Bit 0 : Non-null report ready */
9667 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
9668 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
9669 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */
9670 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */
9671 
9672 /* Register: QDEC_EVENTS_ACCOF */
9673 /* Description: ACC or ACCDBL register overflow */
9674 
9675 /* Bit 0 : ACC or ACCDBL register overflow */
9676 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
9677 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
9678 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */
9679 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */
9680 
9681 /* Register: QDEC_EVENTS_DBLRDY */
9682 /* Description: Double displacement(s) detected */
9683 
9684 /* Bit 0 : Double displacement(s) detected */
9685 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
9686 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
9687 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */
9688 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */
9689 
9690 /* Register: QDEC_EVENTS_STOPPED */
9691 /* Description: QDEC has been stopped */
9692 
9693 /* Bit 0 : QDEC has been stopped */
9694 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9695 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9696 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9697 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9698 
9699 /* Register: QDEC_PUBLISH_SAMPLERDY */
9700 /* Description: Publish configuration for event SAMPLERDY */
9701 
9702 /* Bit 31 :   */
9703 #define QDEC_PUBLISH_SAMPLERDY_EN_Pos (31UL) /*!< Position of EN field. */
9704 #define QDEC_PUBLISH_SAMPLERDY_EN_Msk (0x1UL << QDEC_PUBLISH_SAMPLERDY_EN_Pos) /*!< Bit mask of EN field. */
9705 #define QDEC_PUBLISH_SAMPLERDY_EN_Disabled (0UL) /*!< Disable publishing */
9706 #define QDEC_PUBLISH_SAMPLERDY_EN_Enabled (1UL) /*!< Enable publishing */
9707 
9708 /* Bits 7..0 : DPPI channel that event SAMPLERDY will publish to. */
9709 #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9710 #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9711 
9712 /* Register: QDEC_PUBLISH_REPORTRDY */
9713 /* Description: Publish configuration for event REPORTRDY */
9714 
9715 /* Bit 31 :   */
9716 #define QDEC_PUBLISH_REPORTRDY_EN_Pos (31UL) /*!< Position of EN field. */
9717 #define QDEC_PUBLISH_REPORTRDY_EN_Msk (0x1UL << QDEC_PUBLISH_REPORTRDY_EN_Pos) /*!< Bit mask of EN field. */
9718 #define QDEC_PUBLISH_REPORTRDY_EN_Disabled (0UL) /*!< Disable publishing */
9719 #define QDEC_PUBLISH_REPORTRDY_EN_Enabled (1UL) /*!< Enable publishing */
9720 
9721 /* Bits 7..0 : DPPI channel that event REPORTRDY will publish to. */
9722 #define QDEC_PUBLISH_REPORTRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9723 #define QDEC_PUBLISH_REPORTRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_REPORTRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9724 
9725 /* Register: QDEC_PUBLISH_ACCOF */
9726 /* Description: Publish configuration for event ACCOF */
9727 
9728 /* Bit 31 :   */
9729 #define QDEC_PUBLISH_ACCOF_EN_Pos (31UL) /*!< Position of EN field. */
9730 #define QDEC_PUBLISH_ACCOF_EN_Msk (0x1UL << QDEC_PUBLISH_ACCOF_EN_Pos) /*!< Bit mask of EN field. */
9731 #define QDEC_PUBLISH_ACCOF_EN_Disabled (0UL) /*!< Disable publishing */
9732 #define QDEC_PUBLISH_ACCOF_EN_Enabled (1UL) /*!< Enable publishing */
9733 
9734 /* Bits 7..0 : DPPI channel that event ACCOF will publish to. */
9735 #define QDEC_PUBLISH_ACCOF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9736 #define QDEC_PUBLISH_ACCOF_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_ACCOF_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9737 
9738 /* Register: QDEC_PUBLISH_DBLRDY */
9739 /* Description: Publish configuration for event DBLRDY */
9740 
9741 /* Bit 31 :   */
9742 #define QDEC_PUBLISH_DBLRDY_EN_Pos (31UL) /*!< Position of EN field. */
9743 #define QDEC_PUBLISH_DBLRDY_EN_Msk (0x1UL << QDEC_PUBLISH_DBLRDY_EN_Pos) /*!< Bit mask of EN field. */
9744 #define QDEC_PUBLISH_DBLRDY_EN_Disabled (0UL) /*!< Disable publishing */
9745 #define QDEC_PUBLISH_DBLRDY_EN_Enabled (1UL) /*!< Enable publishing */
9746 
9747 /* Bits 7..0 : DPPI channel that event DBLRDY will publish to. */
9748 #define QDEC_PUBLISH_DBLRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9749 #define QDEC_PUBLISH_DBLRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_DBLRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9750 
9751 /* Register: QDEC_PUBLISH_STOPPED */
9752 /* Description: Publish configuration for event STOPPED */
9753 
9754 /* Bit 31 :   */
9755 #define QDEC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
9756 #define QDEC_PUBLISH_STOPPED_EN_Msk (0x1UL << QDEC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
9757 #define QDEC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
9758 #define QDEC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
9759 
9760 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
9761 #define QDEC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9762 #define QDEC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9763 
9764 /* Register: QDEC_SHORTS */
9765 /* Description: Shortcuts between local events and tasks */
9766 
9767 /* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
9768 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
9769 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
9770 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9771 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9772 
9773 /* Bit 5 : Shortcut between event DBLRDY and task STOP */
9774 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
9775 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
9776 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9777 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9778 
9779 /* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
9780 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
9781 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
9782 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
9783 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
9784 
9785 /* Bit 3 : Shortcut between event REPORTRDY and task STOP */
9786 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
9787 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
9788 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9789 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9790 
9791 /* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
9792 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
9793 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
9794 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
9795 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
9796 
9797 /* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
9798 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
9799 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
9800 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9801 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9802 
9803 /* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
9804 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
9805 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
9806 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9807 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9808 
9809 /* Register: QDEC_INTENSET */
9810 /* Description: Enable interrupt */
9811 
9812 /* Bit 4 : Write '1' to enable interrupt for event STOPPED */
9813 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
9814 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9815 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9816 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9817 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9818 
9819 /* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
9820 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
9821 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
9822 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9823 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9824 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
9825 
9826 /* Bit 2 : Write '1' to enable interrupt for event ACCOF */
9827 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9828 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
9829 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9830 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9831 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
9832 
9833 /* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
9834 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
9835 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
9836 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9837 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9838 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
9839 
9840 /* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
9841 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
9842 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
9843 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9844 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9845 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
9846 
9847 /* Register: QDEC_INTENCLR */
9848 /* Description: Disable interrupt */
9849 
9850 /* Bit 4 : Write '1' to disable interrupt for event STOPPED */
9851 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
9852 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9853 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9854 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9855 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9856 
9857 /* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
9858 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
9859 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
9860 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9861 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9862 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
9863 
9864 /* Bit 2 : Write '1' to disable interrupt for event ACCOF */
9865 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9866 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
9867 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9868 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9869 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
9870 
9871 /* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
9872 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
9873 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
9874 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9875 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9876 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
9877 
9878 /* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
9879 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
9880 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
9881 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9882 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9883 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
9884 
9885 /* Register: QDEC_ENABLE */
9886 /* Description: Enable the quadrature decoder */
9887 
9888 /* Bit 0 : Enable or disable the quadrature decoder */
9889 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9890 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9891 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
9892 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
9893 
9894 /* Register: QDEC_LEDPOL */
9895 /* Description: LED output pin polarity */
9896 
9897 /* Bit 0 : LED output pin polarity */
9898 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
9899 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
9900 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
9901 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
9902 
9903 /* Register: QDEC_SAMPLEPER */
9904 /* Description: Sample period */
9905 
9906 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
9907 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
9908 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
9909 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
9910 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
9911 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
9912 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
9913 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
9914 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
9915 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
9916 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
9917 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
9918 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
9919 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
9920 
9921 /* Register: QDEC_SAMPLE */
9922 /* Description: Motion sample value */
9923 
9924 /* Bits 31..0 : Last motion sample */
9925 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
9926 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
9927 
9928 /* Register: QDEC_REPORTPER */
9929 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
9930 
9931 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */
9932 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
9933 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
9934 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */
9935 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */
9936 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */
9937 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */
9938 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */
9939 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */
9940 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */
9941 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */
9942 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */
9943 
9944 /* Register: QDEC_ACC */
9945 /* Description: Register accumulating the valid transitions */
9946 
9947 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */
9948 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
9949 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
9950 
9951 /* Register: QDEC_ACCREAD */
9952 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
9953 
9954 /* Bits 31..0 : Snapshot of the ACC register. */
9955 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
9956 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
9957 
9958 /* Register: QDEC_PSEL_LED */
9959 /* Description: Pin select for LED signal */
9960 
9961 /* Bit 31 : Connection */
9962 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9963 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9964 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
9965 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
9966 
9967 /* Bit 5 : Port number */
9968 #define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */
9969 #define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */
9970 
9971 /* Bits 4..0 : Pin number */
9972 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
9973 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
9974 
9975 /* Register: QDEC_PSEL_A */
9976 /* Description: Pin select for A signal */
9977 
9978 /* Bit 31 : Connection */
9979 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9980 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9981 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
9982 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
9983 
9984 /* Bit 5 : Port number */
9985 #define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */
9986 #define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */
9987 
9988 /* Bits 4..0 : Pin number */
9989 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
9990 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
9991 
9992 /* Register: QDEC_PSEL_B */
9993 /* Description: Pin select for B signal */
9994 
9995 /* Bit 31 : Connection */
9996 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9997 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9998 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
9999 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
10000 
10001 /* Bit 5 : Port number */
10002 #define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */
10003 #define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */
10004 
10005 /* Bits 4..0 : Pin number */
10006 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
10007 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
10008 
10009 /* Register: QDEC_DBFEN */
10010 /* Description: Enable input debounce filters */
10011 
10012 /* Bit 0 : Enable input debounce filters */
10013 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
10014 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
10015 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
10016 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
10017 
10018 /* Register: QDEC_LEDPRE */
10019 /* Description: Time period the LED is switched ON prior to sampling */
10020 
10021 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
10022 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
10023 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
10024 
10025 /* Register: QDEC_ACCDBL */
10026 /* Description: Register accumulating the number of detected double transitions */
10027 
10028 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
10029 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
10030 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
10031 
10032 /* Register: QDEC_ACCDBLREAD */
10033 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
10034 
10035 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
10036 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
10037 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
10038 
10039 
10040 /* Peripheral: QSPI */
10041 /* Description: External flash interface 0 */
10042 
10043 /* Register: QSPI_TASKS_ACTIVATE */
10044 /* Description: Activate QSPI interface */
10045 
10046 /* Bit 0 : Activate QSPI interface */
10047 #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
10048 #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
10049 #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */
10050 
10051 /* Register: QSPI_TASKS_READSTART */
10052 /* Description: Start transfer from external flash memory to internal RAM */
10053 
10054 /* Bit 0 : Start transfer from external flash memory to internal RAM */
10055 #define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */
10056 #define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */
10057 #define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (1UL) /*!< Trigger task */
10058 
10059 /* Register: QSPI_TASKS_WRITESTART */
10060 /* Description: Start transfer from internal RAM to external flash memory */
10061 
10062 /* Bit 0 : Start transfer from internal RAM to external flash memory */
10063 #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */
10064 #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */
10065 #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (1UL) /*!< Trigger task */
10066 
10067 /* Register: QSPI_TASKS_ERASESTART */
10068 /* Description: Start external flash memory erase operation */
10069 
10070 /* Bit 0 : Start external flash memory erase operation */
10071 #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */
10072 #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */
10073 #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (1UL) /*!< Trigger task */
10074 
10075 /* Register: QSPI_TASKS_DEACTIVATE */
10076 /* Description: Deactivate QSPI interface */
10077 
10078 /* Bit 0 : Deactivate QSPI interface */
10079 #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */
10080 #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */
10081 #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (1UL) /*!< Trigger task */
10082 
10083 /* Register: QSPI_SUBSCRIBE_ACTIVATE */
10084 /* Description: Subscribe configuration for task ACTIVATE */
10085 
10086 /* Bit 31 :   */
10087 #define QSPI_SUBSCRIBE_ACTIVATE_EN_Pos (31UL) /*!< Position of EN field. */
10088 #define QSPI_SUBSCRIBE_ACTIVATE_EN_Msk (0x1UL << QSPI_SUBSCRIBE_ACTIVATE_EN_Pos) /*!< Bit mask of EN field. */
10089 #define QSPI_SUBSCRIBE_ACTIVATE_EN_Disabled (0UL) /*!< Disable subscription */
10090 #define QSPI_SUBSCRIBE_ACTIVATE_EN_Enabled (1UL) /*!< Enable subscription */
10091 
10092 /* Bits 7..0 : DPPI channel that task ACTIVATE will subscribe to */
10093 #define QSPI_SUBSCRIBE_ACTIVATE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10094 #define QSPI_SUBSCRIBE_ACTIVATE_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_ACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10095 
10096 /* Register: QSPI_SUBSCRIBE_READSTART */
10097 /* Description: Subscribe configuration for task READSTART */
10098 
10099 /* Bit 31 :   */
10100 #define QSPI_SUBSCRIBE_READSTART_EN_Pos (31UL) /*!< Position of EN field. */
10101 #define QSPI_SUBSCRIBE_READSTART_EN_Msk (0x1UL << QSPI_SUBSCRIBE_READSTART_EN_Pos) /*!< Bit mask of EN field. */
10102 #define QSPI_SUBSCRIBE_READSTART_EN_Disabled (0UL) /*!< Disable subscription */
10103 #define QSPI_SUBSCRIBE_READSTART_EN_Enabled (1UL) /*!< Enable subscription */
10104 
10105 /* Bits 7..0 : DPPI channel that task READSTART will subscribe to */
10106 #define QSPI_SUBSCRIBE_READSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10107 #define QSPI_SUBSCRIBE_READSTART_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_READSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10108 
10109 /* Register: QSPI_SUBSCRIBE_WRITESTART */
10110 /* Description: Subscribe configuration for task WRITESTART */
10111 
10112 /* Bit 31 :   */
10113 #define QSPI_SUBSCRIBE_WRITESTART_EN_Pos (31UL) /*!< Position of EN field. */
10114 #define QSPI_SUBSCRIBE_WRITESTART_EN_Msk (0x1UL << QSPI_SUBSCRIBE_WRITESTART_EN_Pos) /*!< Bit mask of EN field. */
10115 #define QSPI_SUBSCRIBE_WRITESTART_EN_Disabled (0UL) /*!< Disable subscription */
10116 #define QSPI_SUBSCRIBE_WRITESTART_EN_Enabled (1UL) /*!< Enable subscription */
10117 
10118 /* Bits 7..0 : DPPI channel that task WRITESTART will subscribe to */
10119 #define QSPI_SUBSCRIBE_WRITESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10120 #define QSPI_SUBSCRIBE_WRITESTART_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_WRITESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10121 
10122 /* Register: QSPI_SUBSCRIBE_ERASESTART */
10123 /* Description: Subscribe configuration for task ERASESTART */
10124 
10125 /* Bit 31 :   */
10126 #define QSPI_SUBSCRIBE_ERASESTART_EN_Pos (31UL) /*!< Position of EN field. */
10127 #define QSPI_SUBSCRIBE_ERASESTART_EN_Msk (0x1UL << QSPI_SUBSCRIBE_ERASESTART_EN_Pos) /*!< Bit mask of EN field. */
10128 #define QSPI_SUBSCRIBE_ERASESTART_EN_Disabled (0UL) /*!< Disable subscription */
10129 #define QSPI_SUBSCRIBE_ERASESTART_EN_Enabled (1UL) /*!< Enable subscription */
10130 
10131 /* Bits 7..0 : DPPI channel that task ERASESTART will subscribe to */
10132 #define QSPI_SUBSCRIBE_ERASESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10133 #define QSPI_SUBSCRIBE_ERASESTART_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_ERASESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10134 
10135 /* Register: QSPI_SUBSCRIBE_DEACTIVATE */
10136 /* Description: Subscribe configuration for task DEACTIVATE */
10137 
10138 /* Bit 31 :   */
10139 #define QSPI_SUBSCRIBE_DEACTIVATE_EN_Pos (31UL) /*!< Position of EN field. */
10140 #define QSPI_SUBSCRIBE_DEACTIVATE_EN_Msk (0x1UL << QSPI_SUBSCRIBE_DEACTIVATE_EN_Pos) /*!< Bit mask of EN field. */
10141 #define QSPI_SUBSCRIBE_DEACTIVATE_EN_Disabled (0UL) /*!< Disable subscription */
10142 #define QSPI_SUBSCRIBE_DEACTIVATE_EN_Enabled (1UL) /*!< Enable subscription */
10143 
10144 /* Bits 7..0 : DPPI channel that task DEACTIVATE will subscribe to */
10145 #define QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10146 #define QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10147 
10148 /* Register: QSPI_EVENTS_READY */
10149 /* Description: QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. */
10150 
10151 /* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. */
10152 #define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
10153 #define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
10154 #define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
10155 #define QSPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
10156 
10157 /* Register: QSPI_PUBLISH_READY */
10158 /* Description: Publish configuration for event READY */
10159 
10160 /* Bit 31 :   */
10161 #define QSPI_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
10162 #define QSPI_PUBLISH_READY_EN_Msk (0x1UL << QSPI_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
10163 #define QSPI_PUBLISH_READY_EN_Disabled (0UL) /*!< Disable publishing */
10164 #define QSPI_PUBLISH_READY_EN_Enabled (1UL) /*!< Enable publishing */
10165 
10166 /* Bits 7..0 : DPPI channel that event READY will publish to. */
10167 #define QSPI_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10168 #define QSPI_PUBLISH_READY_CHIDX_Msk (0xFFUL << QSPI_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10169 
10170 /* Register: QSPI_INTEN */
10171 /* Description: Enable or disable interrupt */
10172 
10173 /* Bit 0 : Enable or disable interrupt for event READY */
10174 #define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
10175 #define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */
10176 #define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */
10177 #define QSPI_INTEN_READY_Enabled (1UL) /*!< Enable */
10178 
10179 /* Register: QSPI_INTENSET */
10180 /* Description: Enable interrupt */
10181 
10182 /* Bit 0 : Write '1' to enable interrupt for event READY */
10183 #define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
10184 #define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
10185 #define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
10186 #define QSPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10187 #define QSPI_INTENSET_READY_Set (1UL) /*!< Enable */
10188 
10189 /* Register: QSPI_INTENCLR */
10190 /* Description: Disable interrupt */
10191 
10192 /* Bit 0 : Write '1' to disable interrupt for event READY */
10193 #define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
10194 #define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
10195 #define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
10196 #define QSPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10197 #define QSPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
10198 
10199 /* Register: QSPI_ENABLE */
10200 /* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */
10201 
10202 /* Bit 0 : Enable or disable QSPI */
10203 #define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10204 #define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10205 #define QSPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable QSPI */
10206 #define QSPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QSPI */
10207 
10208 /* Register: QSPI_READ_SRC */
10209 /* Description: Flash memory source address */
10210 
10211 /* Bits 31..0 : Word-aligned flash memory source address. */
10212 #define QSPI_READ_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
10213 #define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
10214 
10215 /* Register: QSPI_READ_DST */
10216 /* Description: RAM destination address */
10217 
10218 /* Bits 31..0 : Word-aligned RAM destination address. */
10219 #define QSPI_READ_DST_DST_Pos (0UL) /*!< Position of DST field. */
10220 #define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos) /*!< Bit mask of DST field. */
10221 
10222 /* Register: QSPI_READ_CNT */
10223 /* Description: Read transfer length */
10224 
10225 /* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */
10226 #define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
10227 #define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
10228 
10229 /* Register: QSPI_WRITE_DST */
10230 /* Description: Flash destination address */
10231 
10232 /* Bits 31..0 : Word-aligned flash destination address. */
10233 #define QSPI_WRITE_DST_DST_Pos (0UL) /*!< Position of DST field. */
10234 #define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos) /*!< Bit mask of DST field. */
10235 
10236 /* Register: QSPI_WRITE_SRC */
10237 /* Description: RAM source address */
10238 
10239 /* Bits 31..0 : Word-aligned RAM source address. */
10240 #define QSPI_WRITE_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
10241 #define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
10242 
10243 /* Register: QSPI_WRITE_CNT */
10244 /* Description: Write transfer length */
10245 
10246 /* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */
10247 #define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
10248 #define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
10249 
10250 /* Register: QSPI_ERASE_PTR */
10251 /* Description: Start address of flash block to be erased */
10252 
10253 /* Bits 31..0 : Word-aligned start address of block to be erased. */
10254 #define QSPI_ERASE_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10255 #define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10256 
10257 /* Register: QSPI_ERASE_LEN */
10258 /* Description: Size of block to be erased. */
10259 
10260 /* Bits 1..0 : LEN */
10261 #define QSPI_ERASE_LEN_LEN_Pos (0UL) /*!< Position of LEN field. */
10262 #define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos) /*!< Bit mask of LEN field. */
10263 #define QSPI_ERASE_LEN_LEN_4KB (0UL) /*!< Erase 4 kB block (flash command 0x20) */
10264 #define QSPI_ERASE_LEN_LEN_64KB (1UL) /*!< Erase 64 kB block (flash command 0xD8) */
10265 #define QSPI_ERASE_LEN_LEN_All (2UL) /*!< Erase all (flash command 0xC7) */
10266 
10267 /* Register: QSPI_PSEL_SCK */
10268 /* Description: Pin select for serial clock SCK */
10269 
10270 /* Bit 31 : Connection */
10271 #define QSPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10272 #define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10273 #define QSPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
10274 #define QSPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
10275 
10276 /* Bit 5 : Port number */
10277 #define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
10278 #define QSPI_PSEL_SCK_PORT_Msk (0x1UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
10279 
10280 /* Bits 4..0 : Pin number */
10281 #define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
10282 #define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
10283 
10284 /* Register: QSPI_PSEL_CSN */
10285 /* Description: Pin select for chip select signal CSN. */
10286 
10287 /* Bit 31 : Connection */
10288 #define QSPI_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10289 #define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10290 #define QSPI_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
10291 #define QSPI_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
10292 
10293 /* Bit 5 : Port number */
10294 #define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
10295 #define QSPI_PSEL_CSN_PORT_Msk (0x1UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
10296 
10297 /* Bits 4..0 : Pin number */
10298 #define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
10299 #define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
10300 
10301 /* Register: QSPI_PSEL_IO0 */
10302 /* Description: Pin select for serial data MOSI/IO0. */
10303 
10304 /* Bit 31 : Connection */
10305 #define QSPI_PSEL_IO0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10306 #define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10307 #define QSPI_PSEL_IO0_CONNECT_Connected (0UL) /*!< Connect */
10308 #define QSPI_PSEL_IO0_CONNECT_Disconnected (1UL) /*!< Disconnect */
10309 
10310 /* Bit 5 : Port number */
10311 #define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */
10312 #define QSPI_PSEL_IO0_PORT_Msk (0x1UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */
10313 
10314 /* Bits 4..0 : Pin number */
10315 #define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */
10316 #define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos) /*!< Bit mask of PIN field. */
10317 
10318 /* Register: QSPI_PSEL_IO1 */
10319 /* Description: Pin select for serial data MISO/IO1. */
10320 
10321 /* Bit 31 : Connection */
10322 #define QSPI_PSEL_IO1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10323 #define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10324 #define QSPI_PSEL_IO1_CONNECT_Connected (0UL) /*!< Connect */
10325 #define QSPI_PSEL_IO1_CONNECT_Disconnected (1UL) /*!< Disconnect */
10326 
10327 /* Bit 5 : Port number */
10328 #define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */
10329 #define QSPI_PSEL_IO1_PORT_Msk (0x1UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */
10330 
10331 /* Bits 4..0 : Pin number */
10332 #define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */
10333 #define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */
10334 
10335 /* Register: QSPI_PSEL_IO2 */
10336 /* Description: Pin select for serial data WP/IO2. */
10337 
10338 /* Bit 31 : Connection */
10339 #define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10340 #define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10341 #define QSPI_PSEL_IO2_CONNECT_Connected (0UL) /*!< Connect */
10342 #define QSPI_PSEL_IO2_CONNECT_Disconnected (1UL) /*!< Disconnect */
10343 
10344 /* Bit 5 : Port number */
10345 #define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */
10346 #define QSPI_PSEL_IO2_PORT_Msk (0x1UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */
10347 
10348 /* Bits 4..0 : Pin number */
10349 #define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */
10350 #define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */
10351 
10352 /* Register: QSPI_PSEL_IO3 */
10353 /* Description: Pin select for serial data HOLD/IO3. */
10354 
10355 /* Bit 31 : Connection */
10356 #define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10357 #define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10358 #define QSPI_PSEL_IO3_CONNECT_Connected (0UL) /*!< Connect */
10359 #define QSPI_PSEL_IO3_CONNECT_Disconnected (1UL) /*!< Disconnect */
10360 
10361 /* Bit 5 : Port number */
10362 #define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */
10363 #define QSPI_PSEL_IO3_PORT_Msk (0x1UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */
10364 
10365 /* Bits 4..0 : Pin number */
10366 #define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */
10367 #define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos) /*!< Bit mask of PIN field. */
10368 
10369 /* Register: QSPI_XIPOFFSET */
10370 /* Description: Address offset into the external memory for Execute in Place operation. */
10371 
10372 /* Bits 31..0 : Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. */
10373 #define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL) /*!< Position of XIPOFFSET field. */
10374 #define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos) /*!< Bit mask of XIPOFFSET field. */
10375 
10376 /* Register: QSPI_IFCONFIG0 */
10377 /* Description: Interface configuration. */
10378 
10379 /* Bit 12 : Page size for commands PP, PP2O, PP4O and PP4IO. */
10380 #define QSPI_IFCONFIG0_PPSIZE_Pos (12UL) /*!< Position of PPSIZE field. */
10381 #define QSPI_IFCONFIG0_PPSIZE_Msk (0x1UL << QSPI_IFCONFIG0_PPSIZE_Pos) /*!< Bit mask of PPSIZE field. */
10382 #define QSPI_IFCONFIG0_PPSIZE_256Bytes (0UL) /*!< 256 bytes. */
10383 #define QSPI_IFCONFIG0_PPSIZE_512Bytes (1UL) /*!< 512 bytes. */
10384 
10385 /* Bit 7 : Enable deep power-down mode (DPM) feature. */
10386 #define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */
10387 #define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */
10388 #define QSPI_IFCONFIG0_DPMENABLE_Disable (0UL) /*!< Disable DPM feature. */
10389 #define QSPI_IFCONFIG0_DPMENABLE_Enable (1UL) /*!< Enable DPM feature. */
10390 
10391 /* Bit 6 : Addressing mode. */
10392 #define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL) /*!< Position of ADDRMODE field. */
10393 #define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos) /*!< Bit mask of ADDRMODE field. */
10394 #define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL) /*!< 24-bit addressing. */
10395 #define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL) /*!< 32-bit addressing. */
10396 
10397 /* Bits 5..3 : Configure number of data lines and opcode used for writing. */
10398 #define QSPI_IFCONFIG0_WRITEOC_Pos (3UL) /*!< Position of WRITEOC field. */
10399 #define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos) /*!< Bit mask of WRITEOC field. */
10400 #define QSPI_IFCONFIG0_WRITEOC_PP (0UL) /*!< Single data line SPI. PP (opcode 0x02). */
10401 #define QSPI_IFCONFIG0_WRITEOC_PP2O (1UL) /*!< Dual data line SPI. PP2O (opcode 0xA2). */
10402 #define QSPI_IFCONFIG0_WRITEOC_PP4O (2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */
10403 #define QSPI_IFCONFIG0_WRITEOC_PP4IO (3UL) /*!< Quad data line SPI. PP4IO (opcode 0x38). */
10404 
10405 /* Bits 2..0 : Configure number of data lines and opcode used for reading. */
10406 #define QSPI_IFCONFIG0_READOC_Pos (0UL) /*!< Position of READOC field. */
10407 #define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos) /*!< Bit mask of READOC field. */
10408 #define QSPI_IFCONFIG0_READOC_FASTREAD (0UL) /*!< Single data line SPI. FAST_READ (opcode 0x0B). */
10409 #define QSPI_IFCONFIG0_READOC_READ2O (1UL) /*!< Dual data line SPI. READ2O (opcode 0x3B). */
10410 #define QSPI_IFCONFIG0_READOC_READ2IO (2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */
10411 #define QSPI_IFCONFIG0_READOC_READ4O (3UL) /*!< Quad data line SPI. READ4O (opcode 0x6B). */
10412 #define QSPI_IFCONFIG0_READOC_READ4IO (4UL) /*!< Quad data line SPI. READ4IO (opcode 0xEB). */
10413 
10414 /* Register: QSPI_XIPEN */
10415 /* Description: Enable Execute in Place operation. */
10416 
10417 /* Bit 0 : Enable XIP AHB Slave interface and access to XIP memory range */
10418 #define QSPI_XIPEN_XIPEN_Pos (0UL) /*!< Position of XIPEN field. */
10419 #define QSPI_XIPEN_XIPEN_Msk (0x1UL << QSPI_XIPEN_XIPEN_Pos) /*!< Bit mask of XIPEN field. */
10420 #define QSPI_XIPEN_XIPEN_Disable (0UL) /*!< Disable XIP interface */
10421 #define QSPI_XIPEN_XIPEN_Enable (1UL) /*!< Enable XIP interface */
10422 
10423 /* Register: QSPI_XIP_ENC_KEY0 */
10424 /* Description: Bits 31:0 of XIP AES KEY */
10425 
10426 /* Bits 31..0 : Bits 31:0 of XIP AES KEY */
10427 #define QSPI_XIP_ENC_KEY0_KEY0_Pos (0UL) /*!< Position of KEY0 field. */
10428 #define QSPI_XIP_ENC_KEY0_KEY0_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY0_KEY0_Pos) /*!< Bit mask of KEY0 field. */
10429 
10430 /* Register: QSPI_XIP_ENC_KEY1 */
10431 /* Description: Bits 63:32 of XIP AES KEY */
10432 
10433 /* Bits 31..0 : Bits 63:32 of XIP AES KEY */
10434 #define QSPI_XIP_ENC_KEY1_KEY1_Pos (0UL) /*!< Position of KEY1 field. */
10435 #define QSPI_XIP_ENC_KEY1_KEY1_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY1_KEY1_Pos) /*!< Bit mask of KEY1 field. */
10436 
10437 /* Register: QSPI_XIP_ENC_KEY2 */
10438 /* Description: Bits 95:64 of XIP AES KEY */
10439 
10440 /* Bits 31..0 : Bits 95:64 of XIP AES KEY */
10441 #define QSPI_XIP_ENC_KEY2_KEY2_Pos (0UL) /*!< Position of KEY2 field. */
10442 #define QSPI_XIP_ENC_KEY2_KEY2_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY2_KEY2_Pos) /*!< Bit mask of KEY2 field. */
10443 
10444 /* Register: QSPI_XIP_ENC_KEY3 */
10445 /* Description: Bits 127:96 of XIP AES KEY */
10446 
10447 /* Bits 31..0 : Bits 127:96 of XIP AES KEY */
10448 #define QSPI_XIP_ENC_KEY3_KEY3_Pos (0UL) /*!< Position of KEY3 field. */
10449 #define QSPI_XIP_ENC_KEY3_KEY3_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_KEY3_KEY3_Pos) /*!< Bit mask of KEY3 field. */
10450 
10451 /* Register: QSPI_XIP_ENC_NONCE0 */
10452 /* Description: Bits 31:0 of XIP NONCE */
10453 
10454 /* Bits 31..0 : Bits 31:0 of XIP NONCE */
10455 #define QSPI_XIP_ENC_NONCE0_NONCE0_Pos (0UL) /*!< Position of NONCE0 field. */
10456 #define QSPI_XIP_ENC_NONCE0_NONCE0_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_NONCE0_NONCE0_Pos) /*!< Bit mask of NONCE0 field. */
10457 
10458 /* Register: QSPI_XIP_ENC_NONCE1 */
10459 /* Description: Bits 63:32 of XIP NONCE */
10460 
10461 /* Bits 31..0 : Bits 63:32 of XIP NONCE */
10462 #define QSPI_XIP_ENC_NONCE1_NONCE1_Pos (0UL) /*!< Position of NONCE1 field. */
10463 #define QSPI_XIP_ENC_NONCE1_NONCE1_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_NONCE1_NONCE1_Pos) /*!< Bit mask of NONCE1 field. */
10464 
10465 /* Register: QSPI_XIP_ENC_NONCE2 */
10466 /* Description: Bits 95:64 of XIP NONCE */
10467 
10468 /* Bits 31..0 : Bits 95:64 of XIP NONCE */
10469 #define QSPI_XIP_ENC_NONCE2_NONCE2_Pos (0UL) /*!< Position of NONCE2 field. */
10470 #define QSPI_XIP_ENC_NONCE2_NONCE2_Msk (0xFFFFFFFFUL << QSPI_XIP_ENC_NONCE2_NONCE2_Pos) /*!< Bit mask of NONCE2 field. */
10471 
10472 /* Register: QSPI_XIP_ENC_ENABLE */
10473 /* Description: Enable stream cipher for XIP */
10474 
10475 /* Bit 0 : Enable or disable stream cipher for XIP */
10476 #define QSPI_XIP_ENC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10477 #define QSPI_XIP_ENC_ENABLE_ENABLE_Msk (0x1UL << QSPI_XIP_ENC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10478 #define QSPI_XIP_ENC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable stream cipher for QSPI XIP */
10479 #define QSPI_XIP_ENC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable stream cipher for QSPI XIP */
10480 
10481 /* Register: QSPI_DMA_ENC_KEY0 */
10482 /* Description: Bits 31:0 of DMA AES KEY */
10483 
10484 /* Bits 31..0 : Bits 31:0 of DMA AES KEY */
10485 #define QSPI_DMA_ENC_KEY0_KEY0_Pos (0UL) /*!< Position of KEY0 field. */
10486 #define QSPI_DMA_ENC_KEY0_KEY0_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY0_KEY0_Pos) /*!< Bit mask of KEY0 field. */
10487 
10488 /* Register: QSPI_DMA_ENC_KEY1 */
10489 /* Description: Bits 63:32 of DMA AES KEY */
10490 
10491 /* Bits 31..0 : Bits 63:32 of DMA AES KEY */
10492 #define QSPI_DMA_ENC_KEY1_KEY1_Pos (0UL) /*!< Position of KEY1 field. */
10493 #define QSPI_DMA_ENC_KEY1_KEY1_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY1_KEY1_Pos) /*!< Bit mask of KEY1 field. */
10494 
10495 /* Register: QSPI_DMA_ENC_KEY2 */
10496 /* Description: Bits 95:64 of DMA AES KEY */
10497 
10498 /* Bits 31..0 : Bits 95:64 of DMA AES KEY */
10499 #define QSPI_DMA_ENC_KEY2_KEY2_Pos (0UL) /*!< Position of KEY2 field. */
10500 #define QSPI_DMA_ENC_KEY2_KEY2_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY2_KEY2_Pos) /*!< Bit mask of KEY2 field. */
10501 
10502 /* Register: QSPI_DMA_ENC_KEY3 */
10503 /* Description: Bits 127:96 of DMA AES KEY */
10504 
10505 /* Bits 31..0 : Bits 127:96 of DMA AES KEY */
10506 #define QSPI_DMA_ENC_KEY3_KEY3_Pos (0UL) /*!< Position of KEY3 field. */
10507 #define QSPI_DMA_ENC_KEY3_KEY3_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_KEY3_KEY3_Pos) /*!< Bit mask of KEY3 field. */
10508 
10509 /* Register: QSPI_DMA_ENC_NONCE0 */
10510 /* Description: Bits 31:0 of DMA NONCE */
10511 
10512 /* Bits 31..0 : Bits 31:0 of DMA NONCE */
10513 #define QSPI_DMA_ENC_NONCE0_NONCE0_Pos (0UL) /*!< Position of NONCE0 field. */
10514 #define QSPI_DMA_ENC_NONCE0_NONCE0_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE0_NONCE0_Pos) /*!< Bit mask of NONCE0 field. */
10515 
10516 /* Register: QSPI_DMA_ENC_NONCE1 */
10517 /* Description: Bits 63:32 of DMA NONCE */
10518 
10519 /* Bits 31..0 : Bits 63:32 of DMA NONCE */
10520 #define QSPI_DMA_ENC_NONCE1_NONCE1_Pos (0UL) /*!< Position of NONCE1 field. */
10521 #define QSPI_DMA_ENC_NONCE1_NONCE1_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE1_NONCE1_Pos) /*!< Bit mask of NONCE1 field. */
10522 
10523 /* Register: QSPI_DMA_ENC_NONCE2 */
10524 /* Description: Bits 95:64 of DMA NONCE */
10525 
10526 /* Bits 31..0 : Bits 95:64 of DMA NONCE */
10527 #define QSPI_DMA_ENC_NONCE2_NONCE2_Pos (0UL) /*!< Position of NONCE2 field. */
10528 #define QSPI_DMA_ENC_NONCE2_NONCE2_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE2_NONCE2_Pos) /*!< Bit mask of NONCE2 field. */
10529 
10530 /* Register: QSPI_DMA_ENC_ENABLE */
10531 /* Description: Enable stream cipher for EasyDMA */
10532 
10533 /* Bit 0 : Enable or disable stream cipher for EasyDMA */
10534 #define QSPI_DMA_ENC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10535 #define QSPI_DMA_ENC_ENABLE_ENABLE_Msk (0x1UL << QSPI_DMA_ENC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10536 #define QSPI_DMA_ENC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable stream cipher for QSPI EasyDMA */
10537 #define QSPI_DMA_ENC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable stream cipher for QSPI EasyDMA */
10538 
10539 /* Register: QSPI_IFCONFIG1 */
10540 /* Description: Interface configuration. */
10541 
10542 /* Bits 31..28 : SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1)). */
10543 #define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */
10544 #define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */
10545 
10546 /* Bit 25 : Select SPI mode. */
10547 #define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */
10548 #define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */
10549 #define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */
10550 #define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1). */
10551 
10552 /* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */
10553 #define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */
10554 #define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos) /*!< Bit mask of DPMEN field. */
10555 #define QSPI_IFCONFIG1_DPMEN_Exit (0UL) /*!< Exit DPM. */
10556 #define QSPI_IFCONFIG1_DPMEN_Enter (1UL) /*!< Enter DPM. */
10557 
10558 /* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 32 MHz periods (31.25 ns). */
10559 #define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */
10560 #define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */
10561 
10562 /* Register: QSPI_STATUS */
10563 /* Description: Status register. */
10564 
10565 /* Bits 31..24 : Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */
10566 #define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */
10567 #define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */
10568 
10569 /* Bit 3 : Ready status. */
10570 #define QSPI_STATUS_READY_Pos (3UL) /*!< Position of READY field. */
10571 #define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos) /*!< Bit mask of READY field. */
10572 #define QSPI_STATUS_READY_BUSY (0UL) /*!< QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. */
10573 #define QSPI_STATUS_READY_READY (1UL) /*!< QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. */
10574 
10575 /* Bit 2 : Deep power-down mode (DPM) status of external flash. */
10576 #define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */
10577 #define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos) /*!< Bit mask of DPM field. */
10578 #define QSPI_STATUS_DPM_Disabled (0UL) /*!< External flash is not in DPM. */
10579 #define QSPI_STATUS_DPM_Enabled (1UL) /*!< External flash is in DPM. */
10580 
10581 /* Register: QSPI_DPMDUR */
10582 /* Description: Set the duration required to enter/exit deep power-down mode (DPM). */
10583 
10584 /* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 31.25 ns. */
10585 #define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */
10586 #define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */
10587 
10588 /* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 31.25 ns */
10589 #define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */
10590 #define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */
10591 
10592 /* Register: QSPI_ADDRCONF */
10593 /* Description: Extended address configuration. */
10594 
10595 /* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */
10596 #define QSPI_ADDRCONF_WREN_Pos (27UL) /*!< Position of WREN field. */
10597 #define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
10598 #define QSPI_ADDRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */
10599 #define QSPI_ADDRCONF_WREN_Enable (1UL) /*!< Send WREN. */
10600 
10601 /* Bit 26 : Wait for write complete before sending command. */
10602 #define QSPI_ADDRCONF_WIPWAIT_Pos (26UL) /*!< Position of WIPWAIT field. */
10603 #define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
10604 #define QSPI_ADDRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */
10605 #define QSPI_ADDRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */
10606 
10607 /* Bits 25..24 : Extended addressing mode. */
10608 #define QSPI_ADDRCONF_MODE_Pos (24UL) /*!< Position of MODE field. */
10609 #define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */
10610 #define QSPI_ADDRCONF_MODE_NoInstr (0UL) /*!< Do not send any instruction. */
10611 #define QSPI_ADDRCONF_MODE_Opcode (1UL) /*!< Send opcode. */
10612 #define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, BYTE0. */
10613 #define QSPI_ADDRCONF_MODE_All (3UL) /*!< Send opcode, BYTE0, BYTE1. */
10614 
10615 /* Bits 23..16 : Byte 1 following byte 0. */
10616 #define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */
10617 #define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
10618 
10619 /* Bits 15..8 : Byte 0 following opcode. */
10620 #define QSPI_ADDRCONF_BYTE0_Pos (8UL) /*!< Position of BYTE0 field. */
10621 #define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
10622 
10623 /* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */
10624 #define QSPI_ADDRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
10625 #define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
10626 
10627 /* Register: QSPI_CINSTRCONF */
10628 /* Description: Custom instruction configuration register. */
10629 
10630 /* Bit 17 : Stop (finalize) long frame transaction */
10631 #define QSPI_CINSTRCONF_LFSTOP_Pos (17UL) /*!< Position of LFSTOP field. */
10632 #define QSPI_CINSTRCONF_LFSTOP_Msk (0x1UL << QSPI_CINSTRCONF_LFSTOP_Pos) /*!< Bit mask of LFSTOP field. */
10633 #define QSPI_CINSTRCONF_LFSTOP_Stop (1UL) /*!< Stop */
10634 
10635 /* Bit 16 : Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. */
10636 #define QSPI_CINSTRCONF_LFEN_Pos (16UL) /*!< Position of LFEN field. */
10637 #define QSPI_CINSTRCONF_LFEN_Msk (0x1UL << QSPI_CINSTRCONF_LFEN_Pos) /*!< Bit mask of LFEN field. */
10638 #define QSPI_CINSTRCONF_LFEN_Disable (0UL) /*!< Long frame mode disabled */
10639 #define QSPI_CINSTRCONF_LFEN_Enable (1UL) /*!< Long frame mode enabled */
10640 
10641 /* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */
10642 #define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */
10643 #define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
10644 #define QSPI_CINSTRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */
10645 #define QSPI_CINSTRCONF_WREN_Enable (1UL) /*!< Send WREN. */
10646 
10647 /* Bit 14 : Wait for write complete before sending command. */
10648 #define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL) /*!< Position of WIPWAIT field. */
10649 #define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
10650 #define QSPI_CINSTRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */
10651 #define QSPI_CINSTRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */
10652 
10653 /* Bit 13 : Level of the IO3 pin (if connected) during transmission of custom instruction. */
10654 #define QSPI_CINSTRCONF_LIO3_Pos (13UL) /*!< Position of LIO3 field. */
10655 #define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos) /*!< Bit mask of LIO3 field. */
10656 
10657 /* Bit 12 : Level of the IO2 pin (if connected) during transmission of custom instruction. */
10658 #define QSPI_CINSTRCONF_LIO2_Pos (12UL) /*!< Position of LIO2 field. */
10659 #define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos) /*!< Bit mask of LIO2 field. */
10660 
10661 /* Bits 11..8 : Length of custom instruction in number of bytes. */
10662 #define QSPI_CINSTRCONF_LENGTH_Pos (8UL) /*!< Position of LENGTH field. */
10663 #define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
10664 #define QSPI_CINSTRCONF_LENGTH_1B (1UL) /*!< Send opcode only. */
10665 #define QSPI_CINSTRCONF_LENGTH_2B (2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */
10666 #define QSPI_CINSTRCONF_LENGTH_3B (3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. */
10667 #define QSPI_CINSTRCONF_LENGTH_4B (4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. */
10668 #define QSPI_CINSTRCONF_LENGTH_5B (5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. */
10669 #define QSPI_CINSTRCONF_LENGTH_6B (6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. */
10670 #define QSPI_CINSTRCONF_LENGTH_7B (7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. */
10671 #define QSPI_CINSTRCONF_LENGTH_8B (8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. */
10672 #define QSPI_CINSTRCONF_LENGTH_9B (9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. */
10673 
10674 /* Bits 7..0 : Opcode of Custom instruction. */
10675 #define QSPI_CINSTRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
10676 #define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
10677 
10678 /* Register: QSPI_CINSTRDAT0 */
10679 /* Description: Custom instruction data register 0. */
10680 
10681 /* Bits 31..24 : Data byte 3 */
10682 #define QSPI_CINSTRDAT0_BYTE3_Pos (24UL) /*!< Position of BYTE3 field. */
10683 #define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos) /*!< Bit mask of BYTE3 field. */
10684 
10685 /* Bits 23..16 : Data byte 2 */
10686 #define QSPI_CINSTRDAT0_BYTE2_Pos (16UL) /*!< Position of BYTE2 field. */
10687 #define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos) /*!< Bit mask of BYTE2 field. */
10688 
10689 /* Bits 15..8 : Data byte 1 */
10690 #define QSPI_CINSTRDAT0_BYTE1_Pos (8UL) /*!< Position of BYTE1 field. */
10691 #define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
10692 
10693 /* Bits 7..0 : Data byte 0 */
10694 #define QSPI_CINSTRDAT0_BYTE0_Pos (0UL) /*!< Position of BYTE0 field. */
10695 #define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
10696 
10697 /* Register: QSPI_CINSTRDAT1 */
10698 /* Description: Custom instruction data register 1. */
10699 
10700 /* Bits 31..24 : Data byte 7 */
10701 #define QSPI_CINSTRDAT1_BYTE7_Pos (24UL) /*!< Position of BYTE7 field. */
10702 #define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos) /*!< Bit mask of BYTE7 field. */
10703 
10704 /* Bits 23..16 : Data byte 6 */
10705 #define QSPI_CINSTRDAT1_BYTE6_Pos (16UL) /*!< Position of BYTE6 field. */
10706 #define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos) /*!< Bit mask of BYTE6 field. */
10707 
10708 /* Bits 15..8 : Data byte 5 */
10709 #define QSPI_CINSTRDAT1_BYTE5_Pos (8UL) /*!< Position of BYTE5 field. */
10710 #define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos) /*!< Bit mask of BYTE5 field. */
10711 
10712 /* Bits 7..0 : Data byte 4 */
10713 #define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */
10714 #define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */
10715 
10716 /* Register: QSPI_IFTIMING */
10717 /* Description: SPI interface timing. */
10718 
10719 /* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK. */
10720 #define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */
10721 #define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
10722 
10723 
10724 /* Peripheral: REGULATORS */
10725 /* Description: Voltage regulators 0 */
10726 
10727 /* Register: REGULATORS_MAINREGSTATUS */
10728 /* Description: Main supply status */
10729 
10730 /* Bit 0 : VREGH status */
10731 #define REGULATORS_MAINREGSTATUS_VREGH_Pos (0UL) /*!< Position of VREGH field. */
10732 #define REGULATORS_MAINREGSTATUS_VREGH_Msk (0x1UL << REGULATORS_MAINREGSTATUS_VREGH_Pos) /*!< Bit mask of VREGH field. */
10733 #define REGULATORS_MAINREGSTATUS_VREGH_Inactive (0UL) /*!< Normal voltage mode. Voltage supplied on VDD and VDDH. */
10734 #define REGULATORS_MAINREGSTATUS_VREGH_Active (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */
10735 
10736 /* Register: REGULATORS_SYSTEMOFF */
10737 /* Description: System OFF register */
10738 
10739 /* Bit 0 : Enable System OFF mode */
10740 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
10741 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
10742 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
10743 
10744 /* Register: REGULATORS_POFCON */
10745 /* Description: Power-fail comparator configuration */
10746 
10747 /* Bits 11..8 : Power-fail comparator threshold setting for voltage supply on VDDH */
10748 #define REGULATORS_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */
10749 #define REGULATORS_POFCON_THRESHOLDVDDH_Msk (0xFUL << REGULATORS_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */
10750 #define REGULATORS_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */
10751 #define REGULATORS_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */
10752 #define REGULATORS_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */
10753 #define REGULATORS_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */
10754 #define REGULATORS_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */
10755 #define REGULATORS_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */
10756 #define REGULATORS_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */
10757 #define REGULATORS_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */
10758 #define REGULATORS_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */
10759 #define REGULATORS_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */
10760 #define REGULATORS_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */
10761 #define REGULATORS_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */
10762 #define REGULATORS_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */
10763 #define REGULATORS_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */
10764 #define REGULATORS_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */
10765 #define REGULATORS_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */
10766 
10767 /* Bits 4..1 : Power-fail comparator threshold setting */
10768 #define REGULATORS_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
10769 #define REGULATORS_POFCON_THRESHOLD_Msk (0xFUL << REGULATORS_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
10770 #define REGULATORS_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
10771 #define REGULATORS_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
10772 #define REGULATORS_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
10773 #define REGULATORS_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
10774 #define REGULATORS_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
10775 #define REGULATORS_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
10776 #define REGULATORS_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
10777 #define REGULATORS_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
10778 #define REGULATORS_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
10779 #define REGULATORS_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
10780 
10781 /* Bit 0 : Enable or disable power-fail comparator */
10782 #define REGULATORS_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
10783 #define REGULATORS_POFCON_POF_Msk (0x1UL << REGULATORS_POFCON_POF_Pos) /*!< Bit mask of POF field. */
10784 #define REGULATORS_POFCON_POF_Disabled (0UL) /*!< Disable */
10785 #define REGULATORS_POFCON_POF_Enabled (1UL) /*!< Enable */
10786 
10787 /* Register: REGULATORS_VREGMAIN_DCDCEN */
10788 /* Description: DC/DC enable register for VREGMAIN */
10789 
10790 /* Bit 0 : Enable or disable DC/DC converter */
10791 #define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
10792 #define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
10793 #define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
10794 #define REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
10795 
10796 /* Register: REGULATORS_VREGRADIO_DCDCEN */
10797 /* Description: DC/DC enable register for VREGRADIO */
10798 
10799 /* Bit 0 : Enable or disable DC/DC converter */
10800 #define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
10801 #define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
10802 #define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
10803 #define REGULATORS_VREGRADIO_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
10804 
10805 /* Register: REGULATORS_VREGH_DCDCEN */
10806 /* Description: DC/DC enable register for VREGH */
10807 
10808 /* Bit 0 : Enable or disable DC/DC converter */
10809 #define REGULATORS_VREGH_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
10810 #define REGULATORS_VREGH_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_VREGH_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
10811 #define REGULATORS_VREGH_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
10812 #define REGULATORS_VREGH_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
10813 
10814 
10815 /* Peripheral: RESET */
10816 /* Description: Reset control 0 */
10817 
10818 /* Register: RESET_RESETREAS */
10819 /* Description: Reset reason */
10820 
10821 /* Bit 26 : Reset after wakeup from System OFF mode due to VBUS rising into valid range */
10822 #define RESET_RESETREAS_VBUS_Pos (26UL) /*!< Position of VBUS field. */
10823 #define RESET_RESETREAS_VBUS_Msk (0x1UL << RESET_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
10824 #define RESET_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */
10825 #define RESET_RESETREAS_VBUS_Detected (1UL) /*!< Detected */
10826 
10827 /* Bit 25 : Reset from application watchdog timer 1 detected */
10828 #define RESET_RESETREAS_DOG1_Pos (25UL) /*!< Position of DOG1 field. */
10829 #define RESET_RESETREAS_DOG1_Msk (0x1UL << RESET_RESETREAS_DOG1_Pos) /*!< Bit mask of DOG1 field. */
10830 #define RESET_RESETREAS_DOG1_NotDetected (0UL) /*!< Not detected */
10831 #define RESET_RESETREAS_DOG1_Detected (1UL) /*!< Detected */
10832 
10833 /* Bit 24 : Reset after wakeup from System OFF mode due to NFC field being detected */
10834 #define RESET_RESETREAS_NFC_Pos (24UL) /*!< Position of NFC field. */
10835 #define RESET_RESETREAS_NFC_Msk (0x1UL << RESET_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
10836 #define RESET_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
10837 #define RESET_RESETREAS_NFC_Detected (1UL) /*!< Detected */
10838 
10839 /* Bit 7 : Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode */
10840 #define RESET_RESETREAS_DIF_Pos (7UL) /*!< Position of DIF field. */
10841 #define RESET_RESETREAS_DIF_Msk (0x1UL << RESET_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
10842 #define RESET_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
10843 #define RESET_RESETREAS_DIF_Detected (1UL) /*!< Detected */
10844 
10845 /* Bit 6 : Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP */
10846 #define RESET_RESETREAS_LPCOMP_Pos (6UL) /*!< Position of LPCOMP field. */
10847 #define RESET_RESETREAS_LPCOMP_Msk (0x1UL << RESET_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
10848 #define RESET_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
10849 #define RESET_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
10850 
10851 /* Bit 5 : Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO */
10852 #define RESET_RESETREAS_OFF_Pos (5UL) /*!< Position of OFF field. */
10853 #define RESET_RESETREAS_OFF_Msk (0x1UL << RESET_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
10854 #define RESET_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
10855 #define RESET_RESETREAS_OFF_Detected (1UL) /*!< Detected */
10856 
10857 /* Bit 4 : Reset from application CPU lockup detected */
10858 #define RESET_RESETREAS_LOCKUP_Pos (4UL) /*!< Position of LOCKUP field. */
10859 #define RESET_RESETREAS_LOCKUP_Msk (0x1UL << RESET_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
10860 #define RESET_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
10861 #define RESET_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
10862 
10863 /* Bit 3 : Reset from application soft reset detected */
10864 #define RESET_RESETREAS_SREQ_Pos (3UL) /*!< Position of SREQ field. */
10865 #define RESET_RESETREAS_SREQ_Msk (0x1UL << RESET_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
10866 #define RESET_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
10867 #define RESET_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
10868 
10869 /* Bit 2 : Reset from application CTRL-AP detected */
10870 #define RESET_RESETREAS_CTRLAP_Pos (2UL) /*!< Position of CTRLAP field. */
10871 #define RESET_RESETREAS_CTRLAP_Msk (0x1UL << RESET_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */
10872 #define RESET_RESETREAS_CTRLAP_NotDetected (0UL) /*!< Not detected */
10873 #define RESET_RESETREAS_CTRLAP_Detected (1UL) /*!< Detected */
10874 
10875 /* Bit 1 : Reset from application watchdog timer 0 detected */
10876 #define RESET_RESETREAS_DOG0_Pos (1UL) /*!< Position of DOG0 field. */
10877 #define RESET_RESETREAS_DOG0_Msk (0x1UL << RESET_RESETREAS_DOG0_Pos) /*!< Bit mask of DOG0 field. */
10878 #define RESET_RESETREAS_DOG0_NotDetected (0UL) /*!< Not detected */
10879 #define RESET_RESETREAS_DOG0_Detected (1UL) /*!< Detected */
10880 
10881 /* Bit 0 : Reset from pin reset detected */
10882 #define RESET_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
10883 #define RESET_RESETREAS_RESETPIN_Msk (0x1UL << RESET_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
10884 #define RESET_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
10885 #define RESET_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
10886 
10887 /* Register: RESET_NETWORK_FORCEOFF */
10888 /* Description: Force network core off */
10889 
10890 /* Bit 0 : Force network core off */
10891 #define RESET_NETWORK_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
10892 #define RESET_NETWORK_FORCEOFF_FORCEOFF_Msk (0x1UL << RESET_NETWORK_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
10893 #define RESET_NETWORK_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release Force-OFF */
10894 #define RESET_NETWORK_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold Force-OFF */
10895 
10896 
10897 /* Peripheral: RTC */
10898 /* Description: Real-time counter 0 */
10899 
10900 /* Register: RTC_TASKS_START */
10901 /* Description: Start RTC counter */
10902 
10903 /* Bit 0 : Start RTC counter */
10904 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10905 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10906 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
10907 
10908 /* Register: RTC_TASKS_STOP */
10909 /* Description: Stop RTC counter */
10910 
10911 /* Bit 0 : Stop RTC counter */
10912 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10913 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10914 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
10915 
10916 /* Register: RTC_TASKS_CLEAR */
10917 /* Description: Clear RTC counter */
10918 
10919 /* Bit 0 : Clear RTC counter */
10920 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
10921 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
10922 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
10923 
10924 /* Register: RTC_TASKS_TRIGOVRFLW */
10925 /* Description: Set counter to 0xFFFFF0 */
10926 
10927 /* Bit 0 : Set counter to 0xFFFFF0 */
10928 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
10929 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
10930 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
10931 
10932 /* Register: RTC_TASKS_CAPTURE */
10933 /* Description: Description collection: Capture RTC counter to CC[n] register */
10934 
10935 /* Bit 0 : Capture RTC counter to CC[n] register */
10936 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
10937 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
10938 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
10939 
10940 /* Register: RTC_SUBSCRIBE_START */
10941 /* Description: Subscribe configuration for task START */
10942 
10943 /* Bit 31 :   */
10944 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
10945 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
10946 #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
10947 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
10948 
10949 /* Bits 7..0 : DPPI channel that task START will subscribe to */
10950 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10951 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10952 
10953 /* Register: RTC_SUBSCRIBE_STOP */
10954 /* Description: Subscribe configuration for task STOP */
10955 
10956 /* Bit 31 :   */
10957 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
10958 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
10959 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
10960 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
10961 
10962 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
10963 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10964 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10965 
10966 /* Register: RTC_SUBSCRIBE_CLEAR */
10967 /* Description: Subscribe configuration for task CLEAR */
10968 
10969 /* Bit 31 :   */
10970 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
10971 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
10972 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
10973 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
10974 
10975 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
10976 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10977 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10978 
10979 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */
10980 /* Description: Subscribe configuration for task TRIGOVRFLW */
10981 
10982 /* Bit 31 :   */
10983 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
10984 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */
10985 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */
10986 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */
10987 
10988 /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */
10989 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10990 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10991 
10992 /* Register: RTC_SUBSCRIBE_CAPTURE */
10993 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
10994 
10995 /* Bit 31 :   */
10996 #define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
10997 #define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
10998 #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
10999 #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
11000 
11001 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
11002 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11003 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11004 
11005 /* Register: RTC_EVENTS_TICK */
11006 /* Description: Event on counter increment */
11007 
11008 /* Bit 0 : Event on counter increment */
11009 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
11010 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
11011 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
11012 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
11013 
11014 /* Register: RTC_EVENTS_OVRFLW */
11015 /* Description: Event on counter overflow */
11016 
11017 /* Bit 0 : Event on counter overflow */
11018 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
11019 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
11020 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
11021 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
11022 
11023 /* Register: RTC_EVENTS_COMPARE */
11024 /* Description: Description collection: Compare event on CC[n] match */
11025 
11026 /* Bit 0 : Compare event on CC[n] match */
11027 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
11028 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
11029 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
11030 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
11031 
11032 /* Register: RTC_PUBLISH_TICK */
11033 /* Description: Publish configuration for event TICK */
11034 
11035 /* Bit 31 :   */
11036 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */
11037 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */
11038 #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */
11039 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */
11040 
11041 /* Bits 7..0 : DPPI channel that event TICK will publish to. */
11042 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11043 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11044 
11045 /* Register: RTC_PUBLISH_OVRFLW */
11046 /* Description: Publish configuration for event OVRFLW */
11047 
11048 /* Bit 31 :   */
11049 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
11050 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */
11051 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */
11052 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */
11053 
11054 /* Bits 7..0 : DPPI channel that event OVRFLW will publish to. */
11055 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11056 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11057 
11058 /* Register: RTC_PUBLISH_COMPARE */
11059 /* Description: Description collection: Publish configuration for event COMPARE[n] */
11060 
11061 /* Bit 31 :   */
11062 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
11063 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
11064 #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
11065 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
11066 
11067 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */
11068 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11069 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11070 
11071 /* Register: RTC_SHORTS */
11072 /* Description: Shortcuts between local events and tasks */
11073 
11074 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
11075 #define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
11076 #define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
11077 #define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
11078 #define RTC_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
11079 
11080 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
11081 #define RTC_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
11082 #define RTC_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
11083 #define RTC_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
11084 #define RTC_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
11085 
11086 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
11087 #define RTC_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
11088 #define RTC_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
11089 #define RTC_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
11090 #define RTC_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
11091 
11092 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
11093 #define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
11094 #define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
11095 #define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
11096 #define RTC_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
11097 
11098 /* Register: RTC_INTENSET */
11099 /* Description: Enable interrupt */
11100 
11101 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
11102 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11103 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11104 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11105 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11106 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
11107 
11108 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
11109 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11110 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11111 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11112 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11113 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
11114 
11115 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
11116 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11117 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11118 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11119 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11120 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
11121 
11122 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
11123 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11124 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11125 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11126 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11127 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
11128 
11129 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
11130 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11131 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11132 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11133 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11134 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
11135 
11136 /* Bit 0 : Write '1' to enable interrupt for event TICK */
11137 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
11138 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
11139 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11140 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11141 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
11142 
11143 /* Register: RTC_INTENCLR */
11144 /* Description: Disable interrupt */
11145 
11146 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
11147 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11148 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11149 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11150 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11151 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
11152 
11153 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
11154 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11155 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11156 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11157 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11158 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
11159 
11160 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
11161 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11162 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11163 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11164 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11165 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
11166 
11167 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
11168 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11169 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11170 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11171 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11172 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
11173 
11174 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
11175 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11176 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11177 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11178 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11179 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
11180 
11181 /* Bit 0 : Write '1' to disable interrupt for event TICK */
11182 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
11183 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
11184 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11185 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11186 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
11187 
11188 /* Register: RTC_EVTEN */
11189 /* Description: Enable or disable event routing */
11190 
11191 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
11192 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11193 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11194 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
11195 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
11196 
11197 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
11198 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11199 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11200 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
11201 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
11202 
11203 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
11204 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11205 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11206 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
11207 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
11208 
11209 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
11210 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11211 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11212 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
11213 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
11214 
11215 /* Bit 1 : Enable or disable event routing for event OVRFLW */
11216 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11217 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11218 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
11219 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
11220 
11221 /* Bit 0 : Enable or disable event routing for event TICK */
11222 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
11223 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
11224 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
11225 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
11226 
11227 /* Register: RTC_EVTENSET */
11228 /* Description: Enable event routing */
11229 
11230 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
11231 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11232 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11233 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11234 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11235 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
11236 
11237 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
11238 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11239 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11240 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11241 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11242 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
11243 
11244 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
11245 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11246 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11247 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11248 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11249 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
11250 
11251 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
11252 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11253 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11254 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11255 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11256 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
11257 
11258 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
11259 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11260 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11261 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11262 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11263 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
11264 
11265 /* Bit 0 : Write '1' to enable event routing for event TICK */
11266 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
11267 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
11268 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11269 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11270 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
11271 
11272 /* Register: RTC_EVTENCLR */
11273 /* Description: Disable event routing */
11274 
11275 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
11276 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
11277 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
11278 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11279 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11280 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
11281 
11282 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
11283 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
11284 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
11285 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11286 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11287 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
11288 
11289 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
11290 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
11291 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
11292 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11293 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11294 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
11295 
11296 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
11297 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
11298 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
11299 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11300 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11301 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
11302 
11303 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
11304 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
11305 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
11306 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11307 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11308 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
11309 
11310 /* Bit 0 : Write '1' to disable event routing for event TICK */
11311 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
11312 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
11313 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11314 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11315 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
11316 
11317 /* Register: RTC_COUNTER */
11318 /* Description: Current counter value */
11319 
11320 /* Bits 23..0 : Counter value */
11321 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
11322 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
11323 
11324 /* Register: RTC_PRESCALER */
11325 /* Description: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */
11326 
11327 /* Bits 11..0 : Prescaler value */
11328 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
11329 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
11330 
11331 /* Register: RTC_CC */
11332 /* Description: Description collection: Compare register n */
11333 
11334 /* Bits 23..0 : Compare value */
11335 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
11336 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
11337 
11338 
11339 /* Peripheral: SAADC */
11340 /* Description: Analog to Digital Converter 0 */
11341 
11342 /* Register: SAADC_TASKS_START */
11343 /* Description: Start the ADC and prepare the result buffer in RAM */
11344 
11345 /* Bit 0 : Start the ADC and prepare the result buffer in RAM */
11346 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11347 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11348 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
11349 
11350 /* Register: SAADC_TASKS_SAMPLE */
11351 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */
11352 
11353 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
11354 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
11355 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
11356 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
11357 
11358 /* Register: SAADC_TASKS_STOP */
11359 /* Description: Stop the ADC and terminate any ongoing conversion */
11360 
11361 /* Bit 0 : Stop the ADC and terminate any ongoing conversion */
11362 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
11363 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
11364 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
11365 
11366 /* Register: SAADC_TASKS_CALIBRATEOFFSET */
11367 /* Description: Starts offset auto-calibration */
11368 
11369 /* Bit 0 : Starts offset auto-calibration */
11370 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
11371 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
11372 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
11373 
11374 /* Register: SAADC_SUBSCRIBE_START */
11375 /* Description: Subscribe configuration for task START */
11376 
11377 /* Bit 31 :   */
11378 #define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
11379 #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
11380 #define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
11381 #define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
11382 
11383 /* Bits 7..0 : DPPI channel that task START will subscribe to */
11384 #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11385 #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11386 
11387 /* Register: SAADC_SUBSCRIBE_SAMPLE */
11388 /* Description: Subscribe configuration for task SAMPLE */
11389 
11390 /* Bit 31 :   */
11391 #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
11392 #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
11393 #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */
11394 #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */
11395 
11396 /* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */
11397 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11398 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11399 
11400 /* Register: SAADC_SUBSCRIBE_STOP */
11401 /* Description: Subscribe configuration for task STOP */
11402 
11403 /* Bit 31 :   */
11404 #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
11405 #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
11406 #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
11407 #define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
11408 
11409 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
11410 #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11411 #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11412 
11413 /* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */
11414 /* Description: Subscribe configuration for task CALIBRATEOFFSET */
11415 
11416 /* Bit 31 :   */
11417 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */
11418 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */
11419 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */
11420 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */
11421 
11422 /* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */
11423 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11424 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11425 
11426 /* Register: SAADC_EVENTS_STARTED */
11427 /* Description: The ADC has started */
11428 
11429 /* Bit 0 : The ADC has started */
11430 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
11431 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
11432 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
11433 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
11434 
11435 /* Register: SAADC_EVENTS_END */
11436 /* Description: The ADC has filled up the Result buffer */
11437 
11438 /* Bit 0 : The ADC has filled up the Result buffer */
11439 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
11440 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
11441 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
11442 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
11443 
11444 /* Register: SAADC_EVENTS_DONE */
11445 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
11446 
11447 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
11448 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
11449 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
11450 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
11451 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
11452 
11453 /* Register: SAADC_EVENTS_RESULTDONE */
11454 /* Description: A result is ready to get transferred to RAM */
11455 
11456 /* Bit 0 : A result is ready to get transferred to RAM */
11457 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
11458 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
11459 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
11460 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
11461 
11462 /* Register: SAADC_EVENTS_CALIBRATEDONE */
11463 /* Description: Calibration is complete */
11464 
11465 /* Bit 0 : Calibration is complete */
11466 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
11467 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
11468 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
11469 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
11470 
11471 /* Register: SAADC_EVENTS_STOPPED */
11472 /* Description: The ADC has stopped */
11473 
11474 /* Bit 0 : The ADC has stopped */
11475 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
11476 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
11477 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
11478 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
11479 
11480 /* Register: SAADC_EVENTS_CH_LIMITH */
11481 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
11482 
11483 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
11484 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
11485 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
11486 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
11487 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
11488 
11489 /* Register: SAADC_EVENTS_CH_LIMITL */
11490 /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */
11491 
11492 /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
11493 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
11494 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
11495 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
11496 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
11497 
11498 /* Register: SAADC_PUBLISH_STARTED */
11499 /* Description: Publish configuration for event STARTED */
11500 
11501 /* Bit 31 :   */
11502 #define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
11503 #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
11504 #define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
11505 #define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
11506 
11507 /* Bits 7..0 : DPPI channel that event STARTED will publish to. */
11508 #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11509 #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11510 
11511 /* Register: SAADC_PUBLISH_END */
11512 /* Description: Publish configuration for event END */
11513 
11514 /* Bit 31 :   */
11515 #define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
11516 #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
11517 #define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
11518 #define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
11519 
11520 /* Bits 7..0 : DPPI channel that event END will publish to. */
11521 #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11522 #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11523 
11524 /* Register: SAADC_PUBLISH_DONE */
11525 /* Description: Publish configuration for event DONE */
11526 
11527 /* Bit 31 :   */
11528 #define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
11529 #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
11530 #define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */
11531 #define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
11532 
11533 /* Bits 7..0 : DPPI channel that event DONE will publish to. */
11534 #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11535 #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11536 
11537 /* Register: SAADC_PUBLISH_RESULTDONE */
11538 /* Description: Publish configuration for event RESULTDONE */
11539 
11540 /* Bit 31 :   */
11541 #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */
11542 #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */
11543 #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */
11544 #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */
11545 
11546 /* Bits 7..0 : DPPI channel that event RESULTDONE will publish to. */
11547 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11548 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11549 
11550 /* Register: SAADC_PUBLISH_CALIBRATEDONE */
11551 /* Description: Publish configuration for event CALIBRATEDONE */
11552 
11553 /* Bit 31 :   */
11554 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */
11555 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */
11556 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */
11557 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */
11558 
11559 /* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to. */
11560 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11561 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11562 
11563 /* Register: SAADC_PUBLISH_STOPPED */
11564 /* Description: Publish configuration for event STOPPED */
11565 
11566 /* Bit 31 :   */
11567 #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
11568 #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
11569 #define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
11570 #define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
11571 
11572 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
11573 #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11574 #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11575 
11576 /* Register: SAADC_PUBLISH_CH_LIMITH */
11577 /* Description: Description cluster: Publish configuration for event CH[n].LIMITH */
11578 
11579 /* Bit 31 :   */
11580 #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */
11581 #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */
11582 #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */
11583 #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */
11584 
11585 /* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to. */
11586 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11587 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11588 
11589 /* Register: SAADC_PUBLISH_CH_LIMITL */
11590 /* Description: Description cluster: Publish configuration for event CH[n].LIMITL */
11591 
11592 /* Bit 31 :   */
11593 #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */
11594 #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */
11595 #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */
11596 #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */
11597 
11598 /* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to. */
11599 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
11600 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
11601 
11602 /* Register: SAADC_INTEN */
11603 /* Description: Enable or disable interrupt */
11604 
11605 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
11606 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
11607 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
11608 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
11609 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
11610 
11611 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
11612 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
11613 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
11614 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
11615 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
11616 
11617 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
11618 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
11619 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
11620 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
11621 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
11622 
11623 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
11624 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
11625 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
11626 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
11627 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
11628 
11629 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
11630 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
11631 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
11632 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
11633 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
11634 
11635 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
11636 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
11637 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
11638 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
11639 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
11640 
11641 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
11642 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
11643 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
11644 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
11645 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
11646 
11647 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
11648 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
11649 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
11650 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
11651 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
11652 
11653 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
11654 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
11655 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
11656 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
11657 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
11658 
11659 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
11660 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
11661 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
11662 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
11663 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
11664 
11665 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
11666 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
11667 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
11668 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
11669 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
11670 
11671 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
11672 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
11673 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
11674 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
11675 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
11676 
11677 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
11678 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
11679 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
11680 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
11681 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
11682 
11683 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
11684 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
11685 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
11686 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
11687 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
11688 
11689 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
11690 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
11691 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
11692 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
11693 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
11694 
11695 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
11696 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
11697 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
11698 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
11699 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
11700 
11701 /* Bit 5 : Enable or disable interrupt for event STOPPED */
11702 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
11703 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11704 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11705 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11706 
11707 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
11708 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
11709 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
11710 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
11711 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
11712 
11713 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
11714 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
11715 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
11716 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
11717 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
11718 
11719 /* Bit 2 : Enable or disable interrupt for event DONE */
11720 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
11721 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
11722 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
11723 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
11724 
11725 /* Bit 1 : Enable or disable interrupt for event END */
11726 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
11727 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
11728 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
11729 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
11730 
11731 /* Bit 0 : Enable or disable interrupt for event STARTED */
11732 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
11733 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
11734 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
11735 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
11736 
11737 /* Register: SAADC_INTENSET */
11738 /* Description: Enable interrupt */
11739 
11740 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
11741 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
11742 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
11743 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11744 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11745 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
11746 
11747 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
11748 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
11749 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
11750 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11751 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11752 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
11753 
11754 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
11755 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
11756 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
11757 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11758 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11759 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
11760 
11761 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
11762 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
11763 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
11764 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11765 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11766 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
11767 
11768 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
11769 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
11770 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
11771 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11772 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11773 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
11774 
11775 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
11776 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
11777 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
11778 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11779 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11780 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
11781 
11782 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
11783 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
11784 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
11785 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11786 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11787 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
11788 
11789 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
11790 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
11791 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
11792 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11793 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11794 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
11795 
11796 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
11797 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
11798 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
11799 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
11800 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
11801 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
11802 
11803 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
11804 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
11805 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
11806 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
11807 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
11808 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
11809 
11810 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
11811 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
11812 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
11813 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
11814 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
11815 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
11816 
11817 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
11818 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
11819 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
11820 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
11821 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
11822 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
11823 
11824 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
11825 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
11826 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
11827 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
11828 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
11829 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
11830 
11831 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
11832 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
11833 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
11834 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
11835 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
11836 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
11837 
11838 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
11839 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
11840 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
11841 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
11842 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
11843 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
11844 
11845 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
11846 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
11847 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
11848 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
11849 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
11850 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
11851 
11852 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
11853 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
11854 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11855 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11856 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11857 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11858 
11859 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
11860 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
11861 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
11862 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
11863 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
11864 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
11865 
11866 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
11867 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
11868 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
11869 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
11870 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
11871 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
11872 
11873 /* Bit 2 : Write '1' to enable interrupt for event DONE */
11874 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
11875 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
11876 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
11877 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
11878 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
11879 
11880 /* Bit 1 : Write '1' to enable interrupt for event END */
11881 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
11882 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
11883 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
11884 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
11885 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
11886 
11887 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
11888 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
11889 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
11890 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
11891 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
11892 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
11893 
11894 /* Register: SAADC_INTENCLR */
11895 /* Description: Disable interrupt */
11896 
11897 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
11898 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
11899 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
11900 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11901 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11902 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
11903 
11904 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
11905 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
11906 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
11907 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11908 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11909 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
11910 
11911 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
11912 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
11913 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
11914 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11915 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11916 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
11917 
11918 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
11919 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
11920 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
11921 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11922 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11923 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
11924 
11925 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
11926 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
11927 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
11928 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11929 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11930 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
11931 
11932 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
11933 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
11934 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
11935 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11936 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11937 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
11938 
11939 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
11940 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
11941 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
11942 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11943 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11944 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
11945 
11946 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
11947 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
11948 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
11949 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11950 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11951 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
11952 
11953 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
11954 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
11955 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
11956 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
11957 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
11958 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
11959 
11960 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
11961 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
11962 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
11963 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
11964 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
11965 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
11966 
11967 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
11968 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
11969 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
11970 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
11971 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
11972 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
11973 
11974 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
11975 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
11976 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
11977 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
11978 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
11979 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
11980 
11981 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
11982 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
11983 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
11984 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
11985 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
11986 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
11987 
11988 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
11989 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
11990 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
11991 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
11992 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
11993 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
11994 
11995 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
11996 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
11997 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
11998 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
11999 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
12000 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
12001 
12002 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
12003 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
12004 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
12005 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
12006 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
12007 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
12008 
12009 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
12010 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
12011 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12012 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12013 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12014 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
12015 
12016 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
12017 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
12018 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
12019 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
12020 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
12021 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
12022 
12023 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
12024 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
12025 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
12026 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
12027 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
12028 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
12029 
12030 /* Bit 2 : Write '1' to disable interrupt for event DONE */
12031 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
12032 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
12033 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
12034 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
12035 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
12036 
12037 /* Bit 1 : Write '1' to disable interrupt for event END */
12038 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
12039 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
12040 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12041 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12042 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
12043 
12044 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
12045 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
12046 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
12047 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
12048 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
12049 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
12050 
12051 /* Register: SAADC_STATUS */
12052 /* Description: Status */
12053 
12054 /* Bit 0 : Status */
12055 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
12056 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
12057 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No ongoing conversion. */
12058 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Single conversion in progress. */
12059 
12060 /* Register: SAADC_ENABLE */
12061 /* Description: Enable or disable ADC */
12062 
12063 /* Bit 0 : Enable or disable ADC */
12064 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12065 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12066 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
12067 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
12068 
12069 /* Register: SAADC_CH_PSELP */
12070 /* Description: Description cluster: Input positive pin selection for CH[n] */
12071 
12072 /* Bits 4..0 : Analog positive input channel */
12073 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
12074 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
12075 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
12076 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
12077 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
12078 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
12079 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
12080 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
12081 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
12082 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
12083 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
12084 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
12085 #define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0xDUL) /*!< VDDH/5 */
12086 
12087 /* Register: SAADC_CH_PSELN */
12088 /* Description: Description cluster: Input negative pin selection for CH[n] */
12089 
12090 /* Bits 4..0 : Analog negative input, enables differential channel */
12091 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
12092 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
12093 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
12094 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
12095 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
12096 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
12097 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
12098 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
12099 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
12100 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
12101 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
12102 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
12103 #define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0xDUL) /*!< VDDH/5 */
12104 
12105 /* Register: SAADC_CH_CONFIG */
12106 /* Description: Description cluster: Input configuration for CH[n] */
12107 
12108 /* Bit 24 : Enable burst mode */
12109 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
12110 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
12111 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
12112 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
12113 
12114 /* Bit 20 : Enable differential mode */
12115 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
12116 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
12117 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to ADC shorted to GND */
12118 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
12119 
12120 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
12121 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
12122 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
12123 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
12124 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
12125 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
12126 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
12127 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
12128 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
12129 
12130 /* Bit 12 : Reference control */
12131 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
12132 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
12133 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
12134 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
12135 
12136 /* Bits 10..8 : Gain control */
12137 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
12138 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
12139 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
12140 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
12141 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
12142 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
12143 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
12144 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
12145 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
12146 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
12147 
12148 /* Bits 5..4 : Negative channel resistor control */
12149 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
12150 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
12151 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
12152 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
12153 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
12154 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
12155 
12156 /* Bits 1..0 : Positive channel resistor control */
12157 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
12158 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
12159 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
12160 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
12161 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
12162 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
12163 
12164 /* Register: SAADC_CH_LIMIT */
12165 /* Description: Description cluster: High/low limits for event monitoring a channel */
12166 
12167 /* Bits 31..16 : High level limit */
12168 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
12169 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
12170 
12171 /* Bits 15..0 : Low level limit */
12172 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
12173 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
12174 
12175 /* Register: SAADC_RESOLUTION */
12176 /* Description: Resolution configuration */
12177 
12178 /* Bits 2..0 : Set the resolution */
12179 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
12180 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
12181 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
12182 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
12183 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
12184 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
12185 
12186 /* Register: SAADC_OVERSAMPLE */
12187 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
12188 
12189 /* Bits 3..0 : Oversample control */
12190 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
12191 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
12192 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
12193 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
12194 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
12195 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
12196 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
12197 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
12198 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
12199 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
12200 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
12201 
12202 /* Register: SAADC_SAMPLERATE */
12203 /* Description: Controls normal or continuous sample rate */
12204 
12205 /* Bit 12 : Select mode for sample rate control */
12206 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
12207 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
12208 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
12209 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
12210 
12211 /* Bits 10..0 : Capture and compare value; sample rate is 16 MHz/CC */
12212 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
12213 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
12214 
12215 /* Register: SAADC_RESULT_PTR */
12216 /* Description: Data pointer */
12217 
12218 /* Bits 31..0 : Data pointer */
12219 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12220 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12221 
12222 /* Register: SAADC_RESULT_MAXCNT */
12223 /* Description: Maximum number of buffer words to transfer */
12224 
12225 /* Bits 14..0 : Maximum number of buffer words to transfer */
12226 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12227 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12228 
12229 /* Register: SAADC_RESULT_AMOUNT */
12230 /* Description: Number of buffer words transferred since last START */
12231 
12232 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
12233 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12234 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12235 
12236 
12237 /* Peripheral: SPIM */
12238 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
12239 
12240 /* Register: SPIM_TASKS_START */
12241 /* Description: Start SPI transaction */
12242 
12243 /* Bit 0 : Start SPI transaction */
12244 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
12245 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
12246 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
12247 
12248 /* Register: SPIM_TASKS_STOP */
12249 /* Description: Stop SPI transaction */
12250 
12251 /* Bit 0 : Stop SPI transaction */
12252 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12253 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12254 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
12255 
12256 /* Register: SPIM_TASKS_SUSPEND */
12257 /* Description: Suspend SPI transaction */
12258 
12259 /* Bit 0 : Suspend SPI transaction */
12260 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
12261 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
12262 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
12263 
12264 /* Register: SPIM_TASKS_RESUME */
12265 /* Description: Resume SPI transaction */
12266 
12267 /* Bit 0 : Resume SPI transaction */
12268 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
12269 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
12270 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
12271 
12272 /* Register: SPIM_SUBSCRIBE_START */
12273 /* Description: Subscribe configuration for task START */
12274 
12275 /* Bit 31 :   */
12276 #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
12277 #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
12278 #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
12279 #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
12280 
12281 /* Bits 7..0 : DPPI channel that task START will subscribe to */
12282 #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12283 #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12284 
12285 /* Register: SPIM_SUBSCRIBE_STOP */
12286 /* Description: Subscribe configuration for task STOP */
12287 
12288 /* Bit 31 :   */
12289 #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
12290 #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
12291 #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
12292 #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
12293 
12294 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
12295 #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12296 #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12297 
12298 /* Register: SPIM_SUBSCRIBE_SUSPEND */
12299 /* Description: Subscribe configuration for task SUSPEND */
12300 
12301 /* Bit 31 :   */
12302 #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
12303 #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
12304 #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
12305 #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
12306 
12307 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
12308 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12309 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12310 
12311 /* Register: SPIM_SUBSCRIBE_RESUME */
12312 /* Description: Subscribe configuration for task RESUME */
12313 
12314 /* Bit 31 :   */
12315 #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
12316 #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
12317 #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
12318 #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
12319 
12320 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
12321 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12322 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12323 
12324 /* Register: SPIM_EVENTS_STOPPED */
12325 /* Description: SPI transaction has stopped */
12326 
12327 /* Bit 0 : SPI transaction has stopped */
12328 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
12329 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
12330 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
12331 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
12332 
12333 /* Register: SPIM_EVENTS_ENDRX */
12334 /* Description: End of RXD buffer reached */
12335 
12336 /* Bit 0 : End of RXD buffer reached */
12337 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
12338 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
12339 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
12340 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
12341 
12342 /* Register: SPIM_EVENTS_END */
12343 /* Description: End of RXD buffer and TXD buffer reached */
12344 
12345 /* Bit 0 : End of RXD buffer and TXD buffer reached */
12346 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
12347 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
12348 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
12349 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
12350 
12351 /* Register: SPIM_EVENTS_ENDTX */
12352 /* Description: End of TXD buffer reached */
12353 
12354 /* Bit 0 : End of TXD buffer reached */
12355 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
12356 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
12357 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
12358 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
12359 
12360 /* Register: SPIM_EVENTS_STARTED */
12361 /* Description: Transaction started */
12362 
12363 /* Bit 0 : Transaction started */
12364 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
12365 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
12366 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
12367 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
12368 
12369 /* Register: SPIM_PUBLISH_STOPPED */
12370 /* Description: Publish configuration for event STOPPED */
12371 
12372 /* Bit 31 :   */
12373 #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
12374 #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
12375 #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
12376 #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
12377 
12378 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
12379 #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12380 #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12381 
12382 /* Register: SPIM_PUBLISH_ENDRX */
12383 /* Description: Publish configuration for event ENDRX */
12384 
12385 /* Bit 31 :   */
12386 #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
12387 #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
12388 #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
12389 #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
12390 
12391 /* Bits 7..0 : DPPI channel that event ENDRX will publish to. */
12392 #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12393 #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12394 
12395 /* Register: SPIM_PUBLISH_END */
12396 /* Description: Publish configuration for event END */
12397 
12398 /* Bit 31 :   */
12399 #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
12400 #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
12401 #define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
12402 #define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
12403 
12404 /* Bits 7..0 : DPPI channel that event END will publish to. */
12405 #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12406 #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12407 
12408 /* Register: SPIM_PUBLISH_ENDTX */
12409 /* Description: Publish configuration for event ENDTX */
12410 
12411 /* Bit 31 :   */
12412 #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
12413 #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
12414 #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
12415 #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
12416 
12417 /* Bits 7..0 : DPPI channel that event ENDTX will publish to. */
12418 #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12419 #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12420 
12421 /* Register: SPIM_PUBLISH_STARTED */
12422 /* Description: Publish configuration for event STARTED */
12423 
12424 /* Bit 31 :   */
12425 #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
12426 #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
12427 #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
12428 #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
12429 
12430 /* Bits 7..0 : DPPI channel that event STARTED will publish to. */
12431 #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12432 #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12433 
12434 /* Register: SPIM_SHORTS */
12435 /* Description: Shortcuts between local events and tasks */
12436 
12437 /* Bit 17 : Shortcut between event END and task START */
12438 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
12439 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
12440 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
12441 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
12442 
12443 /* Register: SPIM_INTENSET */
12444 /* Description: Enable interrupt */
12445 
12446 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
12447 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
12448 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
12449 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
12450 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
12451 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
12452 
12453 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
12454 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12455 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12456 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12457 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12458 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
12459 
12460 /* Bit 6 : Write '1' to enable interrupt for event END */
12461 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
12462 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
12463 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12464 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12465 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
12466 
12467 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
12468 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12469 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12470 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12471 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12472 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12473 
12474 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
12475 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12476 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12477 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12478 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12479 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
12480 
12481 /* Register: SPIM_INTENCLR */
12482 /* Description: Disable interrupt */
12483 
12484 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
12485 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
12486 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
12487 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
12488 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
12489 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
12490 
12491 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
12492 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12493 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12494 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12495 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12496 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
12497 
12498 /* Bit 6 : Write '1' to disable interrupt for event END */
12499 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
12500 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
12501 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12502 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12503 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
12504 
12505 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
12506 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12507 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12508 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12509 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12510 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12511 
12512 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
12513 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12514 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12515 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12516 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12517 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
12518 
12519 /* Register: SPIM_STALLSTAT */
12520 /* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */
12521 
12522 /* Bit 1 : Stall status for EasyDMA RAM writes */
12523 #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */
12524 #define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */
12525 #define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */
12526 #define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */
12527 
12528 /* Bit 0 : Stall status for EasyDMA RAM reads */
12529 #define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */
12530 #define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */
12531 #define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */
12532 #define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */
12533 
12534 /* Register: SPIM_ENABLE */
12535 /* Description: Enable SPIM */
12536 
12537 /* Bits 3..0 : Enable or disable SPIM */
12538 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12539 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12540 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
12541 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
12542 
12543 /* Register: SPIM_PSEL_SCK */
12544 /* Description: Pin select for SCK */
12545 
12546 /* Bit 31 : Connection */
12547 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12548 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12549 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
12550 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
12551 
12552 /* Bit 5 : Port number */
12553 #define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
12554 #define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
12555 
12556 /* Bits 4..0 : Pin number */
12557 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
12558 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
12559 
12560 /* Register: SPIM_PSEL_MOSI */
12561 /* Description: Pin select for MOSI signal */
12562 
12563 /* Bit 31 : Connection */
12564 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12565 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12566 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
12567 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
12568 
12569 /* Bit 5 : Port number */
12570 #define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
12571 #define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
12572 
12573 /* Bits 4..0 : Pin number */
12574 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
12575 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
12576 
12577 /* Register: SPIM_PSEL_MISO */
12578 /* Description: Pin select for MISO signal */
12579 
12580 /* Bit 31 : Connection */
12581 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12582 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12583 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
12584 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
12585 
12586 /* Bit 5 : Port number */
12587 #define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
12588 #define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
12589 
12590 /* Bits 4..0 : Pin number */
12591 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
12592 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
12593 
12594 /* Register: SPIM_PSEL_CSN */
12595 /* Description: Pin select for CSN */
12596 
12597 /* Bit 31 : Connection */
12598 #define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12599 #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12600 #define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
12601 #define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
12602 
12603 /* Bit 5 : Port number */
12604 #define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
12605 #define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
12606 
12607 /* Bits 4..0 : Pin number */
12608 #define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
12609 #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
12610 
12611 /* Register: SPIM_FREQUENCY */
12612 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
12613 
12614 /* Bits 31..0 : SPI master data rate */
12615 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
12616 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
12617 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
12618 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
12619 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
12620 #define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
12621 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
12622 #define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
12623 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
12624 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
12625 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
12626 
12627 /* Register: SPIM_RXD_PTR */
12628 /* Description: Data pointer */
12629 
12630 /* Bits 31..0 : Data pointer */
12631 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12632 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12633 
12634 /* Register: SPIM_RXD_MAXCNT */
12635 /* Description: Maximum number of bytes in receive buffer */
12636 
12637 /* Bits 15..0 : Maximum number of bytes in receive buffer */
12638 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12639 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12640 
12641 /* Register: SPIM_RXD_AMOUNT */
12642 /* Description: Number of bytes transferred in the last transaction */
12643 
12644 /* Bits 15..0 : Number of bytes transferred in the last transaction */
12645 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12646 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12647 
12648 /* Register: SPIM_RXD_LIST */
12649 /* Description: EasyDMA list type */
12650 
12651 /* Bits 1..0 : List type */
12652 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
12653 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
12654 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12655 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
12656 
12657 /* Register: SPIM_TXD_PTR */
12658 /* Description: Data pointer */
12659 
12660 /* Bits 31..0 : Data pointer */
12661 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12662 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12663 
12664 /* Register: SPIM_TXD_MAXCNT */
12665 /* Description: Number of bytes in transmit buffer */
12666 
12667 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
12668 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12669 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12670 
12671 /* Register: SPIM_TXD_AMOUNT */
12672 /* Description: Number of bytes transferred in the last transaction */
12673 
12674 /* Bits 15..0 : Number of bytes transferred in the last transaction */
12675 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12676 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12677 
12678 /* Register: SPIM_TXD_LIST */
12679 /* Description: EasyDMA list type */
12680 
12681 /* Bits 1..0 : List type */
12682 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
12683 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
12684 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
12685 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
12686 
12687 /* Register: SPIM_CONFIG */
12688 /* Description: Configuration register */
12689 
12690 /* Bit 2 : Serial clock (SCK) polarity */
12691 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12692 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
12693 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12694 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
12695 
12696 /* Bit 1 : Serial clock (SCK) phase */
12697 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
12698 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
12699 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
12700 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
12701 
12702 /* Bit 0 : Bit order */
12703 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
12704 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
12705 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
12706 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
12707 
12708 /* Register: SPIM_IFTIMING_RXDELAY */
12709 /* Description: Sample delay for input serial data on MISO */
12710 
12711 /* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */
12712 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */
12713 #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
12714 
12715 /* Register: SPIM_IFTIMING_CSNDUR */
12716 /* Description: Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. */
12717 
12718 /* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */
12719 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
12720 #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */
12721 
12722 /* Register: SPIM_CSNPOL */
12723 /* Description: Polarity of CSN output */
12724 
12725 /* Bit 0 : Polarity of CSN output */
12726 #define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */
12727 #define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */
12728 #define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */
12729 #define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */
12730 
12731 /* Register: SPIM_PSELDCX */
12732 /* Description: Pin select for DCX signal */
12733 
12734 /* Bit 31 : Connection */
12735 #define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12736 #define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12737 #define SPIM_PSELDCX_CONNECT_Connected (0UL) /*!< Connect */
12738 #define SPIM_PSELDCX_CONNECT_Disconnected (1UL) /*!< Disconnect */
12739 
12740 /* Bit 5 : Port number */
12741 #define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */
12742 #define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */
12743 
12744 /* Bits 4..0 : Pin number */
12745 #define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */
12746 #define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */
12747 
12748 /* Register: SPIM_DCXCNT */
12749 /* Description: DCX configuration */
12750 
12751 /* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */
12752 #define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */
12753 #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */
12754 
12755 /* Register: SPIM_ORC */
12756 /* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
12757 
12758 /* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
12759 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
12760 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
12761 
12762 
12763 /* Peripheral: SPIS */
12764 /* Description: SPI Slave 0 */
12765 
12766 /* Register: SPIS_TASKS_ACQUIRE */
12767 /* Description: Acquire SPI semaphore */
12768 
12769 /* Bit 0 : Acquire SPI semaphore */
12770 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
12771 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
12772 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
12773 
12774 /* Register: SPIS_TASKS_RELEASE */
12775 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
12776 
12777 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
12778 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
12779 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
12780 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
12781 
12782 /* Register: SPIS_SUBSCRIBE_ACQUIRE */
12783 /* Description: Subscribe configuration for task ACQUIRE */
12784 
12785 /* Bit 31 :   */
12786 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */
12787 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */
12788 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */
12789 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */
12790 
12791 /* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */
12792 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12793 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12794 
12795 /* Register: SPIS_SUBSCRIBE_RELEASE */
12796 /* Description: Subscribe configuration for task RELEASE */
12797 
12798 /* Bit 31 :   */
12799 #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */
12800 #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */
12801 #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */
12802 #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */
12803 
12804 /* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */
12805 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12806 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12807 
12808 /* Register: SPIS_EVENTS_END */
12809 /* Description: Granted transaction completed */
12810 
12811 /* Bit 0 : Granted transaction completed */
12812 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
12813 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
12814 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
12815 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
12816 
12817 /* Register: SPIS_EVENTS_ENDRX */
12818 /* Description: End of RXD buffer reached */
12819 
12820 /* Bit 0 : End of RXD buffer reached */
12821 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
12822 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
12823 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
12824 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
12825 
12826 /* Register: SPIS_EVENTS_ACQUIRED */
12827 /* Description: Semaphore acquired */
12828 
12829 /* Bit 0 : Semaphore acquired */
12830 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
12831 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
12832 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
12833 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
12834 
12835 /* Register: SPIS_PUBLISH_END */
12836 /* Description: Publish configuration for event END */
12837 
12838 /* Bit 31 :   */
12839 #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
12840 #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
12841 #define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
12842 #define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
12843 
12844 /* Bits 7..0 : DPPI channel that event END will publish to. */
12845 #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12846 #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12847 
12848 /* Register: SPIS_PUBLISH_ENDRX */
12849 /* Description: Publish configuration for event ENDRX */
12850 
12851 /* Bit 31 :   */
12852 #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
12853 #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
12854 #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
12855 #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
12856 
12857 /* Bits 7..0 : DPPI channel that event ENDRX will publish to. */
12858 #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12859 #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12860 
12861 /* Register: SPIS_PUBLISH_ACQUIRED */
12862 /* Description: Publish configuration for event ACQUIRED */
12863 
12864 /* Bit 31 :   */
12865 #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */
12866 #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */
12867 #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */
12868 #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */
12869 
12870 /* Bits 7..0 : DPPI channel that event ACQUIRED will publish to. */
12871 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
12872 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
12873 
12874 /* Register: SPIS_SHORTS */
12875 /* Description: Shortcuts between local events and tasks */
12876 
12877 /* Bit 2 : Shortcut between event END and task ACQUIRE */
12878 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
12879 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
12880 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
12881 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
12882 
12883 /* Register: SPIS_INTENSET */
12884 /* Description: Enable interrupt */
12885 
12886 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
12887 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
12888 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
12889 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
12890 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
12891 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
12892 
12893 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
12894 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12895 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12896 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12897 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12898 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12899 
12900 /* Bit 1 : Write '1' to enable interrupt for event END */
12901 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
12902 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
12903 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12904 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12905 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
12906 
12907 /* Register: SPIS_INTENCLR */
12908 /* Description: Disable interrupt */
12909 
12910 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
12911 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
12912 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
12913 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
12914 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
12915 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
12916 
12917 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
12918 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12919 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12920 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12921 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12922 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12923 
12924 /* Bit 1 : Write '1' to disable interrupt for event END */
12925 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
12926 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
12927 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12928 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12929 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
12930 
12931 /* Register: SPIS_SEMSTAT */
12932 /* Description: Semaphore status register */
12933 
12934 /* Bits 1..0 : Semaphore status */
12935 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
12936 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
12937 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
12938 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
12939 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
12940 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
12941 
12942 /* Register: SPIS_STATUS */
12943 /* Description: Status from last transaction */
12944 
12945 /* Bit 1 : RX buffer overflow detected, and prevented */
12946 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
12947 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
12948 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
12949 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
12950 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
12951 
12952 /* Bit 0 : TX buffer over-read detected, and prevented */
12953 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
12954 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
12955 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
12956 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
12957 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
12958 
12959 /* Register: SPIS_ENABLE */
12960 /* Description: Enable SPI slave */
12961 
12962 /* Bits 3..0 : Enable or disable SPI slave */
12963 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12964 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12965 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
12966 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
12967 
12968 /* Register: SPIS_PSEL_SCK */
12969 /* Description: Pin select for SCK */
12970 
12971 /* Bit 31 : Connection */
12972 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12973 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12974 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
12975 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
12976 
12977 /* Bit 5 : Port number */
12978 #define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
12979 #define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
12980 
12981 /* Bits 4..0 : Pin number */
12982 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
12983 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
12984 
12985 /* Register: SPIS_PSEL_MISO */
12986 /* Description: Pin select for MISO signal */
12987 
12988 /* Bit 31 : Connection */
12989 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12990 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12991 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
12992 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
12993 
12994 /* Bit 5 : Port number */
12995 #define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
12996 #define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
12997 
12998 /* Bits 4..0 : Pin number */
12999 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
13000 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
13001 
13002 /* Register: SPIS_PSEL_MOSI */
13003 /* Description: Pin select for MOSI signal */
13004 
13005 /* Bit 31 : Connection */
13006 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13007 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13008 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
13009 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
13010 
13011 /* Bit 5 : Port number */
13012 #define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
13013 #define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
13014 
13015 /* Bits 4..0 : Pin number */
13016 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
13017 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
13018 
13019 /* Register: SPIS_PSEL_CSN */
13020 /* Description: Pin select for CSN signal */
13021 
13022 /* Bit 31 : Connection */
13023 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13024 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13025 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
13026 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
13027 
13028 /* Bit 5 : Port number */
13029 #define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
13030 #define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
13031 
13032 /* Bits 4..0 : Pin number */
13033 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
13034 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
13035 
13036 /* Register: SPIS_RXD_PTR */
13037 /* Description: RXD data pointer */
13038 
13039 /* Bits 31..0 : RXD data pointer */
13040 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
13041 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
13042 
13043 /* Register: SPIS_RXD_MAXCNT */
13044 /* Description: Maximum number of bytes in receive buffer */
13045 
13046 /* Bits 15..0 : Maximum number of bytes in receive buffer */
13047 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
13048 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
13049 
13050 /* Register: SPIS_RXD_AMOUNT */
13051 /* Description: Number of bytes received in last granted transaction */
13052 
13053 /* Bits 15..0 : Number of bytes received in the last granted transaction */
13054 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
13055 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
13056 
13057 /* Register: SPIS_RXD_LIST */
13058 /* Description: EasyDMA list type */
13059 
13060 /* Bits 1..0 : List type */
13061 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
13062 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
13063 #define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
13064 #define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
13065 
13066 /* Register: SPIS_TXD_PTR */
13067 /* Description: TXD data pointer */
13068 
13069 /* Bits 31..0 : TXD data pointer */
13070 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
13071 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
13072 
13073 /* Register: SPIS_TXD_MAXCNT */
13074 /* Description: Maximum number of bytes in transmit buffer */
13075 
13076 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
13077 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
13078 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
13079 
13080 /* Register: SPIS_TXD_AMOUNT */
13081 /* Description: Number of bytes transmitted in last granted transaction */
13082 
13083 /* Bits 15..0 : Number of bytes transmitted in last granted transaction */
13084 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
13085 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
13086 
13087 /* Register: SPIS_TXD_LIST */
13088 /* Description: EasyDMA list type */
13089 
13090 /* Bits 1..0 : List type */
13091 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
13092 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
13093 #define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
13094 #define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
13095 
13096 /* Register: SPIS_CONFIG */
13097 /* Description: Configuration register */
13098 
13099 /* Bit 2 : Serial clock (SCK) polarity */
13100 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
13101 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
13102 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
13103 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
13104 
13105 /* Bit 1 : Serial clock (SCK) phase */
13106 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
13107 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
13108 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
13109 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
13110 
13111 /* Bit 0 : Bit order */
13112 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
13113 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
13114 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
13115 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
13116 
13117 /* Register: SPIS_DEF */
13118 /* Description: Default character. Character clocked out in case of an ignored transaction. */
13119 
13120 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
13121 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
13122 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
13123 
13124 /* Register: SPIS_ORC */
13125 /* Description: Over-read character */
13126 
13127 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
13128 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
13129 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
13130 
13131 
13132 /* Peripheral: SPU */
13133 /* Description: System protection unit */
13134 
13135 /* Register: SPU_EVENTS_RAMACCERR */
13136 /* Description: A security violation has been detected for the RAM memory space */
13137 
13138 /* Bit 0 : A security violation has been detected for the RAM memory space */
13139 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */
13140 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */
13141 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0UL) /*!< Event not generated */
13142 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL) /*!< Event generated */
13143 
13144 /* Register: SPU_EVENTS_FLASHACCERR */
13145 /* Description: A security violation has been detected for the flash memory space */
13146 
13147 /* Bit 0 : A security violation has been detected for the flash memory space */
13148 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */
13149 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */
13150 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0UL) /*!< Event not generated */
13151 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL) /*!< Event generated */
13152 
13153 /* Register: SPU_EVENTS_PERIPHACCERR */
13154 /* Description: A security violation has been detected on one or several peripherals */
13155 
13156 /* Bit 0 : A security violation has been detected on one or several peripherals */
13157 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */
13158 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */
13159 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0UL) /*!< Event not generated */
13160 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL) /*!< Event generated */
13161 
13162 /* Register: SPU_PUBLISH_RAMACCERR */
13163 /* Description: Publish configuration for event RAMACCERR */
13164 
13165 /* Bit 31 :   */
13166 #define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */
13167 #define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */
13168 #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */
13169 #define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */
13170 
13171 /* Bits 7..0 : DPPI channel that event RAMACCERR will publish to. */
13172 #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
13173 #define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
13174 
13175 /* Register: SPU_PUBLISH_FLASHACCERR */
13176 /* Description: Publish configuration for event FLASHACCERR */
13177 
13178 /* Bit 31 :   */
13179 #define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
13180 #define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */
13181 #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
13182 #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
13183 
13184 /* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to. */
13185 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
13186 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
13187 
13188 /* Register: SPU_PUBLISH_PERIPHACCERR */
13189 /* Description: Publish configuration for event PERIPHACCERR */
13190 
13191 /* Bit 31 :   */
13192 #define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
13193 #define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */
13194 #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
13195 #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
13196 
13197 /* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to. */
13198 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
13199 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
13200 
13201 /* Register: SPU_INTEN */
13202 /* Description: Enable or disable interrupt */
13203 
13204 /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */
13205 #define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
13206 #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
13207 #define SPU_INTEN_PERIPHACCERR_Disabled (0UL) /*!< Disable */
13208 #define SPU_INTEN_PERIPHACCERR_Enabled (1UL) /*!< Enable */
13209 
13210 /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */
13211 #define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
13212 #define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
13213 #define SPU_INTEN_FLASHACCERR_Disabled (0UL) /*!< Disable */
13214 #define SPU_INTEN_FLASHACCERR_Enabled (1UL) /*!< Enable */
13215 
13216 /* Bit 0 : Enable or disable interrupt for event RAMACCERR */
13217 #define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
13218 #define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
13219 #define SPU_INTEN_RAMACCERR_Disabled (0UL) /*!< Disable */
13220 #define SPU_INTEN_RAMACCERR_Enabled (1UL) /*!< Enable */
13221 
13222 /* Register: SPU_INTENSET */
13223 /* Description: Enable interrupt */
13224 
13225 /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */
13226 #define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
13227 #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
13228 #define SPU_INTENSET_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
13229 #define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
13230 #define SPU_INTENSET_PERIPHACCERR_Set (1UL) /*!< Enable */
13231 
13232 /* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */
13233 #define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
13234 #define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
13235 #define SPU_INTENSET_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
13236 #define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
13237 #define SPU_INTENSET_FLASHACCERR_Set (1UL) /*!< Enable */
13238 
13239 /* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */
13240 #define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
13241 #define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
13242 #define SPU_INTENSET_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
13243 #define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
13244 #define SPU_INTENSET_RAMACCERR_Set (1UL) /*!< Enable */
13245 
13246 /* Register: SPU_INTENCLR */
13247 /* Description: Disable interrupt */
13248 
13249 /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */
13250 #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
13251 #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
13252 #define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
13253 #define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
13254 #define SPU_INTENCLR_PERIPHACCERR_Clear (1UL) /*!< Disable */
13255 
13256 /* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */
13257 #define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
13258 #define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
13259 #define SPU_INTENCLR_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
13260 #define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
13261 #define SPU_INTENCLR_FLASHACCERR_Clear (1UL) /*!< Disable */
13262 
13263 /* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */
13264 #define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
13265 #define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
13266 #define SPU_INTENCLR_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
13267 #define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
13268 #define SPU_INTENCLR_RAMACCERR_Clear (1UL) /*!< Disable */
13269 
13270 /* Register: SPU_CAP */
13271 /* Description: Show implemented features for the current device */
13272 
13273 /* Bit 0 : Show Arm TrustZone status */
13274 #define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */
13275 #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */
13276 #define SPU_CAP_TZM_NotAvailable (0UL) /*!< Arm TrustZone support not available */
13277 #define SPU_CAP_TZM_Enabled (1UL) /*!< Arm TrustZone support is available */
13278 
13279 /* Register: SPU_CPULOCK */
13280 /* Description: Configure bits to lock down CPU features at runtime */
13281 
13282 /* Bit 4 : Write '1' to prevent updating the secure SAU regions until the next reset */
13283 #define SPU_CPULOCK_LOCKSAU_Pos (4UL) /*!< Position of LOCKSAU field. */
13284 #define SPU_CPULOCK_LOCKSAU_Msk (0x1UL << SPU_CPULOCK_LOCKSAU_Pos) /*!< Bit mask of LOCKSAU field. */
13285 #define SPU_CPULOCK_LOCKSAU_Unlocked (0UL) /*!< These registers can be updated */
13286 #define SPU_CPULOCK_LOCKSAU_Locked (1UL) /*!< Disables writes to the SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers from software or from a debug agent connected to the processor */
13287 
13288 /* Bit 3 : Write '1' to prevent updating the Non-secure MPU regions until the next reset */
13289 #define SPU_CPULOCK_LOCKNSMPU_Pos (3UL) /*!< Position of LOCKNSMPU field. */
13290 #define SPU_CPULOCK_LOCKNSMPU_Msk (0x1UL << SPU_CPULOCK_LOCKNSMPU_Pos) /*!< Bit mask of LOCKNSMPU field. */
13291 #define SPU_CPULOCK_LOCKNSMPU_Unlocked (0UL) /*!< These registers can be updated */
13292 #define SPU_CPULOCK_LOCKNSMPU_Locked (1UL) /*!< Disables writes to the MPU_CTRL_NS, MPU_RNR_NS, MPU_RBAR_NS, MPU_RLAR_NS, MPU_RBAR_A_NSn and MPU_RLAR_A_NSn from software or from a debug agent connected to the processor */
13293 
13294 /* Bit 2 : Write '1' to prevent updating the secure MPU regions until the next reset */
13295 #define SPU_CPULOCK_LOCKSMPU_Pos (2UL) /*!< Position of LOCKSMPU field. */
13296 #define SPU_CPULOCK_LOCKSMPU_Msk (0x1UL << SPU_CPULOCK_LOCKSMPU_Pos) /*!< Bit mask of LOCKSMPU field. */
13297 #define SPU_CPULOCK_LOCKSMPU_Unlocked (0UL) /*!< These registers can be updated */
13298 #define SPU_CPULOCK_LOCKSMPU_Locked (1UL) /*!< Disables writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An and MPU_RLAR_An from software or from a debug agent connected to the processor in Secure state */
13299 
13300 /* Bit 1 : Write '1' to prevent updating the non-secure vector table base address until the next reset */
13301 #define SPU_CPULOCK_LOCKNSVTOR_Pos (1UL) /*!< Position of LOCKNSVTOR field. */
13302 #define SPU_CPULOCK_LOCKNSVTOR_Msk (0x1UL << SPU_CPULOCK_LOCKNSVTOR_Pos) /*!< Bit mask of LOCKNSVTOR field. */
13303 #define SPU_CPULOCK_LOCKNSVTOR_Unlocked (0UL) /*!< The address of the non-secure vector table can be updated */
13304 #define SPU_CPULOCK_LOCKNSVTOR_Locked (1UL) /*!< The address of the non-secure vector table is locked */
13305 
13306 /* Bit 0 : Write '1' to prevent updating the secure interrupt configuration until the next reset */
13307 #define SPU_CPULOCK_LOCKSVTAIRCR_Pos (0UL) /*!< Position of LOCKSVTAIRCR field. */
13308 #define SPU_CPULOCK_LOCKSVTAIRCR_Msk (0x1UL << SPU_CPULOCK_LOCKSVTAIRCR_Pos) /*!< Bit mask of LOCKSVTAIRCR field. */
13309 #define SPU_CPULOCK_LOCKSVTAIRCR_Unlocked (0UL) /*!< These registers can be updated */
13310 #define SPU_CPULOCK_LOCKSVTAIRCR_Locked (1UL) /*!< Disables writes to the VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS registers */
13311 
13312 /* Register: SPU_EXTDOMAIN_PERM */
13313 /* Description: Description cluster: Access  for bus access generated from the external domain n List capabilities of the external domain  n */
13314 
13315 /* Bit 8 :   */
13316 #define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
13317 #define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
13318 #define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
13319 #define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
13320 
13321 /* Bit 4 : Peripheral security mapping */
13322 #define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
13323 #define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
13324 #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-secure attribute set */
13325 #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attribute set */
13326 
13327 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
13328 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
13329 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
13330 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set */
13331 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL) /*!< The bus access from this external domain always have the secure attribute set */
13332 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */
13333 
13334 /* Register: SPU_DPPI_PERM */
13335 /* Description: Description cluster: Select between secure and non-secure attribute  for the DPPI channels */
13336 
13337 /* Bit 31 : Select secure attribute */
13338 #define SPU_DPPI_PERM_CHANNEL31_Pos (31UL) /*!< Position of CHANNEL31 field. */
13339 #define SPU_DPPI_PERM_CHANNEL31_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL31_Pos) /*!< Bit mask of CHANNEL31 field. */
13340 #define SPU_DPPI_PERM_CHANNEL31_NonSecure (0UL) /*!< Channel 31 has its non-secure attribute set */
13341 #define SPU_DPPI_PERM_CHANNEL31_Secure (1UL) /*!< Channel 31 has its secure attribute set */
13342 
13343 /* Bit 30 : Select secure attribute */
13344 #define SPU_DPPI_PERM_CHANNEL30_Pos (30UL) /*!< Position of CHANNEL30 field. */
13345 #define SPU_DPPI_PERM_CHANNEL30_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL30_Pos) /*!< Bit mask of CHANNEL30 field. */
13346 #define SPU_DPPI_PERM_CHANNEL30_NonSecure (0UL) /*!< Channel 30 has its non-secure attribute set */
13347 #define SPU_DPPI_PERM_CHANNEL30_Secure (1UL) /*!< Channel 30 has its secure attribute set */
13348 
13349 /* Bit 29 : Select secure attribute */
13350 #define SPU_DPPI_PERM_CHANNEL29_Pos (29UL) /*!< Position of CHANNEL29 field. */
13351 #define SPU_DPPI_PERM_CHANNEL29_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL29_Pos) /*!< Bit mask of CHANNEL29 field. */
13352 #define SPU_DPPI_PERM_CHANNEL29_NonSecure (0UL) /*!< Channel 29 has its non-secure attribute set */
13353 #define SPU_DPPI_PERM_CHANNEL29_Secure (1UL) /*!< Channel 29 has its secure attribute set */
13354 
13355 /* Bit 28 : Select secure attribute */
13356 #define SPU_DPPI_PERM_CHANNEL28_Pos (28UL) /*!< Position of CHANNEL28 field. */
13357 #define SPU_DPPI_PERM_CHANNEL28_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL28_Pos) /*!< Bit mask of CHANNEL28 field. */
13358 #define SPU_DPPI_PERM_CHANNEL28_NonSecure (0UL) /*!< Channel 28 has its non-secure attribute set */
13359 #define SPU_DPPI_PERM_CHANNEL28_Secure (1UL) /*!< Channel 28 has its secure attribute set */
13360 
13361 /* Bit 27 : Select secure attribute */
13362 #define SPU_DPPI_PERM_CHANNEL27_Pos (27UL) /*!< Position of CHANNEL27 field. */
13363 #define SPU_DPPI_PERM_CHANNEL27_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL27_Pos) /*!< Bit mask of CHANNEL27 field. */
13364 #define SPU_DPPI_PERM_CHANNEL27_NonSecure (0UL) /*!< Channel 27 has its non-secure attribute set */
13365 #define SPU_DPPI_PERM_CHANNEL27_Secure (1UL) /*!< Channel 27 has its secure attribute set */
13366 
13367 /* Bit 26 : Select secure attribute */
13368 #define SPU_DPPI_PERM_CHANNEL26_Pos (26UL) /*!< Position of CHANNEL26 field. */
13369 #define SPU_DPPI_PERM_CHANNEL26_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL26_Pos) /*!< Bit mask of CHANNEL26 field. */
13370 #define SPU_DPPI_PERM_CHANNEL26_NonSecure (0UL) /*!< Channel 26 has its non-secure attribute set */
13371 #define SPU_DPPI_PERM_CHANNEL26_Secure (1UL) /*!< Channel 26 has its secure attribute set */
13372 
13373 /* Bit 25 : Select secure attribute */
13374 #define SPU_DPPI_PERM_CHANNEL25_Pos (25UL) /*!< Position of CHANNEL25 field. */
13375 #define SPU_DPPI_PERM_CHANNEL25_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL25_Pos) /*!< Bit mask of CHANNEL25 field. */
13376 #define SPU_DPPI_PERM_CHANNEL25_NonSecure (0UL) /*!< Channel 25 has its non-secure attribute set */
13377 #define SPU_DPPI_PERM_CHANNEL25_Secure (1UL) /*!< Channel 25 has its secure attribute set */
13378 
13379 /* Bit 24 : Select secure attribute */
13380 #define SPU_DPPI_PERM_CHANNEL24_Pos (24UL) /*!< Position of CHANNEL24 field. */
13381 #define SPU_DPPI_PERM_CHANNEL24_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL24_Pos) /*!< Bit mask of CHANNEL24 field. */
13382 #define SPU_DPPI_PERM_CHANNEL24_NonSecure (0UL) /*!< Channel 24 has its non-secure attribute set */
13383 #define SPU_DPPI_PERM_CHANNEL24_Secure (1UL) /*!< Channel 24 has its secure attribute set */
13384 
13385 /* Bit 23 : Select secure attribute */
13386 #define SPU_DPPI_PERM_CHANNEL23_Pos (23UL) /*!< Position of CHANNEL23 field. */
13387 #define SPU_DPPI_PERM_CHANNEL23_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL23_Pos) /*!< Bit mask of CHANNEL23 field. */
13388 #define SPU_DPPI_PERM_CHANNEL23_NonSecure (0UL) /*!< Channel 23 has its non-secure attribute set */
13389 #define SPU_DPPI_PERM_CHANNEL23_Secure (1UL) /*!< Channel 23 has its secure attribute set */
13390 
13391 /* Bit 22 : Select secure attribute */
13392 #define SPU_DPPI_PERM_CHANNEL22_Pos (22UL) /*!< Position of CHANNEL22 field. */
13393 #define SPU_DPPI_PERM_CHANNEL22_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL22_Pos) /*!< Bit mask of CHANNEL22 field. */
13394 #define SPU_DPPI_PERM_CHANNEL22_NonSecure (0UL) /*!< Channel 22 has its non-secure attribute set */
13395 #define SPU_DPPI_PERM_CHANNEL22_Secure (1UL) /*!< Channel 22 has its secure attribute set */
13396 
13397 /* Bit 21 : Select secure attribute */
13398 #define SPU_DPPI_PERM_CHANNEL21_Pos (21UL) /*!< Position of CHANNEL21 field. */
13399 #define SPU_DPPI_PERM_CHANNEL21_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL21_Pos) /*!< Bit mask of CHANNEL21 field. */
13400 #define SPU_DPPI_PERM_CHANNEL21_NonSecure (0UL) /*!< Channel 21 has its non-secure attribute set */
13401 #define SPU_DPPI_PERM_CHANNEL21_Secure (1UL) /*!< Channel 21 has its secure attribute set */
13402 
13403 /* Bit 20 : Select secure attribute */
13404 #define SPU_DPPI_PERM_CHANNEL20_Pos (20UL) /*!< Position of CHANNEL20 field. */
13405 #define SPU_DPPI_PERM_CHANNEL20_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL20_Pos) /*!< Bit mask of CHANNEL20 field. */
13406 #define SPU_DPPI_PERM_CHANNEL20_NonSecure (0UL) /*!< Channel 20 has its non-secure attribute set */
13407 #define SPU_DPPI_PERM_CHANNEL20_Secure (1UL) /*!< Channel 20 has its secure attribute set */
13408 
13409 /* Bit 19 : Select secure attribute */
13410 #define SPU_DPPI_PERM_CHANNEL19_Pos (19UL) /*!< Position of CHANNEL19 field. */
13411 #define SPU_DPPI_PERM_CHANNEL19_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL19_Pos) /*!< Bit mask of CHANNEL19 field. */
13412 #define SPU_DPPI_PERM_CHANNEL19_NonSecure (0UL) /*!< Channel 19 has its non-secure attribute set */
13413 #define SPU_DPPI_PERM_CHANNEL19_Secure (1UL) /*!< Channel 19 has its secure attribute set */
13414 
13415 /* Bit 18 : Select secure attribute */
13416 #define SPU_DPPI_PERM_CHANNEL18_Pos (18UL) /*!< Position of CHANNEL18 field. */
13417 #define SPU_DPPI_PERM_CHANNEL18_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL18_Pos) /*!< Bit mask of CHANNEL18 field. */
13418 #define SPU_DPPI_PERM_CHANNEL18_NonSecure (0UL) /*!< Channel 18 has its non-secure attribute set */
13419 #define SPU_DPPI_PERM_CHANNEL18_Secure (1UL) /*!< Channel 18 has its secure attribute set */
13420 
13421 /* Bit 17 : Select secure attribute */
13422 #define SPU_DPPI_PERM_CHANNEL17_Pos (17UL) /*!< Position of CHANNEL17 field. */
13423 #define SPU_DPPI_PERM_CHANNEL17_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL17_Pos) /*!< Bit mask of CHANNEL17 field. */
13424 #define SPU_DPPI_PERM_CHANNEL17_NonSecure (0UL) /*!< Channel 17 has its non-secure attribute set */
13425 #define SPU_DPPI_PERM_CHANNEL17_Secure (1UL) /*!< Channel 17 has its secure attribute set */
13426 
13427 /* Bit 16 : Select secure attribute */
13428 #define SPU_DPPI_PERM_CHANNEL16_Pos (16UL) /*!< Position of CHANNEL16 field. */
13429 #define SPU_DPPI_PERM_CHANNEL16_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL16_Pos) /*!< Bit mask of CHANNEL16 field. */
13430 #define SPU_DPPI_PERM_CHANNEL16_NonSecure (0UL) /*!< Channel 16 has its non-secure attribute set */
13431 #define SPU_DPPI_PERM_CHANNEL16_Secure (1UL) /*!< Channel 16 has its secure attribute set */
13432 
13433 /* Bit 15 : Select secure attribute */
13434 #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */
13435 #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */
13436 #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel 15 has its non-secure attribute set */
13437 #define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel 15 has its secure attribute set */
13438 
13439 /* Bit 14 : Select secure attribute */
13440 #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */
13441 #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */
13442 #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel 14 has its non-secure attribute set */
13443 #define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel 14 has its secure attribute set */
13444 
13445 /* Bit 13 : Select secure attribute */
13446 #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */
13447 #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */
13448 #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel 13 has its non-secure attribute set */
13449 #define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel 13 has its secure attribute set */
13450 
13451 /* Bit 12 : Select secure attribute */
13452 #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */
13453 #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */
13454 #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel 12 has its non-secure attribute set */
13455 #define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel 12 has its secure attribute set */
13456 
13457 /* Bit 11 : Select secure attribute */
13458 #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */
13459 #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */
13460 #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel 11 has its non-secure attribute set */
13461 #define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel 11 has its secure attribute set */
13462 
13463 /* Bit 10 : Select secure attribute */
13464 #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */
13465 #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */
13466 #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel 10 has its non-secure attribute set */
13467 #define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel 10 has its secure attribute set */
13468 
13469 /* Bit 9 : Select secure attribute */
13470 #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */
13471 #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */
13472 #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel 9 has its non-secure attribute set */
13473 #define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel 9 has its secure attribute set */
13474 
13475 /* Bit 8 : Select secure attribute */
13476 #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */
13477 #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */
13478 #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel 8 has its non-secure attribute set */
13479 #define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel 8 has its secure attribute set */
13480 
13481 /* Bit 7 : Select secure attribute */
13482 #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */
13483 #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */
13484 #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel 7 has its non-secure attribute set */
13485 #define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel 7 has its secure attribute set */
13486 
13487 /* Bit 6 : Select secure attribute */
13488 #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */
13489 #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */
13490 #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel 6 has its non-secure attribute set */
13491 #define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel 6 has its secure attribute set */
13492 
13493 /* Bit 5 : Select secure attribute */
13494 #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */
13495 #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */
13496 #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel 5 has its non-secure attribute set */
13497 #define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel 5 has its secure attribute set */
13498 
13499 /* Bit 4 : Select secure attribute */
13500 #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */
13501 #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */
13502 #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel 4 has its non-secure attribute set */
13503 #define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel 4 has its secure attribute set */
13504 
13505 /* Bit 3 : Select secure attribute */
13506 #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */
13507 #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */
13508 #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel 3 has its non-secure attribute set */
13509 #define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel 3 has its secure attribute set */
13510 
13511 /* Bit 2 : Select secure attribute */
13512 #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */
13513 #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */
13514 #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel 2 has its non-secure attribute set */
13515 #define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel 2 has its secure attribute set */
13516 
13517 /* Bit 1 : Select secure attribute */
13518 #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */
13519 #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */
13520 #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel 1 has its non-secure attribute set */
13521 #define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel 1 has its secure attribute set */
13522 
13523 /* Bit 0 : Select secure attribute */
13524 #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */
13525 #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */
13526 #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel 0 has its non-secure attribute set */
13527 #define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel 0 has its secure attribute set */
13528 
13529 /* Register: SPU_DPPI_LOCK */
13530 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */
13531 
13532 /* Bit 0 :   */
13533 #define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
13534 #define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
13535 #define SPU_DPPI_LOCK_LOCK_Unlocked (0UL) /*!< DPPI[n].PERM register content can be changed */
13536 #define SPU_DPPI_LOCK_LOCK_Locked (1UL) /*!< DPPI[n].PERM register can't be changed until next reset */
13537 
13538 /* Register: SPU_GPIOPORT_PERM */
13539 /* Description: Description cluster: Select between secure and non-secure attribute  for pins 0 to 31  of port n */
13540 
13541 /* Bit 31 : Select secure attribute attribute for PIN 31. */
13542 #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
13543 #define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */
13544 #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL) /*!< Pin 31 has its non-secure attribute set */
13545 #define SPU_GPIOPORT_PERM_PIN31_Secure (1UL) /*!< Pin 31 has its secure attribute set */
13546 
13547 /* Bit 30 : Select secure attribute attribute for PIN 30. */
13548 #define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
13549 #define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */
13550 #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL) /*!< Pin 30 has its non-secure attribute set */
13551 #define SPU_GPIOPORT_PERM_PIN30_Secure (1UL) /*!< Pin 30 has its secure attribute set */
13552 
13553 /* Bit 29 : Select secure attribute attribute for PIN 29. */
13554 #define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
13555 #define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */
13556 #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL) /*!< Pin 29 has its non-secure attribute set */
13557 #define SPU_GPIOPORT_PERM_PIN29_Secure (1UL) /*!< Pin 29 has its secure attribute set */
13558 
13559 /* Bit 28 : Select secure attribute attribute for PIN 28. */
13560 #define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
13561 #define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */
13562 #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL) /*!< Pin 28 has its non-secure attribute set */
13563 #define SPU_GPIOPORT_PERM_PIN28_Secure (1UL) /*!< Pin 28 has its secure attribute set */
13564 
13565 /* Bit 27 : Select secure attribute attribute for PIN 27. */
13566 #define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
13567 #define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */
13568 #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL) /*!< Pin 27 has its non-secure attribute set */
13569 #define SPU_GPIOPORT_PERM_PIN27_Secure (1UL) /*!< Pin 27 has its secure attribute set */
13570 
13571 /* Bit 26 : Select secure attribute attribute for PIN 26. */
13572 #define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
13573 #define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */
13574 #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL) /*!< Pin 26 has its non-secure attribute set */
13575 #define SPU_GPIOPORT_PERM_PIN26_Secure (1UL) /*!< Pin 26 has its secure attribute set */
13576 
13577 /* Bit 25 : Select secure attribute attribute for PIN 25. */
13578 #define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
13579 #define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */
13580 #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL) /*!< Pin 25 has its non-secure attribute set */
13581 #define SPU_GPIOPORT_PERM_PIN25_Secure (1UL) /*!< Pin 25 has its secure attribute set */
13582 
13583 /* Bit 24 : Select secure attribute attribute for PIN 24. */
13584 #define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
13585 #define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */
13586 #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL) /*!< Pin 24 has its non-secure attribute set */
13587 #define SPU_GPIOPORT_PERM_PIN24_Secure (1UL) /*!< Pin 24 has its secure attribute set */
13588 
13589 /* Bit 23 : Select secure attribute attribute for PIN 23. */
13590 #define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
13591 #define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */
13592 #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL) /*!< Pin 23 has its non-secure attribute set */
13593 #define SPU_GPIOPORT_PERM_PIN23_Secure (1UL) /*!< Pin 23 has its secure attribute set */
13594 
13595 /* Bit 22 : Select secure attribute attribute for PIN 22. */
13596 #define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
13597 #define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */
13598 #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL) /*!< Pin 22 has its non-secure attribute set */
13599 #define SPU_GPIOPORT_PERM_PIN22_Secure (1UL) /*!< Pin 22 has its secure attribute set */
13600 
13601 /* Bit 21 : Select secure attribute attribute for PIN 21. */
13602 #define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
13603 #define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */
13604 #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL) /*!< Pin 21 has its non-secure attribute set */
13605 #define SPU_GPIOPORT_PERM_PIN21_Secure (1UL) /*!< Pin 21 has its secure attribute set */
13606 
13607 /* Bit 20 : Select secure attribute attribute for PIN 20. */
13608 #define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
13609 #define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */
13610 #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL) /*!< Pin 20 has its non-secure attribute set */
13611 #define SPU_GPIOPORT_PERM_PIN20_Secure (1UL) /*!< Pin 20 has its secure attribute set */
13612 
13613 /* Bit 19 : Select secure attribute attribute for PIN 19. */
13614 #define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
13615 #define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */
13616 #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL) /*!< Pin 19 has its non-secure attribute set */
13617 #define SPU_GPIOPORT_PERM_PIN19_Secure (1UL) /*!< Pin 19 has its secure attribute set */
13618 
13619 /* Bit 18 : Select secure attribute attribute for PIN 18. */
13620 #define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
13621 #define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */
13622 #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL) /*!< Pin 18 has its non-secure attribute set */
13623 #define SPU_GPIOPORT_PERM_PIN18_Secure (1UL) /*!< Pin 18 has its secure attribute set */
13624 
13625 /* Bit 17 : Select secure attribute attribute for PIN 17. */
13626 #define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
13627 #define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */
13628 #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL) /*!< Pin 17 has its non-secure attribute set */
13629 #define SPU_GPIOPORT_PERM_PIN17_Secure (1UL) /*!< Pin 17 has its secure attribute set */
13630 
13631 /* Bit 16 : Select secure attribute attribute for PIN 16. */
13632 #define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
13633 #define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */
13634 #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL) /*!< Pin 16 has its non-secure attribute set */
13635 #define SPU_GPIOPORT_PERM_PIN16_Secure (1UL) /*!< Pin 16 has its secure attribute set */
13636 
13637 /* Bit 15 : Select secure attribute attribute for PIN 15. */
13638 #define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
13639 #define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */
13640 #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL) /*!< Pin 15 has its non-secure attribute set */
13641 #define SPU_GPIOPORT_PERM_PIN15_Secure (1UL) /*!< Pin 15 has its secure attribute set */
13642 
13643 /* Bit 14 : Select secure attribute attribute for PIN 14. */
13644 #define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
13645 #define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */
13646 #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL) /*!< Pin 14 has its non-secure attribute set */
13647 #define SPU_GPIOPORT_PERM_PIN14_Secure (1UL) /*!< Pin 14 has its secure attribute set */
13648 
13649 /* Bit 13 : Select secure attribute attribute for PIN 13. */
13650 #define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
13651 #define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */
13652 #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL) /*!< Pin 13 has its non-secure attribute set */
13653 #define SPU_GPIOPORT_PERM_PIN13_Secure (1UL) /*!< Pin 13 has its secure attribute set */
13654 
13655 /* Bit 12 : Select secure attribute attribute for PIN 12. */
13656 #define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
13657 #define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */
13658 #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL) /*!< Pin 12 has its non-secure attribute set */
13659 #define SPU_GPIOPORT_PERM_PIN12_Secure (1UL) /*!< Pin 12 has its secure attribute set */
13660 
13661 /* Bit 11 : Select secure attribute attribute for PIN 11. */
13662 #define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
13663 #define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */
13664 #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL) /*!< Pin 11 has its non-secure attribute set */
13665 #define SPU_GPIOPORT_PERM_PIN11_Secure (1UL) /*!< Pin 11 has its secure attribute set */
13666 
13667 /* Bit 10 : Select secure attribute attribute for PIN 10. */
13668 #define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
13669 #define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */
13670 #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL) /*!< Pin 10 has its non-secure attribute set */
13671 #define SPU_GPIOPORT_PERM_PIN10_Secure (1UL) /*!< Pin 10 has its secure attribute set */
13672 
13673 /* Bit 9 : Select secure attribute attribute for PIN 9. */
13674 #define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
13675 #define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */
13676 #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL) /*!< Pin 9 has its non-secure attribute set */
13677 #define SPU_GPIOPORT_PERM_PIN9_Secure (1UL) /*!< Pin 9 has its secure attribute set */
13678 
13679 /* Bit 8 : Select secure attribute attribute for PIN 8. */
13680 #define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
13681 #define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */
13682 #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL) /*!< Pin 8 has its non-secure attribute set */
13683 #define SPU_GPIOPORT_PERM_PIN8_Secure (1UL) /*!< Pin 8 has its secure attribute set */
13684 
13685 /* Bit 7 : Select secure attribute attribute for PIN 7. */
13686 #define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
13687 #define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */
13688 #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL) /*!< Pin 7 has its non-secure attribute set */
13689 #define SPU_GPIOPORT_PERM_PIN7_Secure (1UL) /*!< Pin 7 has its secure attribute set */
13690 
13691 /* Bit 6 : Select secure attribute attribute for PIN 6. */
13692 #define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
13693 #define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */
13694 #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL) /*!< Pin 6 has its non-secure attribute set */
13695 #define SPU_GPIOPORT_PERM_PIN6_Secure (1UL) /*!< Pin 6 has its secure attribute set */
13696 
13697 /* Bit 5 : Select secure attribute attribute for PIN 5. */
13698 #define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
13699 #define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */
13700 #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL) /*!< Pin 5 has its non-secure attribute set */
13701 #define SPU_GPIOPORT_PERM_PIN5_Secure (1UL) /*!< Pin 5 has its secure attribute set */
13702 
13703 /* Bit 4 : Select secure attribute attribute for PIN 4. */
13704 #define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
13705 #define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */
13706 #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL) /*!< Pin 4 has its non-secure attribute set */
13707 #define SPU_GPIOPORT_PERM_PIN4_Secure (1UL) /*!< Pin 4 has its secure attribute set */
13708 
13709 /* Bit 3 : Select secure attribute attribute for PIN 3. */
13710 #define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
13711 #define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */
13712 #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL) /*!< Pin 3 has its non-secure attribute set */
13713 #define SPU_GPIOPORT_PERM_PIN3_Secure (1UL) /*!< Pin 3 has its secure attribute set */
13714 
13715 /* Bit 2 : Select secure attribute attribute for PIN 2. */
13716 #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
13717 #define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */
13718 #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */
13719 #define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */
13720 
13721 /* Bit 1 : Select secure attribute attribute for PIN 1. */
13722 #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
13723 #define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */
13724 #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */
13725 #define SPU_GPIOPORT_PERM_PIN1_Secure (1UL) /*!< Pin 1 has its secure attribute set */
13726 
13727 /* Bit 0 : Select secure attribute attribute for PIN 0. */
13728 #define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
13729 #define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */
13730 #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL) /*!< Pin 0 has its non-secure attribute set */
13731 #define SPU_GPIOPORT_PERM_PIN0_Secure (1UL) /*!< Pin 0 has its secure attribute set */
13732 
13733 /* Register: SPU_GPIOPORT_LOCK */
13734 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */
13735 
13736 /* Bit 0 :   */
13737 #define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
13738 #define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
13739 #define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0UL) /*!< GPIOPORT[n].PERM register content can be changed */
13740 #define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */
13741 
13742 /* Register: SPU_FLASHNSC_REGION */
13743 /* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */
13744 
13745 /* Bit 8 :   */
13746 #define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
13747 #define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
13748 #define SPU_FLASHNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */
13749 #define SPU_FLASHNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
13750 
13751 /* Bits 5..0 : Region number */
13752 #define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
13753 #define SPU_FLASHNSC_REGION_REGION_Msk (0x3FUL << SPU_FLASHNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
13754 
13755 /* Register: SPU_FLASHNSC_SIZE */
13756 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
13757 
13758 /* Bit 8 :   */
13759 #define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
13760 #define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
13761 #define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */
13762 #define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
13763 
13764 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
13765 #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
13766 #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
13767 #define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
13768 #define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with size 32 bytes */
13769 #define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with size 64 bytes */
13770 #define SPU_FLASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with size 128 bytes */
13771 #define SPU_FLASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with size 256 bytes */
13772 #define SPU_FLASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with size 512 bytes */
13773 #define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with size 1024 bytes */
13774 #define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with size 2048 bytes */
13775 #define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with size 4096 bytes */
13776 
13777 /* Register: SPU_RAMNSC_REGION */
13778 /* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */
13779 
13780 /* Bit 8 :   */
13781 #define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
13782 #define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
13783 #define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */
13784 #define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
13785 
13786 /* Bits 5..0 : Region number */
13787 #define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
13788 #define SPU_RAMNSC_REGION_REGION_Msk (0x3FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
13789 
13790 /* Register: SPU_RAMNSC_SIZE */
13791 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
13792 
13793 /* Bit 8 :   */
13794 #define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
13795 #define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
13796 #define SPU_RAMNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */
13797 #define SPU_RAMNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
13798 
13799 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
13800 #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
13801 #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
13802 #define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
13803 #define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with size 32 bytes */
13804 #define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with size 64 bytes */
13805 #define SPU_RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with size 128 bytes */
13806 #define SPU_RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with size 256 bytes */
13807 #define SPU_RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with size 512 bytes */
13808 #define SPU_RAMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with size 1024 bytes */
13809 #define SPU_RAMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with size 2048 bytes */
13810 #define SPU_RAMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with size 4096 bytes */
13811 
13812 /* Register: SPU_FLASHREGION_PERM */
13813 /* Description: Description cluster: Access permissions for flash region n */
13814 
13815 /* Bit 8 :   */
13816 #define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
13817 #define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
13818 #define SPU_FLASHREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
13819 #define SPU_FLASHREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
13820 
13821 /* Bit 4 : Security attribute for flash region n */
13822 #define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
13823 #define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
13824 #define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0UL) /*!< Flash region n security attribute is non-secure */
13825 #define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL) /*!< Flash region n security attribute is secure */
13826 
13827 /* Bit 2 : Configure read permissions for flash region n */
13828 #define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
13829 #define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
13830 #define SPU_FLASHREGION_PERM_READ_Disable (0UL) /*!< Block read operation from flash region n */
13831 #define SPU_FLASHREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from flash region n */
13832 
13833 /* Bit 1 : Configure write permission for flash region n */
13834 #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
13835 #define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
13836 #define SPU_FLASHREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to region n */
13837 #define SPU_FLASHREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to region n */
13838 
13839 /* Bit 0 : Configure instruction fetch permissions from flash region n */
13840 #define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
13841 #define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
13842 #define SPU_FLASHREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from flash region n */
13843 #define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from flash region n */
13844 
13845 /* Register: SPU_RAMREGION_PERM */
13846 /* Description: Description cluster: Access permissions for RAM region n */
13847 
13848 /* Bit 8 :   */
13849 #define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
13850 #define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
13851 #define SPU_RAMREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
13852 #define SPU_RAMREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
13853 
13854 /* Bit 4 : Security attribute for RAM region n */
13855 #define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
13856 #define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
13857 #define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL) /*!< RAM region n security attribute is non-secure */
13858 #define SPU_RAMREGION_PERM_SECATTR_Secure (1UL) /*!< RAM region n security attribute is secure */
13859 
13860 /* Bit 2 : Configure read permissions for RAM region n */
13861 #define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
13862 #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
13863 #define SPU_RAMREGION_PERM_READ_Disable (0UL) /*!< Block read operation from RAM region n */
13864 #define SPU_RAMREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from RAM region n */
13865 
13866 /* Bit 1 : Configure write permission for RAM region n */
13867 #define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
13868 #define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
13869 #define SPU_RAMREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to RAM region n */
13870 #define SPU_RAMREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to RAM region n */
13871 
13872 /* Bit 0 : Configure instruction fetch permissions from RAM region n */
13873 #define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
13874 #define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
13875 #define SPU_RAMREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from RAM region n */
13876 #define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from RAM region n */
13877 
13878 /* Register: SPU_PERIPHID_PERM */
13879 /* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */
13880 
13881 /* Bit 31 : Indicate if a peripheral is present with ID n */
13882 #define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */
13883 #define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
13884 #define SPU_PERIPHID_PERM_PRESENT_NotPresent (0UL) /*!< Peripheral is not present */
13885 #define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL) /*!< Peripheral is present */
13886 
13887 /* Bit 8 :   */
13888 #define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
13889 #define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
13890 #define SPU_PERIPHID_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
13891 #define SPU_PERIPHID_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
13892 
13893 /* Bit 5 : Security attribution for the DMA transfer */
13894 #define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */
13895 #define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */
13896 #define SPU_PERIPHID_PERM_DMASEC_NonSecure (0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */
13897 #define SPU_PERIPHID_PERM_DMASEC_Secure (1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */
13898 
13899 /* Bit 4 : Peripheral security mapping */
13900 #define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
13901 #define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
13902 #define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */
13903 #define SPU_PERIPHID_PERM_SECATTR_Secure (1UL) /*!< Peripheral is mapped in secure peripheral address space */
13904 
13905 /* Bits 3..2 : Indicates if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */
13906 #define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */
13907 #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */
13908 #define SPU_PERIPHID_PERM_DMA_NoDMA (0UL) /*!< Peripheral has no DMA capability */
13909 #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */
13910 #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */
13911 
13912 /* Bits 1..0 : Define configuration capabilities for Arm TrustZone Cortex-M secure attribute */
13913 #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
13914 #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
13915 #define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL) /*!< This peripheral is always accessible as a non-secure peripheral */
13916 #define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL) /*!< This peripheral is always accessible as a secure peripheral */
13917 #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */
13918 #define SPU_PERIPHID_PERM_SECUREMAPPING_Split (3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */
13919 
13920 
13921 /* Peripheral: TAD */
13922 /* Description: Trace and debug control */
13923 
13924 /* Register: TAD_CLOCKSTART */
13925 /* Description: Start all trace and debug clocks. */
13926 
13927 /* Bit 0 :   */
13928 #define TAD_CLOCKSTART_START_Pos (0UL) /*!< Position of START field. */
13929 #define TAD_CLOCKSTART_START_Msk (0x1UL << TAD_CLOCKSTART_START_Pos) /*!< Bit mask of START field. */
13930 #define TAD_CLOCKSTART_START_Start (1UL) /*!< Start all trace and debug clocks. */
13931 
13932 /* Register: TAD_CLOCKSTOP */
13933 /* Description: Stop all trace and debug clocks. */
13934 
13935 /* Bit 0 :   */
13936 #define TAD_CLOCKSTOP_STOP_Pos (0UL) /*!< Position of STOP field. */
13937 #define TAD_CLOCKSTOP_STOP_Msk (0x1UL << TAD_CLOCKSTOP_STOP_Pos) /*!< Bit mask of STOP field. */
13938 #define TAD_CLOCKSTOP_STOP_Stop (1UL) /*!< Stop all trace and debug clocks. */
13939 
13940 /* Register: TAD_ENABLE */
13941 /* Description: Enable debug domain and aquire selected GPIOs */
13942 
13943 /* Bit 0 :   */
13944 #define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13945 #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13946 #define TAD_ENABLE_ENABLE_DISABLED (0UL) /*!< Disable debug domain and release selected GPIOs */
13947 #define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */
13948 
13949 /* Register: TAD_PSEL_TRACECLK */
13950 /* Description: Pin configuration for TRACECLK */
13951 
13952 /* Bit 31 : Connection */
13953 #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13954 #define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13955 #define TAD_PSEL_TRACECLK_CONNECT_Connected (0UL) /*!< Connect */
13956 #define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
13957 
13958 /* Bits 4..0 : Pin number */
13959 #define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */
13960 #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */
13961 #define TAD_PSEL_TRACECLK_PIN_Traceclk (12UL) /*!< TRACECLK pin */
13962 
13963 /* Register: TAD_PSEL_TRACEDATA0 */
13964 /* Description: Pin configuration for TRACEDATA[0] */
13965 
13966 /* Bit 31 : Connection */
13967 #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13968 #define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13969 #define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0UL) /*!< Connect */
13970 #define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL) /*!< Disconnect */
13971 
13972 /* Bits 4..0 : Pin number */
13973 #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */
13974 #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */
13975 #define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (11UL) /*!< TRACEDATA0 pin */
13976 
13977 /* Register: TAD_PSEL_TRACEDATA1 */
13978 /* Description: Pin configuration for TRACEDATA[1] */
13979 
13980 /* Bit 31 : Connection */
13981 #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13982 #define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13983 #define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0UL) /*!< Connect */
13984 #define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL) /*!< Disconnect */
13985 
13986 /* Bits 4..0 : Pin number */
13987 #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */
13988 #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */
13989 #define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (10UL) /*!< TRACEDATA1 pin */
13990 
13991 /* Register: TAD_PSEL_TRACEDATA2 */
13992 /* Description: Pin configuration for TRACEDATA[2] */
13993 
13994 /* Bit 31 : Connection */
13995 #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13996 #define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13997 #define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0UL) /*!< Connect */
13998 #define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL) /*!< Disconnect */
13999 
14000 /* Bits 4..0 : Pin number */
14001 #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */
14002 #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */
14003 #define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (9UL) /*!< TRACEDATA2 pin */
14004 
14005 /* Register: TAD_PSEL_TRACEDATA3 */
14006 /* Description: Pin configuration for TRACEDATA[3] */
14007 
14008 /* Bit 31 : Connection */
14009 #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14010 #define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14011 #define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0UL) /*!< Connect */
14012 #define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL) /*!< Disconnect */
14013 
14014 /* Bits 4..0 : Pin number */
14015 #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */
14016 #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */
14017 #define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (8UL) /*!< TRACEDATA3 pin */
14018 
14019 /* Register: TAD_TRACEPORTSPEED */
14020 /* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */
14021 
14022 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */
14023 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
14024 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
14025 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_64MHz (0UL) /*!< Trace Port clock is: 64MHz */
14026 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (1UL) /*!< Trace Port clock is: 32MHz */
14027 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (2UL) /*!< Trace Port clock is: 16MHz */
14028 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (3UL) /*!< Trace Port clock is: 8MHz */
14029 
14030 
14031 /* Peripheral: TIMER */
14032 /* Description: Timer/Counter 0 */
14033 
14034 /* Register: TIMER_TASKS_START */
14035 /* Description: Start Timer */
14036 
14037 /* Bit 0 : Start Timer */
14038 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
14039 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
14040 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
14041 
14042 /* Register: TIMER_TASKS_STOP */
14043 /* Description: Stop Timer */
14044 
14045 /* Bit 0 : Stop Timer */
14046 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
14047 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
14048 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
14049 
14050 /* Register: TIMER_TASKS_COUNT */
14051 /* Description: Increment Timer (Counter mode only) */
14052 
14053 /* Bit 0 : Increment Timer (Counter mode only) */
14054 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
14055 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
14056 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
14057 
14058 /* Register: TIMER_TASKS_CLEAR */
14059 /* Description: Clear time */
14060 
14061 /* Bit 0 : Clear time */
14062 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
14063 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
14064 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
14065 
14066 /* Register: TIMER_TASKS_SHUTDOWN */
14067 /* Description: Deprecated register - Shut down timer */
14068 
14069 /* Bit 0 : Deprecated field -  Shut down timer */
14070 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
14071 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
14072 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
14073 
14074 /* Register: TIMER_TASKS_CAPTURE */
14075 /* Description: Description collection: Capture Timer value to CC[n] register */
14076 
14077 /* Bit 0 : Capture Timer value to CC[n] register */
14078 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
14079 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
14080 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
14081 
14082 /* Register: TIMER_SUBSCRIBE_START */
14083 /* Description: Subscribe configuration for task START */
14084 
14085 /* Bit 31 :   */
14086 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
14087 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
14088 #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
14089 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
14090 
14091 /* Bits 7..0 : DPPI channel that task START will subscribe to */
14092 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14093 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14094 
14095 /* Register: TIMER_SUBSCRIBE_STOP */
14096 /* Description: Subscribe configuration for task STOP */
14097 
14098 /* Bit 31 :   */
14099 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
14100 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
14101 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
14102 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
14103 
14104 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
14105 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14106 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14107 
14108 /* Register: TIMER_SUBSCRIBE_COUNT */
14109 /* Description: Subscribe configuration for task COUNT */
14110 
14111 /* Bit 31 :   */
14112 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */
14113 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */
14114 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */
14115 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */
14116 
14117 /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */
14118 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14119 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14120 
14121 /* Register: TIMER_SUBSCRIBE_CLEAR */
14122 /* Description: Subscribe configuration for task CLEAR */
14123 
14124 /* Bit 31 :   */
14125 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
14126 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
14127 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
14128 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
14129 
14130 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
14131 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14132 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14133 
14134 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */
14135 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */
14136 
14137 /* Bit 31 :   */
14138 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */
14139 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */
14140 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */
14141 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */
14142 
14143 /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */
14144 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14145 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14146 
14147 /* Register: TIMER_SUBSCRIBE_CAPTURE */
14148 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
14149 
14150 /* Bit 31 :   */
14151 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
14152 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
14153 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
14154 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
14155 
14156 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
14157 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14158 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14159 
14160 /* Register: TIMER_EVENTS_COMPARE */
14161 /* Description: Description collection: Compare event on CC[n] match */
14162 
14163 /* Bit 0 : Compare event on CC[n] match */
14164 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
14165 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
14166 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
14167 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
14168 
14169 /* Register: TIMER_PUBLISH_COMPARE */
14170 /* Description: Description collection: Publish configuration for event COMPARE[n] */
14171 
14172 /* Bit 31 :   */
14173 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
14174 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
14175 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
14176 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
14177 
14178 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */
14179 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14180 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14181 
14182 /* Register: TIMER_SHORTS */
14183 /* Description: Shortcuts between local events and tasks */
14184 
14185 /* Bit 21 : Shortcut between event COMPARE[5] and task STOP */
14186 #define TIMER_SHORTS_COMPARE5_STOP_Pos (21UL) /*!< Position of COMPARE5_STOP field. */
14187 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
14188 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
14189 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
14190 
14191 /* Bit 20 : Shortcut between event COMPARE[4] and task STOP */
14192 #define TIMER_SHORTS_COMPARE4_STOP_Pos (20UL) /*!< Position of COMPARE4_STOP field. */
14193 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
14194 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
14195 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
14196 
14197 /* Bit 19 : Shortcut between event COMPARE[3] and task STOP */
14198 #define TIMER_SHORTS_COMPARE3_STOP_Pos (19UL) /*!< Position of COMPARE3_STOP field. */
14199 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
14200 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
14201 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
14202 
14203 /* Bit 18 : Shortcut between event COMPARE[2] and task STOP */
14204 #define TIMER_SHORTS_COMPARE2_STOP_Pos (18UL) /*!< Position of COMPARE2_STOP field. */
14205 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
14206 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
14207 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
14208 
14209 /* Bit 17 : Shortcut between event COMPARE[1] and task STOP */
14210 #define TIMER_SHORTS_COMPARE1_STOP_Pos (17UL) /*!< Position of COMPARE1_STOP field. */
14211 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
14212 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
14213 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
14214 
14215 /* Bit 16 : Shortcut between event COMPARE[0] and task STOP */
14216 #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL) /*!< Position of COMPARE0_STOP field. */
14217 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
14218 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
14219 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
14220 
14221 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
14222 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
14223 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
14224 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
14225 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
14226 
14227 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
14228 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
14229 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
14230 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
14231 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
14232 
14233 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
14234 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
14235 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
14236 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
14237 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
14238 
14239 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
14240 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
14241 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
14242 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
14243 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
14244 
14245 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
14246 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
14247 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
14248 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
14249 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
14250 
14251 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
14252 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
14253 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
14254 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
14255 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
14256 
14257 /* Register: TIMER_INTEN */
14258 /* Description: Enable or disable interrupt */
14259 
14260 /* Bit 21 : Enable or disable interrupt for event COMPARE[5] */
14261 #define TIMER_INTEN_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
14262 #define TIMER_INTEN_COMPARE5_Msk (0x1UL << TIMER_INTEN_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
14263 #define TIMER_INTEN_COMPARE5_Disabled (0UL) /*!< Disable */
14264 #define TIMER_INTEN_COMPARE5_Enabled (1UL) /*!< Enable */
14265 
14266 /* Bit 20 : Enable or disable interrupt for event COMPARE[4] */
14267 #define TIMER_INTEN_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
14268 #define TIMER_INTEN_COMPARE4_Msk (0x1UL << TIMER_INTEN_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
14269 #define TIMER_INTEN_COMPARE4_Disabled (0UL) /*!< Disable */
14270 #define TIMER_INTEN_COMPARE4_Enabled (1UL) /*!< Enable */
14271 
14272 /* Bit 19 : Enable or disable interrupt for event COMPARE[3] */
14273 #define TIMER_INTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
14274 #define TIMER_INTEN_COMPARE3_Msk (0x1UL << TIMER_INTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
14275 #define TIMER_INTEN_COMPARE3_Disabled (0UL) /*!< Disable */
14276 #define TIMER_INTEN_COMPARE3_Enabled (1UL) /*!< Enable */
14277 
14278 /* Bit 18 : Enable or disable interrupt for event COMPARE[2] */
14279 #define TIMER_INTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
14280 #define TIMER_INTEN_COMPARE2_Msk (0x1UL << TIMER_INTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
14281 #define TIMER_INTEN_COMPARE2_Disabled (0UL) /*!< Disable */
14282 #define TIMER_INTEN_COMPARE2_Enabled (1UL) /*!< Enable */
14283 
14284 /* Bit 17 : Enable or disable interrupt for event COMPARE[1] */
14285 #define TIMER_INTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
14286 #define TIMER_INTEN_COMPARE1_Msk (0x1UL << TIMER_INTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
14287 #define TIMER_INTEN_COMPARE1_Disabled (0UL) /*!< Disable */
14288 #define TIMER_INTEN_COMPARE1_Enabled (1UL) /*!< Enable */
14289 
14290 /* Bit 16 : Enable or disable interrupt for event COMPARE[0] */
14291 #define TIMER_INTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
14292 #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
14293 #define TIMER_INTEN_COMPARE0_Disabled (0UL) /*!< Disable */
14294 #define TIMER_INTEN_COMPARE0_Enabled (1UL) /*!< Enable */
14295 
14296 /* Register: TIMER_INTENSET */
14297 /* Description: Enable interrupt */
14298 
14299 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
14300 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
14301 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
14302 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
14303 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
14304 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
14305 
14306 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
14307 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
14308 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
14309 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
14310 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
14311 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
14312 
14313 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
14314 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
14315 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
14316 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
14317 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
14318 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
14319 
14320 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
14321 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
14322 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
14323 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
14324 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
14325 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
14326 
14327 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
14328 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
14329 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
14330 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
14331 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
14332 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
14333 
14334 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
14335 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
14336 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
14337 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
14338 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
14339 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
14340 
14341 /* Register: TIMER_INTENCLR */
14342 /* Description: Disable interrupt */
14343 
14344 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
14345 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
14346 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
14347 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
14348 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
14349 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
14350 
14351 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
14352 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
14353 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
14354 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
14355 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
14356 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
14357 
14358 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
14359 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
14360 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
14361 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
14362 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
14363 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
14364 
14365 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
14366 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
14367 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
14368 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
14369 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
14370 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
14371 
14372 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
14373 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
14374 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
14375 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
14376 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
14377 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
14378 
14379 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
14380 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
14381 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
14382 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
14383 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
14384 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
14385 
14386 /* Register: TIMER_MODE */
14387 /* Description: Timer mode selection */
14388 
14389 /* Bits 1..0 : Timer mode */
14390 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
14391 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
14392 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
14393 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
14394 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
14395 
14396 /* Register: TIMER_BITMODE */
14397 /* Description: Configure the number of bits used by the TIMER */
14398 
14399 /* Bits 1..0 : Timer bit width */
14400 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
14401 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
14402 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
14403 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
14404 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
14405 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
14406 
14407 /* Register: TIMER_PRESCALER */
14408 /* Description: Timer prescaler register */
14409 
14410 /* Bits 3..0 : Prescaler value */
14411 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
14412 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
14413 
14414 /* Register: TIMER_CC */
14415 /* Description: Description collection: Capture/Compare register n */
14416 
14417 /* Bits 31..0 : Capture/Compare value */
14418 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
14419 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
14420 
14421 /* Register: TIMER_ONESHOTEN */
14422 /* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */
14423 
14424 /* Bit 0 : Enable one-shot operation */
14425 #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */
14426 #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */
14427 #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */
14428 #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */
14429 
14430 
14431 /* Peripheral: TWIM */
14432 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
14433 
14434 /* Register: TWIM_TASKS_STARTRX */
14435 /* Description: Start TWI receive sequence */
14436 
14437 /* Bit 0 : Start TWI receive sequence */
14438 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
14439 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
14440 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
14441 
14442 /* Register: TWIM_TASKS_STARTTX */
14443 /* Description: Start TWI transmit sequence */
14444 
14445 /* Bit 0 : Start TWI transmit sequence */
14446 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
14447 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
14448 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
14449 
14450 /* Register: TWIM_TASKS_STOP */
14451 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
14452 
14453 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
14454 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
14455 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
14456 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
14457 
14458 /* Register: TWIM_TASKS_SUSPEND */
14459 /* Description: Suspend TWI transaction */
14460 
14461 /* Bit 0 : Suspend TWI transaction */
14462 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
14463 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
14464 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
14465 
14466 /* Register: TWIM_TASKS_RESUME */
14467 /* Description: Resume TWI transaction */
14468 
14469 /* Bit 0 : Resume TWI transaction */
14470 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
14471 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
14472 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
14473 
14474 /* Register: TWIM_SUBSCRIBE_STARTRX */
14475 /* Description: Subscribe configuration for task STARTRX */
14476 
14477 /* Bit 31 :   */
14478 #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
14479 #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
14480 #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
14481 #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
14482 
14483 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
14484 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14485 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14486 
14487 /* Register: TWIM_SUBSCRIBE_STARTTX */
14488 /* Description: Subscribe configuration for task STARTTX */
14489 
14490 /* Bit 31 :   */
14491 #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
14492 #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
14493 #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
14494 #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
14495 
14496 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
14497 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14498 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14499 
14500 /* Register: TWIM_SUBSCRIBE_STOP */
14501 /* Description: Subscribe configuration for task STOP */
14502 
14503 /* Bit 31 :   */
14504 #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
14505 #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
14506 #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
14507 #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
14508 
14509 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
14510 #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14511 #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14512 
14513 /* Register: TWIM_SUBSCRIBE_SUSPEND */
14514 /* Description: Subscribe configuration for task SUSPEND */
14515 
14516 /* Bit 31 :   */
14517 #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
14518 #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
14519 #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
14520 #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
14521 
14522 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
14523 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14524 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14525 
14526 /* Register: TWIM_SUBSCRIBE_RESUME */
14527 /* Description: Subscribe configuration for task RESUME */
14528 
14529 /* Bit 31 :   */
14530 #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
14531 #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
14532 #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
14533 #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
14534 
14535 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
14536 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14537 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14538 
14539 /* Register: TWIM_EVENTS_STOPPED */
14540 /* Description: TWI stopped */
14541 
14542 /* Bit 0 : TWI stopped */
14543 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
14544 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
14545 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
14546 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
14547 
14548 /* Register: TWIM_EVENTS_ERROR */
14549 /* Description: TWI error */
14550 
14551 /* Bit 0 : TWI error */
14552 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14553 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14554 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
14555 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
14556 
14557 /* Register: TWIM_EVENTS_SUSPENDED */
14558 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */
14559 
14560 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
14561 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
14562 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
14563 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
14564 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
14565 
14566 /* Register: TWIM_EVENTS_RXSTARTED */
14567 /* Description: Receive sequence started */
14568 
14569 /* Bit 0 : Receive sequence started */
14570 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
14571 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
14572 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14573 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
14574 
14575 /* Register: TWIM_EVENTS_TXSTARTED */
14576 /* Description: Transmit sequence started */
14577 
14578 /* Bit 0 : Transmit sequence started */
14579 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
14580 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
14581 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14582 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
14583 
14584 /* Register: TWIM_EVENTS_LASTRX */
14585 /* Description: Byte boundary, starting to receive the last byte */
14586 
14587 /* Bit 0 : Byte boundary, starting to receive the last byte */
14588 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
14589 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
14590 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
14591 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
14592 
14593 /* Register: TWIM_EVENTS_LASTTX */
14594 /* Description: Byte boundary, starting to transmit the last byte */
14595 
14596 /* Bit 0 : Byte boundary, starting to transmit the last byte */
14597 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
14598 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
14599 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
14600 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
14601 
14602 /* Register: TWIM_PUBLISH_STOPPED */
14603 /* Description: Publish configuration for event STOPPED */
14604 
14605 /* Bit 31 :   */
14606 #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
14607 #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
14608 #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
14609 #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
14610 
14611 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
14612 #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14613 #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14614 
14615 /* Register: TWIM_PUBLISH_ERROR */
14616 /* Description: Publish configuration for event ERROR */
14617 
14618 /* Bit 31 :   */
14619 #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
14620 #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
14621 #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
14622 #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
14623 
14624 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */
14625 #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14626 #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14627 
14628 /* Register: TWIM_PUBLISH_SUSPENDED */
14629 /* Description: Publish configuration for event SUSPENDED */
14630 
14631 /* Bit 31 :   */
14632 #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */
14633 #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */
14634 #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */
14635 #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */
14636 
14637 /* Bits 7..0 : DPPI channel that event SUSPENDED will publish to. */
14638 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14639 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14640 
14641 /* Register: TWIM_PUBLISH_RXSTARTED */
14642 /* Description: Publish configuration for event RXSTARTED */
14643 
14644 /* Bit 31 :   */
14645 #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
14646 #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
14647 #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
14648 #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
14649 
14650 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to. */
14651 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14652 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14653 
14654 /* Register: TWIM_PUBLISH_TXSTARTED */
14655 /* Description: Publish configuration for event TXSTARTED */
14656 
14657 /* Bit 31 :   */
14658 #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
14659 #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
14660 #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
14661 #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
14662 
14663 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to. */
14664 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14665 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14666 
14667 /* Register: TWIM_PUBLISH_LASTRX */
14668 /* Description: Publish configuration for event LASTRX */
14669 
14670 /* Bit 31 :   */
14671 #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */
14672 #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */
14673 #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */
14674 #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */
14675 
14676 /* Bits 7..0 : DPPI channel that event LASTRX will publish to. */
14677 #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14678 #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14679 
14680 /* Register: TWIM_PUBLISH_LASTTX */
14681 /* Description: Publish configuration for event LASTTX */
14682 
14683 /* Bit 31 :   */
14684 #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */
14685 #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */
14686 #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */
14687 #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */
14688 
14689 /* Bits 7..0 : DPPI channel that event LASTTX will publish to. */
14690 #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
14691 #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
14692 
14693 /* Register: TWIM_SHORTS */
14694 /* Description: Shortcuts between local events and tasks */
14695 
14696 /* Bit 12 : Shortcut between event LASTRX and task STOP */
14697 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
14698 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
14699 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
14700 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
14701 
14702 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
14703 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
14704 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
14705 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
14706 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
14707 
14708 /* Bit 9 : Shortcut between event LASTTX and task STOP */
14709 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
14710 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
14711 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
14712 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
14713 
14714 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
14715 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
14716 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
14717 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
14718 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
14719 
14720 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
14721 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
14722 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
14723 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
14724 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
14725 
14726 /* Register: TWIM_INTEN */
14727 /* Description: Enable or disable interrupt */
14728 
14729 /* Bit 24 : Enable or disable interrupt for event LASTTX */
14730 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
14731 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
14732 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
14733 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
14734 
14735 /* Bit 23 : Enable or disable interrupt for event LASTRX */
14736 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
14737 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
14738 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
14739 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
14740 
14741 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
14742 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14743 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14744 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
14745 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
14746 
14747 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
14748 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14749 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14750 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
14751 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
14752 
14753 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
14754 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
14755 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
14756 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
14757 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
14758 
14759 /* Bit 9 : Enable or disable interrupt for event ERROR */
14760 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14761 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
14762 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
14763 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
14764 
14765 /* Bit 1 : Enable or disable interrupt for event STOPPED */
14766 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14767 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14768 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
14769 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
14770 
14771 /* Register: TWIM_INTENSET */
14772 /* Description: Enable interrupt */
14773 
14774 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
14775 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
14776 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
14777 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
14778 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
14779 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
14780 
14781 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
14782 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
14783 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
14784 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
14785 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
14786 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
14787 
14788 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
14789 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14790 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14791 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14792 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14793 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
14794 
14795 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
14796 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14797 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14798 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14799 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14800 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
14801 
14802 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
14803 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
14804 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
14805 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
14806 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
14807 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
14808 
14809 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
14810 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14811 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
14812 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14813 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14814 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
14815 
14816 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
14817 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14818 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14819 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14820 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14821 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
14822 
14823 /* Register: TWIM_INTENCLR */
14824 /* Description: Disable interrupt */
14825 
14826 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
14827 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
14828 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
14829 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
14830 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
14831 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
14832 
14833 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
14834 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
14835 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
14836 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
14837 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
14838 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
14839 
14840 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
14841 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14842 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14843 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14844 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14845 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
14846 
14847 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
14848 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14849 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14850 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14851 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14852 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
14853 
14854 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
14855 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
14856 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
14857 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
14858 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
14859 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
14860 
14861 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
14862 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14863 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
14864 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14865 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14866 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
14867 
14868 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
14869 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
14870 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
14871 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14872 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14873 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
14874 
14875 /* Register: TWIM_ERRORSRC */
14876 /* Description: Error source */
14877 
14878 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
14879 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
14880 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
14881 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
14882 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
14883 
14884 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
14885 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
14886 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
14887 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
14888 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
14889 
14890 /* Bit 0 : Overrun error */
14891 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
14892 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
14893 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
14894 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
14895 
14896 /* Register: TWIM_ENABLE */
14897 /* Description: Enable TWIM */
14898 
14899 /* Bits 3..0 : Enable or disable TWIM */
14900 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14901 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14902 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
14903 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
14904 
14905 /* Register: TWIM_PSEL_SCL */
14906 /* Description: Pin select for SCL signal */
14907 
14908 /* Bit 31 : Connection */
14909 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14910 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14911 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
14912 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
14913 
14914 /* Bit 5 : Port number */
14915 #define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
14916 #define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
14917 
14918 /* Bits 4..0 : Pin number */
14919 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
14920 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
14921 
14922 /* Register: TWIM_PSEL_SDA */
14923 /* Description: Pin select for SDA signal */
14924 
14925 /* Bit 31 : Connection */
14926 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14927 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14928 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
14929 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
14930 
14931 /* Bit 5 : Port number */
14932 #define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
14933 #define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
14934 
14935 /* Bits 4..0 : Pin number */
14936 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
14937 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
14938 
14939 /* Register: TWIM_FREQUENCY */
14940 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
14941 
14942 /* Bits 31..0 : TWI master clock frequency */
14943 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
14944 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
14945 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
14946 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
14947 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
14948 #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL) /*!< 1000 kbps */
14949 
14950 /* Register: TWIM_RXD_PTR */
14951 /* Description: Data pointer */
14952 
14953 /* Bits 31..0 : Data pointer */
14954 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14955 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14956 
14957 /* Register: TWIM_RXD_MAXCNT */
14958 /* Description: Maximum number of bytes in receive buffer */
14959 
14960 /* Bits 15..0 : Maximum number of bytes in receive buffer */
14961 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14962 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14963 
14964 /* Register: TWIM_RXD_AMOUNT */
14965 /* Description: Number of bytes transferred in the last transaction */
14966 
14967 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
14968 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14969 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14970 
14971 /* Register: TWIM_RXD_LIST */
14972 /* Description: EasyDMA list type */
14973 
14974 /* Bits 2..0 : List type */
14975 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
14976 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
14977 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
14978 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
14979 
14980 /* Register: TWIM_TXD_PTR */
14981 /* Description: Data pointer */
14982 
14983 /* Bits 31..0 : Data pointer */
14984 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14985 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14986 
14987 /* Register: TWIM_TXD_MAXCNT */
14988 /* Description: Maximum number of bytes in transmit buffer */
14989 
14990 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
14991 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14992 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14993 
14994 /* Register: TWIM_TXD_AMOUNT */
14995 /* Description: Number of bytes transferred in the last transaction */
14996 
14997 /* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
14998 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14999 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
15000 
15001 /* Register: TWIM_TXD_LIST */
15002 /* Description: EasyDMA list type */
15003 
15004 /* Bits 2..0 : List type */
15005 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
15006 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
15007 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
15008 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
15009 
15010 /* Register: TWIM_ADDRESS */
15011 /* Description: Address used in the TWI transfer */
15012 
15013 /* Bits 6..0 : Address used in the TWI transfer */
15014 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
15015 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
15016 
15017 
15018 /* Peripheral: TWIS */
15019 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
15020 
15021 /* Register: TWIS_TASKS_STOP */
15022 /* Description: Stop TWI transaction */
15023 
15024 /* Bit 0 : Stop TWI transaction */
15025 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
15026 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
15027 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
15028 
15029 /* Register: TWIS_TASKS_SUSPEND */
15030 /* Description: Suspend TWI transaction */
15031 
15032 /* Bit 0 : Suspend TWI transaction */
15033 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
15034 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
15035 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
15036 
15037 /* Register: TWIS_TASKS_RESUME */
15038 /* Description: Resume TWI transaction */
15039 
15040 /* Bit 0 : Resume TWI transaction */
15041 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
15042 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
15043 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
15044 
15045 /* Register: TWIS_TASKS_PREPARERX */
15046 /* Description: Prepare the TWI slave to respond to a write command */
15047 
15048 /* Bit 0 : Prepare the TWI slave to respond to a write command */
15049 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
15050 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
15051 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
15052 
15053 /* Register: TWIS_TASKS_PREPARETX */
15054 /* Description: Prepare the TWI slave to respond to a read command */
15055 
15056 /* Bit 0 : Prepare the TWI slave to respond to a read command */
15057 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
15058 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
15059 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
15060 
15061 /* Register: TWIS_SUBSCRIBE_STOP */
15062 /* Description: Subscribe configuration for task STOP */
15063 
15064 /* Bit 31 :   */
15065 #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
15066 #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
15067 #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
15068 #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
15069 
15070 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
15071 #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15072 #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15073 
15074 /* Register: TWIS_SUBSCRIBE_SUSPEND */
15075 /* Description: Subscribe configuration for task SUSPEND */
15076 
15077 /* Bit 31 :   */
15078 #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
15079 #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
15080 #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
15081 #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
15082 
15083 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */
15084 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15085 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15086 
15087 /* Register: TWIS_SUBSCRIBE_RESUME */
15088 /* Description: Subscribe configuration for task RESUME */
15089 
15090 /* Bit 31 :   */
15091 #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
15092 #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
15093 #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
15094 #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
15095 
15096 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */
15097 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15098 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15099 
15100 /* Register: TWIS_SUBSCRIBE_PREPARERX */
15101 /* Description: Subscribe configuration for task PREPARERX */
15102 
15103 /* Bit 31 :   */
15104 #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */
15105 #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */
15106 #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */
15107 #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */
15108 
15109 /* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */
15110 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15111 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15112 
15113 /* Register: TWIS_SUBSCRIBE_PREPARETX */
15114 /* Description: Subscribe configuration for task PREPARETX */
15115 
15116 /* Bit 31 :   */
15117 #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */
15118 #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */
15119 #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */
15120 #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */
15121 
15122 /* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */
15123 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15124 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15125 
15126 /* Register: TWIS_EVENTS_STOPPED */
15127 /* Description: TWI stopped */
15128 
15129 /* Bit 0 : TWI stopped */
15130 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
15131 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
15132 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
15133 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
15134 
15135 /* Register: TWIS_EVENTS_ERROR */
15136 /* Description: TWI error */
15137 
15138 /* Bit 0 : TWI error */
15139 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
15140 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
15141 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
15142 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
15143 
15144 /* Register: TWIS_EVENTS_RXSTARTED */
15145 /* Description: Receive sequence started */
15146 
15147 /* Bit 0 : Receive sequence started */
15148 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
15149 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
15150 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
15151 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
15152 
15153 /* Register: TWIS_EVENTS_TXSTARTED */
15154 /* Description: Transmit sequence started */
15155 
15156 /* Bit 0 : Transmit sequence started */
15157 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
15158 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
15159 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
15160 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
15161 
15162 /* Register: TWIS_EVENTS_WRITE */
15163 /* Description: Write command received */
15164 
15165 /* Bit 0 : Write command received */
15166 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
15167 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
15168 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
15169 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
15170 
15171 /* Register: TWIS_EVENTS_READ */
15172 /* Description: Read command received */
15173 
15174 /* Bit 0 : Read command received */
15175 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
15176 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
15177 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
15178 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
15179 
15180 /* Register: TWIS_PUBLISH_STOPPED */
15181 /* Description: Publish configuration for event STOPPED */
15182 
15183 /* Bit 31 :   */
15184 #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
15185 #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
15186 #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
15187 #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
15188 
15189 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
15190 #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15191 #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15192 
15193 /* Register: TWIS_PUBLISH_ERROR */
15194 /* Description: Publish configuration for event ERROR */
15195 
15196 /* Bit 31 :   */
15197 #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
15198 #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
15199 #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
15200 #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
15201 
15202 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */
15203 #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15204 #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15205 
15206 /* Register: TWIS_PUBLISH_RXSTARTED */
15207 /* Description: Publish configuration for event RXSTARTED */
15208 
15209 /* Bit 31 :   */
15210 #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
15211 #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
15212 #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
15213 #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
15214 
15215 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to. */
15216 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15217 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15218 
15219 /* Register: TWIS_PUBLISH_TXSTARTED */
15220 /* Description: Publish configuration for event TXSTARTED */
15221 
15222 /* Bit 31 :   */
15223 #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
15224 #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
15225 #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
15226 #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
15227 
15228 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to. */
15229 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15230 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15231 
15232 /* Register: TWIS_PUBLISH_WRITE */
15233 /* Description: Publish configuration for event WRITE */
15234 
15235 /* Bit 31 :   */
15236 #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */
15237 #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */
15238 #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */
15239 #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */
15240 
15241 /* Bits 7..0 : DPPI channel that event WRITE will publish to. */
15242 #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15243 #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15244 
15245 /* Register: TWIS_PUBLISH_READ */
15246 /* Description: Publish configuration for event READ */
15247 
15248 /* Bit 31 :   */
15249 #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */
15250 #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */
15251 #define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */
15252 #define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */
15253 
15254 /* Bits 7..0 : DPPI channel that event READ will publish to. */
15255 #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15256 #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15257 
15258 /* Register: TWIS_SHORTS */
15259 /* Description: Shortcuts between local events and tasks */
15260 
15261 /* Bit 14 : Shortcut between event READ and task SUSPEND */
15262 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
15263 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
15264 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
15265 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
15266 
15267 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
15268 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
15269 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
15270 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
15271 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
15272 
15273 /* Register: TWIS_INTEN */
15274 /* Description: Enable or disable interrupt */
15275 
15276 /* Bit 26 : Enable or disable interrupt for event READ */
15277 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
15278 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
15279 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
15280 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
15281 
15282 /* Bit 25 : Enable or disable interrupt for event WRITE */
15283 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
15284 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
15285 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
15286 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
15287 
15288 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
15289 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15290 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15291 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
15292 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
15293 
15294 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
15295 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15296 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15297 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
15298 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
15299 
15300 /* Bit 9 : Enable or disable interrupt for event ERROR */
15301 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15302 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
15303 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
15304 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
15305 
15306 /* Bit 1 : Enable or disable interrupt for event STOPPED */
15307 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15308 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15309 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
15310 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
15311 
15312 /* Register: TWIS_INTENSET */
15313 /* Description: Enable interrupt */
15314 
15315 /* Bit 26 : Write '1' to enable interrupt for event READ */
15316 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
15317 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
15318 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
15319 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
15320 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
15321 
15322 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
15323 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
15324 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
15325 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
15326 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
15327 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
15328 
15329 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
15330 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15331 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15332 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15333 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15334 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
15335 
15336 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
15337 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15338 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15339 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15340 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15341 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
15342 
15343 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
15344 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15345 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
15346 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
15347 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
15348 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
15349 
15350 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
15351 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15352 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15353 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
15354 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
15355 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
15356 
15357 /* Register: TWIS_INTENCLR */
15358 /* Description: Disable interrupt */
15359 
15360 /* Bit 26 : Write '1' to disable interrupt for event READ */
15361 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
15362 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
15363 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
15364 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
15365 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
15366 
15367 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
15368 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
15369 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
15370 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
15371 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
15372 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
15373 
15374 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
15375 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15376 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15377 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15378 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15379 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
15380 
15381 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
15382 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15383 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15384 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15385 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15386 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
15387 
15388 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
15389 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15390 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
15391 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
15392 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
15393 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
15394 
15395 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
15396 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
15397 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
15398 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
15399 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
15400 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
15401 
15402 /* Register: TWIS_ERRORSRC */
15403 /* Description: Error source */
15404 
15405 /* Bit 3 : TX buffer over-read detected, and prevented */
15406 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
15407 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
15408 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
15409 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
15410 
15411 /* Bit 2 : NACK sent after receiving a data byte */
15412 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
15413 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
15414 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
15415 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
15416 
15417 /* Bit 0 : RX buffer overflow detected, and prevented */
15418 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
15419 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
15420 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
15421 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
15422 
15423 /* Register: TWIS_MATCH */
15424 /* Description: Status register indicating which address had a match */
15425 
15426 /* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */
15427 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
15428 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
15429 
15430 /* Register: TWIS_ENABLE */
15431 /* Description: Enable TWIS */
15432 
15433 /* Bits 3..0 : Enable or disable TWIS */
15434 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
15435 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
15436 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
15437 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
15438 
15439 /* Register: TWIS_PSEL_SCL */
15440 /* Description: Pin select for SCL signal */
15441 
15442 /* Bit 31 : Connection */
15443 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15444 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15445 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
15446 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
15447 
15448 /* Bit 5 : Port number */
15449 #define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
15450 #define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
15451 
15452 /* Bits 4..0 : Pin number */
15453 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
15454 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
15455 
15456 /* Register: TWIS_PSEL_SDA */
15457 /* Description: Pin select for SDA signal */
15458 
15459 /* Bit 31 : Connection */
15460 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
15461 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
15462 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
15463 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
15464 
15465 /* Bit 5 : Port number */
15466 #define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
15467 #define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
15468 
15469 /* Bits 4..0 : Pin number */
15470 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
15471 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
15472 
15473 /* Register: TWIS_RXD_PTR */
15474 /* Description: RXD Data pointer */
15475 
15476 /* Bits 31..0 : RXD Data pointer */
15477 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
15478 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
15479 
15480 /* Register: TWIS_RXD_MAXCNT */
15481 /* Description: Maximum number of bytes in RXD buffer */
15482 
15483 /* Bits 15..0 : Maximum number of bytes in RXD buffer */
15484 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
15485 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
15486 
15487 /* Register: TWIS_RXD_AMOUNT */
15488 /* Description: Number of bytes transferred in the last RXD transaction */
15489 
15490 /* Bits 15..0 : Number of bytes transferred in the last RXD transaction */
15491 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
15492 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
15493 
15494 /* Register: TWIS_RXD_LIST */
15495 /* Description: EasyDMA list type */
15496 
15497 /* Bits 1..0 : List type */
15498 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
15499 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
15500 #define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
15501 #define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
15502 
15503 /* Register: TWIS_TXD_PTR */
15504 /* Description: TXD Data pointer */
15505 
15506 /* Bits 31..0 : TXD Data pointer */
15507 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
15508 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
15509 
15510 /* Register: TWIS_TXD_MAXCNT */
15511 /* Description: Maximum number of bytes in TXD buffer */
15512 
15513 /* Bits 15..0 : Maximum number of bytes in TXD buffer */
15514 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
15515 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
15516 
15517 /* Register: TWIS_TXD_AMOUNT */
15518 /* Description: Number of bytes transferred in the last TXD transaction */
15519 
15520 /* Bits 15..0 : Number of bytes transferred in the last TXD transaction */
15521 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
15522 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
15523 
15524 /* Register: TWIS_TXD_LIST */
15525 /* Description: EasyDMA list type */
15526 
15527 /* Bits 1..0 : List type */
15528 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
15529 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
15530 #define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
15531 #define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
15532 
15533 /* Register: TWIS_ADDRESS */
15534 /* Description: Description collection: TWI slave address n */
15535 
15536 /* Bits 6..0 : TWI slave address */
15537 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
15538 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
15539 
15540 /* Register: TWIS_CONFIG */
15541 /* Description: Configuration register for the address match mechanism */
15542 
15543 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
15544 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
15545 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
15546 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
15547 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
15548 
15549 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
15550 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
15551 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
15552 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
15553 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
15554 
15555 /* Register: TWIS_ORC */
15556 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
15557 
15558 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
15559 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
15560 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
15561 
15562 
15563 /* Peripheral: UARTE */
15564 /* Description: UART with EasyDMA 0 */
15565 
15566 /* Register: UARTE_TASKS_STARTRX */
15567 /* Description: Start UART receiver */
15568 
15569 /* Bit 0 : Start UART receiver */
15570 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
15571 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
15572 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
15573 
15574 /* Register: UARTE_TASKS_STOPRX */
15575 /* Description: Stop UART receiver */
15576 
15577 /* Bit 0 : Stop UART receiver */
15578 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
15579 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
15580 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
15581 
15582 /* Register: UARTE_TASKS_STARTTX */
15583 /* Description: Start UART transmitter */
15584 
15585 /* Bit 0 : Start UART transmitter */
15586 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
15587 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
15588 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
15589 
15590 /* Register: UARTE_TASKS_STOPTX */
15591 /* Description: Stop UART transmitter */
15592 
15593 /* Bit 0 : Stop UART transmitter */
15594 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
15595 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
15596 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
15597 
15598 /* Register: UARTE_TASKS_FLUSHRX */
15599 /* Description: Flush RX FIFO into RX buffer */
15600 
15601 /* Bit 0 : Flush RX FIFO into RX buffer */
15602 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
15603 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
15604 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
15605 
15606 /* Register: UARTE_SUBSCRIBE_STARTRX */
15607 /* Description: Subscribe configuration for task STARTRX */
15608 
15609 /* Bit 31 :   */
15610 #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
15611 #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
15612 #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
15613 #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
15614 
15615 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */
15616 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15617 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15618 
15619 /* Register: UARTE_SUBSCRIBE_STOPRX */
15620 /* Description: Subscribe configuration for task STOPRX */
15621 
15622 /* Bit 31 :   */
15623 #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */
15624 #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */
15625 #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */
15626 #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */
15627 
15628 /* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */
15629 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15630 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15631 
15632 /* Register: UARTE_SUBSCRIBE_STARTTX */
15633 /* Description: Subscribe configuration for task STARTTX */
15634 
15635 /* Bit 31 :   */
15636 #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
15637 #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
15638 #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
15639 #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
15640 
15641 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */
15642 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15643 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15644 
15645 /* Register: UARTE_SUBSCRIBE_STOPTX */
15646 /* Description: Subscribe configuration for task STOPTX */
15647 
15648 /* Bit 31 :   */
15649 #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */
15650 #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */
15651 #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */
15652 #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */
15653 
15654 /* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */
15655 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15656 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15657 
15658 /* Register: UARTE_SUBSCRIBE_FLUSHRX */
15659 /* Description: Subscribe configuration for task FLUSHRX */
15660 
15661 /* Bit 31 :   */
15662 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */
15663 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */
15664 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */
15665 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */
15666 
15667 /* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */
15668 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15669 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15670 
15671 /* Register: UARTE_EVENTS_CTS */
15672 /* Description: CTS is activated (set low). Clear To Send. */
15673 
15674 /* Bit 0 : CTS is activated (set low). Clear To Send. */
15675 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
15676 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
15677 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
15678 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
15679 
15680 /* Register: UARTE_EVENTS_NCTS */
15681 /* Description: CTS is deactivated (set high). Not Clear To Send. */
15682 
15683 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
15684 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
15685 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
15686 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
15687 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
15688 
15689 /* Register: UARTE_EVENTS_RXDRDY */
15690 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
15691 
15692 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
15693 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
15694 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
15695 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
15696 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
15697 
15698 /* Register: UARTE_EVENTS_ENDRX */
15699 /* Description: Receive buffer is filled up */
15700 
15701 /* Bit 0 : Receive buffer is filled up */
15702 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
15703 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
15704 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
15705 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
15706 
15707 /* Register: UARTE_EVENTS_TXDRDY */
15708 /* Description: Data sent from TXD */
15709 
15710 /* Bit 0 : Data sent from TXD */
15711 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
15712 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
15713 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
15714 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
15715 
15716 /* Register: UARTE_EVENTS_ENDTX */
15717 /* Description: Last TX byte transmitted */
15718 
15719 /* Bit 0 : Last TX byte transmitted */
15720 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
15721 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
15722 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
15723 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
15724 
15725 /* Register: UARTE_EVENTS_ERROR */
15726 /* Description: Error detected */
15727 
15728 /* Bit 0 : Error detected */
15729 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
15730 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
15731 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
15732 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
15733 
15734 /* Register: UARTE_EVENTS_RXTO */
15735 /* Description: Receiver timeout */
15736 
15737 /* Bit 0 : Receiver timeout */
15738 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
15739 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
15740 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
15741 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
15742 
15743 /* Register: UARTE_EVENTS_RXSTARTED */
15744 /* Description: UART receiver has started */
15745 
15746 /* Bit 0 : UART receiver has started */
15747 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
15748 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
15749 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
15750 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
15751 
15752 /* Register: UARTE_EVENTS_TXSTARTED */
15753 /* Description: UART transmitter has started */
15754 
15755 /* Bit 0 : UART transmitter has started */
15756 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
15757 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
15758 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
15759 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
15760 
15761 /* Register: UARTE_EVENTS_TXSTOPPED */
15762 /* Description: Transmitter stopped */
15763 
15764 /* Bit 0 : Transmitter stopped */
15765 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
15766 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
15767 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
15768 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
15769 
15770 /* Register: UARTE_PUBLISH_CTS */
15771 /* Description: Publish configuration for event CTS */
15772 
15773 /* Bit 31 :   */
15774 #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */
15775 #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */
15776 #define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */
15777 #define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */
15778 
15779 /* Bits 7..0 : DPPI channel that event CTS will publish to. */
15780 #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15781 #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15782 
15783 /* Register: UARTE_PUBLISH_NCTS */
15784 /* Description: Publish configuration for event NCTS */
15785 
15786 /* Bit 31 :   */
15787 #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */
15788 #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */
15789 #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */
15790 #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */
15791 
15792 /* Bits 7..0 : DPPI channel that event NCTS will publish to. */
15793 #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15794 #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15795 
15796 /* Register: UARTE_PUBLISH_RXDRDY */
15797 /* Description: Publish configuration for event RXDRDY */
15798 
15799 /* Bit 31 :   */
15800 #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
15801 #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */
15802 #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
15803 #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
15804 
15805 /* Bits 7..0 : DPPI channel that event RXDRDY will publish to. */
15806 #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15807 #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15808 
15809 /* Register: UARTE_PUBLISH_ENDRX */
15810 /* Description: Publish configuration for event ENDRX */
15811 
15812 /* Bit 31 :   */
15813 #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
15814 #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
15815 #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
15816 #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
15817 
15818 /* Bits 7..0 : DPPI channel that event ENDRX will publish to. */
15819 #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15820 #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15821 
15822 /* Register: UARTE_PUBLISH_TXDRDY */
15823 /* Description: Publish configuration for event TXDRDY */
15824 
15825 /* Bit 31 :   */
15826 #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
15827 #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */
15828 #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
15829 #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
15830 
15831 /* Bits 7..0 : DPPI channel that event TXDRDY will publish to. */
15832 #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15833 #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15834 
15835 /* Register: UARTE_PUBLISH_ENDTX */
15836 /* Description: Publish configuration for event ENDTX */
15837 
15838 /* Bit 31 :   */
15839 #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
15840 #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
15841 #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
15842 #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
15843 
15844 /* Bits 7..0 : DPPI channel that event ENDTX will publish to. */
15845 #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15846 #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15847 
15848 /* Register: UARTE_PUBLISH_ERROR */
15849 /* Description: Publish configuration for event ERROR */
15850 
15851 /* Bit 31 :   */
15852 #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
15853 #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
15854 #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
15855 #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
15856 
15857 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */
15858 #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15859 #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15860 
15861 /* Register: UARTE_PUBLISH_RXTO */
15862 /* Description: Publish configuration for event RXTO */
15863 
15864 /* Bit 31 :   */
15865 #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */
15866 #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */
15867 #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */
15868 #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */
15869 
15870 /* Bits 7..0 : DPPI channel that event RXTO will publish to. */
15871 #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15872 #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15873 
15874 /* Register: UARTE_PUBLISH_RXSTARTED */
15875 /* Description: Publish configuration for event RXSTARTED */
15876 
15877 /* Bit 31 :   */
15878 #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
15879 #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
15880 #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
15881 #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
15882 
15883 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to. */
15884 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15885 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15886 
15887 /* Register: UARTE_PUBLISH_TXSTARTED */
15888 /* Description: Publish configuration for event TXSTARTED */
15889 
15890 /* Bit 31 :   */
15891 #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
15892 #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
15893 #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
15894 #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
15895 
15896 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to. */
15897 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15898 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15899 
15900 /* Register: UARTE_PUBLISH_TXSTOPPED */
15901 /* Description: Publish configuration for event TXSTOPPED */
15902 
15903 /* Bit 31 :   */
15904 #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
15905 #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */
15906 #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
15907 #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
15908 
15909 /* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to. */
15910 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
15911 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
15912 
15913 /* Register: UARTE_SHORTS */
15914 /* Description: Shortcuts between local events and tasks */
15915 
15916 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
15917 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
15918 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
15919 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
15920 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
15921 
15922 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
15923 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
15924 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
15925 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
15926 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
15927 
15928 /* Register: UARTE_INTEN */
15929 /* Description: Enable or disable interrupt */
15930 
15931 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
15932 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
15933 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
15934 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
15935 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
15936 
15937 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
15938 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
15939 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
15940 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
15941 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
15942 
15943 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
15944 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
15945 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
15946 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
15947 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
15948 
15949 /* Bit 17 : Enable or disable interrupt for event RXTO */
15950 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
15951 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
15952 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
15953 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
15954 
15955 /* Bit 9 : Enable or disable interrupt for event ERROR */
15956 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
15957 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
15958 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
15959 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
15960 
15961 /* Bit 8 : Enable or disable interrupt for event ENDTX */
15962 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
15963 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
15964 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
15965 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
15966 
15967 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
15968 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
15969 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
15970 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
15971 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
15972 
15973 /* Bit 4 : Enable or disable interrupt for event ENDRX */
15974 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
15975 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
15976 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
15977 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
15978 
15979 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
15980 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
15981 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
15982 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
15983 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
15984 
15985 /* Bit 1 : Enable or disable interrupt for event NCTS */
15986 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
15987 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
15988 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
15989 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
15990 
15991 /* Bit 0 : Enable or disable interrupt for event CTS */
15992 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
15993 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
15994 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
15995 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
15996 
15997 /* Register: UARTE_INTENSET */
15998 /* Description: Enable interrupt */
15999 
16000 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
16001 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
16002 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
16003 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
16004 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
16005 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
16006 
16007 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
16008 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
16009 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
16010 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
16011 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
16012 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
16013 
16014 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
16015 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
16016 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
16017 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
16018 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
16019 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
16020 
16021 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
16022 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
16023 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
16024 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
16025 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
16026 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
16027 
16028 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
16029 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
16030 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
16031 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
16032 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
16033 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
16034 
16035 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
16036 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
16037 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
16038 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
16039 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
16040 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
16041 
16042 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
16043 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
16044 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
16045 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
16046 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
16047 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
16048 
16049 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
16050 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
16051 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
16052 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
16053 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
16054 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
16055 
16056 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
16057 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
16058 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
16059 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
16060 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
16061 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
16062 
16063 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
16064 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
16065 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
16066 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
16067 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
16068 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
16069 
16070 /* Bit 0 : Write '1' to enable interrupt for event CTS */
16071 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
16072 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
16073 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
16074 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
16075 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
16076 
16077 /* Register: UARTE_INTENCLR */
16078 /* Description: Disable interrupt */
16079 
16080 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
16081 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
16082 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
16083 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
16084 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
16085 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
16086 
16087 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
16088 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
16089 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
16090 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
16091 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
16092 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
16093 
16094 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
16095 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
16096 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
16097 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
16098 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
16099 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
16100 
16101 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
16102 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
16103 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
16104 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
16105 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
16106 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
16107 
16108 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
16109 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
16110 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
16111 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
16112 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
16113 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
16114 
16115 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
16116 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
16117 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
16118 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
16119 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
16120 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
16121 
16122 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
16123 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
16124 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
16125 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
16126 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
16127 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
16128 
16129 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
16130 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
16131 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
16132 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
16133 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
16134 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
16135 
16136 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
16137 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
16138 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
16139 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
16140 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
16141 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
16142 
16143 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
16144 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
16145 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
16146 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
16147 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
16148 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
16149 
16150 /* Bit 0 : Write '1' to disable interrupt for event CTS */
16151 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
16152 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
16153 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
16154 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
16155 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
16156 
16157 /* Register: UARTE_ERRORSRC */
16158 /* Description: Error source */
16159 
16160 /* Bit 3 : Break condition */
16161 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
16162 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
16163 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
16164 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
16165 
16166 /* Bit 2 : Framing error occurred */
16167 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
16168 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
16169 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
16170 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
16171 
16172 /* Bit 1 : Parity error */
16173 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
16174 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
16175 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
16176 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
16177 
16178 /* Bit 0 : Overrun error */
16179 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
16180 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
16181 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
16182 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
16183 
16184 /* Register: UARTE_ENABLE */
16185 /* Description: Enable UART */
16186 
16187 /* Bits 3..0 : Enable or disable UARTE */
16188 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
16189 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
16190 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
16191 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
16192 
16193 /* Register: UARTE_PSEL_RTS */
16194 /* Description: Pin select for RTS signal */
16195 
16196 /* Bit 31 : Connection */
16197 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16198 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16199 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
16200 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
16201 
16202 /* Bit 5 : Port number */
16203 #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
16204 #define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
16205 
16206 /* Bits 4..0 : Pin number */
16207 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
16208 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
16209 
16210 /* Register: UARTE_PSEL_TXD */
16211 /* Description: Pin select for TXD signal */
16212 
16213 /* Bit 31 : Connection */
16214 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16215 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16216 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
16217 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
16218 
16219 /* Bit 5 : Port number */
16220 #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
16221 #define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
16222 
16223 /* Bits 4..0 : Pin number */
16224 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
16225 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
16226 
16227 /* Register: UARTE_PSEL_CTS */
16228 /* Description: Pin select for CTS signal */
16229 
16230 /* Bit 31 : Connection */
16231 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16232 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16233 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
16234 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
16235 
16236 /* Bit 5 : Port number */
16237 #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
16238 #define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
16239 
16240 /* Bits 4..0 : Pin number */
16241 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
16242 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
16243 
16244 /* Register: UARTE_PSEL_RXD */
16245 /* Description: Pin select for RXD signal */
16246 
16247 /* Bit 31 : Connection */
16248 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
16249 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
16250 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
16251 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
16252 
16253 /* Bit 5 : Port number */
16254 #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
16255 #define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
16256 
16257 /* Bits 4..0 : Pin number */
16258 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
16259 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
16260 
16261 /* Register: UARTE_BAUDRATE */
16262 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
16263 
16264 /* Bits 31..0 : Baud rate */
16265 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
16266 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
16267 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
16268 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
16269 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
16270 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
16271 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
16272 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
16273 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
16274 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
16275 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
16276 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
16277 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
16278 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
16279 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
16280 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
16281 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
16282 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
16283 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
16284 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
16285 
16286 /* Register: UARTE_RXD_PTR */
16287 /* Description: Data pointer */
16288 
16289 /* Bits 31..0 : Data pointer */
16290 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16291 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16292 
16293 /* Register: UARTE_RXD_MAXCNT */
16294 /* Description: Maximum number of bytes in receive buffer */
16295 
16296 /* Bits 15..0 : Maximum number of bytes in receive buffer */
16297 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16298 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16299 
16300 /* Register: UARTE_RXD_AMOUNT */
16301 /* Description: Number of bytes transferred in the last transaction */
16302 
16303 /* Bits 15..0 : Number of bytes transferred in the last transaction */
16304 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16305 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16306 
16307 /* Register: UARTE_TXD_PTR */
16308 /* Description: Data pointer */
16309 
16310 /* Bits 31..0 : Data pointer */
16311 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
16312 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
16313 
16314 /* Register: UARTE_TXD_MAXCNT */
16315 /* Description: Maximum number of bytes in transmit buffer */
16316 
16317 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
16318 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
16319 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
16320 
16321 /* Register: UARTE_TXD_AMOUNT */
16322 /* Description: Number of bytes transferred in the last transaction */
16323 
16324 /* Bits 15..0 : Number of bytes transferred in the last transaction */
16325 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
16326 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
16327 
16328 /* Register: UARTE_CONFIG */
16329 /* Description: Configuration of parity and hardware flow control */
16330 
16331 /* Bit 8 : Even or odd parity type */
16332 #define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
16333 #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
16334 #define UARTE_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
16335 #define UARTE_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
16336 
16337 /* Bit 4 : Stop bits */
16338 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
16339 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
16340 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
16341 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
16342 
16343 /* Bits 3..1 : Parity */
16344 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
16345 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
16346 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
16347 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
16348 
16349 /* Bit 0 : Hardware flow control */
16350 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
16351 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
16352 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
16353 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
16354 
16355 
16356 /* Peripheral: UICR */
16357 /* Description: User Information Configuration Registers User information configuration registers */
16358 
16359 /* Register: UICR_APPROTECT */
16360 /* Description: Access port protection */
16361 
16362 /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and
16363           memory mapped addresses. */
16364 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
16365 #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
16366 #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
16367 #define UICR_APPROTECT_PALL_Unprotected (0x50FA50FAUL) /*!< Unprotected */
16368 
16369 /* Register: UICR_VREGHVOUT */
16370 /* Description: Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP. */
16371 
16372 /* Bits 2..0 : VREGH regulator output voltage. */
16373 #define UICR_VREGHVOUT_VREGHVOUT_Pos (0UL) /*!< Position of VREGHVOUT field. */
16374 #define UICR_VREGHVOUT_VREGHVOUT_Msk (0x7UL << UICR_VREGHVOUT_VREGHVOUT_Pos) /*!< Bit mask of VREGHVOUT field. */
16375 #define UICR_VREGHVOUT_VREGHVOUT_1V8 (0UL) /*!< 1.8 V */
16376 #define UICR_VREGHVOUT_VREGHVOUT_2V1 (1UL) /*!< 2.1 V */
16377 #define UICR_VREGHVOUT_VREGHVOUT_2V4 (2UL) /*!< 2.4 V */
16378 #define UICR_VREGHVOUT_VREGHVOUT_2V7 (3UL) /*!< 2.7 V */
16379 #define UICR_VREGHVOUT_VREGHVOUT_3V0 (4UL) /*!< 3.0 V */
16380 #define UICR_VREGHVOUT_VREGHVOUT_3V3 (5UL) /*!< 3.3 V */
16381 #define UICR_VREGHVOUT_VREGHVOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */
16382 
16383 /* Register: UICR_HFXOCNT */
16384 /* Description: HFXO startup counter */
16385 
16386 /* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */
16387 #define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */
16388 #define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */
16389 #define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL) /*!< Min debounce time = (0*64 us + 0.5 us) */
16390 #define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (254UL) /*!< Max debounce time = (254*64 us + 0.5 us) */
16391 #define UICR_HFXOCNT_HFXOCNT_DefaultDebounceTime (255UL) /*!< Default debounce time for erased UICR = 4*64 us + 0.5 us */
16392 
16393 /* Register: UICR_SECUREAPPROTECT */
16394 /* Description: Secure access port protection */
16395 
16396 /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure memory
16397         mapped addresses. */
16398 #define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
16399 #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
16400 #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
16401 #define UICR_SECUREAPPROTECT_PALL_Unprotected (0x50FA50FAUL) /*!< Unprotected */
16402 
16403 /* Register: UICR_ERASEPROTECT */
16404 /* Description: Erase protection */
16405 
16406 /* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. */
16407 #define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
16408 #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
16409 #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
16410 #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
16411 
16412 /* Register: UICR_TINSTANCE */
16413 /* Description: SW-DP Target instance */
16414 
16415 /* Bits 31..28 : TINSTANCE bits are negated and used in the SW-DP DLPIDR.TINSTANCE field. E.g. 0xF in this field is translated to 0x0 in DLPIDR.TINSTANCE field. */
16416 #define UICR_TINSTANCE_TINSTANCE_Pos (28UL) /*!< Position of TINSTANCE field. */
16417 #define UICR_TINSTANCE_TINSTANCE_Msk (0xFUL << UICR_TINSTANCE_TINSTANCE_Pos) /*!< Bit mask of TINSTANCE field. */
16418 
16419 /* Register: UICR_NFCPINS */
16420 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
16421 
16422 /* Bit 0 : Setting of pins dedicated to NFC functionality */
16423 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
16424 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
16425 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
16426 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
16427 
16428 /* Register: UICR_OTP */
16429 /* Description: Description collection: One time programmable memory */
16430 
16431 /* Bits 31..16 : Upper half word */
16432 #define UICR_OTP_UPPER_Pos (16UL) /*!< Position of UPPER field. */
16433 #define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos) /*!< Bit mask of UPPER field. */
16434 
16435 /* Bits 15..0 : Lower half word */
16436 #define UICR_OTP_LOWER_Pos (0UL) /*!< Position of LOWER field. */
16437 #define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos) /*!< Bit mask of LOWER field. */
16438 
16439 /* Register: UICR_KEYSLOT_CONFIG_DEST */
16440 /* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3])
16441           will be pushed by KMU. Note that this address must match that of a peripherals
16442           APB mapped write-only key registers, else the KMU can push this key value into
16443           an address range which the CPU can potentially read. */
16444 
16445 /* Bits 31..0 : Secure APB destination address */
16446 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */
16447 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */
16448 
16449 /* Register: UICR_KEYSLOT_CONFIG_PERM */
16450 /* Description: Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */
16451 
16452 /* Bit 16 : Revocation state for the key slot */
16453 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */
16454 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */
16455 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL) /*!< Key value registers can no longer be read or pushed */
16456 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */
16457 
16458 /* Bit 2 : Push permission for key slot */
16459 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */
16460 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */
16461 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */
16462 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */
16463 
16464 /* Bit 1 : Read permission for key slot */
16465 #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */
16466 #define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */
16467 #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL) /*!< Disable read from key value registers */
16468 #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */
16469 
16470 /* Bit 0 : Write permission for key slot */
16471 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */
16472 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
16473 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL) /*!< Disable write to the key value registers */
16474 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */
16475 
16476 /* Register: UICR_KEYSLOT_KEY_VALUE */
16477 /* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */
16478 
16479 /* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot */
16480 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
16481 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
16482 
16483 
16484 /* Peripheral: USBD */
16485 /* Description: Universal serial bus device 0 */
16486 
16487 /* Register: USBD_TASKS_STARTEPIN */
16488 /* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
16489 
16490 /* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */
16491 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */
16492 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */
16493 #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */
16494 
16495 /* Register: USBD_TASKS_STARTISOIN */
16496 /* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
16497 
16498 /* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */
16499 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */
16500 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */
16501 #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */
16502 
16503 /* Register: USBD_TASKS_STARTEPOUT */
16504 /* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
16505 
16506 /* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */
16507 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */
16508 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */
16509 #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */
16510 
16511 /* Register: USBD_TASKS_STARTISOOUT */
16512 /* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
16513 
16514 /* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */
16515 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */
16516 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */
16517 #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */
16518 
16519 /* Register: USBD_TASKS_EP0RCVOUT */
16520 /* Description: Allows OUT data stage on control endpoint 0 */
16521 
16522 /* Bit 0 : Allows OUT data stage on control endpoint 0 */
16523 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */
16524 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */
16525 #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */
16526 
16527 /* Register: USBD_TASKS_EP0STATUS */
16528 /* Description: Allows status stage on control endpoint 0 */
16529 
16530 /* Bit 0 : Allows status stage on control endpoint 0 */
16531 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */
16532 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */
16533 #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */
16534 
16535 /* Register: USBD_TASKS_EP0STALL */
16536 /* Description: Stalls data and status stage on control endpoint 0 */
16537 
16538 /* Bit 0 : Stalls data and status stage on control endpoint 0 */
16539 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */
16540 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */
16541 #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */
16542 
16543 /* Register: USBD_TASKS_DPDMDRIVE */
16544 /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */
16545 
16546 /* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */
16547 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */
16548 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */
16549 #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */
16550 
16551 /* Register: USBD_TASKS_DPDMNODRIVE */
16552 /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */
16553 
16554 /* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */
16555 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */
16556 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */
16557 #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */
16558 
16559 /* Register: USBD_SUBSCRIBE_STARTEPIN */
16560 /* Description: Description collection: Subscribe configuration for task STARTEPIN[n] */
16561 
16562 /* Bit 31 :   */
16563 #define USBD_SUBSCRIBE_STARTEPIN_EN_Pos (31UL) /*!< Position of EN field. */
16564 #define USBD_SUBSCRIBE_STARTEPIN_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTEPIN_EN_Pos) /*!< Bit mask of EN field. */
16565 #define USBD_SUBSCRIBE_STARTEPIN_EN_Disabled (0UL) /*!< Disable subscription */
16566 #define USBD_SUBSCRIBE_STARTEPIN_EN_Enabled (1UL) /*!< Enable subscription */
16567 
16568 /* Bits 7..0 : DPPI channel that task STARTEPIN[n] will subscribe to */
16569 #define USBD_SUBSCRIBE_STARTEPIN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16570 #define USBD_SUBSCRIBE_STARTEPIN_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTEPIN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16571 
16572 /* Register: USBD_SUBSCRIBE_STARTISOIN */
16573 /* Description: Subscribe configuration for task STARTISOIN */
16574 
16575 /* Bit 31 :   */
16576 #define USBD_SUBSCRIBE_STARTISOIN_EN_Pos (31UL) /*!< Position of EN field. */
16577 #define USBD_SUBSCRIBE_STARTISOIN_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTISOIN_EN_Pos) /*!< Bit mask of EN field. */
16578 #define USBD_SUBSCRIBE_STARTISOIN_EN_Disabled (0UL) /*!< Disable subscription */
16579 #define USBD_SUBSCRIBE_STARTISOIN_EN_Enabled (1UL) /*!< Enable subscription */
16580 
16581 /* Bits 7..0 : DPPI channel that task STARTISOIN will subscribe to */
16582 #define USBD_SUBSCRIBE_STARTISOIN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16583 #define USBD_SUBSCRIBE_STARTISOIN_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTISOIN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16584 
16585 /* Register: USBD_SUBSCRIBE_STARTEPOUT */
16586 /* Description: Description collection: Subscribe configuration for task STARTEPOUT[n] */
16587 
16588 /* Bit 31 :   */
16589 #define USBD_SUBSCRIBE_STARTEPOUT_EN_Pos (31UL) /*!< Position of EN field. */
16590 #define USBD_SUBSCRIBE_STARTEPOUT_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTEPOUT_EN_Pos) /*!< Bit mask of EN field. */
16591 #define USBD_SUBSCRIBE_STARTEPOUT_EN_Disabled (0UL) /*!< Disable subscription */
16592 #define USBD_SUBSCRIBE_STARTEPOUT_EN_Enabled (1UL) /*!< Enable subscription */
16593 
16594 /* Bits 7..0 : DPPI channel that task STARTEPOUT[n] will subscribe to */
16595 #define USBD_SUBSCRIBE_STARTEPOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16596 #define USBD_SUBSCRIBE_STARTEPOUT_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTEPOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16597 
16598 /* Register: USBD_SUBSCRIBE_STARTISOOUT */
16599 /* Description: Subscribe configuration for task STARTISOOUT */
16600 
16601 /* Bit 31 :   */
16602 #define USBD_SUBSCRIBE_STARTISOOUT_EN_Pos (31UL) /*!< Position of EN field. */
16603 #define USBD_SUBSCRIBE_STARTISOOUT_EN_Msk (0x1UL << USBD_SUBSCRIBE_STARTISOOUT_EN_Pos) /*!< Bit mask of EN field. */
16604 #define USBD_SUBSCRIBE_STARTISOOUT_EN_Disabled (0UL) /*!< Disable subscription */
16605 #define USBD_SUBSCRIBE_STARTISOOUT_EN_Enabled (1UL) /*!< Enable subscription */
16606 
16607 /* Bits 7..0 : DPPI channel that task STARTISOOUT will subscribe to */
16608 #define USBD_SUBSCRIBE_STARTISOOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16609 #define USBD_SUBSCRIBE_STARTISOOUT_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_STARTISOOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16610 
16611 /* Register: USBD_SUBSCRIBE_EP0RCVOUT */
16612 /* Description: Subscribe configuration for task EP0RCVOUT */
16613 
16614 /* Bit 31 :   */
16615 #define USBD_SUBSCRIBE_EP0RCVOUT_EN_Pos (31UL) /*!< Position of EN field. */
16616 #define USBD_SUBSCRIBE_EP0RCVOUT_EN_Msk (0x1UL << USBD_SUBSCRIBE_EP0RCVOUT_EN_Pos) /*!< Bit mask of EN field. */
16617 #define USBD_SUBSCRIBE_EP0RCVOUT_EN_Disabled (0UL) /*!< Disable subscription */
16618 #define USBD_SUBSCRIBE_EP0RCVOUT_EN_Enabled (1UL) /*!< Enable subscription */
16619 
16620 /* Bits 7..0 : DPPI channel that task EP0RCVOUT will subscribe to */
16621 #define USBD_SUBSCRIBE_EP0RCVOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16622 #define USBD_SUBSCRIBE_EP0RCVOUT_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_EP0RCVOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16623 
16624 /* Register: USBD_SUBSCRIBE_EP0STATUS */
16625 /* Description: Subscribe configuration for task EP0STATUS */
16626 
16627 /* Bit 31 :   */
16628 #define USBD_SUBSCRIBE_EP0STATUS_EN_Pos (31UL) /*!< Position of EN field. */
16629 #define USBD_SUBSCRIBE_EP0STATUS_EN_Msk (0x1UL << USBD_SUBSCRIBE_EP0STATUS_EN_Pos) /*!< Bit mask of EN field. */
16630 #define USBD_SUBSCRIBE_EP0STATUS_EN_Disabled (0UL) /*!< Disable subscription */
16631 #define USBD_SUBSCRIBE_EP0STATUS_EN_Enabled (1UL) /*!< Enable subscription */
16632 
16633 /* Bits 7..0 : DPPI channel that task EP0STATUS will subscribe to */
16634 #define USBD_SUBSCRIBE_EP0STATUS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16635 #define USBD_SUBSCRIBE_EP0STATUS_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_EP0STATUS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16636 
16637 /* Register: USBD_SUBSCRIBE_EP0STALL */
16638 /* Description: Subscribe configuration for task EP0STALL */
16639 
16640 /* Bit 31 :   */
16641 #define USBD_SUBSCRIBE_EP0STALL_EN_Pos (31UL) /*!< Position of EN field. */
16642 #define USBD_SUBSCRIBE_EP0STALL_EN_Msk (0x1UL << USBD_SUBSCRIBE_EP0STALL_EN_Pos) /*!< Bit mask of EN field. */
16643 #define USBD_SUBSCRIBE_EP0STALL_EN_Disabled (0UL) /*!< Disable subscription */
16644 #define USBD_SUBSCRIBE_EP0STALL_EN_Enabled (1UL) /*!< Enable subscription */
16645 
16646 /* Bits 7..0 : DPPI channel that task EP0STALL will subscribe to */
16647 #define USBD_SUBSCRIBE_EP0STALL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16648 #define USBD_SUBSCRIBE_EP0STALL_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_EP0STALL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16649 
16650 /* Register: USBD_SUBSCRIBE_DPDMDRIVE */
16651 /* Description: Subscribe configuration for task DPDMDRIVE */
16652 
16653 /* Bit 31 :   */
16654 #define USBD_SUBSCRIBE_DPDMDRIVE_EN_Pos (31UL) /*!< Position of EN field. */
16655 #define USBD_SUBSCRIBE_DPDMDRIVE_EN_Msk (0x1UL << USBD_SUBSCRIBE_DPDMDRIVE_EN_Pos) /*!< Bit mask of EN field. */
16656 #define USBD_SUBSCRIBE_DPDMDRIVE_EN_Disabled (0UL) /*!< Disable subscription */
16657 #define USBD_SUBSCRIBE_DPDMDRIVE_EN_Enabled (1UL) /*!< Enable subscription */
16658 
16659 /* Bits 7..0 : DPPI channel that task DPDMDRIVE will subscribe to */
16660 #define USBD_SUBSCRIBE_DPDMDRIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16661 #define USBD_SUBSCRIBE_DPDMDRIVE_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_DPDMDRIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16662 
16663 /* Register: USBD_SUBSCRIBE_DPDMNODRIVE */
16664 /* Description: Subscribe configuration for task DPDMNODRIVE */
16665 
16666 /* Bit 31 :   */
16667 #define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Pos (31UL) /*!< Position of EN field. */
16668 #define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Msk (0x1UL << USBD_SUBSCRIBE_DPDMNODRIVE_EN_Pos) /*!< Bit mask of EN field. */
16669 #define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Disabled (0UL) /*!< Disable subscription */
16670 #define USBD_SUBSCRIBE_DPDMNODRIVE_EN_Enabled (1UL) /*!< Enable subscription */
16671 
16672 /* Bits 7..0 : DPPI channel that task DPDMNODRIVE will subscribe to */
16673 #define USBD_SUBSCRIBE_DPDMNODRIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16674 #define USBD_SUBSCRIBE_DPDMNODRIVE_CHIDX_Msk (0xFFUL << USBD_SUBSCRIBE_DPDMNODRIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16675 
16676 /* Register: USBD_EVENTS_USBRESET */
16677 /* Description: Signals that a USB reset condition has been detected on USB lines */
16678 
16679 /* Bit 0 : Signals that a USB reset condition has been detected on USB lines */
16680 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */
16681 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */
16682 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */
16683 #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */
16684 
16685 /* Register: USBD_EVENTS_STARTED */
16686 /* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
16687 
16688 /* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */
16689 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
16690 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
16691 #define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
16692 #define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
16693 
16694 /* Register: USBD_EVENTS_ENDEPIN */
16695 /* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
16696 
16697 /* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */
16698 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */
16699 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */
16700 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */
16701 #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */
16702 
16703 /* Register: USBD_EVENTS_EP0DATADONE */
16704 /* Description: An acknowledged data transfer has taken place on the control endpoint */
16705 
16706 /* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */
16707 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */
16708 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */
16709 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */
16710 #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */
16711 
16712 /* Register: USBD_EVENTS_ENDISOIN */
16713 /* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
16714 
16715 /* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */
16716 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */
16717 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */
16718 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */
16719 #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */
16720 
16721 /* Register: USBD_EVENTS_ENDEPOUT */
16722 /* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
16723 
16724 /* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */
16725 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */
16726 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */
16727 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */
16728 #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */
16729 
16730 /* Register: USBD_EVENTS_ENDISOOUT */
16731 /* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
16732 
16733 /* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */
16734 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */
16735 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */
16736 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */
16737 #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */
16738 
16739 /* Register: USBD_EVENTS_SOF */
16740 /* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */
16741 
16742 /* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */
16743 #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */
16744 #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */
16745 #define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */
16746 #define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */
16747 
16748 /* Register: USBD_EVENTS_USBEVENT */
16749 /* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
16750 
16751 /* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */
16752 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */
16753 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */
16754 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */
16755 #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */
16756 
16757 /* Register: USBD_EVENTS_EP0SETUP */
16758 /* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */
16759 
16760 /* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */
16761 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */
16762 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */
16763 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */
16764 #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */
16765 
16766 /* Register: USBD_EVENTS_EPDATA */
16767 /* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
16768 
16769 /* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */
16770 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */
16771 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */
16772 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */
16773 #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */
16774 
16775 /* Register: USBD_PUBLISH_USBRESET */
16776 /* Description: Publish configuration for event USBRESET */
16777 
16778 /* Bit 31 :   */
16779 #define USBD_PUBLISH_USBRESET_EN_Pos (31UL) /*!< Position of EN field. */
16780 #define USBD_PUBLISH_USBRESET_EN_Msk (0x1UL << USBD_PUBLISH_USBRESET_EN_Pos) /*!< Bit mask of EN field. */
16781 #define USBD_PUBLISH_USBRESET_EN_Disabled (0UL) /*!< Disable publishing */
16782 #define USBD_PUBLISH_USBRESET_EN_Enabled (1UL) /*!< Enable publishing */
16783 
16784 /* Bits 7..0 : DPPI channel that event USBRESET will publish to. */
16785 #define USBD_PUBLISH_USBRESET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16786 #define USBD_PUBLISH_USBRESET_CHIDX_Msk (0xFFUL << USBD_PUBLISH_USBRESET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16787 
16788 /* Register: USBD_PUBLISH_STARTED */
16789 /* Description: Publish configuration for event STARTED */
16790 
16791 /* Bit 31 :   */
16792 #define USBD_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
16793 #define USBD_PUBLISH_STARTED_EN_Msk (0x1UL << USBD_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
16794 #define USBD_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
16795 #define USBD_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
16796 
16797 /* Bits 7..0 : DPPI channel that event STARTED will publish to. */
16798 #define USBD_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16799 #define USBD_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << USBD_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16800 
16801 /* Register: USBD_PUBLISH_ENDEPIN */
16802 /* Description: Description collection: Publish configuration for event ENDEPIN[n] */
16803 
16804 /* Bit 31 :   */
16805 #define USBD_PUBLISH_ENDEPIN_EN_Pos (31UL) /*!< Position of EN field. */
16806 #define USBD_PUBLISH_ENDEPIN_EN_Msk (0x1UL << USBD_PUBLISH_ENDEPIN_EN_Pos) /*!< Bit mask of EN field. */
16807 #define USBD_PUBLISH_ENDEPIN_EN_Disabled (0UL) /*!< Disable publishing */
16808 #define USBD_PUBLISH_ENDEPIN_EN_Enabled (1UL) /*!< Enable publishing */
16809 
16810 /* Bits 7..0 : DPPI channel that event ENDEPIN[n] will publish to. */
16811 #define USBD_PUBLISH_ENDEPIN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16812 #define USBD_PUBLISH_ENDEPIN_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDEPIN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16813 
16814 /* Register: USBD_PUBLISH_EP0DATADONE */
16815 /* Description: Publish configuration for event EP0DATADONE */
16816 
16817 /* Bit 31 :   */
16818 #define USBD_PUBLISH_EP0DATADONE_EN_Pos (31UL) /*!< Position of EN field. */
16819 #define USBD_PUBLISH_EP0DATADONE_EN_Msk (0x1UL << USBD_PUBLISH_EP0DATADONE_EN_Pos) /*!< Bit mask of EN field. */
16820 #define USBD_PUBLISH_EP0DATADONE_EN_Disabled (0UL) /*!< Disable publishing */
16821 #define USBD_PUBLISH_EP0DATADONE_EN_Enabled (1UL) /*!< Enable publishing */
16822 
16823 /* Bits 7..0 : DPPI channel that event EP0DATADONE will publish to. */
16824 #define USBD_PUBLISH_EP0DATADONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16825 #define USBD_PUBLISH_EP0DATADONE_CHIDX_Msk (0xFFUL << USBD_PUBLISH_EP0DATADONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16826 
16827 /* Register: USBD_PUBLISH_ENDISOIN */
16828 /* Description: Publish configuration for event ENDISOIN */
16829 
16830 /* Bit 31 :   */
16831 #define USBD_PUBLISH_ENDISOIN_EN_Pos (31UL) /*!< Position of EN field. */
16832 #define USBD_PUBLISH_ENDISOIN_EN_Msk (0x1UL << USBD_PUBLISH_ENDISOIN_EN_Pos) /*!< Bit mask of EN field. */
16833 #define USBD_PUBLISH_ENDISOIN_EN_Disabled (0UL) /*!< Disable publishing */
16834 #define USBD_PUBLISH_ENDISOIN_EN_Enabled (1UL) /*!< Enable publishing */
16835 
16836 /* Bits 7..0 : DPPI channel that event ENDISOIN will publish to. */
16837 #define USBD_PUBLISH_ENDISOIN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16838 #define USBD_PUBLISH_ENDISOIN_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDISOIN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16839 
16840 /* Register: USBD_PUBLISH_ENDEPOUT */
16841 /* Description: Description collection: Publish configuration for event ENDEPOUT[n] */
16842 
16843 /* Bit 31 :   */
16844 #define USBD_PUBLISH_ENDEPOUT_EN_Pos (31UL) /*!< Position of EN field. */
16845 #define USBD_PUBLISH_ENDEPOUT_EN_Msk (0x1UL << USBD_PUBLISH_ENDEPOUT_EN_Pos) /*!< Bit mask of EN field. */
16846 #define USBD_PUBLISH_ENDEPOUT_EN_Disabled (0UL) /*!< Disable publishing */
16847 #define USBD_PUBLISH_ENDEPOUT_EN_Enabled (1UL) /*!< Enable publishing */
16848 
16849 /* Bits 7..0 : DPPI channel that event ENDEPOUT[n] will publish to. */
16850 #define USBD_PUBLISH_ENDEPOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16851 #define USBD_PUBLISH_ENDEPOUT_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDEPOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16852 
16853 /* Register: USBD_PUBLISH_ENDISOOUT */
16854 /* Description: Publish configuration for event ENDISOOUT */
16855 
16856 /* Bit 31 :   */
16857 #define USBD_PUBLISH_ENDISOOUT_EN_Pos (31UL) /*!< Position of EN field. */
16858 #define USBD_PUBLISH_ENDISOOUT_EN_Msk (0x1UL << USBD_PUBLISH_ENDISOOUT_EN_Pos) /*!< Bit mask of EN field. */
16859 #define USBD_PUBLISH_ENDISOOUT_EN_Disabled (0UL) /*!< Disable publishing */
16860 #define USBD_PUBLISH_ENDISOOUT_EN_Enabled (1UL) /*!< Enable publishing */
16861 
16862 /* Bits 7..0 : DPPI channel that event ENDISOOUT will publish to. */
16863 #define USBD_PUBLISH_ENDISOOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16864 #define USBD_PUBLISH_ENDISOOUT_CHIDX_Msk (0xFFUL << USBD_PUBLISH_ENDISOOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16865 
16866 /* Register: USBD_PUBLISH_SOF */
16867 /* Description: Publish configuration for event SOF */
16868 
16869 /* Bit 31 :   */
16870 #define USBD_PUBLISH_SOF_EN_Pos (31UL) /*!< Position of EN field. */
16871 #define USBD_PUBLISH_SOF_EN_Msk (0x1UL << USBD_PUBLISH_SOF_EN_Pos) /*!< Bit mask of EN field. */
16872 #define USBD_PUBLISH_SOF_EN_Disabled (0UL) /*!< Disable publishing */
16873 #define USBD_PUBLISH_SOF_EN_Enabled (1UL) /*!< Enable publishing */
16874 
16875 /* Bits 7..0 : DPPI channel that event SOF will publish to. */
16876 #define USBD_PUBLISH_SOF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16877 #define USBD_PUBLISH_SOF_CHIDX_Msk (0xFFUL << USBD_PUBLISH_SOF_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16878 
16879 /* Register: USBD_PUBLISH_USBEVENT */
16880 /* Description: Publish configuration for event USBEVENT */
16881 
16882 /* Bit 31 :   */
16883 #define USBD_PUBLISH_USBEVENT_EN_Pos (31UL) /*!< Position of EN field. */
16884 #define USBD_PUBLISH_USBEVENT_EN_Msk (0x1UL << USBD_PUBLISH_USBEVENT_EN_Pos) /*!< Bit mask of EN field. */
16885 #define USBD_PUBLISH_USBEVENT_EN_Disabled (0UL) /*!< Disable publishing */
16886 #define USBD_PUBLISH_USBEVENT_EN_Enabled (1UL) /*!< Enable publishing */
16887 
16888 /* Bits 7..0 : DPPI channel that event USBEVENT will publish to. */
16889 #define USBD_PUBLISH_USBEVENT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16890 #define USBD_PUBLISH_USBEVENT_CHIDX_Msk (0xFFUL << USBD_PUBLISH_USBEVENT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16891 
16892 /* Register: USBD_PUBLISH_EP0SETUP */
16893 /* Description: Publish configuration for event EP0SETUP */
16894 
16895 /* Bit 31 :   */
16896 #define USBD_PUBLISH_EP0SETUP_EN_Pos (31UL) /*!< Position of EN field. */
16897 #define USBD_PUBLISH_EP0SETUP_EN_Msk (0x1UL << USBD_PUBLISH_EP0SETUP_EN_Pos) /*!< Bit mask of EN field. */
16898 #define USBD_PUBLISH_EP0SETUP_EN_Disabled (0UL) /*!< Disable publishing */
16899 #define USBD_PUBLISH_EP0SETUP_EN_Enabled (1UL) /*!< Enable publishing */
16900 
16901 /* Bits 7..0 : DPPI channel that event EP0SETUP will publish to. */
16902 #define USBD_PUBLISH_EP0SETUP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16903 #define USBD_PUBLISH_EP0SETUP_CHIDX_Msk (0xFFUL << USBD_PUBLISH_EP0SETUP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16904 
16905 /* Register: USBD_PUBLISH_EPDATA */
16906 /* Description: Publish configuration for event EPDATA */
16907 
16908 /* Bit 31 :   */
16909 #define USBD_PUBLISH_EPDATA_EN_Pos (31UL) /*!< Position of EN field. */
16910 #define USBD_PUBLISH_EPDATA_EN_Msk (0x1UL << USBD_PUBLISH_EPDATA_EN_Pos) /*!< Bit mask of EN field. */
16911 #define USBD_PUBLISH_EPDATA_EN_Disabled (0UL) /*!< Disable publishing */
16912 #define USBD_PUBLISH_EPDATA_EN_Enabled (1UL) /*!< Enable publishing */
16913 
16914 /* Bits 7..0 : DPPI channel that event EPDATA will publish to. */
16915 #define USBD_PUBLISH_EPDATA_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
16916 #define USBD_PUBLISH_EPDATA_CHIDX_Msk (0xFFUL << USBD_PUBLISH_EPDATA_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
16917 
16918 /* Register: USBD_SHORTS */
16919 /* Description: Shortcuts between local events and tasks */
16920 
16921 /* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */
16922 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */
16923 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */
16924 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */
16925 #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */
16926 
16927 /* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */
16928 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */
16929 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */
16930 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
16931 #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
16932 
16933 /* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */
16934 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
16935 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */
16936 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
16937 #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
16938 
16939 /* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */
16940 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */
16941 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */
16942 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */
16943 #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */
16944 
16945 /* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */
16946 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */
16947 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */
16948 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */
16949 #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */
16950 
16951 /* Register: USBD_INTEN */
16952 /* Description: Enable or disable interrupt */
16953 
16954 /* Bit 24 : Enable or disable interrupt for event EPDATA */
16955 #define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
16956 #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
16957 #define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */
16958 #define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */
16959 
16960 /* Bit 23 : Enable or disable interrupt for event EP0SETUP */
16961 #define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
16962 #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
16963 #define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */
16964 #define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */
16965 
16966 /* Bit 22 : Enable or disable interrupt for event USBEVENT */
16967 #define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
16968 #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
16969 #define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */
16970 #define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */
16971 
16972 /* Bit 21 : Enable or disable interrupt for event SOF */
16973 #define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
16974 #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
16975 #define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */
16976 #define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */
16977 
16978 /* Bit 20 : Enable or disable interrupt for event ENDISOOUT */
16979 #define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
16980 #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
16981 #define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */
16982 #define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */
16983 
16984 /* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */
16985 #define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
16986 #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
16987 #define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */
16988 #define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */
16989 
16990 /* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */
16991 #define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
16992 #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
16993 #define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */
16994 #define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */
16995 
16996 /* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */
16997 #define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
16998 #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
16999 #define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */
17000 #define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */
17001 
17002 /* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */
17003 #define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
17004 #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
17005 #define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */
17006 #define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */
17007 
17008 /* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */
17009 #define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
17010 #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
17011 #define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */
17012 #define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */
17013 
17014 /* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */
17015 #define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
17016 #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
17017 #define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */
17018 #define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */
17019 
17020 /* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */
17021 #define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
17022 #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
17023 #define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */
17024 #define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */
17025 
17026 /* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */
17027 #define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
17028 #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
17029 #define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */
17030 #define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */
17031 
17032 /* Bit 11 : Enable or disable interrupt for event ENDISOIN */
17033 #define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
17034 #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
17035 #define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */
17036 #define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */
17037 
17038 /* Bit 10 : Enable or disable interrupt for event EP0DATADONE */
17039 #define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
17040 #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
17041 #define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */
17042 #define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */
17043 
17044 /* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */
17045 #define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
17046 #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
17047 #define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */
17048 #define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */
17049 
17050 /* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */
17051 #define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
17052 #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
17053 #define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */
17054 #define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */
17055 
17056 /* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */
17057 #define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
17058 #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
17059 #define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */
17060 #define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */
17061 
17062 /* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */
17063 #define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
17064 #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
17065 #define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */
17066 #define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */
17067 
17068 /* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */
17069 #define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
17070 #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
17071 #define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */
17072 #define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */
17073 
17074 /* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */
17075 #define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
17076 #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
17077 #define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */
17078 #define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */
17079 
17080 /* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */
17081 #define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
17082 #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
17083 #define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */
17084 #define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */
17085 
17086 /* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */
17087 #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
17088 #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
17089 #define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */
17090 #define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */
17091 
17092 /* Bit 1 : Enable or disable interrupt for event STARTED */
17093 #define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
17094 #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
17095 #define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */
17096 #define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */
17097 
17098 /* Bit 0 : Enable or disable interrupt for event USBRESET */
17099 #define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
17100 #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
17101 #define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */
17102 #define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */
17103 
17104 /* Register: USBD_INTENSET */
17105 /* Description: Enable interrupt */
17106 
17107 /* Bit 24 : Write '1' to enable interrupt for event EPDATA */
17108 #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
17109 #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
17110 #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */
17111 #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */
17112 #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */
17113 
17114 /* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */
17115 #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
17116 #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
17117 #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
17118 #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
17119 #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */
17120 
17121 /* Bit 22 : Write '1' to enable interrupt for event USBEVENT */
17122 #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
17123 #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
17124 #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
17125 #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
17126 #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */
17127 
17128 /* Bit 21 : Write '1' to enable interrupt for event SOF */
17129 #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
17130 #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
17131 #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
17132 #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
17133 #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */
17134 
17135 /* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */
17136 #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
17137 #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
17138 #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
17139 #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
17140 #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */
17141 
17142 /* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */
17143 #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
17144 #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
17145 #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
17146 #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
17147 #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */
17148 
17149 /* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */
17150 #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
17151 #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
17152 #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
17153 #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
17154 #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */
17155 
17156 /* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */
17157 #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
17158 #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
17159 #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
17160 #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
17161 #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */
17162 
17163 /* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */
17164 #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
17165 #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
17166 #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
17167 #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
17168 #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */
17169 
17170 /* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */
17171 #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
17172 #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
17173 #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
17174 #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
17175 #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */
17176 
17177 /* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */
17178 #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
17179 #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
17180 #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
17181 #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
17182 #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */
17183 
17184 /* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */
17185 #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
17186 #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
17187 #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
17188 #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
17189 #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */
17190 
17191 /* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */
17192 #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
17193 #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
17194 #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
17195 #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
17196 #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */
17197 
17198 /* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */
17199 #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
17200 #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
17201 #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
17202 #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
17203 #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */
17204 
17205 /* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */
17206 #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
17207 #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
17208 #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
17209 #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
17210 #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */
17211 
17212 /* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */
17213 #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
17214 #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
17215 #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
17216 #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
17217 #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */
17218 
17219 /* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */
17220 #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
17221 #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
17222 #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
17223 #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
17224 #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */
17225 
17226 /* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */
17227 #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
17228 #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
17229 #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
17230 #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
17231 #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */
17232 
17233 /* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */
17234 #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
17235 #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
17236 #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
17237 #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
17238 #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */
17239 
17240 /* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */
17241 #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
17242 #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
17243 #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
17244 #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
17245 #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */
17246 
17247 /* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */
17248 #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
17249 #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
17250 #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
17251 #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
17252 #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */
17253 
17254 /* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */
17255 #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
17256 #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
17257 #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
17258 #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
17259 #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */
17260 
17261 /* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */
17262 #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
17263 #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
17264 #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
17265 #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
17266 #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */
17267 
17268 /* Bit 1 : Write '1' to enable interrupt for event STARTED */
17269 #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */
17270 #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
17271 #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
17272 #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
17273 #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */
17274 
17275 /* Bit 0 : Write '1' to enable interrupt for event USBRESET */
17276 #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
17277 #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
17278 #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */
17279 #define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */
17280 #define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */
17281 
17282 /* Register: USBD_INTENCLR */
17283 /* Description: Disable interrupt */
17284 
17285 /* Bit 24 : Write '1' to disable interrupt for event EPDATA */
17286 #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
17287 #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
17288 #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */
17289 #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */
17290 #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */
17291 
17292 /* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */
17293 #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
17294 #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
17295 #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
17296 #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
17297 #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */
17298 
17299 /* Bit 22 : Write '1' to disable interrupt for event USBEVENT */
17300 #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
17301 #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
17302 #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
17303 #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
17304 #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */
17305 
17306 /* Bit 21 : Write '1' to disable interrupt for event SOF */
17307 #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
17308 #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
17309 #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
17310 #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
17311 #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */
17312 
17313 /* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */
17314 #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
17315 #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
17316 #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
17317 #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
17318 #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */
17319 
17320 /* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */
17321 #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
17322 #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
17323 #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
17324 #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
17325 #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */
17326 
17327 /* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */
17328 #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
17329 #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
17330 #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
17331 #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
17332 #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */
17333 
17334 /* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */
17335 #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
17336 #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
17337 #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
17338 #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
17339 #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */
17340 
17341 /* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */
17342 #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
17343 #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
17344 #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
17345 #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
17346 #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */
17347 
17348 /* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */
17349 #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
17350 #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
17351 #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
17352 #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
17353 #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */
17354 
17355 /* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */
17356 #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
17357 #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
17358 #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
17359 #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
17360 #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */
17361 
17362 /* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */
17363 #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
17364 #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
17365 #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
17366 #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
17367 #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */
17368 
17369 /* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */
17370 #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
17371 #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
17372 #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
17373 #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
17374 #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */
17375 
17376 /* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */
17377 #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
17378 #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
17379 #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
17380 #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
17381 #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */
17382 
17383 /* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */
17384 #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
17385 #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
17386 #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
17387 #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
17388 #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */
17389 
17390 /* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */
17391 #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
17392 #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
17393 #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
17394 #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
17395 #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */
17396 
17397 /* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */
17398 #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
17399 #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
17400 #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
17401 #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
17402 #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */
17403 
17404 /* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */
17405 #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
17406 #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
17407 #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
17408 #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
17409 #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */
17410 
17411 /* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */
17412 #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
17413 #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
17414 #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
17415 #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
17416 #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */
17417 
17418 /* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */
17419 #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
17420 #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
17421 #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
17422 #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
17423 #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */
17424 
17425 /* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */
17426 #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
17427 #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
17428 #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
17429 #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
17430 #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */
17431 
17432 /* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */
17433 #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
17434 #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
17435 #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
17436 #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
17437 #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */
17438 
17439 /* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */
17440 #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
17441 #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
17442 #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
17443 #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
17444 #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */
17445 
17446 /* Bit 1 : Write '1' to disable interrupt for event STARTED */
17447 #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */
17448 #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
17449 #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
17450 #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
17451 #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
17452 
17453 /* Bit 0 : Write '1' to disable interrupt for event USBRESET */
17454 #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
17455 #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
17456 #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */
17457 #define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */
17458 #define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */
17459 
17460 /* Register: USBD_EVENTCAUSE */
17461 /* Description: Details on what caused the USBEVENT event */
17462 
17463 /* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */
17464 #define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
17465 #define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
17466 #define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
17467 #define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */
17468 
17469 /* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
17470 #define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */
17471 #define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */
17472 #define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */
17473 #define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */
17474 
17475 /* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */
17476 #define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
17477 #define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
17478 #define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */
17479 #define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */
17480 
17481 /* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */
17482 #define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
17483 #define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
17484 #define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */
17485 #define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */
17486 
17487 /* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
17488 #define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */
17489 #define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */
17490 #define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */
17491 #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */
17492 
17493 /* Register: USBD_HALTED_EPIN */
17494 /* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
17495 
17496 /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
17497 #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
17498 #define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
17499 #define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
17500 #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
17501 
17502 /* Register: USBD_HALTED_EPOUT */
17503 /* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
17504 
17505 /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
17506 #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
17507 #define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
17508 #define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
17509 #define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
17510 
17511 /* Register: USBD_EPSTATUS */
17512 /* Description: Provides information on which endpoint's EasyDMA registers have been captured */
17513 
17514 /* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17515 #define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */
17516 #define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */
17517 #define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17518 #define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17519 
17520 /* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17521 #define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
17522 #define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
17523 #define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17524 #define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17525 
17526 /* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17527 #define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
17528 #define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
17529 #define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17530 #define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17531 
17532 /* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17533 #define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
17534 #define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
17535 #define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17536 #define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17537 
17538 /* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17539 #define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
17540 #define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
17541 #define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17542 #define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17543 
17544 /* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17545 #define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
17546 #define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
17547 #define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17548 #define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17549 
17550 /* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17551 #define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
17552 #define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
17553 #define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17554 #define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17555 
17556 /* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17557 #define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
17558 #define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
17559 #define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17560 #define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17561 
17562 /* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17563 #define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */
17564 #define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */
17565 #define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17566 #define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17567 
17568 /* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17569 #define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */
17570 #define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */
17571 #define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17572 #define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17573 
17574 /* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17575 #define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
17576 #define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
17577 #define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17578 #define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17579 
17580 /* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17581 #define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
17582 #define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
17583 #define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17584 #define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17585 
17586 /* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17587 #define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
17588 #define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
17589 #define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17590 #define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17591 
17592 /* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17593 #define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
17594 #define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
17595 #define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17596 #define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17597 
17598 /* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17599 #define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
17600 #define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
17601 #define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17602 #define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17603 
17604 /* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17605 #define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
17606 #define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
17607 #define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17608 #define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17609 
17610 /* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17611 #define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
17612 #define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
17613 #define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17614 #define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17615 
17616 /* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */
17617 #define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */
17618 #define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */
17619 #define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
17620 #define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
17621 
17622 /* Register: USBD_EPDATASTATUS */
17623 /* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */
17624 
17625 /* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
17626 #define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
17627 #define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
17628 #define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
17629 #define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17630 
17631 /* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
17632 #define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
17633 #define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
17634 #define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
17635 #define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17636 
17637 /* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
17638 #define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
17639 #define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
17640 #define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
17641 #define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17642 
17643 /* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
17644 #define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
17645 #define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
17646 #define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
17647 #define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17648 
17649 /* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
17650 #define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
17651 #define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
17652 #define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
17653 #define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17654 
17655 /* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
17656 #define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
17657 #define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
17658 #define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
17659 #define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17660 
17661 /* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
17662 #define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
17663 #define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
17664 #define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
17665 #define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17666 
17667 /* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
17668 #define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
17669 #define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
17670 #define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
17671 #define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17672 
17673 /* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
17674 #define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
17675 #define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
17676 #define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
17677 #define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17678 
17679 /* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
17680 #define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
17681 #define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
17682 #define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
17683 #define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17684 
17685 /* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
17686 #define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
17687 #define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
17688 #define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
17689 #define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17690 
17691 /* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
17692 #define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
17693 #define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
17694 #define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
17695 #define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17696 
17697 /* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
17698 #define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
17699 #define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
17700 #define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
17701 #define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17702 
17703 /* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
17704 #define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
17705 #define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
17706 #define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
17707 #define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
17708 
17709 /* Register: USBD_USBADDR */
17710 /* Description: Device USB address */
17711 
17712 /* Bits 6..0 : Device USB address */
17713 #define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
17714 #define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
17715 
17716 /* Register: USBD_BMREQUESTTYPE */
17717 /* Description: SETUP data, byte 0, bmRequestType */
17718 
17719 /* Bit 7 : Data transfer direction */
17720 #define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */
17721 #define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */
17722 #define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */
17723 #define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */
17724 
17725 /* Bits 6..5 : Data transfer type */
17726 #define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */
17727 #define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */
17728 #define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */
17729 #define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */
17730 #define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */
17731 
17732 /* Bits 4..0 : Data transfer type */
17733 #define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */
17734 #define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */
17735 #define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */
17736 #define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */
17737 #define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */
17738 #define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */
17739 
17740 /* Register: USBD_BREQUEST */
17741 /* Description: SETUP data, byte 1, bRequest */
17742 
17743 /* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */
17744 #define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */
17745 #define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */
17746 #define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */
17747 #define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */
17748 #define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */
17749 #define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */
17750 #define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */
17751 #define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */
17752 #define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */
17753 #define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */
17754 #define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */
17755 #define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */
17756 #define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */
17757 
17758 /* Register: USBD_WVALUEL */
17759 /* Description: SETUP data, byte 2, LSB of wValue */
17760 
17761 /* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
17762 #define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */
17763 #define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */
17764 
17765 /* Register: USBD_WVALUEH */
17766 /* Description: SETUP data, byte 3, MSB of wValue */
17767 
17768 /* Bits 7..0 : SETUP data, byte 3, MSB of wValue */
17769 #define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */
17770 #define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */
17771 
17772 /* Register: USBD_WINDEXL */
17773 /* Description: SETUP data, byte 4, LSB of wIndex */
17774 
17775 /* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */
17776 #define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */
17777 #define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */
17778 
17779 /* Register: USBD_WINDEXH */
17780 /* Description: SETUP data, byte 5, MSB of wIndex */
17781 
17782 /* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */
17783 #define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */
17784 #define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */
17785 
17786 /* Register: USBD_WLENGTHL */
17787 /* Description: SETUP data, byte 6, LSB of wLength */
17788 
17789 /* Bits 7..0 : SETUP data, byte 6, LSB of wLength */
17790 #define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */
17791 #define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */
17792 
17793 /* Register: USBD_WLENGTHH */
17794 /* Description: SETUP data, byte 7, MSB of wLength */
17795 
17796 /* Bits 7..0 : SETUP data, byte 7, MSB of wLength */
17797 #define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */
17798 #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */
17799 
17800 /* Register: USBD_SIZE_EPOUT */
17801 /* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */
17802 
17803 /* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */
17804 #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
17805 #define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
17806 
17807 /* Register: USBD_SIZE_ISOOUT */
17808 /* Description: Number of bytes received last on this ISO OUT data endpoint */
17809 
17810 /* Bit 16 : Zero-length data packet received */
17811 #define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
17812 #define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
17813 #define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
17814 #define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
17815 
17816 /* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */
17817 #define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
17818 #define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
17819 
17820 /* Register: USBD_ENABLE */
17821 /* Description: Enable USB */
17822 
17823 /* Bit 0 : Enable USB */
17824 #define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
17825 #define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
17826 #define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */
17827 #define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */
17828 
17829 /* Register: USBD_USBPULLUP */
17830 /* Description: Control of the USB pull-up */
17831 
17832 /* Bit 0 : Control of the USB pull-up on the D+ line */
17833 #define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */
17834 #define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
17835 #define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */
17836 #define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */
17837 
17838 /* Register: USBD_DPDMVALUE */
17839 /* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */
17840 
17841 /* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
17842 #define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
17843 #define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
17844 #define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */
17845 #define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
17846 #define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
17847 
17848 /* Register: USBD_DTOGGLE */
17849 /* Description: Data toggle control and status */
17850 
17851 /* Bits 9..8 : Data toggle value */
17852 #define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
17853 #define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
17854 #define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */
17855 #define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
17856 #define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
17857 
17858 /* Bit 7 : Selects IN or OUT endpoint */
17859 #define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */
17860 #define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */
17861 #define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */
17862 #define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */
17863 
17864 /* Bits 2..0 : Select bulk endpoint number */
17865 #define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */
17866 #define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */
17867 
17868 /* Register: USBD_EPINEN */
17869 /* Description: Endpoint IN enable */
17870 
17871 /* Bit 8 : Enable ISO IN endpoint */
17872 #define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
17873 #define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
17874 #define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */
17875 #define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */
17876 
17877 /* Bit 7 : Enable IN endpoint 7 */
17878 #define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
17879 #define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
17880 #define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
17881 #define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */
17882 
17883 /* Bit 6 : Enable IN endpoint 6 */
17884 #define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
17885 #define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
17886 #define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
17887 #define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
17888 
17889 /* Bit 5 : Enable IN endpoint 5 */
17890 #define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
17891 #define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
17892 #define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
17893 #define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
17894 
17895 /* Bit 4 : Enable IN endpoint 4 */
17896 #define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
17897 #define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
17898 #define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
17899 #define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
17900 
17901 /* Bit 3 : Enable IN endpoint 3 */
17902 #define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
17903 #define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
17904 #define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
17905 #define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
17906 
17907 /* Bit 2 : Enable IN endpoint 2 */
17908 #define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
17909 #define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
17910 #define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
17911 #define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
17912 
17913 /* Bit 1 : Enable IN endpoint 1 */
17914 #define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
17915 #define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
17916 #define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
17917 #define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
17918 
17919 /* Bit 0 : Enable IN endpoint 0 */
17920 #define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
17921 #define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
17922 #define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
17923 #define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
17924 
17925 /* Register: USBD_EPOUTEN */
17926 /* Description: Endpoint OUT enable */
17927 
17928 /* Bit 8 : Enable ISO OUT endpoint 8 */
17929 #define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
17930 #define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
17931 #define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */
17932 #define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */
17933 
17934 /* Bit 7 : Enable OUT endpoint 7 */
17935 #define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
17936 #define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
17937 #define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
17938 #define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
17939 
17940 /* Bit 6 : Enable OUT endpoint 6 */
17941 #define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
17942 #define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
17943 #define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
17944 #define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
17945 
17946 /* Bit 5 : Enable OUT endpoint 5 */
17947 #define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
17948 #define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
17949 #define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
17950 #define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
17951 
17952 /* Bit 4 : Enable OUT endpoint 4 */
17953 #define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
17954 #define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
17955 #define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
17956 #define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
17957 
17958 /* Bit 3 : Enable OUT endpoint 3 */
17959 #define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
17960 #define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
17961 #define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
17962 #define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
17963 
17964 /* Bit 2 : Enable OUT endpoint 2 */
17965 #define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
17966 #define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
17967 #define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
17968 #define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
17969 
17970 /* Bit 1 : Enable OUT endpoint 1 */
17971 #define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
17972 #define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
17973 #define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
17974 #define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
17975 
17976 /* Bit 0 : Enable OUT endpoint 0 */
17977 #define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
17978 #define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
17979 #define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
17980 #define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
17981 
17982 /* Register: USBD_EPSTALL */
17983 /* Description: STALL endpoints */
17984 
17985 /* Bit 8 : Stall selected endpoint */
17986 #define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
17987 #define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
17988 #define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */
17989 #define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */
17990 
17991 /* Bit 7 : Selects IN or OUT endpoint */
17992 #define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */
17993 #define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */
17994 #define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */
17995 #define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */
17996 
17997 /* Bits 2..0 : Select endpoint number */
17998 #define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */
17999 #define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */
18000 
18001 /* Register: USBD_ISOSPLIT */
18002 /* Description: Controls the split of ISO buffers */
18003 
18004 /* Bits 15..0 : Controls the split of ISO buffers */
18005 #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
18006 #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
18007 #define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */
18008 #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */
18009 
18010 /* Register: USBD_FRAMECNTR */
18011 /* Description: Returns the current value of the start of frame counter */
18012 
18013 /* Bits 10..0 : Returns the current value of the start of frame counter */
18014 #define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */
18015 #define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */
18016 
18017 /* Register: USBD_LOWPOWER */
18018 /* Description: Controls USBD peripheral low power mode during USB suspend */
18019 
18020 /* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */
18021 #define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */
18022 #define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */
18023 #define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */
18024 #define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */
18025 
18026 /* Register: USBD_ISOINCONFIG */
18027 /* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
18028 
18029 /* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
18030 #define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
18031 #define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
18032 #define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */
18033 #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */
18034 
18035 /* Register: USBD_EPIN_PTR */
18036 /* Description: Description cluster: Data pointer */
18037 
18038 /* Bits 31..0 : Data pointer */
18039 #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
18040 #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
18041 
18042 /* Register: USBD_EPIN_MAXCNT */
18043 /* Description: Description cluster: Maximum number of bytes to transfer */
18044 
18045 /* Bits 6..0 : Maximum number of bytes to transfer */
18046 #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
18047 #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
18048 
18049 /* Register: USBD_EPIN_AMOUNT */
18050 /* Description: Description cluster: Number of bytes transferred in the last transaction */
18051 
18052 /* Bits 6..0 : Number of bytes transferred in the last transaction */
18053 #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
18054 #define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
18055 
18056 /* Register: USBD_ISOIN_PTR */
18057 /* Description: Data pointer */
18058 
18059 /* Bits 31..0 : Data pointer */
18060 #define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
18061 #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
18062 
18063 /* Register: USBD_ISOIN_MAXCNT */
18064 /* Description: Maximum number of bytes to transfer */
18065 
18066 /* Bits 9..0 : Maximum number of bytes to transfer */
18067 #define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
18068 #define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
18069 
18070 /* Register: USBD_ISOIN_AMOUNT */
18071 /* Description: Number of bytes transferred in the last transaction */
18072 
18073 /* Bits 9..0 : Number of bytes transferred in the last transaction */
18074 #define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
18075 #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
18076 
18077 /* Register: USBD_EPOUT_PTR */
18078 /* Description: Description cluster: Data pointer */
18079 
18080 /* Bits 31..0 : Data pointer */
18081 #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
18082 #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
18083 
18084 /* Register: USBD_EPOUT_MAXCNT */
18085 /* Description: Description cluster: Maximum number of bytes to transfer */
18086 
18087 /* Bits 6..0 : Maximum number of bytes to transfer */
18088 #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
18089 #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
18090 
18091 /* Register: USBD_EPOUT_AMOUNT */
18092 /* Description: Description cluster: Number of bytes transferred in the last transaction */
18093 
18094 /* Bits 6..0 : Number of bytes transferred in the last transaction */
18095 #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
18096 #define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
18097 
18098 /* Register: USBD_ISOOUT_PTR */
18099 /* Description: Data pointer */
18100 
18101 /* Bits 31..0 : Data pointer */
18102 #define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
18103 #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
18104 
18105 /* Register: USBD_ISOOUT_MAXCNT */
18106 /* Description: Maximum number of bytes to transfer */
18107 
18108 /* Bits 9..0 : Maximum number of bytes to transfer */
18109 #define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
18110 #define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
18111 
18112 /* Register: USBD_ISOOUT_AMOUNT */
18113 /* Description: Number of bytes transferred in the last transaction */
18114 
18115 /* Bits 9..0 : Number of bytes transferred in the last transaction */
18116 #define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
18117 #define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
18118 
18119 
18120 /* Peripheral: USBREG */
18121 /* Description: USB Regulator 0 */
18122 
18123 /* Register: USBREG_EVENTS_USBDETECTED */
18124 /* Description: Voltage supply detected on VBUS */
18125 
18126 /* Bit 0 : Voltage supply detected on VBUS */
18127 #define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */
18128 #define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */
18129 #define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */
18130 #define USBREG_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */
18131 
18132 /* Register: USBREG_EVENTS_USBREMOVED */
18133 /* Description: Voltage supply removed from VBUS */
18134 
18135 /* Bit 0 : Voltage supply removed from VBUS */
18136 #define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */
18137 #define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */
18138 #define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */
18139 #define USBREG_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */
18140 
18141 /* Register: USBREG_EVENTS_USBPWRRDY */
18142 /* Description: USB 3.3 V supply ready */
18143 
18144 /* Bit 0 : USB 3.3 V supply ready */
18145 #define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */
18146 #define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */
18147 #define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */
18148 #define USBREG_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */
18149 
18150 /* Register: USBREG_PUBLISH_USBDETECTED */
18151 /* Description: Publish configuration for event USBDETECTED */
18152 
18153 /* Bit 31 :   */
18154 #define USBREG_PUBLISH_USBDETECTED_EN_Pos (31UL) /*!< Position of EN field. */
18155 #define USBREG_PUBLISH_USBDETECTED_EN_Msk (0x1UL << USBREG_PUBLISH_USBDETECTED_EN_Pos) /*!< Bit mask of EN field. */
18156 #define USBREG_PUBLISH_USBDETECTED_EN_Disabled (0UL) /*!< Disable publishing */
18157 #define USBREG_PUBLISH_USBDETECTED_EN_Enabled (1UL) /*!< Enable publishing */
18158 
18159 /* Bits 7..0 : DPPI channel that event USBDETECTED will publish to. */
18160 #define USBREG_PUBLISH_USBDETECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
18161 #define USBREG_PUBLISH_USBDETECTED_CHIDX_Msk (0xFFUL << USBREG_PUBLISH_USBDETECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
18162 
18163 /* Register: USBREG_PUBLISH_USBREMOVED */
18164 /* Description: Publish configuration for event USBREMOVED */
18165 
18166 /* Bit 31 :   */
18167 #define USBREG_PUBLISH_USBREMOVED_EN_Pos (31UL) /*!< Position of EN field. */
18168 #define USBREG_PUBLISH_USBREMOVED_EN_Msk (0x1UL << USBREG_PUBLISH_USBREMOVED_EN_Pos) /*!< Bit mask of EN field. */
18169 #define USBREG_PUBLISH_USBREMOVED_EN_Disabled (0UL) /*!< Disable publishing */
18170 #define USBREG_PUBLISH_USBREMOVED_EN_Enabled (1UL) /*!< Enable publishing */
18171 
18172 /* Bits 7..0 : DPPI channel that event USBREMOVED will publish to. */
18173 #define USBREG_PUBLISH_USBREMOVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
18174 #define USBREG_PUBLISH_USBREMOVED_CHIDX_Msk (0xFFUL << USBREG_PUBLISH_USBREMOVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
18175 
18176 /* Register: USBREG_PUBLISH_USBPWRRDY */
18177 /* Description: Publish configuration for event USBPWRRDY */
18178 
18179 /* Bit 31 :   */
18180 #define USBREG_PUBLISH_USBPWRRDY_EN_Pos (31UL) /*!< Position of EN field. */
18181 #define USBREG_PUBLISH_USBPWRRDY_EN_Msk (0x1UL << USBREG_PUBLISH_USBPWRRDY_EN_Pos) /*!< Bit mask of EN field. */
18182 #define USBREG_PUBLISH_USBPWRRDY_EN_Disabled (0UL) /*!< Disable publishing */
18183 #define USBREG_PUBLISH_USBPWRRDY_EN_Enabled (1UL) /*!< Enable publishing */
18184 
18185 /* Bits 7..0 : DPPI channel that event USBPWRRDY will publish to. */
18186 #define USBREG_PUBLISH_USBPWRRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
18187 #define USBREG_PUBLISH_USBPWRRDY_CHIDX_Msk (0xFFUL << USBREG_PUBLISH_USBPWRRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
18188 
18189 /* Register: USBREG_INTEN */
18190 /* Description: Enable or disable interrupt */
18191 
18192 /* Bit 2 : Enable or disable interrupt for event USBPWRRDY */
18193 #define USBREG_INTEN_USBPWRRDY_Pos (2UL) /*!< Position of USBPWRRDY field. */
18194 #define USBREG_INTEN_USBPWRRDY_Msk (0x1UL << USBREG_INTEN_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
18195 #define USBREG_INTEN_USBPWRRDY_Disabled (0UL) /*!< Disable */
18196 #define USBREG_INTEN_USBPWRRDY_Enabled (1UL) /*!< Enable */
18197 
18198 /* Bit 1 : Enable or disable interrupt for event USBREMOVED */
18199 #define USBREG_INTEN_USBREMOVED_Pos (1UL) /*!< Position of USBREMOVED field. */
18200 #define USBREG_INTEN_USBREMOVED_Msk (0x1UL << USBREG_INTEN_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
18201 #define USBREG_INTEN_USBREMOVED_Disabled (0UL) /*!< Disable */
18202 #define USBREG_INTEN_USBREMOVED_Enabled (1UL) /*!< Enable */
18203 
18204 /* Bit 0 : Enable or disable interrupt for event USBDETECTED */
18205 #define USBREG_INTEN_USBDETECTED_Pos (0UL) /*!< Position of USBDETECTED field. */
18206 #define USBREG_INTEN_USBDETECTED_Msk (0x1UL << USBREG_INTEN_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
18207 #define USBREG_INTEN_USBDETECTED_Disabled (0UL) /*!< Disable */
18208 #define USBREG_INTEN_USBDETECTED_Enabled (1UL) /*!< Enable */
18209 
18210 /* Register: USBREG_INTENSET */
18211 /* Description: Enable interrupt */
18212 
18213 /* Bit 2 : Write '1' to enable interrupt for event USBPWRRDY */
18214 #define USBREG_INTENSET_USBPWRRDY_Pos (2UL) /*!< Position of USBPWRRDY field. */
18215 #define USBREG_INTENSET_USBPWRRDY_Msk (0x1UL << USBREG_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
18216 #define USBREG_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
18217 #define USBREG_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
18218 #define USBREG_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */
18219 
18220 /* Bit 1 : Write '1' to enable interrupt for event USBREMOVED */
18221 #define USBREG_INTENSET_USBREMOVED_Pos (1UL) /*!< Position of USBREMOVED field. */
18222 #define USBREG_INTENSET_USBREMOVED_Msk (0x1UL << USBREG_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
18223 #define USBREG_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
18224 #define USBREG_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
18225 #define USBREG_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */
18226 
18227 /* Bit 0 : Write '1' to enable interrupt for event USBDETECTED */
18228 #define USBREG_INTENSET_USBDETECTED_Pos (0UL) /*!< Position of USBDETECTED field. */
18229 #define USBREG_INTENSET_USBDETECTED_Msk (0x1UL << USBREG_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
18230 #define USBREG_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
18231 #define USBREG_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
18232 #define USBREG_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */
18233 
18234 /* Register: USBREG_INTENCLR */
18235 /* Description: Disable interrupt */
18236 
18237 /* Bit 2 : Write '1' to disable interrupt for event USBPWRRDY */
18238 #define USBREG_INTENCLR_USBPWRRDY_Pos (2UL) /*!< Position of USBPWRRDY field. */
18239 #define USBREG_INTENCLR_USBPWRRDY_Msk (0x1UL << USBREG_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
18240 #define USBREG_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
18241 #define USBREG_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
18242 #define USBREG_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */
18243 
18244 /* Bit 1 : Write '1' to disable interrupt for event USBREMOVED */
18245 #define USBREG_INTENCLR_USBREMOVED_Pos (1UL) /*!< Position of USBREMOVED field. */
18246 #define USBREG_INTENCLR_USBREMOVED_Msk (0x1UL << USBREG_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
18247 #define USBREG_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
18248 #define USBREG_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
18249 #define USBREG_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */
18250 
18251 /* Bit 0 : Write '1' to disable interrupt for event USBDETECTED */
18252 #define USBREG_INTENCLR_USBDETECTED_Pos (0UL) /*!< Position of USBDETECTED field. */
18253 #define USBREG_INTENCLR_USBDETECTED_Msk (0x1UL << USBREG_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
18254 #define USBREG_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
18255 #define USBREG_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
18256 #define USBREG_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */
18257 
18258 /* Register: USBREG_USBREGSTATUS */
18259 /* Description: USB supply status */
18260 
18261 /* Bit 1 : USB supply output settling time elapsed */
18262 #define USBREG_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */
18263 #define USBREG_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << USBREG_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */
18264 #define USBREG_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */
18265 #define USBREG_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */
18266 
18267 /* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */
18268 #define USBREG_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */
18269 #define USBREG_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << USBREG_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */
18270 #define USBREG_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */
18271 #define USBREG_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */
18272 
18273 
18274 /* Peripheral: VMC */
18275 /* Description: Volatile Memory controller 0 */
18276 
18277 /* Register: VMC_RAM_POWER */
18278 /* Description: Description cluster: RAM[n] power control register */
18279 
18280 /* Bit 31 : Keep retention on RAM section S15 of RAM[n] when RAM section is switched off */
18281 #define VMC_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
18282 #define VMC_RAM_POWER_S15RETENTION_Msk (0x1UL << VMC_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
18283 #define VMC_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */
18284 #define VMC_RAM_POWER_S15RETENTION_On (1UL) /*!< On */
18285 
18286 /* Bit 30 : Keep retention on RAM section S14 of RAM[n] when RAM section is switched off */
18287 #define VMC_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
18288 #define VMC_RAM_POWER_S14RETENTION_Msk (0x1UL << VMC_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
18289 #define VMC_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */
18290 #define VMC_RAM_POWER_S14RETENTION_On (1UL) /*!< On */
18291 
18292 /* Bit 29 : Keep retention on RAM section S13 of RAM[n] when RAM section is switched off */
18293 #define VMC_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
18294 #define VMC_RAM_POWER_S13RETENTION_Msk (0x1UL << VMC_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
18295 #define VMC_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */
18296 #define VMC_RAM_POWER_S13RETENTION_On (1UL) /*!< On */
18297 
18298 /* Bit 28 : Keep retention on RAM section S12 of RAM[n] when RAM section is switched off */
18299 #define VMC_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
18300 #define VMC_RAM_POWER_S12RETENTION_Msk (0x1UL << VMC_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
18301 #define VMC_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */
18302 #define VMC_RAM_POWER_S12RETENTION_On (1UL) /*!< On */
18303 
18304 /* Bit 27 : Keep retention on RAM section S11 of RAM[n] when RAM section is switched off */
18305 #define VMC_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
18306 #define VMC_RAM_POWER_S11RETENTION_Msk (0x1UL << VMC_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
18307 #define VMC_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */
18308 #define VMC_RAM_POWER_S11RETENTION_On (1UL) /*!< On */
18309 
18310 /* Bit 26 : Keep retention on RAM section S10 of RAM[n] when RAM section is switched off */
18311 #define VMC_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
18312 #define VMC_RAM_POWER_S10RETENTION_Msk (0x1UL << VMC_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
18313 #define VMC_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */
18314 #define VMC_RAM_POWER_S10RETENTION_On (1UL) /*!< On */
18315 
18316 /* Bit 25 : Keep retention on RAM section S9 of RAM[n] when RAM section is switched off */
18317 #define VMC_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
18318 #define VMC_RAM_POWER_S9RETENTION_Msk (0x1UL << VMC_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
18319 #define VMC_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */
18320 #define VMC_RAM_POWER_S9RETENTION_On (1UL) /*!< On */
18321 
18322 /* Bit 24 : Keep retention on RAM section S8 of RAM[n] when RAM section is switched off */
18323 #define VMC_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
18324 #define VMC_RAM_POWER_S8RETENTION_Msk (0x1UL << VMC_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
18325 #define VMC_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */
18326 #define VMC_RAM_POWER_S8RETENTION_On (1UL) /*!< On */
18327 
18328 /* Bit 23 : Keep retention on RAM section S7 of RAM[n] when RAM section is switched off */
18329 #define VMC_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
18330 #define VMC_RAM_POWER_S7RETENTION_Msk (0x1UL << VMC_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
18331 #define VMC_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */
18332 #define VMC_RAM_POWER_S7RETENTION_On (1UL) /*!< On */
18333 
18334 /* Bit 22 : Keep retention on RAM section S6 of RAM[n] when RAM section is switched off */
18335 #define VMC_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
18336 #define VMC_RAM_POWER_S6RETENTION_Msk (0x1UL << VMC_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
18337 #define VMC_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */
18338 #define VMC_RAM_POWER_S6RETENTION_On (1UL) /*!< On */
18339 
18340 /* Bit 21 : Keep retention on RAM section S5 of RAM[n] when RAM section is switched off */
18341 #define VMC_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
18342 #define VMC_RAM_POWER_S5RETENTION_Msk (0x1UL << VMC_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
18343 #define VMC_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */
18344 #define VMC_RAM_POWER_S5RETENTION_On (1UL) /*!< On */
18345 
18346 /* Bit 20 : Keep retention on RAM section S4 of RAM[n] when RAM section is switched off */
18347 #define VMC_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
18348 #define VMC_RAM_POWER_S4RETENTION_Msk (0x1UL << VMC_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
18349 #define VMC_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */
18350 #define VMC_RAM_POWER_S4RETENTION_On (1UL) /*!< On */
18351 
18352 /* Bit 19 : Keep retention on RAM section S3 of RAM[n] when RAM section is switched off */
18353 #define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
18354 #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
18355 #define VMC_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
18356 #define VMC_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
18357 
18358 /* Bit 18 : Keep retention on RAM section S2 of RAM[n] when RAM section is switched off */
18359 #define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
18360 #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
18361 #define VMC_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
18362 #define VMC_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
18363 
18364 /* Bit 17 : Keep retention on RAM section S1 of RAM[n] when RAM section is switched off */
18365 #define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
18366 #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
18367 #define VMC_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
18368 #define VMC_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
18369 
18370 /* Bit 16 : Keep retention on RAM section S0 of RAM[n] when RAM section is switched off */
18371 #define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
18372 #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
18373 #define VMC_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
18374 #define VMC_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
18375 
18376 /* Bit 15 : Keep RAM section S15 of RAM[n] on or off in System ON mode */
18377 #define VMC_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
18378 #define VMC_RAM_POWER_S15POWER_Msk (0x1UL << VMC_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
18379 #define VMC_RAM_POWER_S15POWER_Off (0UL) /*!< Off */
18380 #define VMC_RAM_POWER_S15POWER_On (1UL) /*!< On */
18381 
18382 /* Bit 14 : Keep RAM section S14 of RAM[n] on or off in System ON mode */
18383 #define VMC_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
18384 #define VMC_RAM_POWER_S14POWER_Msk (0x1UL << VMC_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
18385 #define VMC_RAM_POWER_S14POWER_Off (0UL) /*!< Off */
18386 #define VMC_RAM_POWER_S14POWER_On (1UL) /*!< On */
18387 
18388 /* Bit 13 : Keep RAM section S13 of RAM[n] on or off in System ON mode */
18389 #define VMC_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
18390 #define VMC_RAM_POWER_S13POWER_Msk (0x1UL << VMC_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
18391 #define VMC_RAM_POWER_S13POWER_Off (0UL) /*!< Off */
18392 #define VMC_RAM_POWER_S13POWER_On (1UL) /*!< On */
18393 
18394 /* Bit 12 : Keep RAM section S12 of RAM[n] on or off in System ON mode */
18395 #define VMC_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
18396 #define VMC_RAM_POWER_S12POWER_Msk (0x1UL << VMC_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
18397 #define VMC_RAM_POWER_S12POWER_Off (0UL) /*!< Off */
18398 #define VMC_RAM_POWER_S12POWER_On (1UL) /*!< On */
18399 
18400 /* Bit 11 : Keep RAM section S11 of RAM[n] on or off in System ON mode */
18401 #define VMC_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
18402 #define VMC_RAM_POWER_S11POWER_Msk (0x1UL << VMC_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
18403 #define VMC_RAM_POWER_S11POWER_Off (0UL) /*!< Off */
18404 #define VMC_RAM_POWER_S11POWER_On (1UL) /*!< On */
18405 
18406 /* Bit 10 : Keep RAM section S10 of RAM[n] on or off in System ON mode */
18407 #define VMC_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
18408 #define VMC_RAM_POWER_S10POWER_Msk (0x1UL << VMC_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
18409 #define VMC_RAM_POWER_S10POWER_Off (0UL) /*!< Off */
18410 #define VMC_RAM_POWER_S10POWER_On (1UL) /*!< On */
18411 
18412 /* Bit 9 : Keep RAM section S9 of RAM[n] on or off in System ON mode */
18413 #define VMC_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
18414 #define VMC_RAM_POWER_S9POWER_Msk (0x1UL << VMC_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
18415 #define VMC_RAM_POWER_S9POWER_Off (0UL) /*!< Off */
18416 #define VMC_RAM_POWER_S9POWER_On (1UL) /*!< On */
18417 
18418 /* Bit 8 : Keep RAM section S8 of RAM[n] on or off in System ON mode */
18419 #define VMC_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
18420 #define VMC_RAM_POWER_S8POWER_Msk (0x1UL << VMC_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
18421 #define VMC_RAM_POWER_S8POWER_Off (0UL) /*!< Off */
18422 #define VMC_RAM_POWER_S8POWER_On (1UL) /*!< On */
18423 
18424 /* Bit 7 : Keep RAM section S7 of RAM[n] on or off in System ON mode */
18425 #define VMC_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
18426 #define VMC_RAM_POWER_S7POWER_Msk (0x1UL << VMC_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
18427 #define VMC_RAM_POWER_S7POWER_Off (0UL) /*!< Off */
18428 #define VMC_RAM_POWER_S7POWER_On (1UL) /*!< On */
18429 
18430 /* Bit 6 : Keep RAM section S6 of RAM[n] on or off in System ON mode */
18431 #define VMC_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
18432 #define VMC_RAM_POWER_S6POWER_Msk (0x1UL << VMC_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
18433 #define VMC_RAM_POWER_S6POWER_Off (0UL) /*!< Off */
18434 #define VMC_RAM_POWER_S6POWER_On (1UL) /*!< On */
18435 
18436 /* Bit 5 : Keep RAM section S5 of RAM[n] on or off in System ON mode */
18437 #define VMC_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
18438 #define VMC_RAM_POWER_S5POWER_Msk (0x1UL << VMC_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
18439 #define VMC_RAM_POWER_S5POWER_Off (0UL) /*!< Off */
18440 #define VMC_RAM_POWER_S5POWER_On (1UL) /*!< On */
18441 
18442 /* Bit 4 : Keep RAM section S4 of RAM[n] on or off in System ON mode */
18443 #define VMC_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
18444 #define VMC_RAM_POWER_S4POWER_Msk (0x1UL << VMC_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
18445 #define VMC_RAM_POWER_S4POWER_Off (0UL) /*!< Off */
18446 #define VMC_RAM_POWER_S4POWER_On (1UL) /*!< On */
18447 
18448 /* Bit 3 : Keep RAM section S3 of RAM[n] on or off in System ON mode */
18449 #define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
18450 #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
18451 #define VMC_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
18452 #define VMC_RAM_POWER_S3POWER_On (1UL) /*!< On */
18453 
18454 /* Bit 2 : Keep RAM section S2 of RAM[n] on or off in System ON mode */
18455 #define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
18456 #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
18457 #define VMC_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
18458 #define VMC_RAM_POWER_S2POWER_On (1UL) /*!< On */
18459 
18460 /* Bit 1 : Keep RAM section S1 of RAM[n] on or off in System ON mode */
18461 #define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
18462 #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
18463 #define VMC_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
18464 #define VMC_RAM_POWER_S1POWER_On (1UL) /*!< On */
18465 
18466 /* Bit 0 : Keep RAM section S0 of RAM[n] on or off in System ON mode */
18467 #define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
18468 #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
18469 #define VMC_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
18470 #define VMC_RAM_POWER_S0POWER_On (1UL) /*!< On */
18471 
18472 /* Register: VMC_RAM_POWERSET */
18473 /* Description: Description cluster: RAM[n] power control set register */
18474 
18475 /* Bit 31 : Keep retention on RAM section S15 of RAM[n] when RAM section is switched off */
18476 #define VMC_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
18477 #define VMC_RAM_POWERSET_S15RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
18478 #define VMC_RAM_POWERSET_S15RETENTION_On (1UL) /*!< On */
18479 
18480 /* Bit 30 : Keep retention on RAM section S14 of RAM[n] when RAM section is switched off */
18481 #define VMC_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
18482 #define VMC_RAM_POWERSET_S14RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
18483 #define VMC_RAM_POWERSET_S14RETENTION_On (1UL) /*!< On */
18484 
18485 /* Bit 29 : Keep retention on RAM section S13 of RAM[n] when RAM section is switched off */
18486 #define VMC_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
18487 #define VMC_RAM_POWERSET_S13RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
18488 #define VMC_RAM_POWERSET_S13RETENTION_On (1UL) /*!< On */
18489 
18490 /* Bit 28 : Keep retention on RAM section S12 of RAM[n] when RAM section is switched off */
18491 #define VMC_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
18492 #define VMC_RAM_POWERSET_S12RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
18493 #define VMC_RAM_POWERSET_S12RETENTION_On (1UL) /*!< On */
18494 
18495 /* Bit 27 : Keep retention on RAM section S11 of RAM[n] when RAM section is switched off */
18496 #define VMC_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
18497 #define VMC_RAM_POWERSET_S11RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
18498 #define VMC_RAM_POWERSET_S11RETENTION_On (1UL) /*!< On */
18499 
18500 /* Bit 26 : Keep retention on RAM section S10 of RAM[n] when RAM section is switched off */
18501 #define VMC_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
18502 #define VMC_RAM_POWERSET_S10RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
18503 #define VMC_RAM_POWERSET_S10RETENTION_On (1UL) /*!< On */
18504 
18505 /* Bit 25 : Keep retention on RAM section S9 of RAM[n] when RAM section is switched off */
18506 #define VMC_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
18507 #define VMC_RAM_POWERSET_S9RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
18508 #define VMC_RAM_POWERSET_S9RETENTION_On (1UL) /*!< On */
18509 
18510 /* Bit 24 : Keep retention on RAM section S8 of RAM[n] when RAM section is switched off */
18511 #define VMC_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
18512 #define VMC_RAM_POWERSET_S8RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
18513 #define VMC_RAM_POWERSET_S8RETENTION_On (1UL) /*!< On */
18514 
18515 /* Bit 23 : Keep retention on RAM section S7 of RAM[n] when RAM section is switched off */
18516 #define VMC_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
18517 #define VMC_RAM_POWERSET_S7RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
18518 #define VMC_RAM_POWERSET_S7RETENTION_On (1UL) /*!< On */
18519 
18520 /* Bit 22 : Keep retention on RAM section S6 of RAM[n] when RAM section is switched off */
18521 #define VMC_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
18522 #define VMC_RAM_POWERSET_S6RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
18523 #define VMC_RAM_POWERSET_S6RETENTION_On (1UL) /*!< On */
18524 
18525 /* Bit 21 : Keep retention on RAM section S5 of RAM[n] when RAM section is switched off */
18526 #define VMC_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
18527 #define VMC_RAM_POWERSET_S5RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
18528 #define VMC_RAM_POWERSET_S5RETENTION_On (1UL) /*!< On */
18529 
18530 /* Bit 20 : Keep retention on RAM section S4 of RAM[n] when RAM section is switched off */
18531 #define VMC_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
18532 #define VMC_RAM_POWERSET_S4RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
18533 #define VMC_RAM_POWERSET_S4RETENTION_On (1UL) /*!< On */
18534 
18535 /* Bit 19 : Keep retention on RAM section S3 of RAM[n] when RAM section is switched off */
18536 #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
18537 #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
18538 #define VMC_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
18539 
18540 /* Bit 18 : Keep retention on RAM section S2 of RAM[n] when RAM section is switched off */
18541 #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
18542 #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
18543 #define VMC_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
18544 
18545 /* Bit 17 : Keep retention on RAM section S1 of RAM[n] when RAM section is switched off */
18546 #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
18547 #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
18548 #define VMC_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
18549 
18550 /* Bit 16 : Keep retention on RAM section S0 of RAM[n] when RAM section is switched off */
18551 #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
18552 #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
18553 #define VMC_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
18554 
18555 /* Bit 15 : Keep RAM section S15 of RAM[n] on or off in System ON mode */
18556 #define VMC_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
18557 #define VMC_RAM_POWERSET_S15POWER_Msk (0x1UL << VMC_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
18558 #define VMC_RAM_POWERSET_S15POWER_On (1UL) /*!< On */
18559 
18560 /* Bit 14 : Keep RAM section S14 of RAM[n] on or off in System ON mode */
18561 #define VMC_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
18562 #define VMC_RAM_POWERSET_S14POWER_Msk (0x1UL << VMC_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
18563 #define VMC_RAM_POWERSET_S14POWER_On (1UL) /*!< On */
18564 
18565 /* Bit 13 : Keep RAM section S13 of RAM[n] on or off in System ON mode */
18566 #define VMC_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
18567 #define VMC_RAM_POWERSET_S13POWER_Msk (0x1UL << VMC_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
18568 #define VMC_RAM_POWERSET_S13POWER_On (1UL) /*!< On */
18569 
18570 /* Bit 12 : Keep RAM section S12 of RAM[n] on or off in System ON mode */
18571 #define VMC_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
18572 #define VMC_RAM_POWERSET_S12POWER_Msk (0x1UL << VMC_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
18573 #define VMC_RAM_POWERSET_S12POWER_On (1UL) /*!< On */
18574 
18575 /* Bit 11 : Keep RAM section S11 of RAM[n] on or off in System ON mode */
18576 #define VMC_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
18577 #define VMC_RAM_POWERSET_S11POWER_Msk (0x1UL << VMC_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
18578 #define VMC_RAM_POWERSET_S11POWER_On (1UL) /*!< On */
18579 
18580 /* Bit 10 : Keep RAM section S10 of RAM[n] on or off in System ON mode */
18581 #define VMC_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
18582 #define VMC_RAM_POWERSET_S10POWER_Msk (0x1UL << VMC_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
18583 #define VMC_RAM_POWERSET_S10POWER_On (1UL) /*!< On */
18584 
18585 /* Bit 9 : Keep RAM section S9 of RAM[n] on or off in System ON mode */
18586 #define VMC_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
18587 #define VMC_RAM_POWERSET_S9POWER_Msk (0x1UL << VMC_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
18588 #define VMC_RAM_POWERSET_S9POWER_On (1UL) /*!< On */
18589 
18590 /* Bit 8 : Keep RAM section S8 of RAM[n] on or off in System ON mode */
18591 #define VMC_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
18592 #define VMC_RAM_POWERSET_S8POWER_Msk (0x1UL << VMC_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
18593 #define VMC_RAM_POWERSET_S8POWER_On (1UL) /*!< On */
18594 
18595 /* Bit 7 : Keep RAM section S7 of RAM[n] on or off in System ON mode */
18596 #define VMC_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
18597 #define VMC_RAM_POWERSET_S7POWER_Msk (0x1UL << VMC_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
18598 #define VMC_RAM_POWERSET_S7POWER_On (1UL) /*!< On */
18599 
18600 /* Bit 6 : Keep RAM section S6 of RAM[n] on or off in System ON mode */
18601 #define VMC_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
18602 #define VMC_RAM_POWERSET_S6POWER_Msk (0x1UL << VMC_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
18603 #define VMC_RAM_POWERSET_S6POWER_On (1UL) /*!< On */
18604 
18605 /* Bit 5 : Keep RAM section S5 of RAM[n] on or off in System ON mode */
18606 #define VMC_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
18607 #define VMC_RAM_POWERSET_S5POWER_Msk (0x1UL << VMC_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
18608 #define VMC_RAM_POWERSET_S5POWER_On (1UL) /*!< On */
18609 
18610 /* Bit 4 : Keep RAM section S4 of RAM[n] on or off in System ON mode */
18611 #define VMC_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
18612 #define VMC_RAM_POWERSET_S4POWER_Msk (0x1UL << VMC_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
18613 #define VMC_RAM_POWERSET_S4POWER_On (1UL) /*!< On */
18614 
18615 /* Bit 3 : Keep RAM section S3 of RAM[n] on or off in System ON mode */
18616 #define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
18617 #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
18618 #define VMC_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
18619 
18620 /* Bit 2 : Keep RAM section S2 of RAM[n] on or off in System ON mode */
18621 #define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
18622 #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
18623 #define VMC_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
18624 
18625 /* Bit 1 : Keep RAM section S1 of RAM[n] on or off in System ON mode */
18626 #define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
18627 #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
18628 #define VMC_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
18629 
18630 /* Bit 0 : Keep RAM section S0 of RAM[n] on or off in System ON mode */
18631 #define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
18632 #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
18633 #define VMC_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
18634 
18635 /* Register: VMC_RAM_POWERCLR */
18636 /* Description: Description cluster: RAM[n] power control clear register */
18637 
18638 /* Bit 31 : Keep retention on RAM section S15 of RAM[n] when RAM section is switched off */
18639 #define VMC_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
18640 #define VMC_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
18641 #define VMC_RAM_POWERCLR_S15RETENTION_Off (1UL) /*!< Off */
18642 
18643 /* Bit 30 : Keep retention on RAM section S14 of RAM[n] when RAM section is switched off */
18644 #define VMC_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
18645 #define VMC_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
18646 #define VMC_RAM_POWERCLR_S14RETENTION_Off (1UL) /*!< Off */
18647 
18648 /* Bit 29 : Keep retention on RAM section S13 of RAM[n] when RAM section is switched off */
18649 #define VMC_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
18650 #define VMC_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
18651 #define VMC_RAM_POWERCLR_S13RETENTION_Off (1UL) /*!< Off */
18652 
18653 /* Bit 28 : Keep retention on RAM section S12 of RAM[n] when RAM section is switched off */
18654 #define VMC_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
18655 #define VMC_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
18656 #define VMC_RAM_POWERCLR_S12RETENTION_Off (1UL) /*!< Off */
18657 
18658 /* Bit 27 : Keep retention on RAM section S11 of RAM[n] when RAM section is switched off */
18659 #define VMC_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
18660 #define VMC_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
18661 #define VMC_RAM_POWERCLR_S11RETENTION_Off (1UL) /*!< Off */
18662 
18663 /* Bit 26 : Keep retention on RAM section S10 of RAM[n] when RAM section is switched off */
18664 #define VMC_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
18665 #define VMC_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
18666 #define VMC_RAM_POWERCLR_S10RETENTION_Off (1UL) /*!< Off */
18667 
18668 /* Bit 25 : Keep retention on RAM section S9 of RAM[n] when RAM section is switched off */
18669 #define VMC_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
18670 #define VMC_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
18671 #define VMC_RAM_POWERCLR_S9RETENTION_Off (1UL) /*!< Off */
18672 
18673 /* Bit 24 : Keep retention on RAM section S8 of RAM[n] when RAM section is switched off */
18674 #define VMC_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
18675 #define VMC_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
18676 #define VMC_RAM_POWERCLR_S8RETENTION_Off (1UL) /*!< Off */
18677 
18678 /* Bit 23 : Keep retention on RAM section S7 of RAM[n] when RAM section is switched off */
18679 #define VMC_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
18680 #define VMC_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
18681 #define VMC_RAM_POWERCLR_S7RETENTION_Off (1UL) /*!< Off */
18682 
18683 /* Bit 22 : Keep retention on RAM section S6 of RAM[n] when RAM section is switched off */
18684 #define VMC_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
18685 #define VMC_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
18686 #define VMC_RAM_POWERCLR_S6RETENTION_Off (1UL) /*!< Off */
18687 
18688 /* Bit 21 : Keep retention on RAM section S5 of RAM[n] when RAM section is switched off */
18689 #define VMC_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
18690 #define VMC_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
18691 #define VMC_RAM_POWERCLR_S5RETENTION_Off (1UL) /*!< Off */
18692 
18693 /* Bit 20 : Keep retention on RAM section S4 of RAM[n] when RAM section is switched off */
18694 #define VMC_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
18695 #define VMC_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
18696 #define VMC_RAM_POWERCLR_S4RETENTION_Off (1UL) /*!< Off */
18697 
18698 /* Bit 19 : Keep retention on RAM section S3 of RAM[n] when RAM section is switched off */
18699 #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
18700 #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
18701 #define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
18702 
18703 /* Bit 18 : Keep retention on RAM section S2 of RAM[n] when RAM section is switched off */
18704 #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
18705 #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
18706 #define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
18707 
18708 /* Bit 17 : Keep retention on RAM section S1 of RAM[n] when RAM section is switched off */
18709 #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
18710 #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
18711 #define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
18712 
18713 /* Bit 16 : Keep retention on RAM section S0 of RAM[n] when RAM section is switched off */
18714 #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
18715 #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
18716 #define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
18717 
18718 /* Bit 15 : Keep RAM section S15 of RAM[n] on or off in System ON mode */
18719 #define VMC_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
18720 #define VMC_RAM_POWERCLR_S15POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
18721 #define VMC_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */
18722 
18723 /* Bit 14 : Keep RAM section S14 of RAM[n] on or off in System ON mode */
18724 #define VMC_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
18725 #define VMC_RAM_POWERCLR_S14POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
18726 #define VMC_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */
18727 
18728 /* Bit 13 : Keep RAM section S13 of RAM[n] on or off in System ON mode */
18729 #define VMC_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
18730 #define VMC_RAM_POWERCLR_S13POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
18731 #define VMC_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */
18732 
18733 /* Bit 12 : Keep RAM section S12 of RAM[n] on or off in System ON mode */
18734 #define VMC_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
18735 #define VMC_RAM_POWERCLR_S12POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
18736 #define VMC_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */
18737 
18738 /* Bit 11 : Keep RAM section S11 of RAM[n] on or off in System ON mode */
18739 #define VMC_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
18740 #define VMC_RAM_POWERCLR_S11POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
18741 #define VMC_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */
18742 
18743 /* Bit 10 : Keep RAM section S10 of RAM[n] on or off in System ON mode */
18744 #define VMC_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
18745 #define VMC_RAM_POWERCLR_S10POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
18746 #define VMC_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */
18747 
18748 /* Bit 9 : Keep RAM section S9 of RAM[n] on or off in System ON mode */
18749 #define VMC_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
18750 #define VMC_RAM_POWERCLR_S9POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
18751 #define VMC_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */
18752 
18753 /* Bit 8 : Keep RAM section S8 of RAM[n] on or off in System ON mode */
18754 #define VMC_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
18755 #define VMC_RAM_POWERCLR_S8POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
18756 #define VMC_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */
18757 
18758 /* Bit 7 : Keep RAM section S7 of RAM[n] on or off in System ON mode */
18759 #define VMC_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
18760 #define VMC_RAM_POWERCLR_S7POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
18761 #define VMC_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */
18762 
18763 /* Bit 6 : Keep RAM section S6 of RAM[n] on or off in System ON mode */
18764 #define VMC_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
18765 #define VMC_RAM_POWERCLR_S6POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
18766 #define VMC_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */
18767 
18768 /* Bit 5 : Keep RAM section S5 of RAM[n] on or off in System ON mode */
18769 #define VMC_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
18770 #define VMC_RAM_POWERCLR_S5POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
18771 #define VMC_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */
18772 
18773 /* Bit 4 : Keep RAM section S4 of RAM[n] on or off in System ON mode */
18774 #define VMC_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
18775 #define VMC_RAM_POWERCLR_S4POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
18776 #define VMC_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */
18777 
18778 /* Bit 3 : Keep RAM section S3 of RAM[n] on or off in System ON mode */
18779 #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
18780 #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
18781 #define VMC_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
18782 
18783 /* Bit 2 : Keep RAM section S2 of RAM[n] on or off in System ON mode */
18784 #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
18785 #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
18786 #define VMC_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
18787 
18788 /* Bit 1 : Keep RAM section S1 of RAM[n] on or off in System ON mode */
18789 #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
18790 #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
18791 #define VMC_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
18792 
18793 /* Bit 0 : Keep RAM section S0 of RAM[n] on or off in System ON mode */
18794 #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
18795 #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
18796 #define VMC_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
18797 
18798 
18799 /* Peripheral: WDT */
18800 /* Description: Watchdog Timer 0 */
18801 
18802 /* Register: WDT_TASKS_START */
18803 /* Description: Start WDT */
18804 
18805 /* Bit 0 : Start WDT */
18806 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
18807 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
18808 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
18809 
18810 /* Register: WDT_TASKS_STOP */
18811 /* Description: Stop WDT */
18812 
18813 /* Bit 0 : Stop WDT */
18814 #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
18815 #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
18816 #define WDT_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
18817 
18818 /* Register: WDT_SUBSCRIBE_START */
18819 /* Description: Subscribe configuration for task START */
18820 
18821 /* Bit 31 :   */
18822 #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
18823 #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
18824 #define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
18825 #define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
18826 
18827 /* Bits 7..0 : DPPI channel that task START will subscribe to */
18828 #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
18829 #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
18830 
18831 /* Register: WDT_SUBSCRIBE_STOP */
18832 /* Description: Subscribe configuration for task STOP */
18833 
18834 /* Bit 31 :   */
18835 #define WDT_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
18836 #define WDT_SUBSCRIBE_STOP_EN_Msk (0x1UL << WDT_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
18837 #define WDT_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
18838 #define WDT_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
18839 
18840 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
18841 #define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
18842 #define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
18843 
18844 /* Register: WDT_EVENTS_TIMEOUT */
18845 /* Description: Watchdog timeout */
18846 
18847 /* Bit 0 : Watchdog timeout */
18848 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
18849 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
18850 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
18851 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
18852 
18853 /* Register: WDT_EVENTS_STOPPED */
18854 /* Description: Watchdog stopped */
18855 
18856 /* Bit 0 : Watchdog stopped */
18857 #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
18858 #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
18859 #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
18860 #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
18861 
18862 /* Register: WDT_PUBLISH_TIMEOUT */
18863 /* Description: Publish configuration for event TIMEOUT */
18864 
18865 /* Bit 31 :   */
18866 #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */
18867 #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */
18868 #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */
18869 #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */
18870 
18871 /* Bits 7..0 : DPPI channel that event TIMEOUT will publish to. */
18872 #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
18873 #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
18874 
18875 /* Register: WDT_PUBLISH_STOPPED */
18876 /* Description: Publish configuration for event STOPPED */
18877 
18878 /* Bit 31 :   */
18879 #define WDT_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
18880 #define WDT_PUBLISH_STOPPED_EN_Msk (0x1UL << WDT_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
18881 #define WDT_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
18882 #define WDT_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
18883 
18884 /* Bits 7..0 : DPPI channel that event STOPPED will publish to. */
18885 #define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
18886 #define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
18887 
18888 /* Register: WDT_INTENSET */
18889 /* Description: Enable interrupt */
18890 
18891 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
18892 #define WDT_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
18893 #define WDT_INTENSET_STOPPED_Msk (0x1UL << WDT_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
18894 #define WDT_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
18895 #define WDT_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
18896 #define WDT_INTENSET_STOPPED_Set (1UL) /*!< Enable */
18897 
18898 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
18899 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
18900 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
18901 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
18902 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
18903 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
18904 
18905 /* Register: WDT_INTENCLR */
18906 /* Description: Disable interrupt */
18907 
18908 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
18909 #define WDT_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
18910 #define WDT_INTENCLR_STOPPED_Msk (0x1UL << WDT_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
18911 #define WDT_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
18912 #define WDT_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
18913 #define WDT_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
18914 
18915 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
18916 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
18917 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
18918 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
18919 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
18920 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
18921 
18922 /* Register: WDT_NMIENSET */
18923 /* Description: Enable interrupt */
18924 
18925 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
18926 #define WDT_NMIENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
18927 #define WDT_NMIENSET_STOPPED_Msk (0x1UL << WDT_NMIENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
18928 #define WDT_NMIENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
18929 #define WDT_NMIENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
18930 #define WDT_NMIENSET_STOPPED_Set (1UL) /*!< Enable */
18931 
18932 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
18933 #define WDT_NMIENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
18934 #define WDT_NMIENSET_TIMEOUT_Msk (0x1UL << WDT_NMIENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
18935 #define WDT_NMIENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
18936 #define WDT_NMIENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
18937 #define WDT_NMIENSET_TIMEOUT_Set (1UL) /*!< Enable */
18938 
18939 /* Register: WDT_NMIENCLR */
18940 /* Description: Disable interrupt */
18941 
18942 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
18943 #define WDT_NMIENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
18944 #define WDT_NMIENCLR_STOPPED_Msk (0x1UL << WDT_NMIENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
18945 #define WDT_NMIENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
18946 #define WDT_NMIENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
18947 #define WDT_NMIENCLR_STOPPED_Clear (1UL) /*!< Disable */
18948 
18949 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
18950 #define WDT_NMIENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
18951 #define WDT_NMIENCLR_TIMEOUT_Msk (0x1UL << WDT_NMIENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
18952 #define WDT_NMIENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
18953 #define WDT_NMIENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
18954 #define WDT_NMIENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
18955 
18956 /* Register: WDT_RUNSTATUS */
18957 /* Description: Run status */
18958 
18959 /* Bit 0 : Indicates whether or not WDT is running */
18960 #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */
18961 #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */
18962 #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog is not running */
18963 #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */
18964 
18965 /* Register: WDT_REQSTATUS */
18966 /* Description: Request status */
18967 
18968 /* Bit 7 : Request status for RR[7] register */
18969 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
18970 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
18971 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
18972 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
18973 
18974 /* Bit 6 : Request status for RR[6] register */
18975 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
18976 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
18977 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
18978 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
18979 
18980 /* Bit 5 : Request status for RR[5] register */
18981 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
18982 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
18983 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
18984 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
18985 
18986 /* Bit 4 : Request status for RR[4] register */
18987 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
18988 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
18989 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
18990 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
18991 
18992 /* Bit 3 : Request status for RR[3] register */
18993 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
18994 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
18995 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
18996 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
18997 
18998 /* Bit 2 : Request status for RR[2] register */
18999 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
19000 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
19001 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
19002 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
19003 
19004 /* Bit 1 : Request status for RR[1] register */
19005 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
19006 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
19007 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
19008 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
19009 
19010 /* Bit 0 : Request status for RR[0] register */
19011 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
19012 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
19013 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
19014 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
19015 
19016 /* Register: WDT_CRV */
19017 /* Description: Counter reload value */
19018 
19019 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
19020 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
19021 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
19022 
19023 /* Register: WDT_RREN */
19024 /* Description: Enable register for reload request registers */
19025 
19026 /* Bit 7 : Enable or disable RR[7] register */
19027 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
19028 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
19029 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
19030 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
19031 
19032 /* Bit 6 : Enable or disable RR[6] register */
19033 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
19034 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
19035 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
19036 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
19037 
19038 /* Bit 5 : Enable or disable RR[5] register */
19039 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
19040 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
19041 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
19042 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
19043 
19044 /* Bit 4 : Enable or disable RR[4] register */
19045 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
19046 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
19047 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
19048 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
19049 
19050 /* Bit 3 : Enable or disable RR[3] register */
19051 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
19052 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
19053 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
19054 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
19055 
19056 /* Bit 2 : Enable or disable RR[2] register */
19057 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
19058 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
19059 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
19060 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
19061 
19062 /* Bit 1 : Enable or disable RR[1] register */
19063 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
19064 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
19065 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
19066 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
19067 
19068 /* Bit 0 : Enable or disable RR[0] register */
19069 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
19070 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
19071 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
19072 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
19073 
19074 /* Register: WDT_CONFIG */
19075 /* Description: Configuration register */
19076 
19077 /* Bit 6 : Allow stopping WDT */
19078 #define WDT_CONFIG_STOPEN_Pos (6UL) /*!< Position of STOPEN field. */
19079 #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos) /*!< Bit mask of STOPEN field. */
19080 #define WDT_CONFIG_STOPEN_Disable (0UL) /*!< Do not allow stopping WDT */
19081 #define WDT_CONFIG_STOPEN_Enable (1UL) /*!< Allow stopping WDT */
19082 
19083 /* Bit 3 : Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger */
19084 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
19085 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
19086 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause WDT while the CPU is halted by the debugger */
19087 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep WDT running while the CPU is halted by the debugger */
19088 
19089 /* Bit 0 : Configure WDT to either be paused, or kept running, while the CPU is sleeping */
19090 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
19091 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
19092 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause WDT while the CPU is sleeping */
19093 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep WDT running while the CPU is sleeping */
19094 
19095 /* Register: WDT_TSEN */
19096 /* Description: Task stop enable */
19097 
19098 /* Bits 31..0 : Allow stopping WDT */
19099 #define WDT_TSEN_TSEN_Pos (0UL) /*!< Position of TSEN field. */
19100 #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos) /*!< Bit mask of TSEN field. */
19101 #define WDT_TSEN_TSEN_Enable (0x6E524635UL) /*!< Value to allow stopping WDT */
19102 
19103 /* Register: WDT_RR */
19104 /* Description: Description collection: Reload request n */
19105 
19106 /* Bits 31..0 : Reload request register */
19107 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
19108 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
19109 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
19110 
19111 
19112 /*lint --flb "Leave library region" */
19113 #endif
19114