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Searched refs:TEMP_B5_B5_Msk (Results 1 – 8 of 8) sorted by relevance

/hal_nordic-3.4.0/nrfx/mdk/
Dnrf52805_bitfields.h7803 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ macro
Dnrf52811_bitfields.h9516 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ macro
Dnrf52810_bitfields.h8811 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ macro
Dnrf5340_network_bitfields.h9838 #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ macro
Dnrf52820_bitfields.h8154 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ macro
Dnrf52_bitfields.h12222 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ macro
Dnrf52840_bitfields.h13431 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ macro
Dnrf52833_bitfields.h13068 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ macro