1 /*
2 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
3 
4 SPDX-License-Identifier: BSD-3-Clause
5 
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8 
9 1. Redistributions of source code must retain the above copyright notice, this
10    list of conditions and the following disclaimer.
11 
12 2. Redistributions in binary form must reproduce the above copyright
13    notice, this list of conditions and the following disclaimer in the
14    documentation and/or other materials provided with the distribution.
15 
16 3. Neither the name of Nordic Semiconductor ASA nor the names of its
17    contributors may be used to endorse or promote products derived from this
18    software without specific prior written permission.
19 
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
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29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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31  *
32  * @file     nrf9120.h
33  * @brief    CMSIS HeaderFile
34  * @version  1
35  * @date     04. April 2023
36  * @note     Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:51
37  *           from File 'nrf9120.svd',
38  *           last modified on Tuesday, 04.04.2023 09:57:14
39  */
40 
41 
42 
43 /** @addtogroup Nordic Semiconductor
44   * @{
45   */
46 
47 
48 /** @addtogroup nrf9120
49   * @{
50   */
51 
52 
53 #ifndef NRF9120_H
54 #define NRF9120_H
55 
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59 
60 
61 /** @addtogroup Configuration_of_CMSIS
62   * @{
63   */
64 
65 
66 
67 /* =========================================================================================================================== */
68 /* ================                                Interrupt Number Definition                                ================ */
69 /* =========================================================================================================================== */
70 
71 typedef enum {
72 /* =======================================  ARM Cortex-M33 Specific Interrupt Numbers  ======================================= */
73   Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
74   NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
75   HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
76   MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
77                                                      and No Match                                                              */
78   BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
79                                                      related Fault                                                             */
80   UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
81   SecureFault_IRQn          =  -9,              /*!< -9 Secure Fault Handler                                                   */
82   SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
83   DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
84   PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
85   SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
86 /* ==========================================  nrf9120 Specific Interrupt Numbers  =========================================== */
87   SPU_IRQn                  =   3,              /*!< 3  SPU                                                                    */
88   CLOCK_POWER_IRQn          =   5,              /*!< 5  CLOCK_POWER                                                            */
89   SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn=   8,     /*!< 8  SPIM0_SPIS0_TWIM0_TWIS0_UARTE0                                         */
90   SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn=   9,     /*!< 9  SPIM1_SPIS1_TWIM1_TWIS1_UARTE1                                         */
91   SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn=  10,     /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2                                         */
92   SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn=  11,     /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3                                         */
93   GPIOTE0_IRQn              =  13,              /*!< 13 GPIOTE0                                                                */
94   SAADC_IRQn                =  14,              /*!< 14 SAADC                                                                  */
95   TIMER0_IRQn               =  15,              /*!< 15 TIMER0                                                                 */
96   TIMER1_IRQn               =  16,              /*!< 16 TIMER1                                                                 */
97   TIMER2_IRQn               =  17,              /*!< 17 TIMER2                                                                 */
98   RTC0_IRQn                 =  20,              /*!< 20 RTC0                                                                   */
99   RTC1_IRQn                 =  21,              /*!< 21 RTC1                                                                   */
100   WDT_IRQn                  =  24,              /*!< 24 WDT                                                                    */
101   EGU0_IRQn                 =  27,              /*!< 27 EGU0                                                                   */
102   EGU1_IRQn                 =  28,              /*!< 28 EGU1                                                                   */
103   EGU2_IRQn                 =  29,              /*!< 29 EGU2                                                                   */
104   EGU3_IRQn                 =  30,              /*!< 30 EGU3                                                                   */
105   EGU4_IRQn                 =  31,              /*!< 31 EGU4                                                                   */
106   EGU5_IRQn                 =  32,              /*!< 32 EGU5                                                                   */
107   PWM0_IRQn                 =  33,              /*!< 33 PWM0                                                                   */
108   PWM1_IRQn                 =  34,              /*!< 34 PWM1                                                                   */
109   PWM2_IRQn                 =  35,              /*!< 35 PWM2                                                                   */
110   PWM3_IRQn                 =  36,              /*!< 36 PWM3                                                                   */
111   PDM_IRQn                  =  38,              /*!< 38 PDM                                                                    */
112   I2S_IRQn                  =  40,              /*!< 40 I2S                                                                    */
113   IPC_IRQn                  =  42,              /*!< 42 IPC                                                                    */
114   FPU_IRQn                  =  44,              /*!< 44 FPU                                                                    */
115   GPIOTE1_IRQn              =  49,              /*!< 49 GPIOTE1                                                                */
116   KMU_IRQn                  =  57,              /*!< 57 KMU                                                                    */
117   CRYPTOCELL_IRQn           =  64               /*!< 64 CRYPTOCELL                                                             */
118 } IRQn_Type;
119 
120 
121 
122 /* =========================================================================================================================== */
123 /* ================                           Processor and Core Peripheral Section                           ================ */
124 /* =========================================================================================================================== */
125 
126 /* ==========================  Configuration of the ARM Cortex-M33 Processor and Core Peripherals  =========================== */
127 #define __CM33_REV                 0x0004U      /*!< CM33 Core Revision                                                        */
128 #define __INTERRUPTS_MAX                   240        /*!< Top interrupt number                                                      */
129 #define __DSP_PRESENT                  1        /*!< DSP present or not                                                        */
130 #define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */
131 #define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
132 #define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
133 #define __MPU_PRESENT                  1        /*!< MPU present                                                               */
134 #define __FPU_PRESENT                  1        /*!< FPU present                                                               */
135 #define __FPU_DP                       0        /*!< Double Precision FPU                                                      */
136 #define __SAUREGION_PRESENT            0        /*!< SAU region present                                                        */
137 
138 
139 /** @} */ /* End of group Configuration_of_CMSIS */
140 
141 #include "core_cm33.h"                          /*!< ARM Cortex-M33 processor and core peripherals                             */
142 #include "system_nrf9120.h"                     /*!< nrf9120 System                                                            */
143 
144 #ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
145   #define __IM   __I
146 #endif
147 #ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
148   #define __OM   __O
149 #endif
150 #ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
151   #define __IOM  __IO
152 #endif
153 
154 
155 /* =========================================================================================================================== */
156 /* ================                              Device Specific Cluster Section                              ================ */
157 /* =========================================================================================================================== */
158 
159 
160 /** @addtogroup Device_Peripheral_clusters
161   * @{
162   */
163 
164 
165 /**
166   * @brief FICR_SIPINFO [SIPINFO] (SIP-specific device info)
167   */
168 typedef struct {
169   __IM  uint32_t  PARTNO;                       /*!< (@ 0x00000000) SIP part number                                            */
170   __IM  uint8_t   HWREVISION[4];                /*!< (@ 0x00000004) Description collection: SIP hardware revision,
171                                                                     encoded in ASCII, ex B0A or B1A                            */
172   __IM  uint8_t   VARIANT[4];                   /*!< (@ 0x00000008) Description collection: SIP VARIANT, encoded
173                                                                     in ASCII, ex SIAA, SIBA or SICA                            */
174 } FICR_SIPINFO_Type;                            /*!< Size = 12 (0xc)                                                           */
175 
176 
177 /**
178   * @brief FICR_INFO [INFO] (Device info)
179   */
180 typedef struct {
181   __IM  uint32_t  RESERVED;
182   __IM  uint32_t  DEVICEID[2];                  /*!< (@ 0x00000004) Description collection: Device identifier                  */
183   __IM  uint32_t  PART;                         /*!< (@ 0x0000000C) Part code                                                  */
184   __IM  uint32_t  VARIANT;                      /*!< (@ 0x00000010) Part Variant, Hardware version and Production
185                                                                     configuration                                              */
186   __IM  uint32_t  PACKAGE;                      /*!< (@ 0x00000014) Package option                                             */
187   __IM  uint32_t  RAM;                          /*!< (@ 0x00000018) RAM variant                                                */
188   __IM  uint32_t  FLASH;                        /*!< (@ 0x0000001C) Flash variant                                              */
189   __IM  uint32_t  CODEPAGESIZE;                 /*!< (@ 0x00000020) Code memory page size                                      */
190   __IM  uint32_t  CODESIZE;                     /*!< (@ 0x00000024) Code memory size                                           */
191   __IM  uint32_t  DEVICETYPE;                   /*!< (@ 0x00000028) Device type                                                */
192 } FICR_INFO_Type;                               /*!< Size = 44 (0x2c)                                                          */
193 
194 
195 /**
196   * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified)
197   */
198 typedef struct {
199   __IM  uint32_t  ADDR;                         /*!< (@ 0x00000000) Description cluster: Address                               */
200   __IM  uint32_t  DATA;                         /*!< (@ 0x00000004) Description cluster: Data                                  */
201 } FICR_TRIMCNF_Type;                            /*!< Size = 8 (0x8)                                                            */
202 
203 
204 /**
205   * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data)
206   */
207 typedef struct {
208   __IM  uint32_t  BYTES;                        /*!< (@ 0x00000000) Amount of bytes for the required entropy bits              */
209   __IM  uint32_t  RCCUTOFF;                     /*!< (@ 0x00000004) Repetition counter cutoff                                  */
210   __IM  uint32_t  APCUTOFF;                     /*!< (@ 0x00000008) Adaptive proportion cutoff                                 */
211   __IM  uint32_t  STARTUP;                      /*!< (@ 0x0000000C) Amount of bytes for the startup tests                      */
212   __IM  uint32_t  ROSC1;                        /*!< (@ 0x00000010) Sample count for ring oscillator 1                         */
213   __IM  uint32_t  ROSC2;                        /*!< (@ 0x00000014) Sample count for ring oscillator 2                         */
214   __IM  uint32_t  ROSC3;                        /*!< (@ 0x00000018) Sample count for ring oscillator 3                         */
215   __IM  uint32_t  ROSC4;                        /*!< (@ 0x0000001C) Sample count for ring oscillator 4                         */
216 } FICR_TRNG90B_Type;                            /*!< Size = 32 (0x20)                                                          */
217 
218 
219 /**
220   * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified)
221   */
222 typedef struct {
223   __IOM uint32_t  DEST;                         /*!< (@ 0x00000000) Description cluster: Destination address where
224                                                                     content of the key value registers (KEYSLOT.KEYn.VALUE[0-3
225                                                                     ) will be pushed by KMU. Note that this
226                                                                     address must match that of a peripherals
227                                                                     APB mapped write-only key registers, else
228                                                                     the KMU can push this key value into an
229                                                                     address range which the CPU can potentially
230                                                                     read.                                                      */
231   __IOM uint32_t  PERM;                         /*!< (@ 0x00000004) Description cluster: Define permissions for the
232                                                                     key slot. Bits 0-15 and 16-31 can only be
233                                                                     written when equal to 0xFFFF.                              */
234 } UICR_KEYSLOT_CONFIG_Type;                     /*!< Size = 8 (0x8)                                                            */
235 
236 
237 /**
238   * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified)
239   */
240 typedef struct {
241   __IOM uint32_t  VALUE[4];                     /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32]
242                                                                     of value assigned to KMU key slot.                         */
243 } UICR_KEYSLOT_KEY_Type;                        /*!< Size = 16 (0x10)                                                          */
244 
245 
246 /**
247   * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified)
248   */
249 typedef struct {
250   __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128];   /*!< (@ 0x00000000) Unspecified                                                */
251   __IOM UICR_KEYSLOT_KEY_Type KEY[128];         /*!< (@ 0x00000400) Unspecified                                                */
252 } UICR_KEYSLOT_Type;                            /*!< Size = 3072 (0xc00)                                                       */
253 
254 
255 /**
256   * @brief TAD_PSEL [PSEL] (Unspecified)
257   */
258 typedef struct {
259   __IOM uint32_t  TRACECLK;                     /*!< (@ 0x00000000) Pin configuration for TRACECLK                             */
260   __IOM uint32_t  TRACEDATA0;                   /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0]                         */
261   __IOM uint32_t  TRACEDATA1;                   /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1]                         */
262   __IOM uint32_t  TRACEDATA2;                   /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2]                         */
263   __IOM uint32_t  TRACEDATA3;                   /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3]                         */
264 } TAD_PSEL_Type;                                /*!< Size = 20 (0x14)                                                          */
265 
266 
267 /**
268   * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified)
269   */
270 typedef struct {
271   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Access for bus access generated
272                                                                     from the external domain n List capabilities
273                                                                     of the external domain n                                   */
274 } SPU_EXTDOMAIN_Type;                           /*!< Size = 4 (0x4)                                                            */
275 
276 
277 /**
278   * @brief SPU_DPPI [DPPI] (Unspecified)
279   */
280 typedef struct {
281   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Select between secure and
282                                                                     non-secure attribute for the DPPI channels.                */
283   __IOM uint32_t  LOCK;                         /*!< (@ 0x00000004) Description cluster: Prevent further modification
284                                                                     of the corresponding PERM register                         */
285 } SPU_DPPI_Type;                                /*!< Size = 8 (0x8)                                                            */
286 
287 
288 /**
289   * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified)
290   */
291 typedef struct {
292   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Select between secure and
293                                                                     non-secure attribute for pins 0 to 31 of
294                                                                     port n.                                                    */
295   __IOM uint32_t  LOCK;                         /*!< (@ 0x00000004) Description cluster: Prevent further modification
296                                                                     of the corresponding PERM register                         */
297 } SPU_GPIOPORT_Type;                            /*!< Size = 8 (0x8)                                                            */
298 
299 
300 /**
301   * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified)
302   */
303 typedef struct {
304   __IOM uint32_t  REGION;                       /*!< (@ 0x00000000) Description cluster: Define which flash region
305                                                                     can contain the non-secure callable (NSC)
306                                                                     region n                                                   */
307   __IOM uint32_t  SIZE;                         /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure
308                                                                     callable (NSC) region n                                    */
309 } SPU_FLASHNSC_Type;                            /*!< Size = 8 (0x8)                                                            */
310 
311 
312 /**
313   * @brief SPU_RAMNSC [RAMNSC] (Unspecified)
314   */
315 typedef struct {
316   __IOM uint32_t  REGION;                       /*!< (@ 0x00000000) Description cluster: Define which RAM region
317                                                                     can contain the non-secure callable (NSC)
318                                                                     region n                                                   */
319   __IOM uint32_t  SIZE;                         /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure
320                                                                     callable (NSC) region n                                    */
321 } SPU_RAMNSC_Type;                              /*!< Size = 8 (0x8)                                                            */
322 
323 
324 /**
325   * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified)
326   */
327 typedef struct {
328   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Access permissions for flash
329                                                                     region n                                                   */
330 } SPU_FLASHREGION_Type;                         /*!< Size = 4 (0x4)                                                            */
331 
332 
333 /**
334   * @brief SPU_RAMREGION [RAMREGION] (Unspecified)
335   */
336 typedef struct {
337   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Access permissions for RAM
338                                                                     region n                                                   */
339 } SPU_RAMREGION_Type;                           /*!< Size = 4 (0x4)                                                            */
340 
341 
342 /**
343   * @brief SPU_PERIPHID [PERIPHID] (Unspecified)
344   */
345 typedef struct {
346   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: List capabilities and access
347                                                                     permissions for the peripheral with ID n                   */
348 } SPU_PERIPHID_Type;                            /*!< Size = 4 (0x4)                                                            */
349 
350 
351 /**
352   * @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem)
353   */
354 typedef struct {
355   __IOM uint32_t  STARTN;                       /*!< (@ 0x00000000) Start LTE modem                                            */
356   __IOM uint32_t  FORCEOFF;                     /*!< (@ 0x00000004) Force off LTE modem                                        */
357 } POWER_LTEMODEM_Type;                          /*!< Size = 8 (0x8)                                                            */
358 
359 
360 /**
361   * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified)
362   */
363 typedef struct {
364   __IM  uint32_t  RXDATA;                       /*!< (@ 0x00000000) Data sent from the debugger to the CPU.                    */
365   __IM  uint32_t  RXSTATUS;                     /*!< (@ 0x00000004) This register shows a status that indicates if
366                                                                     data sent from the debugger to the CPU has
367                                                                     been read.                                                 */
368   __IM  uint32_t  RESERVED[30];
369   __IOM uint32_t  TXDATA;                       /*!< (@ 0x00000080) Data sent from the CPU to the debugger.                    */
370   __IM  uint32_t  TXSTATUS;                     /*!< (@ 0x00000084) This register shows a status that indicates if
371                                                                     the data sent from the CPU to the debugger
372                                                                     has been read.                                             */
373 } CTRLAPPERI_MAILBOX_Type;                      /*!< Size = 136 (0x88)                                                         */
374 
375 
376 /**
377   * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified)
378   */
379 typedef struct {
380   __IOM uint32_t  LOCK;                         /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE
381                                                                     register from being written until next reset.              */
382   __IOM uint32_t  DISABLE;                      /*!< (@ 0x00000004) This register disables the ERASEPROTECT register
383                                                                     and performs an ERASEALL operation.                        */
384 } CTRLAPPERI_ERASEPROTECT_Type;                 /*!< Size = 8 (0x8)                                                            */
385 
386 
387 /**
388   * @brief SPIM_PSEL [PSEL] (Unspecified)
389   */
390 typedef struct {
391   __IOM uint32_t  SCK;                          /*!< (@ 0x00000000) Pin select for SCK                                         */
392   __IOM uint32_t  MOSI;                         /*!< (@ 0x00000004) Pin select for MOSI signal                                 */
393   __IOM uint32_t  MISO;                         /*!< (@ 0x00000008) Pin select for MISO signal                                 */
394 } SPIM_PSEL_Type;                               /*!< Size = 12 (0xc)                                                           */
395 
396 
397 /**
398   * @brief SPIM_RXD [RXD] (RXD EasyDMA channel)
399   */
400 typedef struct {
401   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
402   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in receive buffer                  */
403   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last transaction        */
404   __IOM uint32_t  LIST;                         /*!< (@ 0x0000000C) EasyDMA list type                                          */
405 } SPIM_RXD_Type;                                /*!< Size = 16 (0x10)                                                          */
406 
407 
408 /**
409   * @brief SPIM_TXD [TXD] (TXD EasyDMA channel)
410   */
411 typedef struct {
412   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
413   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer                 */
414   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last transaction        */
415   __IOM uint32_t  LIST;                         /*!< (@ 0x0000000C) EasyDMA list type                                          */
416 } SPIM_TXD_Type;                                /*!< Size = 16 (0x10)                                                          */
417 
418 
419 /**
420   * @brief SPIS_PSEL [PSEL] (Unspecified)
421   */
422 typedef struct {
423   __IOM uint32_t  SCK;                          /*!< (@ 0x00000000) Pin select for SCK                                         */
424   __IOM uint32_t  MISO;                         /*!< (@ 0x00000004) Pin select for MISO signal                                 */
425   __IOM uint32_t  MOSI;                         /*!< (@ 0x00000008) Pin select for MOSI signal                                 */
426   __IOM uint32_t  CSN;                          /*!< (@ 0x0000000C) Pin select for CSN signal                                  */
427 } SPIS_PSEL_Type;                               /*!< Size = 16 (0x10)                                                          */
428 
429 
430 /**
431   * @brief SPIS_RXD [RXD] (Unspecified)
432   */
433 typedef struct {
434   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) RXD data pointer                                           */
435   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in receive buffer                  */
436   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes received in last granted transaction       */
437   __IOM uint32_t  LIST;                         /*!< (@ 0x0000000C) EasyDMA list type                                          */
438 } SPIS_RXD_Type;                                /*!< Size = 16 (0x10)                                                          */
439 
440 
441 /**
442   * @brief SPIS_TXD [TXD] (Unspecified)
443   */
444 typedef struct {
445   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) TXD data pointer                                           */
446   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer                 */
447   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction    */
448   __IOM uint32_t  LIST;                         /*!< (@ 0x0000000C) EasyDMA list type                                          */
449 } SPIS_TXD_Type;                                /*!< Size = 16 (0x10)                                                          */
450 
451 
452 /**
453   * @brief TWIM_PSEL [PSEL] (Unspecified)
454   */
455 typedef struct {
456   __IOM uint32_t  SCL;                          /*!< (@ 0x00000000) Pin select for SCL signal                                  */
457   __IOM uint32_t  SDA;                          /*!< (@ 0x00000004) Pin select for SDA signal                                  */
458 } TWIM_PSEL_Type;                               /*!< Size = 8 (0x8)                                                            */
459 
460 
461 /**
462   * @brief TWIM_RXD [RXD] (RXD EasyDMA channel)
463   */
464 typedef struct {
465   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
466   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in receive buffer                  */
467   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last transaction        */
468   __IOM uint32_t  LIST;                         /*!< (@ 0x0000000C) EasyDMA list type                                          */
469 } TWIM_RXD_Type;                                /*!< Size = 16 (0x10)                                                          */
470 
471 
472 /**
473   * @brief TWIM_TXD [TXD] (TXD EasyDMA channel)
474   */
475 typedef struct {
476   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
477   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer                 */
478   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last transaction        */
479   __IOM uint32_t  LIST;                         /*!< (@ 0x0000000C) EasyDMA list type                                          */
480 } TWIM_TXD_Type;                                /*!< Size = 16 (0x10)                                                          */
481 
482 
483 /**
484   * @brief TWIS_PSEL [PSEL] (Unspecified)
485   */
486 typedef struct {
487   __IOM uint32_t  SCL;                          /*!< (@ 0x00000000) Pin select for SCL signal                                  */
488   __IOM uint32_t  SDA;                          /*!< (@ 0x00000004) Pin select for SDA signal                                  */
489 } TWIS_PSEL_Type;                               /*!< Size = 8 (0x8)                                                            */
490 
491 
492 /**
493   * @brief TWIS_RXD [RXD] (RXD EasyDMA channel)
494   */
495 typedef struct {
496   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) RXD Data pointer                                           */
497   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer                      */
498   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction    */
499   __IOM uint32_t  LIST;                         /*!< (@ 0x0000000C) EasyDMA list type                                          */
500 } TWIS_RXD_Type;                                /*!< Size = 16 (0x10)                                                          */
501 
502 
503 /**
504   * @brief TWIS_TXD [TXD] (TXD EasyDMA channel)
505   */
506 typedef struct {
507   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) TXD Data pointer                                           */
508   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer                      */
509   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction    */
510   __IOM uint32_t  LIST;                         /*!< (@ 0x0000000C) EasyDMA list type                                          */
511 } TWIS_TXD_Type;                                /*!< Size = 16 (0x10)                                                          */
512 
513 
514 /**
515   * @brief UARTE_PSEL [PSEL] (Unspecified)
516   */
517 typedef struct {
518   __IOM uint32_t  RTS;                          /*!< (@ 0x00000000) Pin select for RTS signal                                  */
519   __IOM uint32_t  TXD;                          /*!< (@ 0x00000004) Pin select for TXD signal                                  */
520   __IOM uint32_t  CTS;                          /*!< (@ 0x00000008) Pin select for CTS signal                                  */
521   __IOM uint32_t  RXD;                          /*!< (@ 0x0000000C) Pin select for RXD signal                                  */
522 } UARTE_PSEL_Type;                              /*!< Size = 16 (0x10)                                                          */
523 
524 
525 /**
526   * @brief UARTE_RXD [RXD] (RXD EasyDMA channel)
527   */
528 typedef struct {
529   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
530   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in receive buffer                  */
531   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last transaction        */
532 } UARTE_RXD_Type;                               /*!< Size = 12 (0xc)                                                           */
533 
534 
535 /**
536   * @brief UARTE_TXD [TXD] (TXD EasyDMA channel)
537   */
538 typedef struct {
539   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
540   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer                 */
541   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last transaction        */
542 } UARTE_TXD_Type;                               /*!< Size = 12 (0xc)                                                           */
543 
544 
545 /**
546   * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.)
547   */
548 typedef struct {
549   __IOM uint32_t  LIMITH;                       /*!< (@ 0x00000000) Description cluster: Last results is equal or
550                                                                     above CH[n].LIMIT.HIGH                                     */
551   __IOM uint32_t  LIMITL;                       /*!< (@ 0x00000004) Description cluster: Last results is equal or
552                                                                     below CH[n].LIMIT.LOW                                      */
553 } SAADC_EVENTS_CH_Type;                         /*!< Size = 8 (0x8)                                                            */
554 
555 
556 /**
557   * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events)
558   */
559 typedef struct {
560   __IOM uint32_t  LIMITH;                       /*!< (@ 0x00000000) Description cluster: Publish configuration for
561                                                                     event CH[n].LIMITH                                         */
562   __IOM uint32_t  LIMITL;                       /*!< (@ 0x00000004) Description cluster: Publish configuration for
563                                                                     event CH[n].LIMITL                                         */
564 } SAADC_PUBLISH_CH_Type;                        /*!< Size = 8 (0x8)                                                            */
565 
566 
567 /**
568   * @brief SAADC_CH [CH] (Unspecified)
569   */
570 typedef struct {
571   __IOM uint32_t  PSELP;                        /*!< (@ 0x00000000) Description cluster: Input positive pin selection
572                                                                     for CH[n]                                                  */
573   __IOM uint32_t  PSELN;                        /*!< (@ 0x00000004) Description cluster: Input negative pin selection
574                                                                     for CH[n]                                                  */
575   __IOM uint32_t  CONFIG;                       /*!< (@ 0x00000008) Description cluster: Input configuration for
576                                                                     CH[n]                                                      */
577   __IOM uint32_t  LIMIT;                        /*!< (@ 0x0000000C) Description cluster: High/low limits for event
578                                                                     monitoring a channel                                       */
579 } SAADC_CH_Type;                                /*!< Size = 16 (0x10)                                                          */
580 
581 
582 /**
583   * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel)
584   */
585 typedef struct {
586   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
587   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of buffer words to transfer                 */
588   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of buffer words transferred since last
589                                                                     START                                                      */
590 } SAADC_RESULT_Type;                            /*!< Size = 12 (0xc)                                                           */
591 
592 
593 /**
594   * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks)
595   */
596 typedef struct {
597   __OM  uint32_t  EN;                           /*!< (@ 0x00000000) Description cluster: Enable channel group n                */
598   __OM  uint32_t  DIS;                          /*!< (@ 0x00000004) Description cluster: Disable channel group n               */
599 } DPPIC_TASKS_CHG_Type;                         /*!< Size = 8 (0x8)                                                            */
600 
601 
602 /**
603   * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks)
604   */
605 typedef struct {
606   __IOM uint32_t  EN;                           /*!< (@ 0x00000000) Description cluster: Subscribe configuration
607                                                                     for task CHG[n].EN                                         */
608   __IOM uint32_t  DIS;                          /*!< (@ 0x00000004) Description cluster: Subscribe configuration
609                                                                     for task CHG[n].DIS                                        */
610 } DPPIC_SUBSCRIBE_CHG_Type;                     /*!< Size = 8 (0x8)                                                            */
611 
612 
613 /**
614   * @brief PWM_SEQ [SEQ] (Unspecified)
615   */
616 typedef struct {
617   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Description cluster: Beginning address in RAM
618                                                                     of this sequence                                           */
619   __IOM uint32_t  CNT;                          /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles)
620                                                                     in this sequence                                           */
621   __IOM uint32_t  REFRESH;                      /*!< (@ 0x00000008) Description cluster: Number of additional PWM
622                                                                     periods between samples loaded into compare
623                                                                     register                                                   */
624   __IOM uint32_t  ENDDELAY;                     /*!< (@ 0x0000000C) Description cluster: Time added after the sequence         */
625   __IM  uint32_t  RESERVED[4];
626 } PWM_SEQ_Type;                                 /*!< Size = 32 (0x20)                                                          */
627 
628 
629 /**
630   * @brief PWM_PSEL [PSEL] (Unspecified)
631   */
632 typedef struct {
633   __IOM uint32_t  OUT[4];                       /*!< (@ 0x00000000) Description collection: Output pin select for
634                                                                     PWM channel n                                              */
635 } PWM_PSEL_Type;                                /*!< Size = 16 (0x10)                                                          */
636 
637 
638 /**
639   * @brief PDM_PSEL [PSEL] (Unspecified)
640   */
641 typedef struct {
642   __IOM uint32_t  CLK;                          /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal                */
643   __IOM uint32_t  DIN;                          /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal                */
644 } PDM_PSEL_Type;                                /*!< Size = 8 (0x8)                                                            */
645 
646 
647 /**
648   * @brief PDM_SAMPLE [SAMPLE] (Unspecified)
649   */
650 typedef struct {
651   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) RAM address pointer to write samples to with
652                                                                     EasyDMA                                                    */
653   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA
654                                                                     mode                                                       */
655 } PDM_SAMPLE_Type;                              /*!< Size = 8 (0x8)                                                            */
656 
657 
658 /**
659   * @brief I2S_CONFIG [CONFIG] (Unspecified)
660   */
661 typedef struct {
662   __IOM uint32_t  MODE;                         /*!< (@ 0x00000000) I2S mode.                                                  */
663   __IOM uint32_t  RXEN;                         /*!< (@ 0x00000004) Reception (RX) enable.                                     */
664   __IOM uint32_t  TXEN;                         /*!< (@ 0x00000008) Transmission (TX) enable.                                  */
665   __IOM uint32_t  MCKEN;                        /*!< (@ 0x0000000C) Master clock generator enable.                             */
666   __IOM uint32_t  MCKFREQ;                      /*!< (@ 0x00000010) Master clock generator frequency.                          */
667   __IOM uint32_t  RATIO;                        /*!< (@ 0x00000014) MCK / LRCK ratio.                                          */
668   __IOM uint32_t  SWIDTH;                       /*!< (@ 0x00000018) Sample width.                                              */
669   __IOM uint32_t  ALIGN;                        /*!< (@ 0x0000001C) Alignment of sample within a frame.                        */
670   __IOM uint32_t  FORMAT;                       /*!< (@ 0x00000020) Frame format.                                              */
671   __IOM uint32_t  CHANNELS;                     /*!< (@ 0x00000024) Enable channels.                                           */
672 } I2S_CONFIG_Type;                              /*!< Size = 40 (0x28)                                                          */
673 
674 
675 /**
676   * @brief I2S_RXD [RXD] (Unspecified)
677   */
678 typedef struct {
679   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Receive buffer RAM start address.                          */
680 } I2S_RXD_Type;                                 /*!< Size = 4 (0x4)                                                            */
681 
682 
683 /**
684   * @brief I2S_TXD [TXD] (Unspecified)
685   */
686 typedef struct {
687   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Transmit buffer RAM start address.                         */
688 } I2S_TXD_Type;                                 /*!< Size = 4 (0x4)                                                            */
689 
690 
691 /**
692   * @brief I2S_RXTXD [RXTXD] (Unspecified)
693   */
694 typedef struct {
695   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000000) Size of RXD and TXD buffers.                               */
696 } I2S_RXTXD_Type;                               /*!< Size = 4 (0x4)                                                            */
697 
698 
699 /**
700   * @brief I2S_PSEL [PSEL] (Unspecified)
701   */
702 typedef struct {
703   __IOM uint32_t  MCK;                          /*!< (@ 0x00000000) Pin select for MCK signal.                                 */
704   __IOM uint32_t  SCK;                          /*!< (@ 0x00000004) Pin select for SCK signal.                                 */
705   __IOM uint32_t  LRCK;                         /*!< (@ 0x00000008) Pin select for LRCK signal.                                */
706   __IOM uint32_t  SDIN;                         /*!< (@ 0x0000000C) Pin select for SDIN signal.                                */
707   __IOM uint32_t  SDOUT;                        /*!< (@ 0x00000010) Pin select for SDOUT signal.                               */
708 } I2S_PSEL_Type;                                /*!< Size = 20 (0x14)                                                          */
709 
710 
711 /**
712   * @brief APPROTECT_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified)
713   */
714 typedef struct {
715   __IOM uint32_t  DISABLE;                      /*!< (@ 0x00000000) Software disable SECUREAPPROTECT mechanism                 */
716   __IOM uint32_t  FORCEPROTECT;                 /*!< (@ 0x00000004) Software force SECUREAPPROTECT mechanism                   */
717 } APPROTECT_SECUREAPPROTECT_Type;               /*!< Size = 8 (0x8)                                                            */
718 
719 
720 /**
721   * @brief APPROTECT_APPROTECT [APPROTECT] (Unspecified)
722   */
723 typedef struct {
724   __IOM uint32_t  DISABLE;                      /*!< (@ 0x00000000) Software disable APPROTECT mechanism                       */
725   __IOM uint32_t  FORCEPROTECT;                 /*!< (@ 0x00000004) Software force APPROTECT mechanism                         */
726 } APPROTECT_APPROTECT_Type;                     /*!< Size = 8 (0x8)                                                            */
727 
728 
729 /**
730   * @brief VMC_RAM [RAM] (Unspecified)
731   */
732 typedef struct {
733   __IOM uint32_t  POWER;                        /*!< (@ 0x00000000) Description cluster: RAMn power control register           */
734   __OM  uint32_t  POWERSET;                     /*!< (@ 0x00000004) Description cluster: RAMn power control set register       */
735   __OM  uint32_t  POWERCLR;                     /*!< (@ 0x00000008) Description cluster: RAMn power control clear
736                                                                     register                                                   */
737   __IM  uint32_t  RESERVED;
738 } VMC_RAM_Type;                                 /*!< Size = 16 (0x10)                                                          */
739 
740 
741 /** @} */ /* End of group Device_Peripheral_clusters */
742 
743 
744 /* =========================================================================================================================== */
745 /* ================                            Device Specific Peripheral Section                             ================ */
746 /* =========================================================================================================================== */
747 
748 
749 /** @addtogroup Device_Peripheral_peripherals
750   * @{
751   */
752 
753 
754 
755 /* =========================================================================================================================== */
756 /* ================                                          FICR_S                                           ================ */
757 /* =========================================================================================================================== */
758 
759 
760 /**
761   * @brief Factory Information Configuration Registers (FICR_S)
762   */
763 
764 typedef struct {                                /*!< (@ 0x00FF0000) FICR_S Structure                                           */
765   __IM  uint32_t  RESERVED[80];
766   __IOM FICR_SIPINFO_Type SIPINFO;              /*!< (@ 0x00000140) SIP-specific device info                                   */
767   __IM  uint32_t  RESERVED1[45];
768   __IOM FICR_INFO_Type INFO;                    /*!< (@ 0x00000200) Device info                                                */
769   __IM  uint32_t  RESERVED2[53];
770   __IOM FICR_TRIMCNF_Type TRIMCNF[256];         /*!< (@ 0x00000300) Unspecified                                                */
771   __IM  uint32_t  RESERVED3[64];
772   __IOM FICR_TRNG90B_Type TRNG90B;              /*!< (@ 0x00000C00) NIST800-90B RNG calibration data                           */
773 } NRF_FICR_Type;                                /*!< Size = 3104 (0xc20)                                                       */
774 
775 
776 
777 /* =========================================================================================================================== */
778 /* ================                                          UICR_S                                           ================ */
779 /* =========================================================================================================================== */
780 
781 
782 /**
783   * @brief User information configuration registers User information configuration registers (UICR_S)
784   */
785 
786 typedef struct {                                /*!< (@ 0x00FF8000) UICR_S Structure                                           */
787   __IOM uint32_t  APPROTECT;                    /*!< (@ 0x00000000) Access port protection                                     */
788   __IM  uint32_t  RESERVED[4];
789   __IOM uint32_t  XOSC32M;                      /*!< (@ 0x00000014) Oscillator control                                         */
790   __IM  uint32_t  RESERVED1;
791   __IOM uint32_t  HFXOSRC;                      /*!< (@ 0x0000001C) HFXO clock source selection                                */
792   __IOM uint32_t  HFXOCNT;                      /*!< (@ 0x00000020) HFXO startup counter                                       */
793   __IOM uint32_t  APPNVMCPOFGUARD;              /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE
794                                                                     for Application NVM in POFWARN condition
795                                                                     .                                                          */
796   __IOM uint32_t  PMICCONF;                     /*!< (@ 0x00000028) Polarity of PMIC polarity configuration signals.           */
797   __IOM uint32_t  SECUREAPPROTECT;              /*!< (@ 0x0000002C) Secure access port protection                              */
798   __IOM uint32_t  ERASEPROTECT;                 /*!< (@ 0x00000030) Erase protection                                           */
799   __IM  uint32_t  RESERVED2[53];
800   __IOM uint32_t  OTP[190];                     /*!< (@ 0x00000108) Description collection: One time programmable
801                                                                     memory                                                     */
802   __IOM UICR_KEYSLOT_Type KEYSLOT;              /*!< (@ 0x00000400) Unspecified                                                */
803 } NRF_UICR_Type;                                /*!< Size = 4096 (0x1000)                                                      */
804 
805 
806 
807 /* =========================================================================================================================== */
808 /* ================                                           TAD_S                                           ================ */
809 /* =========================================================================================================================== */
810 
811 
812 /**
813   * @brief Trace and debug control (TAD_S)
814   */
815 
816 typedef struct {                                /*!< (@ 0xE0080000) TAD_S Structure                                            */
817   __OM  uint32_t  TASKS_CLOCKSTART;             /*!< (@ 0x00000000) Start all trace and debug clocks.                          */
818   __OM  uint32_t  TASKS_CLOCKSTOP;              /*!< (@ 0x00000004) Stop all trace and debug clocks.                           */
819   __IM  uint32_t  RESERVED[318];
820   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs              */
821   __IOM TAD_PSEL_Type PSEL;                     /*!< (@ 0x00000504) Unspecified                                                */
822   __IOM uint32_t  TRACEPORTSPEED;               /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface
823                                                                     Reset behavior is the same as debug components             */
824 } NRF_TAD_Type;                                 /*!< Size = 1308 (0x51c)                                                       */
825 
826 
827 
828 /* =========================================================================================================================== */
829 /* ================                                           SPU_S                                           ================ */
830 /* =========================================================================================================================== */
831 
832 
833 /**
834   * @brief System protection unit (SPU_S)
835   */
836 
837 typedef struct {                                /*!< (@ 0x50003000) SPU_S Structure                                            */
838   __IM  uint32_t  RESERVED[64];
839   __IOM uint32_t  EVENTS_RAMACCERR;             /*!< (@ 0x00000100) A security violation has been detected for the
840                                                                     RAM memory space                                           */
841   __IOM uint32_t  EVENTS_FLASHACCERR;           /*!< (@ 0x00000104) A security violation has been detected for the
842                                                                     flash memory space                                         */
843   __IOM uint32_t  EVENTS_PERIPHACCERR;          /*!< (@ 0x00000108) A security violation has been detected on one
844                                                                     or several peripherals                                     */
845   __IM  uint32_t  RESERVED1[29];
846   __IOM uint32_t  PUBLISH_RAMACCERR;            /*!< (@ 0x00000180) Publish configuration for event RAMACCERR                  */
847   __IOM uint32_t  PUBLISH_FLASHACCERR;          /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR                */
848   __IOM uint32_t  PUBLISH_PERIPHACCERR;         /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR               */
849   __IM  uint32_t  RESERVED2[93];
850   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
851   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
852   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
853   __IM  uint32_t  RESERVED3[61];
854   __IM  uint32_t  CAP;                          /*!< (@ 0x00000400) Show implemented features for the current device           */
855   __IM  uint32_t  RESERVED4[15];
856   __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1];        /*!< (@ 0x00000440) Unspecified                                                */
857   __IM  uint32_t  RESERVED5[15];
858   __IOM SPU_DPPI_Type DPPI[1];                  /*!< (@ 0x00000480) Unspecified                                                */
859   __IM  uint32_t  RESERVED6[14];
860   __IOM SPU_GPIOPORT_Type GPIOPORT[1];          /*!< (@ 0x000004C0) Unspecified                                                */
861   __IM  uint32_t  RESERVED7[14];
862   __IOM SPU_FLASHNSC_Type FLASHNSC[2];          /*!< (@ 0x00000500) Unspecified                                                */
863   __IM  uint32_t  RESERVED8[12];
864   __IOM SPU_RAMNSC_Type RAMNSC[2];              /*!< (@ 0x00000540) Unspecified                                                */
865   __IM  uint32_t  RESERVED9[44];
866   __IOM SPU_FLASHREGION_Type FLASHREGION[32];   /*!< (@ 0x00000600) Unspecified                                                */
867   __IM  uint32_t  RESERVED10[32];
868   __IOM SPU_RAMREGION_Type RAMREGION[32];       /*!< (@ 0x00000700) Unspecified                                                */
869   __IM  uint32_t  RESERVED11[32];
870   __IOM SPU_PERIPHID_Type PERIPHID[67];         /*!< (@ 0x00000800) Unspecified                                                */
871 } NRF_SPU_Type;                                 /*!< Size = 2316 (0x90c)                                                       */
872 
873 
874 
875 /* =========================================================================================================================== */
876 /* ================                                       REGULATORS_NS                                       ================ */
877 /* =========================================================================================================================== */
878 
879 
880 /**
881   * @brief Voltage regulators control 0 (REGULATORS_NS)
882   */
883 
884 typedef struct {                                /*!< (@ 0x40004000) REGULATORS_NS Structure                                    */
885   __IM  uint32_t  RESERVED[320];
886   __OM  uint32_t  SYSTEMOFF;                    /*!< (@ 0x00000500) System OFF register                                        */
887   __IM  uint32_t  RESERVED1[4];
888   __IOM uint32_t  EXTPOFCON;                    /*!< (@ 0x00000514) External power failure warning configuration               */
889   __IM  uint32_t  RESERVED2[24];
890   __IOM uint32_t  DCDCEN;                       /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator.           */
891 } NRF_REGULATORS_Type;                          /*!< Size = 1404 (0x57c)                                                       */
892 
893 
894 
895 /* =========================================================================================================================== */
896 /* ================                                         CLOCK_NS                                          ================ */
897 /* =========================================================================================================================== */
898 
899 
900 /**
901   * @brief Clock management 0 (CLOCK_NS)
902   */
903 
904 typedef struct {                                /*!< (@ 0x40005000) CLOCK_NS Structure                                         */
905   __OM  uint32_t  TASKS_HFCLKSTART;             /*!< (@ 0x00000000) Start HFCLK source                                         */
906   __OM  uint32_t  TASKS_HFCLKSTOP;              /*!< (@ 0x00000004) Stop HFCLK source                                          */
907   __OM  uint32_t  TASKS_LFCLKSTART;             /*!< (@ 0x00000008) Start LFCLK source                                         */
908   __OM  uint32_t  TASKS_LFCLKSTOP;              /*!< (@ 0x0000000C) Stop LFCLK source                                          */
909   __IM  uint32_t  RESERVED[28];
910   __IOM uint32_t  SUBSCRIBE_HFCLKSTART;         /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART                */
911   __IOM uint32_t  SUBSCRIBE_HFCLKSTOP;          /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP                 */
912   __IOM uint32_t  SUBSCRIBE_LFCLKSTART;         /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART                */
913   __IOM uint32_t  SUBSCRIBE_LFCLKSTOP;          /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP                 */
914   __IM  uint32_t  RESERVED1[28];
915   __IOM uint32_t  EVENTS_HFCLKSTARTED;          /*!< (@ 0x00000100) HFCLK oscillator started                                   */
916   __IOM uint32_t  EVENTS_LFCLKSTARTED;          /*!< (@ 0x00000104) LFCLK started                                              */
917   __IM  uint32_t  RESERVED2[30];
918   __IOM uint32_t  PUBLISH_HFCLKSTARTED;         /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED               */
919   __IOM uint32_t  PUBLISH_LFCLKSTARTED;         /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED               */
920   __IM  uint32_t  RESERVED3[94];
921   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
922   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
923   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
924   __IM  uint32_t  INTPEND;                      /*!< (@ 0x0000030C) Pending interrupts                                         */
925   __IM  uint32_t  RESERVED4[62];
926   __IM  uint32_t  HFCLKRUN;                     /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been
927                                                                     triggered                                                  */
928   __IM  uint32_t  HFCLKSTAT;                    /*!< (@ 0x0000040C) The register shows if HFXO has been requested
929                                                                     by triggering HFCLKSTART task and if it
930                                                                     has been started (STATE)                                   */
931   __IM  uint32_t  RESERVED5;
932   __IM  uint32_t  LFCLKRUN;                     /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been
933                                                                     triggered                                                  */
934   __IM  uint32_t  LFCLKSTAT;                    /*!< (@ 0x00000418) The register shows which LFCLK source has been
935                                                                     requested (SRC) when triggering LFCLKSTART
936                                                                     task and if the source has been started
937                                                                     (STATE)                                                    */
938   __IM  uint32_t  LFCLKSRCCOPY;                 /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART
939                                                                     task has been triggered                                    */
940   __IM  uint32_t  RESERVED6[62];
941   __IOM uint32_t  LFCLKSRC;                     /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts
942                                                                     starts a clock source selected with this
943                                                                     register.                                                  */
944 } NRF_CLOCK_Type;                               /*!< Size = 1308 (0x51c)                                                       */
945 
946 
947 
948 /* =========================================================================================================================== */
949 /* ================                                         POWER_NS                                          ================ */
950 /* =========================================================================================================================== */
951 
952 
953 /**
954   * @brief Power control 0 (POWER_NS)
955   */
956 
957 typedef struct {                                /*!< (@ 0x40005000) POWER_NS Structure                                         */
958   __IM  uint32_t  RESERVED[28];
959   __OM  uint32_t  TASKS_PWMREQSTART;            /*!< (@ 0x00000070) Request forcing PWM mode in external DC/DC voltage
960                                                                     regulator. (Drives FPWM_DCDC pin high or
961                                                                     low depending on a setting in UICR).                       */
962   __OM  uint32_t  TASKS_PWMREQSTOP;             /*!< (@ 0x00000074) Stop requesting forcing PWM mode in external
963                                                                     DC/DC voltage regulator                                    */
964   __OM  uint32_t  TASKS_CONSTLAT;               /*!< (@ 0x00000078) Enable constant latency mode.                              */
965   __OM  uint32_t  TASKS_LOWPWR;                 /*!< (@ 0x0000007C) Enable low power mode (variable latency)                   */
966   __IM  uint32_t  RESERVED1[28];
967   __IOM uint32_t  SUBSCRIBE_PWMREQSTART;        /*!< (@ 0x000000F0) Subscribe configuration for task PWMREQSTART               */
968   __IOM uint32_t  SUBSCRIBE_PWMREQSTOP;         /*!< (@ 0x000000F4) Subscribe configuration for task PWMREQSTOP                */
969   __IOM uint32_t  SUBSCRIBE_CONSTLAT;           /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT                  */
970   __IOM uint32_t  SUBSCRIBE_LOWPWR;             /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR                    */
971   __IM  uint32_t  RESERVED2[2];
972   __IOM uint32_t  EVENTS_POFWARN;               /*!< (@ 0x00000108) Power failure warning                                      */
973   __IM  uint32_t  RESERVED3[2];
974   __IOM uint32_t  EVENTS_SLEEPENTER;            /*!< (@ 0x00000114) CPU entered WFI/WFE sleep                                  */
975   __IOM uint32_t  EVENTS_SLEEPEXIT;             /*!< (@ 0x00000118) CPU exited WFI/WFE sleep                                   */
976   __IM  uint32_t  RESERVED4[27];
977   __IOM uint32_t  PUBLISH_POFWARN;              /*!< (@ 0x00000188) Publish configuration for event POFWARN                    */
978   __IM  uint32_t  RESERVED5[2];
979   __IOM uint32_t  PUBLISH_SLEEPENTER;           /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER                 */
980   __IOM uint32_t  PUBLISH_SLEEPEXIT;            /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT                  */
981   __IM  uint32_t  RESERVED6[89];
982   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
983   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
984   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
985   __IM  uint32_t  RESERVED7[61];
986   __IOM uint32_t  RESETREAS;                    /*!< (@ 0x00000400) Reset reason                                               */
987   __IM  uint32_t  RESERVED8[15];
988   __IM  uint32_t  POWERSTATUS;                  /*!< (@ 0x00000440) Modem domain power status                                  */
989   __IM  uint32_t  RESERVED9[54];
990   __IOM uint32_t  GPREGRET[2];                  /*!< (@ 0x0000051C) Description collection: General purpose retention
991                                                                     register                                                   */
992   __IM  uint32_t  RESERVED10[59];
993   __IOM POWER_LTEMODEM_Type LTEMODEM;           /*!< (@ 0x00000610) LTE Modem                                                  */
994 } NRF_POWER_Type;                               /*!< Size = 1560 (0x618)                                                       */
995 
996 
997 
998 /* =========================================================================================================================== */
999 /* ================                                      CTRL_AP_PERI_S                                       ================ */
1000 /* =========================================================================================================================== */
1001 
1002 
1003 /**
1004   * @brief Control access port (CTRL_AP_PERI_S)
1005   */
1006 
1007 typedef struct {                                /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure                                   */
1008   __IM  uint32_t  RESERVED[256];
1009   __IOM CTRLAPPERI_MAILBOX_Type MAILBOX;        /*!< (@ 0x00000400) Unspecified                                                */
1010   __IM  uint32_t  RESERVED1[30];
1011   __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified                                              */
1012 } NRF_CTRLAPPERI_Type;                          /*!< Size = 1288 (0x508)                                                       */
1013 
1014 
1015 
1016 /* =========================================================================================================================== */
1017 /* ================                                         SPIM0_NS                                          ================ */
1018 /* =========================================================================================================================== */
1019 
1020 
1021 /**
1022   * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS)
1023   */
1024 
1025 typedef struct {                                /*!< (@ 0x40008000) SPIM0_NS Structure                                         */
1026   __IM  uint32_t  RESERVED[4];
1027   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000010) Start SPI transaction                                      */
1028   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000014) Stop SPI transaction                                       */
1029   __IM  uint32_t  RESERVED1;
1030   __OM  uint32_t  TASKS_SUSPEND;                /*!< (@ 0x0000001C) Suspend SPI transaction                                    */
1031   __OM  uint32_t  TASKS_RESUME;                 /*!< (@ 0x00000020) Resume SPI transaction                                     */
1032   __IM  uint32_t  RESERVED2[27];
1033   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000090) Subscribe configuration for task START                     */
1034   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000094) Subscribe configuration for task STOP                      */
1035   __IM  uint32_t  RESERVED3;
1036   __IOM uint32_t  SUBSCRIBE_SUSPEND;            /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND                   */
1037   __IOM uint32_t  SUBSCRIBE_RESUME;             /*!< (@ 0x000000A0) Subscribe configuration for task RESUME                    */
1038   __IM  uint32_t  RESERVED4[24];
1039   __IOM uint32_t  EVENTS_STOPPED;               /*!< (@ 0x00000104) SPI transaction has stopped                                */
1040   __IM  uint32_t  RESERVED5[2];
1041   __IOM uint32_t  EVENTS_ENDRX;                 /*!< (@ 0x00000110) End of RXD buffer reached                                  */
1042   __IM  uint32_t  RESERVED6;
1043   __IOM uint32_t  EVENTS_END;                   /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached                   */
1044   __IM  uint32_t  RESERVED7;
1045   __IOM uint32_t  EVENTS_ENDTX;                 /*!< (@ 0x00000120) End of TXD buffer reached                                  */
1046   __IM  uint32_t  RESERVED8[10];
1047   __IOM uint32_t  EVENTS_STARTED;               /*!< (@ 0x0000014C) Transaction started                                        */
1048   __IM  uint32_t  RESERVED9[13];
1049   __IOM uint32_t  PUBLISH_STOPPED;              /*!< (@ 0x00000184) Publish configuration for event STOPPED                    */
1050   __IM  uint32_t  RESERVED10[2];
1051   __IOM uint32_t  PUBLISH_ENDRX;                /*!< (@ 0x00000190) Publish configuration for event ENDRX                      */
1052   __IM  uint32_t  RESERVED11;
1053   __IOM uint32_t  PUBLISH_END;                  /*!< (@ 0x00000198) Publish configuration for event END                        */
1054   __IM  uint32_t  RESERVED12;
1055   __IOM uint32_t  PUBLISH_ENDTX;                /*!< (@ 0x000001A0) Publish configuration for event ENDTX                      */
1056   __IM  uint32_t  RESERVED13[10];
1057   __IOM uint32_t  PUBLISH_STARTED;              /*!< (@ 0x000001CC) Publish configuration for event STARTED                    */
1058   __IM  uint32_t  RESERVED14[12];
1059   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
1060   __IM  uint32_t  RESERVED15[64];
1061   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1062   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1063   __IM  uint32_t  RESERVED16[125];
1064   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable SPIM                                                */
1065   __IM  uint32_t  RESERVED17;
1066   __IOM SPIM_PSEL_Type PSEL;                    /*!< (@ 0x00000508) Unspecified                                                */
1067   __IM  uint32_t  RESERVED18[4];
1068   __IOM uint32_t  FREQUENCY;                    /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK
1069                                                                     source selected.                                           */
1070   __IM  uint32_t  RESERVED19[3];
1071   __IOM SPIM_RXD_Type RXD;                      /*!< (@ 0x00000534) RXD EasyDMA channel                                        */
1072   __IOM SPIM_TXD_Type TXD;                      /*!< (@ 0x00000544) TXD EasyDMA channel                                        */
1073   __IOM uint32_t  CONFIG;                       /*!< (@ 0x00000554) Configuration register                                     */
1074   __IM  uint32_t  RESERVED20[26];
1075   __IOM uint32_t  ORC;                          /*!< (@ 0x000005C0) Over-read character. Character clocked out in
1076                                                                     case an over-read of the TXD buffer.                       */
1077 } NRF_SPIM_Type;                                /*!< Size = 1476 (0x5c4)                                                       */
1078 
1079 
1080 
1081 /* =========================================================================================================================== */
1082 /* ================                                         SPIS0_NS                                          ================ */
1083 /* =========================================================================================================================== */
1084 
1085 
1086 /**
1087   * @brief SPI Slave 0 (SPIS0_NS)
1088   */
1089 
1090 typedef struct {                                /*!< (@ 0x40008000) SPIS0_NS Structure                                         */
1091   __IM  uint32_t  RESERVED[9];
1092   __OM  uint32_t  TASKS_ACQUIRE;                /*!< (@ 0x00000024) Acquire SPI semaphore                                      */
1093   __OM  uint32_t  TASKS_RELEASE;                /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave
1094                                                                     to acquire it                                              */
1095   __IM  uint32_t  RESERVED1[30];
1096   __IOM uint32_t  SUBSCRIBE_ACQUIRE;            /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE                   */
1097   __IOM uint32_t  SUBSCRIBE_RELEASE;            /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE                   */
1098   __IM  uint32_t  RESERVED2[22];
1099   __IOM uint32_t  EVENTS_END;                   /*!< (@ 0x00000104) Granted transaction completed                              */
1100   __IM  uint32_t  RESERVED3[2];
1101   __IOM uint32_t  EVENTS_ENDRX;                 /*!< (@ 0x00000110) End of RXD buffer reached                                  */
1102   __IM  uint32_t  RESERVED4[5];
1103   __IOM uint32_t  EVENTS_ACQUIRED;              /*!< (@ 0x00000128) Semaphore acquired                                         */
1104   __IM  uint32_t  RESERVED5[22];
1105   __IOM uint32_t  PUBLISH_END;                  /*!< (@ 0x00000184) Publish configuration for event END                        */
1106   __IM  uint32_t  RESERVED6[2];
1107   __IOM uint32_t  PUBLISH_ENDRX;                /*!< (@ 0x00000190) Publish configuration for event ENDRX                      */
1108   __IM  uint32_t  RESERVED7[5];
1109   __IOM uint32_t  PUBLISH_ACQUIRED;             /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED                   */
1110   __IM  uint32_t  RESERVED8[21];
1111   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
1112   __IM  uint32_t  RESERVED9[64];
1113   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1114   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1115   __IM  uint32_t  RESERVED10[61];
1116   __IM  uint32_t  SEMSTAT;                      /*!< (@ 0x00000400) Semaphore status register                                  */
1117   __IM  uint32_t  RESERVED11[15];
1118   __IOM uint32_t  STATUS;                       /*!< (@ 0x00000440) Status from last transaction                               */
1119   __IM  uint32_t  RESERVED12[47];
1120   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable SPI slave                                           */
1121   __IM  uint32_t  RESERVED13;
1122   __IOM SPIS_PSEL_Type PSEL;                    /*!< (@ 0x00000508) Unspecified                                                */
1123   __IM  uint32_t  RESERVED14[7];
1124   __IOM SPIS_RXD_Type RXD;                      /*!< (@ 0x00000534) Unspecified                                                */
1125   __IOM SPIS_TXD_Type TXD;                      /*!< (@ 0x00000544) Unspecified                                                */
1126   __IOM uint32_t  CONFIG;                       /*!< (@ 0x00000554) Configuration register                                     */
1127   __IM  uint32_t  RESERVED15;
1128   __IOM uint32_t  DEF;                          /*!< (@ 0x0000055C) Default character. Character clocked out in case
1129                                                                     of an ignored transaction.                                 */
1130   __IM  uint32_t  RESERVED16[24];
1131   __IOM uint32_t  ORC;                          /*!< (@ 0x000005C0) Over-read character                                        */
1132 } NRF_SPIS_Type;                                /*!< Size = 1476 (0x5c4)                                                       */
1133 
1134 
1135 
1136 /* =========================================================================================================================== */
1137 /* ================                                         TWIM0_NS                                          ================ */
1138 /* =========================================================================================================================== */
1139 
1140 
1141 /**
1142   * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS)
1143   */
1144 
1145 typedef struct {                                /*!< (@ 0x40008000) TWIM0_NS Structure                                         */
1146   __OM  uint32_t  TASKS_STARTRX;                /*!< (@ 0x00000000) Start TWI receive sequence                                 */
1147   __IM  uint32_t  RESERVED;
1148   __OM  uint32_t  TASKS_STARTTX;                /*!< (@ 0x00000008) Start TWI transmit sequence                                */
1149   __IM  uint32_t  RESERVED1[2];
1150   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the
1151                                                                     TWI master is not suspended.                               */
1152   __IM  uint32_t  RESERVED2;
1153   __OM  uint32_t  TASKS_SUSPEND;                /*!< (@ 0x0000001C) Suspend TWI transaction                                    */
1154   __OM  uint32_t  TASKS_RESUME;                 /*!< (@ 0x00000020) Resume TWI transaction                                     */
1155   __IM  uint32_t  RESERVED3[23];
1156   __IOM uint32_t  SUBSCRIBE_STARTRX;            /*!< (@ 0x00000080) Subscribe configuration for task STARTRX                   */
1157   __IM  uint32_t  RESERVED4;
1158   __IOM uint32_t  SUBSCRIBE_STARTTX;            /*!< (@ 0x00000088) Subscribe configuration for task STARTTX                   */
1159   __IM  uint32_t  RESERVED5[2];
1160   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000094) Subscribe configuration for task STOP                      */
1161   __IM  uint32_t  RESERVED6;
1162   __IOM uint32_t  SUBSCRIBE_SUSPEND;            /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND                   */
1163   __IOM uint32_t  SUBSCRIBE_RESUME;             /*!< (@ 0x000000A0) Subscribe configuration for task RESUME                    */
1164   __IM  uint32_t  RESERVED7[24];
1165   __IOM uint32_t  EVENTS_STOPPED;               /*!< (@ 0x00000104) TWI stopped                                                */
1166   __IM  uint32_t  RESERVED8[7];
1167   __IOM uint32_t  EVENTS_ERROR;                 /*!< (@ 0x00000124) TWI error                                                  */
1168   __IM  uint32_t  RESERVED9[8];
1169   __IOM uint32_t  EVENTS_SUSPENDED;             /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is
1170                                                                     now suspended.                                             */
1171   __IOM uint32_t  EVENTS_RXSTARTED;             /*!< (@ 0x0000014C) Receive sequence started                                   */
1172   __IOM uint32_t  EVENTS_TXSTARTED;             /*!< (@ 0x00000150) Transmit sequence started                                  */
1173   __IM  uint32_t  RESERVED10[2];
1174   __IOM uint32_t  EVENTS_LASTRX;                /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte           */
1175   __IOM uint32_t  EVENTS_LASTTX;                /*!< (@ 0x00000160) Byte boundary, starting to transmit the last
1176                                                                     byte                                                       */
1177   __IM  uint32_t  RESERVED11[8];
1178   __IOM uint32_t  PUBLISH_STOPPED;              /*!< (@ 0x00000184) Publish configuration for event STOPPED                    */
1179   __IM  uint32_t  RESERVED12[7];
1180   __IOM uint32_t  PUBLISH_ERROR;                /*!< (@ 0x000001A4) Publish configuration for event ERROR                      */
1181   __IM  uint32_t  RESERVED13[8];
1182   __IOM uint32_t  PUBLISH_SUSPENDED;            /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED                  */
1183   __IOM uint32_t  PUBLISH_RXSTARTED;            /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED                  */
1184   __IOM uint32_t  PUBLISH_TXSTARTED;            /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED                  */
1185   __IM  uint32_t  RESERVED14[2];
1186   __IOM uint32_t  PUBLISH_LASTRX;               /*!< (@ 0x000001DC) Publish configuration for event LASTRX                     */
1187   __IOM uint32_t  PUBLISH_LASTTX;               /*!< (@ 0x000001E0) Publish configuration for event LASTTX                     */
1188   __IM  uint32_t  RESERVED15[7];
1189   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
1190   __IM  uint32_t  RESERVED16[63];
1191   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1192   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1193   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1194   __IM  uint32_t  RESERVED17[110];
1195   __IOM uint32_t  ERRORSRC;                     /*!< (@ 0x000004C4) Error source                                               */
1196   __IM  uint32_t  RESERVED18[14];
1197   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable TWIM                                                */
1198   __IM  uint32_t  RESERVED19;
1199   __IOM TWIM_PSEL_Type PSEL;                    /*!< (@ 0x00000508) Unspecified                                                */
1200   __IM  uint32_t  RESERVED20[5];
1201   __IOM uint32_t  FREQUENCY;                    /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK
1202                                                                     source selected.                                           */
1203   __IM  uint32_t  RESERVED21[3];
1204   __IOM TWIM_RXD_Type RXD;                      /*!< (@ 0x00000534) RXD EasyDMA channel                                        */
1205   __IOM TWIM_TXD_Type TXD;                      /*!< (@ 0x00000544) TXD EasyDMA channel                                        */
1206   __IM  uint32_t  RESERVED22[13];
1207   __IOM uint32_t  ADDRESS;                      /*!< (@ 0x00000588) Address used in the TWI transfer                           */
1208 } NRF_TWIM_Type;                                /*!< Size = 1420 (0x58c)                                                       */
1209 
1210 
1211 
1212 /* =========================================================================================================================== */
1213 /* ================                                         TWIS0_NS                                          ================ */
1214 /* =========================================================================================================================== */
1215 
1216 
1217 /**
1218   * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS)
1219   */
1220 
1221 typedef struct {                                /*!< (@ 0x40008000) TWIS0_NS Structure                                         */
1222   __IM  uint32_t  RESERVED[5];
1223   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000014) Stop TWI transaction                                       */
1224   __IM  uint32_t  RESERVED1;
1225   __OM  uint32_t  TASKS_SUSPEND;                /*!< (@ 0x0000001C) Suspend TWI transaction                                    */
1226   __OM  uint32_t  TASKS_RESUME;                 /*!< (@ 0x00000020) Resume TWI transaction                                     */
1227   __IM  uint32_t  RESERVED2[3];
1228   __OM  uint32_t  TASKS_PREPARERX;              /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command        */
1229   __OM  uint32_t  TASKS_PREPARETX;              /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command         */
1230   __IM  uint32_t  RESERVED3[23];
1231   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000094) Subscribe configuration for task STOP                      */
1232   __IM  uint32_t  RESERVED4;
1233   __IOM uint32_t  SUBSCRIBE_SUSPEND;            /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND                   */
1234   __IOM uint32_t  SUBSCRIBE_RESUME;             /*!< (@ 0x000000A0) Subscribe configuration for task RESUME                    */
1235   __IM  uint32_t  RESERVED5[3];
1236   __IOM uint32_t  SUBSCRIBE_PREPARERX;          /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX                 */
1237   __IOM uint32_t  SUBSCRIBE_PREPARETX;          /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX                 */
1238   __IM  uint32_t  RESERVED6[19];
1239   __IOM uint32_t  EVENTS_STOPPED;               /*!< (@ 0x00000104) TWI stopped                                                */
1240   __IM  uint32_t  RESERVED7[7];
1241   __IOM uint32_t  EVENTS_ERROR;                 /*!< (@ 0x00000124) TWI error                                                  */
1242   __IM  uint32_t  RESERVED8[9];
1243   __IOM uint32_t  EVENTS_RXSTARTED;             /*!< (@ 0x0000014C) Receive sequence started                                   */
1244   __IOM uint32_t  EVENTS_TXSTARTED;             /*!< (@ 0x00000150) Transmit sequence started                                  */
1245   __IM  uint32_t  RESERVED9[4];
1246   __IOM uint32_t  EVENTS_WRITE;                 /*!< (@ 0x00000164) Write command received                                     */
1247   __IOM uint32_t  EVENTS_READ;                  /*!< (@ 0x00000168) Read command received                                      */
1248   __IM  uint32_t  RESERVED10[6];
1249   __IOM uint32_t  PUBLISH_STOPPED;              /*!< (@ 0x00000184) Publish configuration for event STOPPED                    */
1250   __IM  uint32_t  RESERVED11[7];
1251   __IOM uint32_t  PUBLISH_ERROR;                /*!< (@ 0x000001A4) Publish configuration for event ERROR                      */
1252   __IM  uint32_t  RESERVED12[9];
1253   __IOM uint32_t  PUBLISH_RXSTARTED;            /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED                  */
1254   __IOM uint32_t  PUBLISH_TXSTARTED;            /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED                  */
1255   __IM  uint32_t  RESERVED13[4];
1256   __IOM uint32_t  PUBLISH_WRITE;                /*!< (@ 0x000001E4) Publish configuration for event WRITE                      */
1257   __IOM uint32_t  PUBLISH_READ;                 /*!< (@ 0x000001E8) Publish configuration for event READ                       */
1258   __IM  uint32_t  RESERVED14[5];
1259   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
1260   __IM  uint32_t  RESERVED15[63];
1261   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1262   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1263   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1264   __IM  uint32_t  RESERVED16[113];
1265   __IOM uint32_t  ERRORSRC;                     /*!< (@ 0x000004D0) Error source                                               */
1266   __IM  uint32_t  MATCH;                        /*!< (@ 0x000004D4) Status register indicating which address had
1267                                                                     a match                                                    */
1268   __IM  uint32_t  RESERVED17[10];
1269   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable TWIS                                                */
1270   __IM  uint32_t  RESERVED18;
1271   __IOM TWIS_PSEL_Type PSEL;                    /*!< (@ 0x00000508) Unspecified                                                */
1272   __IM  uint32_t  RESERVED19[9];
1273   __IOM TWIS_RXD_Type RXD;                      /*!< (@ 0x00000534) RXD EasyDMA channel                                        */
1274   __IOM TWIS_TXD_Type TXD;                      /*!< (@ 0x00000544) TXD EasyDMA channel                                        */
1275   __IM  uint32_t  RESERVED20[13];
1276   __IOM uint32_t  ADDRESS[2];                   /*!< (@ 0x00000588) Description collection: TWI slave address n                */
1277   __IM  uint32_t  RESERVED21;
1278   __IOM uint32_t  CONFIG;                       /*!< (@ 0x00000594) Configuration register for the address match
1279                                                                     mechanism                                                  */
1280   __IM  uint32_t  RESERVED22[10];
1281   __IOM uint32_t  ORC;                          /*!< (@ 0x000005C0) Over-read character. Character sent out in case
1282                                                                     of an over-read of the transmit buffer.                    */
1283 } NRF_TWIS_Type;                                /*!< Size = 1476 (0x5c4)                                                       */
1284 
1285 
1286 
1287 /* =========================================================================================================================== */
1288 /* ================                                         UARTE0_NS                                         ================ */
1289 /* =========================================================================================================================== */
1290 
1291 
1292 /**
1293   * @brief UART with EasyDMA 0 (UARTE0_NS)
1294   */
1295 
1296 typedef struct {                                /*!< (@ 0x40008000) UARTE0_NS Structure                                        */
1297   __OM  uint32_t  TASKS_STARTRX;                /*!< (@ 0x00000000) Start UART receiver                                        */
1298   __OM  uint32_t  TASKS_STOPRX;                 /*!< (@ 0x00000004) Stop UART receiver                                         */
1299   __OM  uint32_t  TASKS_STARTTX;                /*!< (@ 0x00000008) Start UART transmitter                                     */
1300   __OM  uint32_t  TASKS_STOPTX;                 /*!< (@ 0x0000000C) Stop UART transmitter                                      */
1301   __IM  uint32_t  RESERVED[7];
1302   __OM  uint32_t  TASKS_FLUSHRX;                /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer                               */
1303   __IM  uint32_t  RESERVED1[20];
1304   __IOM uint32_t  SUBSCRIBE_STARTRX;            /*!< (@ 0x00000080) Subscribe configuration for task STARTRX                   */
1305   __IOM uint32_t  SUBSCRIBE_STOPRX;             /*!< (@ 0x00000084) Subscribe configuration for task STOPRX                    */
1306   __IOM uint32_t  SUBSCRIBE_STARTTX;            /*!< (@ 0x00000088) Subscribe configuration for task STARTTX                   */
1307   __IOM uint32_t  SUBSCRIBE_STOPTX;             /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX                    */
1308   __IM  uint32_t  RESERVED2[7];
1309   __IOM uint32_t  SUBSCRIBE_FLUSHRX;            /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX                   */
1310   __IM  uint32_t  RESERVED3[20];
1311   __IOM uint32_t  EVENTS_CTS;                   /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send.                 */
1312   __IOM uint32_t  EVENTS_NCTS;                  /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send.          */
1313   __IOM uint32_t  EVENTS_RXDRDY;                /*!< (@ 0x00000108) Data received in RXD (but potentially not yet
1314                                                                     transferred to Data RAM)                                   */
1315   __IM  uint32_t  RESERVED4;
1316   __IOM uint32_t  EVENTS_ENDRX;                 /*!< (@ 0x00000110) Receive buffer is filled up                                */
1317   __IM  uint32_t  RESERVED5[2];
1318   __IOM uint32_t  EVENTS_TXDRDY;                /*!< (@ 0x0000011C) Data sent from TXD                                         */
1319   __IOM uint32_t  EVENTS_ENDTX;                 /*!< (@ 0x00000120) Last TX byte transmitted                                   */
1320   __IOM uint32_t  EVENTS_ERROR;                 /*!< (@ 0x00000124) Error detected                                             */
1321   __IM  uint32_t  RESERVED6[7];
1322   __IOM uint32_t  EVENTS_RXTO;                  /*!< (@ 0x00000144) Receiver timeout                                           */
1323   __IM  uint32_t  RESERVED7;
1324   __IOM uint32_t  EVENTS_RXSTARTED;             /*!< (@ 0x0000014C) UART receiver has started                                  */
1325   __IOM uint32_t  EVENTS_TXSTARTED;             /*!< (@ 0x00000150) UART transmitter has started                               */
1326   __IM  uint32_t  RESERVED8;
1327   __IOM uint32_t  EVENTS_TXSTOPPED;             /*!< (@ 0x00000158) Transmitter stopped                                        */
1328   __IM  uint32_t  RESERVED9[9];
1329   __IOM uint32_t  PUBLISH_CTS;                  /*!< (@ 0x00000180) Publish configuration for event CTS                        */
1330   __IOM uint32_t  PUBLISH_NCTS;                 /*!< (@ 0x00000184) Publish configuration for event NCTS                       */
1331   __IOM uint32_t  PUBLISH_RXDRDY;               /*!< (@ 0x00000188) Publish configuration for event RXDRDY                     */
1332   __IM  uint32_t  RESERVED10;
1333   __IOM uint32_t  PUBLISH_ENDRX;                /*!< (@ 0x00000190) Publish configuration for event ENDRX                      */
1334   __IM  uint32_t  RESERVED11[2];
1335   __IOM uint32_t  PUBLISH_TXDRDY;               /*!< (@ 0x0000019C) Publish configuration for event TXDRDY                     */
1336   __IOM uint32_t  PUBLISH_ENDTX;                /*!< (@ 0x000001A0) Publish configuration for event ENDTX                      */
1337   __IOM uint32_t  PUBLISH_ERROR;                /*!< (@ 0x000001A4) Publish configuration for event ERROR                      */
1338   __IM  uint32_t  RESERVED12[7];
1339   __IOM uint32_t  PUBLISH_RXTO;                 /*!< (@ 0x000001C4) Publish configuration for event RXTO                       */
1340   __IM  uint32_t  RESERVED13;
1341   __IOM uint32_t  PUBLISH_RXSTARTED;            /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED                  */
1342   __IOM uint32_t  PUBLISH_TXSTARTED;            /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED                  */
1343   __IM  uint32_t  RESERVED14;
1344   __IOM uint32_t  PUBLISH_TXSTOPPED;            /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED                  */
1345   __IM  uint32_t  RESERVED15[9];
1346   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
1347   __IM  uint32_t  RESERVED16[63];
1348   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1349   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1350   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1351   __IM  uint32_t  RESERVED17[93];
1352   __IOM uint32_t  ERRORSRC;                     /*!< (@ 0x00000480) Error source This register is read/write one
1353                                                                     to clear.                                                  */
1354   __IM  uint32_t  RESERVED18[31];
1355   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable UART                                                */
1356   __IM  uint32_t  RESERVED19;
1357   __IOM UARTE_PSEL_Type PSEL;                   /*!< (@ 0x00000508) Unspecified                                                */
1358   __IM  uint32_t  RESERVED20[3];
1359   __IOM uint32_t  BAUDRATE;                     /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
1360                                                                     selected.                                                  */
1361   __IM  uint32_t  RESERVED21[3];
1362   __IOM UARTE_RXD_Type RXD;                     /*!< (@ 0x00000534) RXD EasyDMA channel                                        */
1363   __IM  uint32_t  RESERVED22;
1364   __IOM UARTE_TXD_Type TXD;                     /*!< (@ 0x00000544) TXD EasyDMA channel                                        */
1365   __IM  uint32_t  RESERVED23[7];
1366   __IOM uint32_t  CONFIG;                       /*!< (@ 0x0000056C) Configuration of parity and hardware flow control          */
1367 } NRF_UARTE_Type;                               /*!< Size = 1392 (0x570)                                                       */
1368 
1369 
1370 
1371 /* =========================================================================================================================== */
1372 /* ================                                         GPIOTE0_S                                         ================ */
1373 /* =========================================================================================================================== */
1374 
1375 
1376 /**
1377   * @brief GPIO Tasks and Events 0 (GPIOTE0_S)
1378   */
1379 
1380 typedef struct {                                /*!< (@ 0x5000D000) GPIOTE0_S Structure                                        */
1381   __OM  uint32_t  TASKS_OUT[8];                 /*!< (@ 0x00000000) Description collection: Task for writing to pin
1382                                                                     specified in CONFIG[n].PSEL. Action on pin
1383                                                                     is configured in CONFIG[n].POLARITY.                       */
1384   __IM  uint32_t  RESERVED[4];
1385   __OM  uint32_t  TASKS_SET[8];                 /*!< (@ 0x00000030) Description collection: Task for writing to pin
1386                                                                     specified in CONFIG[n].PSEL. Action on pin
1387                                                                     is to set it high.                                         */
1388   __IM  uint32_t  RESERVED1[4];
1389   __OM  uint32_t  TASKS_CLR[8];                 /*!< (@ 0x00000060) Description collection: Task for writing to pin
1390                                                                     specified in CONFIG[n].PSEL. Action on pin
1391                                                                     is to set it low.                                          */
1392   __IOM uint32_t  SUBSCRIBE_OUT[8];             /*!< (@ 0x00000080) Description collection: Subscribe configuration
1393                                                                     for task OUT[n]                                            */
1394   __IM  uint32_t  RESERVED2[4];
1395   __IOM uint32_t  SUBSCRIBE_SET[8];             /*!< (@ 0x000000B0) Description collection: Subscribe configuration
1396                                                                     for task SET[n]                                            */
1397   __IM  uint32_t  RESERVED3[4];
1398   __IOM uint32_t  SUBSCRIBE_CLR[8];             /*!< (@ 0x000000E0) Description collection: Subscribe configuration
1399                                                                     for task CLR[n]                                            */
1400   __IOM uint32_t  EVENTS_IN[8];                 /*!< (@ 0x00000100) Description collection: Event generated from
1401                                                                     pin specified in CONFIG[n].PSEL                            */
1402   __IM  uint32_t  RESERVED4[23];
1403   __IOM uint32_t  EVENTS_PORT;                  /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins
1404                                                                     with SENSE mechanism enabled                               */
1405   __IOM uint32_t  PUBLISH_IN[8];                /*!< (@ 0x00000180) Description collection: Publish configuration
1406                                                                     for event IN[n]                                            */
1407   __IM  uint32_t  RESERVED5[23];
1408   __IOM uint32_t  PUBLISH_PORT;                 /*!< (@ 0x000001FC) Publish configuration for event PORT                       */
1409   __IM  uint32_t  RESERVED6[65];
1410   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1411   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1412   __IM  uint32_t  RESERVED7[129];
1413   __IOM uint32_t  CONFIG[8];                    /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
1414                                                                     SET[n], and CLR[n] tasks and IN[n] event                   */
1415 } NRF_GPIOTE_Type;                              /*!< Size = 1328 (0x530)                                                       */
1416 
1417 
1418 
1419 /* =========================================================================================================================== */
1420 /* ================                                         SAADC_NS                                          ================ */
1421 /* =========================================================================================================================== */
1422 
1423 
1424 /**
1425   * @brief Analog to Digital Converter 0 (SAADC_NS)
1426   */
1427 
1428 typedef struct {                                /*!< (@ 0x4000E000) SAADC_NS Structure                                         */
1429   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in
1430                                                                     RAM                                                        */
1431   __OM  uint32_t  TASKS_SAMPLE;                 /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels
1432                                                                     are sampled                                                */
1433   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion         */
1434   __OM  uint32_t  TASKS_CALIBRATEOFFSET;        /*!< (@ 0x0000000C) Starts offset auto-calibration                             */
1435   __IM  uint32_t  RESERVED[28];
1436   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
1437   __IOM uint32_t  SUBSCRIBE_SAMPLE;             /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE                    */
1438   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000088) Subscribe configuration for task STOP                      */
1439   __IOM uint32_t  SUBSCRIBE_CALIBRATEOFFSET;    /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET           */
1440   __IM  uint32_t  RESERVED1[28];
1441   __IOM uint32_t  EVENTS_STARTED;               /*!< (@ 0x00000100) The ADC has started                                        */
1442   __IOM uint32_t  EVENTS_END;                   /*!< (@ 0x00000104) The ADC has filled up the Result buffer                    */
1443   __IOM uint32_t  EVENTS_DONE;                  /*!< (@ 0x00000108) A conversion task has been completed. Depending
1444                                                                     on the mode, multiple conversions might
1445                                                                     be needed for a result to be transferred
1446                                                                     to RAM.                                                    */
1447   __IOM uint32_t  EVENTS_RESULTDONE;            /*!< (@ 0x0000010C) A result is ready to get transferred to RAM.               */
1448   __IOM uint32_t  EVENTS_CALIBRATEDONE;         /*!< (@ 0x00000110) Calibration is complete                                    */
1449   __IOM uint32_t  EVENTS_STOPPED;               /*!< (@ 0x00000114) The ADC has stopped                                        */
1450   __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8];      /*!< (@ 0x00000118) Peripheral events.                                         */
1451   __IM  uint32_t  RESERVED2[10];
1452   __IOM uint32_t  PUBLISH_STARTED;              /*!< (@ 0x00000180) Publish configuration for event STARTED                    */
1453   __IOM uint32_t  PUBLISH_END;                  /*!< (@ 0x00000184) Publish configuration for event END                        */
1454   __IOM uint32_t  PUBLISH_DONE;                 /*!< (@ 0x00000188) Publish configuration for event DONE                       */
1455   __IOM uint32_t  PUBLISH_RESULTDONE;           /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE                 */
1456   __IOM uint32_t  PUBLISH_CALIBRATEDONE;        /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE              */
1457   __IOM uint32_t  PUBLISH_STOPPED;              /*!< (@ 0x00000194) Publish configuration for event STOPPED                    */
1458   __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8];    /*!< (@ 0x00000198) Publish configuration for events                           */
1459   __IM  uint32_t  RESERVED3[74];
1460   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1461   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1462   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1463   __IM  uint32_t  RESERVED4[61];
1464   __IM  uint32_t  STATUS;                       /*!< (@ 0x00000400) Status                                                     */
1465   __IM  uint32_t  RESERVED5[63];
1466   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable or disable ADC                                      */
1467   __IM  uint32_t  RESERVED6[3];
1468   __IOM SAADC_CH_Type CH[8];                    /*!< (@ 0x00000510) Unspecified                                                */
1469   __IM  uint32_t  RESERVED7[24];
1470   __IOM uint32_t  RESOLUTION;                   /*!< (@ 0x000005F0) Resolution configuration                                   */
1471   __IOM uint32_t  OVERSAMPLE;                   /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should
1472                                                                     not be combined with SCAN. The RESOLUTION
1473                                                                     is applied before averaging, thus for high
1474                                                                     OVERSAMPLE a higher RESOLUTION should be
1475                                                                     used.                                                      */
1476   __IOM uint32_t  SAMPLERATE;                   /*!< (@ 0x000005F8) Controls normal or continuous sample rate                  */
1477   __IM  uint32_t  RESERVED8[12];
1478   __IOM SAADC_RESULT_Type RESULT;               /*!< (@ 0x0000062C) RESULT EasyDMA channel                                     */
1479 } NRF_SAADC_Type;                               /*!< Size = 1592 (0x638)                                                       */
1480 
1481 
1482 
1483 /* =========================================================================================================================== */
1484 /* ================                                         TIMER0_NS                                         ================ */
1485 /* =========================================================================================================================== */
1486 
1487 
1488 /**
1489   * @brief Timer/Counter 0 (TIMER0_NS)
1490   */
1491 
1492 typedef struct {                                /*!< (@ 0x4000F000) TIMER0_NS Structure                                        */
1493   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Start Timer                                                */
1494   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000004) Stop Timer                                                 */
1495   __OM  uint32_t  TASKS_COUNT;                  /*!< (@ 0x00000008) Increment Timer (Counter mode only)                        */
1496   __OM  uint32_t  TASKS_CLEAR;                  /*!< (@ 0x0000000C) Clear time                                                 */
1497   __OM  uint32_t  TASKS_SHUTDOWN;               /*!< (@ 0x00000010) Deprecated register - Shut down timer                      */
1498   __IM  uint32_t  RESERVED[11];
1499   __OM  uint32_t  TASKS_CAPTURE[6];             /*!< (@ 0x00000040) Description collection: Capture Timer value to
1500                                                                     CC[n] register                                             */
1501   __IM  uint32_t  RESERVED1[10];
1502   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
1503   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000084) Subscribe configuration for task STOP                      */
1504   __IOM uint32_t  SUBSCRIBE_COUNT;              /*!< (@ 0x00000088) Subscribe configuration for task COUNT                     */
1505   __IOM uint32_t  SUBSCRIBE_CLEAR;              /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR                     */
1506   __IOM uint32_t  SUBSCRIBE_SHUTDOWN;           /*!< (@ 0x00000090) Deprecated register - Subscribe configuration
1507                                                                     for task SHUTDOWN                                          */
1508   __IM  uint32_t  RESERVED2[11];
1509   __IOM uint32_t  SUBSCRIBE_CAPTURE[6];         /*!< (@ 0x000000C0) Description collection: Subscribe configuration
1510                                                                     for task CAPTURE[n]                                        */
1511   __IM  uint32_t  RESERVED3[26];
1512   __IOM uint32_t  EVENTS_COMPARE[6];            /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
1513                                                                     match                                                      */
1514   __IM  uint32_t  RESERVED4[26];
1515   __IOM uint32_t  PUBLISH_COMPARE[6];           /*!< (@ 0x000001C0) Description collection: Publish configuration
1516                                                                     for event COMPARE[n]                                       */
1517   __IM  uint32_t  RESERVED5[10];
1518   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
1519   __IM  uint32_t  RESERVED6[64];
1520   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1521   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1522   __IM  uint32_t  RESERVED7[126];
1523   __IOM uint32_t  MODE;                         /*!< (@ 0x00000504) Timer mode selection                                       */
1524   __IOM uint32_t  BITMODE;                      /*!< (@ 0x00000508) Configure the number of bits used by the TIMER             */
1525   __IM  uint32_t  RESERVED8;
1526   __IOM uint32_t  PRESCALER;                    /*!< (@ 0x00000510) Timer prescaler register                                   */
1527   __IOM uint32_t  ONESHOTEN[6];                 /*!< (@ 0x00000514) Description collection: Enable one-shot operation
1528                                                                     for Capture/Compare channel n                              */
1529   __IM  uint32_t  RESERVED9[5];
1530   __IOM uint32_t  CC[6];                        /*!< (@ 0x00000540) Description collection: Capture/Compare register
1531                                                                     n                                                          */
1532 } NRF_TIMER_Type;                               /*!< Size = 1368 (0x558)                                                       */
1533 
1534 
1535 
1536 /* =========================================================================================================================== */
1537 /* ================                                          RTC0_NS                                          ================ */
1538 /* =========================================================================================================================== */
1539 
1540 
1541 /**
1542   * @brief Real-time counter 0 (RTC0_NS)
1543   */
1544 
1545 typedef struct {                                /*!< (@ 0x40014000) RTC0_NS Structure                                          */
1546   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Start RTC counter                                          */
1547   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000004) Stop RTC counter                                           */
1548   __OM  uint32_t  TASKS_CLEAR;                  /*!< (@ 0x00000008) Clear RTC counter                                          */
1549   __OM  uint32_t  TASKS_TRIGOVRFLW;             /*!< (@ 0x0000000C) Set counter to 0xFFFFF0                                    */
1550   __IM  uint32_t  RESERVED[28];
1551   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
1552   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000084) Subscribe configuration for task STOP                      */
1553   __IOM uint32_t  SUBSCRIBE_CLEAR;              /*!< (@ 0x00000088) Subscribe configuration for task CLEAR                     */
1554   __IOM uint32_t  SUBSCRIBE_TRIGOVRFLW;         /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW                */
1555   __IM  uint32_t  RESERVED1[28];
1556   __IOM uint32_t  EVENTS_TICK;                  /*!< (@ 0x00000100) Event on counter increment                                 */
1557   __IOM uint32_t  EVENTS_OVRFLW;                /*!< (@ 0x00000104) Event on counter overflow                                  */
1558   __IM  uint32_t  RESERVED2[14];
1559   __IOM uint32_t  EVENTS_COMPARE[4];            /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
1560                                                                     match                                                      */
1561   __IM  uint32_t  RESERVED3[12];
1562   __IOM uint32_t  PUBLISH_TICK;                 /*!< (@ 0x00000180) Publish configuration for event TICK                       */
1563   __IOM uint32_t  PUBLISH_OVRFLW;               /*!< (@ 0x00000184) Publish configuration for event OVRFLW                     */
1564   __IM  uint32_t  RESERVED4[14];
1565   __IOM uint32_t  PUBLISH_COMPARE[4];           /*!< (@ 0x000001C0) Description collection: Publish configuration
1566                                                                     for event COMPARE[n]                                       */
1567   __IM  uint32_t  RESERVED5[77];
1568   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1569   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1570   __IM  uint32_t  RESERVED6[13];
1571   __IOM uint32_t  EVTEN;                        /*!< (@ 0x00000340) Enable or disable event routing                            */
1572   __IOM uint32_t  EVTENSET;                     /*!< (@ 0x00000344) Enable event routing                                       */
1573   __IOM uint32_t  EVTENCLR;                     /*!< (@ 0x00000348) Disable event routing                                      */
1574   __IM  uint32_t  RESERVED7[110];
1575   __IM  uint32_t  COUNTER;                      /*!< (@ 0x00000504) Current counter value                                      */
1576   __IOM uint32_t  PRESCALER;                    /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)).
1577                                                                     Must be written when RTC is stopped.                       */
1578   __IM  uint32_t  RESERVED8[13];
1579   __IOM uint32_t  CC[4];                        /*!< (@ 0x00000540) Description collection: Compare register n                 */
1580 } NRF_RTC_Type;                                 /*!< Size = 1360 (0x550)                                                       */
1581 
1582 
1583 
1584 /* =========================================================================================================================== */
1585 /* ================                                         DPPIC_NS                                          ================ */
1586 /* =========================================================================================================================== */
1587 
1588 
1589 /**
1590   * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS)
1591   */
1592 
1593 typedef struct {                                /*!< (@ 0x40017000) DPPIC_NS Structure                                         */
1594   __OM  DPPIC_TASKS_CHG_Type TASKS_CHG[6];      /*!< (@ 0x00000000) Channel group tasks                                        */
1595   __IM  uint32_t  RESERVED[20];
1596   __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks                        */
1597   __IM  uint32_t  RESERVED1[276];
1598   __IOM uint32_t  CHEN;                         /*!< (@ 0x00000500) Channel enable register                                    */
1599   __IOM uint32_t  CHENSET;                      /*!< (@ 0x00000504) Channel enable set register                                */
1600   __IOM uint32_t  CHENCLR;                      /*!< (@ 0x00000508) Channel enable clear register                              */
1601   __IM  uint32_t  RESERVED2[189];
1602   __IOM uint32_t  CHG[6];                       /*!< (@ 0x00000800) Description collection: Channel group n Note:
1603                                                                     Writes to this register are ignored if either
1604                                                                     SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS
1605                                                                     is enabled                                                 */
1606 } NRF_DPPIC_Type;                               /*!< Size = 2072 (0x818)                                                       */
1607 
1608 
1609 
1610 /* =========================================================================================================================== */
1611 /* ================                                          WDT_NS                                           ================ */
1612 /* =========================================================================================================================== */
1613 
1614 
1615 /**
1616   * @brief Watchdog Timer 0 (WDT_NS)
1617   */
1618 
1619 typedef struct {                                /*!< (@ 0x40018000) WDT_NS Structure                                           */
1620   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Start the watchdog                                         */
1621   __IM  uint32_t  RESERVED[31];
1622   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
1623   __IM  uint32_t  RESERVED1[31];
1624   __IOM uint32_t  EVENTS_TIMEOUT;               /*!< (@ 0x00000100) Watchdog timeout                                           */
1625   __IM  uint32_t  RESERVED2[31];
1626   __IOM uint32_t  PUBLISH_TIMEOUT;              /*!< (@ 0x00000180) Publish configuration for event TIMEOUT                    */
1627   __IM  uint32_t  RESERVED3[96];
1628   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1629   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1630   __IM  uint32_t  RESERVED4[61];
1631   __IM  uint32_t  RUNSTATUS;                    /*!< (@ 0x00000400) Run status                                                 */
1632   __IM  uint32_t  REQSTATUS;                    /*!< (@ 0x00000404) Request status                                             */
1633   __IM  uint32_t  RESERVED5[63];
1634   __IOM uint32_t  CRV;                          /*!< (@ 0x00000504) Counter reload value                                       */
1635   __IOM uint32_t  RREN;                         /*!< (@ 0x00000508) Enable register for reload request registers               */
1636   __IOM uint32_t  CONFIG;                       /*!< (@ 0x0000050C) Configuration register                                     */
1637   __IM  uint32_t  RESERVED6[60];
1638   __OM  uint32_t  RR[8];                        /*!< (@ 0x00000600) Description collection: Reload request n                   */
1639 } NRF_WDT_Type;                                 /*!< Size = 1568 (0x620)                                                       */
1640 
1641 
1642 
1643 /* =========================================================================================================================== */
1644 /* ================                                          EGU0_NS                                          ================ */
1645 /* =========================================================================================================================== */
1646 
1647 
1648 /**
1649   * @brief Event generator unit 0 (EGU0_NS)
1650   */
1651 
1652 typedef struct {                                /*!< (@ 0x4001B000) EGU0_NS Structure                                          */
1653   __OM  uint32_t  TASKS_TRIGGER[16];            /*!< (@ 0x00000000) Description collection: Trigger n for triggering
1654                                                                     the corresponding TRIGGERED[n] event                       */
1655   __IM  uint32_t  RESERVED[16];
1656   __IOM uint32_t  SUBSCRIBE_TRIGGER[16];        /*!< (@ 0x00000080) Description collection: Subscribe configuration
1657                                                                     for task TRIGGER[n]                                        */
1658   __IM  uint32_t  RESERVED1[16];
1659   __IOM uint32_t  EVENTS_TRIGGERED[16];         /*!< (@ 0x00000100) Description collection: Event number n generated
1660                                                                     by triggering the corresponding TRIGGER[n]
1661                                                                     task                                                       */
1662   __IM  uint32_t  RESERVED2[16];
1663   __IOM uint32_t  PUBLISH_TRIGGERED[16];        /*!< (@ 0x00000180) Description collection: Publish configuration
1664                                                                     for event TRIGGERED[n]                                     */
1665   __IM  uint32_t  RESERVED3[80];
1666   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1667   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1668   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1669 } NRF_EGU_Type;                                 /*!< Size = 780 (0x30c)                                                        */
1670 
1671 
1672 
1673 /* =========================================================================================================================== */
1674 /* ================                                          PWM0_NS                                          ================ */
1675 /* =========================================================================================================================== */
1676 
1677 
1678 /**
1679   * @brief Pulse width modulation unit 0 (PWM0_NS)
1680   */
1681 
1682 typedef struct {                                /*!< (@ 0x40021000) PWM0_NS Structure                                          */
1683   __IM  uint32_t  RESERVED;
1684   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at
1685                                                                     the end of current PWM period, and stops
1686                                                                     sequence playback                                          */
1687   __OM  uint32_t  TASKS_SEQSTART[2];            /*!< (@ 0x00000008) Description collection: Loads the first PWM value
1688                                                                     on all enabled channels from sequence n,
1689                                                                     and starts playing that sequence at the
1690                                                                     rate defined in SEQ[n]REFRESH and/or DECODER.MODE.
1691                                                                     Causes PWM generation to start if not running.             */
1692   __OM  uint32_t  TASKS_NEXTSTEP;               /*!< (@ 0x00000010) Steps by one value in the current sequence on
1693                                                                     all enabled channels if DECODER.MODE=NextStep.
1694                                                                     Does not cause PWM generation to start if
1695                                                                     not running.                                               */
1696   __IM  uint32_t  RESERVED1[28];
1697   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000084) Subscribe configuration for task STOP                      */
1698   __IOM uint32_t  SUBSCRIBE_SEQSTART[2];        /*!< (@ 0x00000088) Description collection: Subscribe configuration
1699                                                                     for task SEQSTART[n]                                       */
1700   __IOM uint32_t  SUBSCRIBE_NEXTSTEP;           /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP                  */
1701   __IM  uint32_t  RESERVED2[28];
1702   __IOM uint32_t  EVENTS_STOPPED;               /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses
1703                                                                     are no longer generated                                    */
1704   __IOM uint32_t  EVENTS_SEQSTARTED[2];         /*!< (@ 0x00000108) Description collection: First PWM period started
1705                                                                     on sequence n                                              */
1706   __IOM uint32_t  EVENTS_SEQEND[2];             /*!< (@ 0x00000110) Description collection: Emitted at end of every
1707                                                                     sequence n, when last value from RAM has
1708                                                                     been applied to wave counter                               */
1709   __IOM uint32_t  EVENTS_PWMPERIODEND;          /*!< (@ 0x00000118) Emitted at the end of each PWM period                      */
1710   __IOM uint32_t  EVENTS_LOOPSDONE;             /*!< (@ 0x0000011C) Concatenated sequences have been played the amount
1711                                                                     of times defined in LOOP.CNT                               */
1712   __IM  uint32_t  RESERVED3[25];
1713   __IOM uint32_t  PUBLISH_STOPPED;              /*!< (@ 0x00000184) Publish configuration for event STOPPED                    */
1714   __IOM uint32_t  PUBLISH_SEQSTARTED[2];        /*!< (@ 0x00000188) Description collection: Publish configuration
1715                                                                     for event SEQSTARTED[n]                                    */
1716   __IOM uint32_t  PUBLISH_SEQEND[2];            /*!< (@ 0x00000190) Description collection: Publish configuration
1717                                                                     for event SEQEND[n]                                        */
1718   __IOM uint32_t  PUBLISH_PWMPERIODEND;         /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND               */
1719   __IOM uint32_t  PUBLISH_LOOPSDONE;            /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE                  */
1720   __IM  uint32_t  RESERVED4[24];
1721   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
1722   __IM  uint32_t  RESERVED5[63];
1723   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1724   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1725   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1726   __IM  uint32_t  RESERVED6[125];
1727   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) PWM module enable register                                 */
1728   __IOM uint32_t  MODE;                         /*!< (@ 0x00000504) Selects operating mode of the wave counter                 */
1729   __IOM uint32_t  COUNTERTOP;                   /*!< (@ 0x00000508) Value up to which the pulse generator counter
1730                                                                     counts                                                     */
1731   __IOM uint32_t  PRESCALER;                    /*!< (@ 0x0000050C) Configuration for PWM_CLK                                  */
1732   __IOM uint32_t  DECODER;                      /*!< (@ 0x00000510) Configuration of the decoder                               */
1733   __IOM uint32_t  LOOP;                         /*!< (@ 0x00000514) Number of playbacks of a loop                              */
1734   __IM  uint32_t  RESERVED7[2];
1735   __IOM PWM_SEQ_Type SEQ[2];                    /*!< (@ 0x00000520) Unspecified                                                */
1736   __IOM PWM_PSEL_Type PSEL;                     /*!< (@ 0x00000560) Unspecified                                                */
1737 } NRF_PWM_Type;                                 /*!< Size = 1392 (0x570)                                                       */
1738 
1739 
1740 
1741 /* =========================================================================================================================== */
1742 /* ================                                          PDM_NS                                           ================ */
1743 /* =========================================================================================================================== */
1744 
1745 
1746 /**
1747   * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS)
1748   */
1749 
1750 typedef struct {                                /*!< (@ 0x40026000) PDM_NS Structure                                           */
1751   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Starts continuous PDM transfer                             */
1752   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000004) Stops PDM transfer                                         */
1753   __IM  uint32_t  RESERVED[30];
1754   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
1755   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000084) Subscribe configuration for task STOP                      */
1756   __IM  uint32_t  RESERVED1[30];
1757   __IOM uint32_t  EVENTS_STARTED;               /*!< (@ 0x00000100) PDM transfer has started                                   */
1758   __IOM uint32_t  EVENTS_STOPPED;               /*!< (@ 0x00000104) PDM transfer has finished                                  */
1759   __IOM uint32_t  EVENTS_END;                   /*!< (@ 0x00000108) The PDM has written the last sample specified
1760                                                                     by SAMPLE.MAXCNT (or the last sample after
1761                                                                     a STOP task has been received) to Data RAM                 */
1762   __IM  uint32_t  RESERVED2[29];
1763   __IOM uint32_t  PUBLISH_STARTED;              /*!< (@ 0x00000180) Publish configuration for event STARTED                    */
1764   __IOM uint32_t  PUBLISH_STOPPED;              /*!< (@ 0x00000184) Publish configuration for event STOPPED                    */
1765   __IOM uint32_t  PUBLISH_END;                  /*!< (@ 0x00000188) Publish configuration for event END                        */
1766   __IM  uint32_t  RESERVED3[93];
1767   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1768   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1769   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1770   __IM  uint32_t  RESERVED4[125];
1771   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) PDM module enable register                                 */
1772   __IOM uint32_t  PDMCLKCTRL;                   /*!< (@ 0x00000504) PDM clock generator control                                */
1773   __IOM uint32_t  MODE;                         /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones'
1774                                                                     signals                                                    */
1775   __IM  uint32_t  RESERVED5[3];
1776   __IOM uint32_t  GAINL;                        /*!< (@ 0x00000518) Left output gain adjustment                                */
1777   __IOM uint32_t  GAINR;                        /*!< (@ 0x0000051C) Right output gain adjustment                               */
1778   __IOM uint32_t  RATIO;                        /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output
1779                                                                     sample rate. Change PDMCLKCTRL accordingly.                */
1780   __IM  uint32_t  RESERVED6[7];
1781   __IOM PDM_PSEL_Type PSEL;                     /*!< (@ 0x00000540) Unspecified                                                */
1782   __IM  uint32_t  RESERVED7[6];
1783   __IOM PDM_SAMPLE_Type SAMPLE;                 /*!< (@ 0x00000560) Unspecified                                                */
1784 } NRF_PDM_Type;                                 /*!< Size = 1384 (0x568)                                                       */
1785 
1786 
1787 
1788 /* =========================================================================================================================== */
1789 /* ================                                          I2S_NS                                           ================ */
1790 /* =========================================================================================================================== */
1791 
1792 
1793 /**
1794   * @brief Inter-IC Sound 0 (I2S_NS)
1795   */
1796 
1797 typedef struct {                                /*!< (@ 0x40028000) I2S_NS Structure                                           */
1798   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK
1799                                                                     generator when this is enabled.                            */
1800   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator.
1801                                                                     Triggering this task will cause the STOPPED
1802                                                                     event to be generated.                                     */
1803   __IM  uint32_t  RESERVED[30];
1804   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
1805   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000084) Subscribe configuration for task STOP                      */
1806   __IM  uint32_t  RESERVED1[31];
1807   __IOM uint32_t  EVENTS_RXPTRUPD;              /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal
1808                                                                     double-buffers. When the I2S module is started
1809                                                                     and RX is enabled, this event will be generated
1810                                                                     for every RXTXD.MAXCNT words that are received
1811                                                                     on the SDIN pin.                                           */
1812   __IOM uint32_t  EVENTS_STOPPED;               /*!< (@ 0x00000108) I2S transfer stopped.                                      */
1813   __IM  uint32_t  RESERVED2[2];
1814   __IOM uint32_t  EVENTS_TXPTRUPD;              /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal
1815                                                                     double-buffers. When the I2S module is started
1816                                                                     and TX is enabled, this event will be generated
1817                                                                     for every RXTXD.MAXCNT words that are sent
1818                                                                     on the SDOUT pin.                                          */
1819   __IM  uint32_t  RESERVED3[27];
1820   __IOM uint32_t  PUBLISH_RXPTRUPD;             /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD                   */
1821   __IOM uint32_t  PUBLISH_STOPPED;              /*!< (@ 0x00000188) Publish configuration for event STOPPED                    */
1822   __IM  uint32_t  RESERVED4[2];
1823   __IOM uint32_t  PUBLISH_TXPTRUPD;             /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD                   */
1824   __IM  uint32_t  RESERVED5[90];
1825   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1826   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1827   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1828   __IM  uint32_t  RESERVED6[125];
1829   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable I2S module.                                         */
1830   __IOM I2S_CONFIG_Type CONFIG;                 /*!< (@ 0x00000504) Unspecified                                                */
1831   __IM  uint32_t  RESERVED7[3];
1832   __IOM I2S_RXD_Type RXD;                       /*!< (@ 0x00000538) Unspecified                                                */
1833   __IM  uint32_t  RESERVED8;
1834   __IOM I2S_TXD_Type TXD;                       /*!< (@ 0x00000540) Unspecified                                                */
1835   __IM  uint32_t  RESERVED9[3];
1836   __IOM I2S_RXTXD_Type RXTXD;                   /*!< (@ 0x00000550) Unspecified                                                */
1837   __IM  uint32_t  RESERVED10[3];
1838   __IOM I2S_PSEL_Type PSEL;                     /*!< (@ 0x00000560) Unspecified                                                */
1839 } NRF_I2S_Type;                                 /*!< Size = 1396 (0x574)                                                       */
1840 
1841 
1842 
1843 /* =========================================================================================================================== */
1844 /* ================                                          IPC_NS                                           ================ */
1845 /* =========================================================================================================================== */
1846 
1847 
1848 /**
1849   * @brief Interprocessor communication 0 (IPC_NS)
1850   */
1851 
1852 typedef struct {                                /*!< (@ 0x4002A000) IPC_NS Structure                                           */
1853   __OM  uint32_t  TASKS_SEND[8];                /*!< (@ 0x00000000) Description collection: Trigger events on IPC
1854                                                                     channel enabled in SEND_CNF[n]                             */
1855   __IM  uint32_t  RESERVED[24];
1856   __IOM uint32_t  SUBSCRIBE_SEND[8];            /*!< (@ 0x00000080) Description collection: Subscribe configuration
1857                                                                     for task SEND[n]                                           */
1858   __IM  uint32_t  RESERVED1[24];
1859   __IOM uint32_t  EVENTS_RECEIVE[8];            /*!< (@ 0x00000100) Description collection: Event received on one
1860                                                                     or more of the enabled IPC channels in RECEIVE_CNF[n]      */
1861   __IM  uint32_t  RESERVED2[24];
1862   __IOM uint32_t  PUBLISH_RECEIVE[8];           /*!< (@ 0x00000180) Description collection: Publish configuration
1863                                                                     for event RECEIVE[n]                                       */
1864   __IM  uint32_t  RESERVED3[88];
1865   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1866   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1867   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1868   __IM  uint32_t  INTPEND;                      /*!< (@ 0x0000030C) Pending interrupts                                         */
1869   __IM  uint32_t  RESERVED4[128];
1870   __IOM uint32_t  SEND_CNF[8];                  /*!< (@ 0x00000510) Description collection: Send event configuration
1871                                                                     for TASKS_SEND[n]                                          */
1872   __IM  uint32_t  RESERVED5[24];
1873   __IOM uint32_t  RECEIVE_CNF[8];               /*!< (@ 0x00000590) Description collection: Receive event configuration
1874                                                                     for EVENTS_RECEIVE[n]                                      */
1875   __IM  uint32_t  RESERVED6[24];
1876   __IOM uint32_t  GPMEM[4];                     /*!< (@ 0x00000610) Description collection: General purpose memory             */
1877 } NRF_IPC_Type;                                 /*!< Size = 1568 (0x620)                                                       */
1878 
1879 
1880 
1881 /* =========================================================================================================================== */
1882 /* ================                                          FPU_NS                                           ================ */
1883 /* =========================================================================================================================== */
1884 
1885 
1886 /**
1887   * @brief FPU 0 (FPU_NS)
1888   */
1889 
1890 typedef struct {                                /*!< (@ 0x4002C000) FPU_NS Structure                                           */
1891   __IM  uint32_t  UNUSED;                       /*!< (@ 0x00000000) Unused.                                                    */
1892 } NRF_FPU_Type;                                 /*!< Size = 4 (0x4)                                                            */
1893 
1894 
1895 
1896 /* =========================================================================================================================== */
1897 /* ================                                       APPROTECT_NS                                        ================ */
1898 /* =========================================================================================================================== */
1899 
1900 
1901 /**
1902   * @brief Access Port Protection 0 (APPROTECT_NS)
1903   */
1904 
1905 typedef struct {                                /*!< (@ 0x40039000) APPROTECT_NS Structure                                     */
1906   __IM  uint32_t  RESERVED[896];
1907   __IOM APPROTECT_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000E00) Unspecified                                         */
1908   __IM  uint32_t  RESERVED1[2];
1909   __IOM APPROTECT_APPROTECT_Type APPROTECT;     /*!< (@ 0x00000E10) Unspecified                                                */
1910 } NRF_APPROTECT_Type;                           /*!< Size = 3608 (0xe18)                                                       */
1911 
1912 
1913 
1914 /* =========================================================================================================================== */
1915 /* ================                                          KMU_NS                                           ================ */
1916 /* =========================================================================================================================== */
1917 
1918 
1919 /**
1920   * @brief Key management unit 0 (KMU_NS)
1921   */
1922 
1923 typedef struct {                                /*!< (@ 0x40039000) KMU_NS Structure                                           */
1924   __OM  uint32_t  TASKS_PUSH_KEYSLOT;           /*!< (@ 0x00000000) Push a key slot over secure APB                            */
1925   __IM  uint32_t  RESERVED[63];
1926   __IOM uint32_t  EVENTS_KEYSLOT_PUSHED;        /*!< (@ 0x00000100) Key slot successfully pushed over secure APB               */
1927   __IOM uint32_t  EVENTS_KEYSLOT_REVOKED;       /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked
1928                                                                     for selection                                              */
1929   __IOM uint32_t  EVENTS_KEYSLOT_ERROR;         /*!< (@ 0x00000108) No key slot selected, no destination address
1930                                                                     defined, or error during push operation                    */
1931   __IM  uint32_t  RESERVED1[125];
1932   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1933   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1934   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1935   __IM  uint32_t  INTPEND;                      /*!< (@ 0x0000030C) Pending interrupts                                         */
1936   __IM  uint32_t  RESERVED2[63];
1937   __IM  uint32_t  STATUS;                       /*!< (@ 0x0000040C) Status bits for KMU operation                              */
1938   __IM  uint32_t  RESERVED3[60];
1939   __IOM uint32_t  SELECTKEYSLOT;                /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed
1940                                                                     over secure APB when TASKS_PUSH_KEYSLOT
1941                                                                     is started                                                 */
1942 } NRF_KMU_Type;                                 /*!< Size = 1284 (0x504)                                                       */
1943 
1944 
1945 
1946 /* =========================================================================================================================== */
1947 /* ================                                          NVMC_NS                                          ================ */
1948 /* =========================================================================================================================== */
1949 
1950 
1951 /**
1952   * @brief Non-volatile memory controller 0 (NVMC_NS)
1953   */
1954 
1955 typedef struct {                                /*!< (@ 0x40039000) NVMC_NS Structure                                          */
1956   __IM  uint32_t  RESERVED[256];
1957   __IM  uint32_t  READY;                        /*!< (@ 0x00000400) Ready flag                                                 */
1958   __IM  uint32_t  RESERVED1;
1959   __IM  uint32_t  READYNEXT;                    /*!< (@ 0x00000408) Ready flag                                                 */
1960   __IM  uint32_t  RESERVED2[62];
1961   __IOM uint32_t  CONFIG;                       /*!< (@ 0x00000504) Configuration register                                     */
1962   __IM  uint32_t  RESERVED3;
1963   __OM  uint32_t  ERASEALL;                     /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory          */
1964   __IM  uint32_t  RESERVED4[3];
1965   __IOM uint32_t  ERASEPAGEPARTIALCFG;          /*!< (@ 0x0000051C) Register for partial erase configuration                   */
1966   __IM  uint32_t  RESERVED5[8];
1967   __IOM uint32_t  ICACHECNF;                    /*!< (@ 0x00000540) I-code cache configuration register                        */
1968   __IM  uint32_t  RESERVED6;
1969   __IOM uint32_t  IHIT;                         /*!< (@ 0x00000548) I-code cache hit counter                                   */
1970   __IOM uint32_t  IMISS;                        /*!< (@ 0x0000054C) I-code cache miss counter                                  */
1971   __IM  uint32_t  RESERVED7[13];
1972   __IOM uint32_t  CONFIGNS;                     /*!< (@ 0x00000584) Unspecified                                                */
1973   __OM  uint32_t  WRITEUICRNS;                  /*!< (@ 0x00000588) Non-secure APPROTECT enable register                       */
1974 } NRF_NVMC_Type;                                /*!< Size = 1420 (0x58c)                                                       */
1975 
1976 
1977 
1978 /* =========================================================================================================================== */
1979 /* ================                                          VMC_NS                                           ================ */
1980 /* =========================================================================================================================== */
1981 
1982 
1983 /**
1984   * @brief Volatile Memory controller 0 (VMC_NS)
1985   */
1986 
1987 typedef struct {                                /*!< (@ 0x4003A000) VMC_NS Structure                                           */
1988   __IM  uint32_t  RESERVED[384];
1989   __IOM VMC_RAM_Type RAM[8];                    /*!< (@ 0x00000600) Unspecified                                                */
1990 } NRF_VMC_Type;                                 /*!< Size = 1664 (0x680)                                                       */
1991 
1992 
1993 
1994 /* =========================================================================================================================== */
1995 /* ================                                       CC_HOST_RGF_S                                       ================ */
1996 /* =========================================================================================================================== */
1997 
1998 
1999 /**
2000   * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF_S)
2001   */
2002 
2003 typedef struct {                                /*!< (@ 0x50840000) CC_HOST_RGF_S Structure                                    */
2004   __IM  uint32_t  RESERVED[1678];
2005   __IOM uint32_t  HOST_CRYPTOKEY_SEL;           /*!< (@ 0x00001A38) AES hardware key select                                    */
2006   __IM  uint32_t  RESERVED1[4];
2007   __IOM uint32_t  HOST_IOT_KPRTL_LOCK;          /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register.
2008                                                                     When this register is set, K_PRTL cannot
2009                                                                     be used and a zeroed key will be used instead.
2010                                                                     The value of this register is saved in the
2011                                                                     CRYPTOCELL AO power domain.                                */
2012   __IOM uint32_t  HOST_IOT_KDR0;                /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value
2013                                                                     of this register is saved in the CRYPTOCELL
2014                                                                     AO power domain. Reading from this address
2015                                                                     returns the K_DR valid status indicating
2016                                                                     if K_DR is successfully retained.                          */
2017   __OM  uint32_t  HOST_IOT_KDR1;                /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value
2018                                                                     of this register is saved in the CRYPTOCELL
2019                                                                     AO power domain.                                           */
2020   __OM  uint32_t  HOST_IOT_KDR2;                /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value
2021                                                                     of this register is saved in the CRYPTOCELL
2022                                                                     AO power domain.                                           */
2023   __OM  uint32_t  HOST_IOT_KDR3;                /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The
2024                                                                     value of this register is saved in the CRYPTOCELL
2025                                                                     AO power domain.                                           */
2026   __IOM uint32_t  HOST_IOT_LCS;                 /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL
2027                                                                     subsystem                                                  */
2028 } NRF_CC_HOST_RGF_Type;                         /*!< Size = 6756 (0x1a64)                                                      */
2029 
2030 
2031 
2032 /* =========================================================================================================================== */
2033 /* ================                                       CRYPTOCELL_S                                        ================ */
2034 /* =========================================================================================================================== */
2035 
2036 
2037 /**
2038   * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL_S)
2039   */
2040 
2041 typedef struct {                                /*!< (@ 0x50840000) CRYPTOCELL_S Structure                                     */
2042   __IM  uint32_t  RESERVED[320];
2043   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem                                */
2044 } NRF_CRYPTOCELL_Type;                          /*!< Size = 1284 (0x504)                                                       */
2045 
2046 
2047 
2048 /* =========================================================================================================================== */
2049 /* ================                                           P0_NS                                           ================ */
2050 /* =========================================================================================================================== */
2051 
2052 
2053 /**
2054   * @brief GPIO Port 0 (P0_NS)
2055   */
2056 
2057 typedef struct {                                /*!< (@ 0x40842500) P0_NS Structure                                            */
2058   __IM  uint32_t  RESERVED;
2059   __IOM uint32_t  OUT;                          /*!< (@ 0x00000004) Write GPIO port                                            */
2060   __IOM uint32_t  OUTSET;                       /*!< (@ 0x00000008) Set individual bits in GPIO port                           */
2061   __IOM uint32_t  OUTCLR;                       /*!< (@ 0x0000000C) Clear individual bits in GPIO port                         */
2062   __IM  uint32_t  IN;                           /*!< (@ 0x00000010) Read GPIO port                                             */
2063   __IOM uint32_t  DIR;                          /*!< (@ 0x00000014) Direction of GPIO pins                                     */
2064   __IOM uint32_t  DIRSET;                       /*!< (@ 0x00000018) DIR set register                                           */
2065   __IOM uint32_t  DIRCLR;                       /*!< (@ 0x0000001C) DIR clear register                                         */
2066   __IOM uint32_t  LATCH;                        /*!< (@ 0x00000020) Latch register indicating what GPIO pins that
2067                                                                     have met the criteria set in the PIN_CNF[n].SENSE
2068                                                                     registers                                                  */
2069   __IOM uint32_t  DETECTMODE;                   /*!< (@ 0x00000024) Select between default DETECT signal behavior
2070                                                                     and LDETECT mode (For non-secure pin only)                 */
2071   __IOM uint32_t  DETECTMODE_SEC;               /*!< (@ 0x00000028) Select between default DETECT signal behavior
2072                                                                     and LDETECT mode (For secure pin only)                     */
2073   __IM  uint32_t  RESERVED1[117];
2074   __IOM uint32_t  PIN_CNF[32];                  /*!< (@ 0x00000200) Description collection: Configuration of GPIO
2075                                                                     pins                                                       */
2076 } NRF_GPIO_Type;                                /*!< Size = 640 (0x280)                                                        */
2077 
2078 
2079 /** @} */ /* End of group Device_Peripheral_peripherals */
2080 
2081 
2082 /* =========================================================================================================================== */
2083 /* ================                          Device Specific Peripheral Address Map                           ================ */
2084 /* =========================================================================================================================== */
2085 
2086 
2087 /** @addtogroup Device_Peripheral_peripheralAddr
2088   * @{
2089   */
2090 
2091 #define NRF_FICR_S_BASE             0x00FF0000UL
2092 #define NRF_UICR_S_BASE             0x00FF8000UL
2093 #define NRF_TAD_S_BASE              0xE0080000UL
2094 #define NRF_SPU_S_BASE              0x50003000UL
2095 #define NRF_REGULATORS_NS_BASE      0x40004000UL
2096 #define NRF_REGULATORS_S_BASE       0x50004000UL
2097 #define NRF_CLOCK_NS_BASE           0x40005000UL
2098 #define NRF_POWER_NS_BASE           0x40005000UL
2099 #define NRF_CLOCK_S_BASE            0x50005000UL
2100 #define NRF_POWER_S_BASE            0x50005000UL
2101 #define NRF_CTRL_AP_PERI_S_BASE     0x50006000UL
2102 #define NRF_SPIM0_NS_BASE           0x40008000UL
2103 #define NRF_SPIS0_NS_BASE           0x40008000UL
2104 #define NRF_TWIM0_NS_BASE           0x40008000UL
2105 #define NRF_TWIS0_NS_BASE           0x40008000UL
2106 #define NRF_UARTE0_NS_BASE          0x40008000UL
2107 #define NRF_SPIM0_S_BASE            0x50008000UL
2108 #define NRF_SPIS0_S_BASE            0x50008000UL
2109 #define NRF_TWIM0_S_BASE            0x50008000UL
2110 #define NRF_TWIS0_S_BASE            0x50008000UL
2111 #define NRF_UARTE0_S_BASE           0x50008000UL
2112 #define NRF_SPIM1_NS_BASE           0x40009000UL
2113 #define NRF_SPIS1_NS_BASE           0x40009000UL
2114 #define NRF_TWIM1_NS_BASE           0x40009000UL
2115 #define NRF_TWIS1_NS_BASE           0x40009000UL
2116 #define NRF_UARTE1_NS_BASE          0x40009000UL
2117 #define NRF_SPIM1_S_BASE            0x50009000UL
2118 #define NRF_SPIS1_S_BASE            0x50009000UL
2119 #define NRF_TWIM1_S_BASE            0x50009000UL
2120 #define NRF_TWIS1_S_BASE            0x50009000UL
2121 #define NRF_UARTE1_S_BASE           0x50009000UL
2122 #define NRF_SPIM2_NS_BASE           0x4000A000UL
2123 #define NRF_SPIS2_NS_BASE           0x4000A000UL
2124 #define NRF_TWIM2_NS_BASE           0x4000A000UL
2125 #define NRF_TWIS2_NS_BASE           0x4000A000UL
2126 #define NRF_UARTE2_NS_BASE          0x4000A000UL
2127 #define NRF_SPIM2_S_BASE            0x5000A000UL
2128 #define NRF_SPIS2_S_BASE            0x5000A000UL
2129 #define NRF_TWIM2_S_BASE            0x5000A000UL
2130 #define NRF_TWIS2_S_BASE            0x5000A000UL
2131 #define NRF_UARTE2_S_BASE           0x5000A000UL
2132 #define NRF_SPIM3_NS_BASE           0x4000B000UL
2133 #define NRF_SPIS3_NS_BASE           0x4000B000UL
2134 #define NRF_TWIM3_NS_BASE           0x4000B000UL
2135 #define NRF_TWIS3_NS_BASE           0x4000B000UL
2136 #define NRF_UARTE3_NS_BASE          0x4000B000UL
2137 #define NRF_SPIM3_S_BASE            0x5000B000UL
2138 #define NRF_SPIS3_S_BASE            0x5000B000UL
2139 #define NRF_TWIM3_S_BASE            0x5000B000UL
2140 #define NRF_TWIS3_S_BASE            0x5000B000UL
2141 #define NRF_UARTE3_S_BASE           0x5000B000UL
2142 #define NRF_GPIOTE0_S_BASE          0x5000D000UL
2143 #define NRF_SAADC_NS_BASE           0x4000E000UL
2144 #define NRF_SAADC_S_BASE            0x5000E000UL
2145 #define NRF_TIMER0_NS_BASE          0x4000F000UL
2146 #define NRF_TIMER0_S_BASE           0x5000F000UL
2147 #define NRF_TIMER1_NS_BASE          0x40010000UL
2148 #define NRF_TIMER1_S_BASE           0x50010000UL
2149 #define NRF_TIMER2_NS_BASE          0x40011000UL
2150 #define NRF_TIMER2_S_BASE           0x50011000UL
2151 #define NRF_RTC0_NS_BASE            0x40014000UL
2152 #define NRF_RTC0_S_BASE             0x50014000UL
2153 #define NRF_RTC1_NS_BASE            0x40015000UL
2154 #define NRF_RTC1_S_BASE             0x50015000UL
2155 #define NRF_DPPIC_NS_BASE           0x40017000UL
2156 #define NRF_DPPIC_S_BASE            0x50017000UL
2157 #define NRF_WDT_NS_BASE             0x40018000UL
2158 #define NRF_WDT_S_BASE              0x50018000UL
2159 #define NRF_EGU0_NS_BASE            0x4001B000UL
2160 #define NRF_EGU0_S_BASE             0x5001B000UL
2161 #define NRF_EGU1_NS_BASE            0x4001C000UL
2162 #define NRF_EGU1_S_BASE             0x5001C000UL
2163 #define NRF_EGU2_NS_BASE            0x4001D000UL
2164 #define NRF_EGU2_S_BASE             0x5001D000UL
2165 #define NRF_EGU3_NS_BASE            0x4001E000UL
2166 #define NRF_EGU3_S_BASE             0x5001E000UL
2167 #define NRF_EGU4_NS_BASE            0x4001F000UL
2168 #define NRF_EGU4_S_BASE             0x5001F000UL
2169 #define NRF_EGU5_NS_BASE            0x40020000UL
2170 #define NRF_EGU5_S_BASE             0x50020000UL
2171 #define NRF_PWM0_NS_BASE            0x40021000UL
2172 #define NRF_PWM0_S_BASE             0x50021000UL
2173 #define NRF_PWM1_NS_BASE            0x40022000UL
2174 #define NRF_PWM1_S_BASE             0x50022000UL
2175 #define NRF_PWM2_NS_BASE            0x40023000UL
2176 #define NRF_PWM2_S_BASE             0x50023000UL
2177 #define NRF_PWM3_NS_BASE            0x40024000UL
2178 #define NRF_PWM3_S_BASE             0x50024000UL
2179 #define NRF_PDM_NS_BASE             0x40026000UL
2180 #define NRF_PDM_S_BASE              0x50026000UL
2181 #define NRF_I2S_NS_BASE             0x40028000UL
2182 #define NRF_I2S_S_BASE              0x50028000UL
2183 #define NRF_IPC_NS_BASE             0x4002A000UL
2184 #define NRF_IPC_S_BASE              0x5002A000UL
2185 #define NRF_FPU_NS_BASE             0x4002C000UL
2186 #define NRF_FPU_S_BASE              0x5002C000UL
2187 #define NRF_GPIOTE1_NS_BASE         0x40031000UL
2188 #define NRF_APPROTECT_NS_BASE       0x40039000UL
2189 #define NRF_KMU_NS_BASE             0x40039000UL
2190 #define NRF_NVMC_NS_BASE            0x40039000UL
2191 #define NRF_APPROTECT_S_BASE        0x50039000UL
2192 #define NRF_KMU_S_BASE              0x50039000UL
2193 #define NRF_NVMC_S_BASE             0x50039000UL
2194 #define NRF_VMC_NS_BASE             0x4003A000UL
2195 #define NRF_VMC_S_BASE              0x5003A000UL
2196 #define NRF_CC_HOST_RGF_S_BASE      0x50840000UL
2197 #define NRF_CRYPTOCELL_S_BASE       0x50840000UL
2198 #define NRF_P0_NS_BASE              0x40842500UL
2199 #define NRF_P0_S_BASE               0x50842500UL
2200 
2201 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
2202 
2203 
2204 /* =========================================================================================================================== */
2205 /* ================                                  Peripheral declaration                                   ================ */
2206 /* =========================================================================================================================== */
2207 
2208 
2209 /** @addtogroup Device_Peripheral_declaration
2210   * @{
2211   */
2212 
2213 #define NRF_FICR_S                  ((NRF_FICR_Type*)          NRF_FICR_S_BASE)
2214 #define NRF_UICR_S                  ((NRF_UICR_Type*)          NRF_UICR_S_BASE)
2215 #define NRF_TAD_S                   ((NRF_TAD_Type*)           NRF_TAD_S_BASE)
2216 #define NRF_SPU_S                   ((NRF_SPU_Type*)           NRF_SPU_S_BASE)
2217 #define NRF_REGULATORS_NS           ((NRF_REGULATORS_Type*)    NRF_REGULATORS_NS_BASE)
2218 #define NRF_REGULATORS_S            ((NRF_REGULATORS_Type*)    NRF_REGULATORS_S_BASE)
2219 #define NRF_CLOCK_NS                ((NRF_CLOCK_Type*)         NRF_CLOCK_NS_BASE)
2220 #define NRF_POWER_NS                ((NRF_POWER_Type*)         NRF_POWER_NS_BASE)
2221 #define NRF_CLOCK_S                 ((NRF_CLOCK_Type*)         NRF_CLOCK_S_BASE)
2222 #define NRF_POWER_S                 ((NRF_POWER_Type*)         NRF_POWER_S_BASE)
2223 #define NRF_CTRL_AP_PERI_S          ((NRF_CTRLAPPERI_Type*)    NRF_CTRL_AP_PERI_S_BASE)
2224 #define NRF_SPIM0_NS                ((NRF_SPIM_Type*)          NRF_SPIM0_NS_BASE)
2225 #define NRF_SPIS0_NS                ((NRF_SPIS_Type*)          NRF_SPIS0_NS_BASE)
2226 #define NRF_TWIM0_NS                ((NRF_TWIM_Type*)          NRF_TWIM0_NS_BASE)
2227 #define NRF_TWIS0_NS                ((NRF_TWIS_Type*)          NRF_TWIS0_NS_BASE)
2228 #define NRF_UARTE0_NS               ((NRF_UARTE_Type*)         NRF_UARTE0_NS_BASE)
2229 #define NRF_SPIM0_S                 ((NRF_SPIM_Type*)          NRF_SPIM0_S_BASE)
2230 #define NRF_SPIS0_S                 ((NRF_SPIS_Type*)          NRF_SPIS0_S_BASE)
2231 #define NRF_TWIM0_S                 ((NRF_TWIM_Type*)          NRF_TWIM0_S_BASE)
2232 #define NRF_TWIS0_S                 ((NRF_TWIS_Type*)          NRF_TWIS0_S_BASE)
2233 #define NRF_UARTE0_S                ((NRF_UARTE_Type*)         NRF_UARTE0_S_BASE)
2234 #define NRF_SPIM1_NS                ((NRF_SPIM_Type*)          NRF_SPIM1_NS_BASE)
2235 #define NRF_SPIS1_NS                ((NRF_SPIS_Type*)          NRF_SPIS1_NS_BASE)
2236 #define NRF_TWIM1_NS                ((NRF_TWIM_Type*)          NRF_TWIM1_NS_BASE)
2237 #define NRF_TWIS1_NS                ((NRF_TWIS_Type*)          NRF_TWIS1_NS_BASE)
2238 #define NRF_UARTE1_NS               ((NRF_UARTE_Type*)         NRF_UARTE1_NS_BASE)
2239 #define NRF_SPIM1_S                 ((NRF_SPIM_Type*)          NRF_SPIM1_S_BASE)
2240 #define NRF_SPIS1_S                 ((NRF_SPIS_Type*)          NRF_SPIS1_S_BASE)
2241 #define NRF_TWIM1_S                 ((NRF_TWIM_Type*)          NRF_TWIM1_S_BASE)
2242 #define NRF_TWIS1_S                 ((NRF_TWIS_Type*)          NRF_TWIS1_S_BASE)
2243 #define NRF_UARTE1_S                ((NRF_UARTE_Type*)         NRF_UARTE1_S_BASE)
2244 #define NRF_SPIM2_NS                ((NRF_SPIM_Type*)          NRF_SPIM2_NS_BASE)
2245 #define NRF_SPIS2_NS                ((NRF_SPIS_Type*)          NRF_SPIS2_NS_BASE)
2246 #define NRF_TWIM2_NS                ((NRF_TWIM_Type*)          NRF_TWIM2_NS_BASE)
2247 #define NRF_TWIS2_NS                ((NRF_TWIS_Type*)          NRF_TWIS2_NS_BASE)
2248 #define NRF_UARTE2_NS               ((NRF_UARTE_Type*)         NRF_UARTE2_NS_BASE)
2249 #define NRF_SPIM2_S                 ((NRF_SPIM_Type*)          NRF_SPIM2_S_BASE)
2250 #define NRF_SPIS2_S                 ((NRF_SPIS_Type*)          NRF_SPIS2_S_BASE)
2251 #define NRF_TWIM2_S                 ((NRF_TWIM_Type*)          NRF_TWIM2_S_BASE)
2252 #define NRF_TWIS2_S                 ((NRF_TWIS_Type*)          NRF_TWIS2_S_BASE)
2253 #define NRF_UARTE2_S                ((NRF_UARTE_Type*)         NRF_UARTE2_S_BASE)
2254 #define NRF_SPIM3_NS                ((NRF_SPIM_Type*)          NRF_SPIM3_NS_BASE)
2255 #define NRF_SPIS3_NS                ((NRF_SPIS_Type*)          NRF_SPIS3_NS_BASE)
2256 #define NRF_TWIM3_NS                ((NRF_TWIM_Type*)          NRF_TWIM3_NS_BASE)
2257 #define NRF_TWIS3_NS                ((NRF_TWIS_Type*)          NRF_TWIS3_NS_BASE)
2258 #define NRF_UARTE3_NS               ((NRF_UARTE_Type*)         NRF_UARTE3_NS_BASE)
2259 #define NRF_SPIM3_S                 ((NRF_SPIM_Type*)          NRF_SPIM3_S_BASE)
2260 #define NRF_SPIS3_S                 ((NRF_SPIS_Type*)          NRF_SPIS3_S_BASE)
2261 #define NRF_TWIM3_S                 ((NRF_TWIM_Type*)          NRF_TWIM3_S_BASE)
2262 #define NRF_TWIS3_S                 ((NRF_TWIS_Type*)          NRF_TWIS3_S_BASE)
2263 #define NRF_UARTE3_S                ((NRF_UARTE_Type*)         NRF_UARTE3_S_BASE)
2264 #define NRF_GPIOTE0_S               ((NRF_GPIOTE_Type*)        NRF_GPIOTE0_S_BASE)
2265 #define NRF_SAADC_NS                ((NRF_SAADC_Type*)         NRF_SAADC_NS_BASE)
2266 #define NRF_SAADC_S                 ((NRF_SAADC_Type*)         NRF_SAADC_S_BASE)
2267 #define NRF_TIMER0_NS               ((NRF_TIMER_Type*)         NRF_TIMER0_NS_BASE)
2268 #define NRF_TIMER0_S                ((NRF_TIMER_Type*)         NRF_TIMER0_S_BASE)
2269 #define NRF_TIMER1_NS               ((NRF_TIMER_Type*)         NRF_TIMER1_NS_BASE)
2270 #define NRF_TIMER1_S                ((NRF_TIMER_Type*)         NRF_TIMER1_S_BASE)
2271 #define NRF_TIMER2_NS               ((NRF_TIMER_Type*)         NRF_TIMER2_NS_BASE)
2272 #define NRF_TIMER2_S                ((NRF_TIMER_Type*)         NRF_TIMER2_S_BASE)
2273 #define NRF_RTC0_NS                 ((NRF_RTC_Type*)           NRF_RTC0_NS_BASE)
2274 #define NRF_RTC0_S                  ((NRF_RTC_Type*)           NRF_RTC0_S_BASE)
2275 #define NRF_RTC1_NS                 ((NRF_RTC_Type*)           NRF_RTC1_NS_BASE)
2276 #define NRF_RTC1_S                  ((NRF_RTC_Type*)           NRF_RTC1_S_BASE)
2277 #define NRF_DPPIC_NS                ((NRF_DPPIC_Type*)         NRF_DPPIC_NS_BASE)
2278 #define NRF_DPPIC_S                 ((NRF_DPPIC_Type*)         NRF_DPPIC_S_BASE)
2279 #define NRF_WDT_NS                  ((NRF_WDT_Type*)           NRF_WDT_NS_BASE)
2280 #define NRF_WDT_S                   ((NRF_WDT_Type*)           NRF_WDT_S_BASE)
2281 #define NRF_EGU0_NS                 ((NRF_EGU_Type*)           NRF_EGU0_NS_BASE)
2282 #define NRF_EGU0_S                  ((NRF_EGU_Type*)           NRF_EGU0_S_BASE)
2283 #define NRF_EGU1_NS                 ((NRF_EGU_Type*)           NRF_EGU1_NS_BASE)
2284 #define NRF_EGU1_S                  ((NRF_EGU_Type*)           NRF_EGU1_S_BASE)
2285 #define NRF_EGU2_NS                 ((NRF_EGU_Type*)           NRF_EGU2_NS_BASE)
2286 #define NRF_EGU2_S                  ((NRF_EGU_Type*)           NRF_EGU2_S_BASE)
2287 #define NRF_EGU3_NS                 ((NRF_EGU_Type*)           NRF_EGU3_NS_BASE)
2288 #define NRF_EGU3_S                  ((NRF_EGU_Type*)           NRF_EGU3_S_BASE)
2289 #define NRF_EGU4_NS                 ((NRF_EGU_Type*)           NRF_EGU4_NS_BASE)
2290 #define NRF_EGU4_S                  ((NRF_EGU_Type*)           NRF_EGU4_S_BASE)
2291 #define NRF_EGU5_NS                 ((NRF_EGU_Type*)           NRF_EGU5_NS_BASE)
2292 #define NRF_EGU5_S                  ((NRF_EGU_Type*)           NRF_EGU5_S_BASE)
2293 #define NRF_PWM0_NS                 ((NRF_PWM_Type*)           NRF_PWM0_NS_BASE)
2294 #define NRF_PWM0_S                  ((NRF_PWM_Type*)           NRF_PWM0_S_BASE)
2295 #define NRF_PWM1_NS                 ((NRF_PWM_Type*)           NRF_PWM1_NS_BASE)
2296 #define NRF_PWM1_S                  ((NRF_PWM_Type*)           NRF_PWM1_S_BASE)
2297 #define NRF_PWM2_NS                 ((NRF_PWM_Type*)           NRF_PWM2_NS_BASE)
2298 #define NRF_PWM2_S                  ((NRF_PWM_Type*)           NRF_PWM2_S_BASE)
2299 #define NRF_PWM3_NS                 ((NRF_PWM_Type*)           NRF_PWM3_NS_BASE)
2300 #define NRF_PWM3_S                  ((NRF_PWM_Type*)           NRF_PWM3_S_BASE)
2301 #define NRF_PDM_NS                  ((NRF_PDM_Type*)           NRF_PDM_NS_BASE)
2302 #define NRF_PDM_S                   ((NRF_PDM_Type*)           NRF_PDM_S_BASE)
2303 #define NRF_I2S_NS                  ((NRF_I2S_Type*)           NRF_I2S_NS_BASE)
2304 #define NRF_I2S_S                   ((NRF_I2S_Type*)           NRF_I2S_S_BASE)
2305 #define NRF_IPC_NS                  ((NRF_IPC_Type*)           NRF_IPC_NS_BASE)
2306 #define NRF_IPC_S                   ((NRF_IPC_Type*)           NRF_IPC_S_BASE)
2307 #define NRF_FPU_NS                  ((NRF_FPU_Type*)           NRF_FPU_NS_BASE)
2308 #define NRF_FPU_S                   ((NRF_FPU_Type*)           NRF_FPU_S_BASE)
2309 #define NRF_GPIOTE1_NS              ((NRF_GPIOTE_Type*)        NRF_GPIOTE1_NS_BASE)
2310 #define NRF_APPROTECT_NS            ((NRF_APPROTECT_Type*)     NRF_APPROTECT_NS_BASE)
2311 #define NRF_KMU_NS                  ((NRF_KMU_Type*)           NRF_KMU_NS_BASE)
2312 #define NRF_NVMC_NS                 ((NRF_NVMC_Type*)          NRF_NVMC_NS_BASE)
2313 #define NRF_APPROTECT_S             ((NRF_APPROTECT_Type*)     NRF_APPROTECT_S_BASE)
2314 #define NRF_KMU_S                   ((NRF_KMU_Type*)           NRF_KMU_S_BASE)
2315 #define NRF_NVMC_S                  ((NRF_NVMC_Type*)          NRF_NVMC_S_BASE)
2316 #define NRF_VMC_NS                  ((NRF_VMC_Type*)           NRF_VMC_NS_BASE)
2317 #define NRF_VMC_S                   ((NRF_VMC_Type*)           NRF_VMC_S_BASE)
2318 #define NRF_CC_HOST_RGF_S           ((NRF_CC_HOST_RGF_Type*)   NRF_CC_HOST_RGF_S_BASE)
2319 #define NRF_CRYPTOCELL_S            ((NRF_CRYPTOCELL_Type*)    NRF_CRYPTOCELL_S_BASE)
2320 #define NRF_P0_NS                   ((NRF_GPIO_Type*)          NRF_P0_NS_BASE)
2321 #define NRF_P0_S                    ((NRF_GPIO_Type*)          NRF_P0_S_BASE)
2322 
2323 /** @} */ /* End of group Device_Peripheral_declaration */
2324 
2325 
2326 #ifdef __cplusplus
2327 }
2328 #endif
2329 
2330 #endif /* NRF9120_H */
2331 
2332 
2333 /** @} */ /* End of group nrf9120 */
2334 
2335 /** @} */ /* End of group Nordic Semiconductor */
2336