1 /* 2 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. 3 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, this 10 list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its 17 contributors may be used to endorse or promote products derived from this 18 software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 * 32 * @file nrf5340_application.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 04. April 2023 36 * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:39 37 * from File 'nrf5340_application.svd', 38 * last modified on Tuesday, 04.04.2023 09:57:14 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf5340_application 49 * @{ 50 */ 51 52 53 #ifndef NRF5340_APPLICATION_H 54 #define NRF5340_APPLICATION_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 82 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 83 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 84 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 85 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 86 /* ==================================== nrf5340_application Specific Interrupt Numbers ===================================== */ 87 FPU_IRQn = 0, /*!< 0 FPU */ 88 CACHE_IRQn = 1, /*!< 1 CACHE */ 89 SPU_IRQn = 3, /*!< 3 SPU */ 90 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 91 SERIAL0_IRQn = 8, /*!< 8 SERIAL0 */ 92 SERIAL1_IRQn = 9, /*!< 9 SERIAL1 */ 93 SPIM4_IRQn = 10, /*!< 10 SPIM4 */ 94 SERIAL2_IRQn = 11, /*!< 11 SERIAL2 */ 95 SERIAL3_IRQn = 12, /*!< 12 SERIAL3 */ 96 GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ 97 SAADC_IRQn = 14, /*!< 14 SAADC */ 98 TIMER0_IRQn = 15, /*!< 15 TIMER0 */ 99 TIMER1_IRQn = 16, /*!< 16 TIMER1 */ 100 TIMER2_IRQn = 17, /*!< 17 TIMER2 */ 101 RTC0_IRQn = 20, /*!< 20 RTC0 */ 102 RTC1_IRQn = 21, /*!< 21 RTC1 */ 103 WDT0_IRQn = 24, /*!< 24 WDT0 */ 104 WDT1_IRQn = 25, /*!< 25 WDT1 */ 105 COMP_LPCOMP_IRQn = 26, /*!< 26 COMP_LPCOMP */ 106 EGU0_IRQn = 27, /*!< 27 EGU0 */ 107 EGU1_IRQn = 28, /*!< 28 EGU1 */ 108 EGU2_IRQn = 29, /*!< 29 EGU2 */ 109 EGU3_IRQn = 30, /*!< 30 EGU3 */ 110 EGU4_IRQn = 31, /*!< 31 EGU4 */ 111 EGU5_IRQn = 32, /*!< 32 EGU5 */ 112 PWM0_IRQn = 33, /*!< 33 PWM0 */ 113 PWM1_IRQn = 34, /*!< 34 PWM1 */ 114 PWM2_IRQn = 35, /*!< 35 PWM2 */ 115 PWM3_IRQn = 36, /*!< 36 PWM3 */ 116 PDM0_IRQn = 38, /*!< 38 PDM0 */ 117 I2S0_IRQn = 40, /*!< 40 I2S0 */ 118 IPC_IRQn = 42, /*!< 42 IPC */ 119 QSPI_IRQn = 43, /*!< 43 QSPI */ 120 NFCT_IRQn = 45, /*!< 45 NFCT */ 121 GPIOTE1_IRQn = 47, /*!< 47 GPIOTE1 */ 122 QDEC0_IRQn = 51, /*!< 51 QDEC0 */ 123 QDEC1_IRQn = 52, /*!< 52 QDEC1 */ 124 USBD_IRQn = 54, /*!< 54 USBD */ 125 USBREGULATOR_IRQn = 55, /*!< 55 USBREGULATOR */ 126 KMU_IRQn = 57, /*!< 57 KMU */ 127 CRYPTOCELL_IRQn = 68 /*!< 68 CRYPTOCELL */ 128 } IRQn_Type; 129 130 131 132 /* =========================================================================================================================== */ 133 /* ================ Processor and Core Peripheral Section ================ */ 134 /* =========================================================================================================================== */ 135 136 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 137 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 138 #define __INTERRUPTS_MAX 240 /*!< Top interrupt number */ 139 #define __DSP_PRESENT 1 /*!< DSP present or not */ 140 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 141 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 142 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 143 #define __MPU_PRESENT 1 /*!< MPU present */ 144 #define __FPU_PRESENT 1 /*!< FPU present */ 145 #define __FPU_DP 0 /*!< Double Precision FPU */ 146 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 147 148 149 /** @} */ /* End of group Configuration_of_CMSIS */ 150 151 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 152 #include "system_nrf5340_application.h" /*!< nrf5340_application System */ 153 154 #ifndef __IM /*!< Fallback for older CMSIS versions */ 155 #define __IM __I 156 #endif 157 #ifndef __OM /*!< Fallback for older CMSIS versions */ 158 #define __OM __O 159 #endif 160 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 161 #define __IOM __IO 162 #endif 163 164 165 /* =========================================================================================================================== */ 166 /* ================ Device Specific Cluster Section ================ */ 167 /* =========================================================================================================================== */ 168 169 170 /** @addtogroup Device_Peripheral_clusters 171 * @{ 172 */ 173 174 175 /** 176 * @brief CACHEDATA_SET_WAY [WAY] (Unspecified) 177 */ 178 typedef struct { 179 __IOM uint32_t DATA0; /*!< (@ 0x00000000) Description cluster: Cache data bits [31:0] of 180 SET[n], WAY[o]. */ 181 __IOM uint32_t DATA1; /*!< (@ 0x00000004) Description cluster: Cache data bits [63:32] 182 of SET[n], WAY[o]. */ 183 __IOM uint32_t DATA2; /*!< (@ 0x00000008) Description cluster: Cache data bits [95:64] 184 of SET[n], WAY[o]. */ 185 __IOM uint32_t DATA3; /*!< (@ 0x0000000C) Description cluster: Cache data bits [127:96] 186 of SET[n], WAY[o]. */ 187 } CACHEDATA_SET_WAY_Type; /*!< Size = 16 (0x10) */ 188 189 190 /** 191 * @brief CACHEDATA_SET [SET] (Unspecified) 192 */ 193 typedef struct { 194 __IOM CACHEDATA_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) Unspecified */ 195 } CACHEDATA_SET_Type; /*!< Size = 32 (0x20) */ 196 197 198 /** 199 * @brief CACHEINFO_SET [SET] (Unspecified) 200 */ 201 typedef struct { 202 __IOM uint32_t WAY[2]; /*!< (@ 0x00000000) Description collection: Cache information for 203 SET[n], WAY[o]. */ 204 } CACHEINFO_SET_Type; /*!< Size = 8 (0x8) */ 205 206 207 /** 208 * @brief FICR_INFO [INFO] (Device info) 209 */ 210 typedef struct { 211 __IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier */ 212 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 213 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 214 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 215 configuration */ 216 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 217 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 218 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 219 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size in bytes */ 220 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 221 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 222 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 223 224 225 /** 226 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 227 */ 228 typedef struct { 229 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address of the PAR register 230 which will be written */ 231 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 232 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 233 234 235 /** 236 * @brief FICR_NFC [NFC] (Unspecified) 237 */ 238 typedef struct { 239 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read 240 these values to populate NFCID1_3RD_LAST, 241 NFCID1_2ND_LAST and NFCID1_LAST. */ 242 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read 243 these values to populate NFCID1_3RD_LAST, 244 NFCID1_2ND_LAST and NFCID1_LAST. */ 245 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read 246 these values to populate NFCID1_3RD_LAST, 247 NFCID1_2ND_LAST and NFCID1_LAST. */ 248 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read 249 these values to populate NFCID1_3RD_LAST, 250 NFCID1_2ND_LAST and NFCID1_LAST. */ 251 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 252 253 254 /** 255 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 256 */ 257 typedef struct { 258 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 259 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 260 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 261 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 262 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 263 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 264 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 265 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 266 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 267 268 269 /** 270 * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) 271 */ 272 typedef struct { 273 __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where 274 content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 275 ) will be pushed by KMU. Note that this 276 address must match that of a peripherals 277 APB mapped write-only key registers, else 278 the KMU can push this key value into an 279 address range which the CPU can potentially 280 read. */ 281 __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the 282 key slot. Bits 0-15 and 16-31 can only be 283 written when equal to 0xFFFF. */ 284 } UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ 285 286 287 /** 288 * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) 289 */ 290 typedef struct { 291 __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] 292 of value assigned to KMU key slot. */ 293 } UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ 294 295 296 /** 297 * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) 298 */ 299 typedef struct { 300 __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ 301 __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ 302 } UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ 303 304 305 /** 306 * @brief TAD_PSEL [PSEL] (Unspecified) 307 */ 308 typedef struct { 309 __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */ 310 __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */ 311 __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */ 312 __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */ 313 __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */ 314 } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ 315 316 317 /** 318 * @brief DCNF_EXTPERI [EXTPERI] (Unspecified) 319 */ 320 typedef struct { 321 __IOM uint32_t PROTECT; /*!< (@ 0x00000000) Description cluster: Control access for master 322 connected to AMLI master port EXTPERI[n] */ 323 } DCNF_EXTPERI_Type; /*!< Size = 4 (0x4) */ 324 325 326 /** 327 * @brief DCNF_EXTRAM [EXTRAM] (Unspecified) 328 */ 329 typedef struct { 330 __IOM uint32_t PROTECT; /*!< (@ 0x00000000) Description cluster: Control access from master 331 connected to AMLI master port EXTRAM[n] */ 332 } DCNF_EXTRAM_Type; /*!< Size = 4 (0x4) */ 333 334 335 /** 336 * @brief DCNF_EXTCODE [EXTCODE] (Unspecified) 337 */ 338 typedef struct { 339 __IOM uint32_t PROTECT; /*!< (@ 0x00000000) Description cluster: Control access from master 340 connected to AMLI master port EXTCODE[n] */ 341 } DCNF_EXTCODE_Type; /*!< Size = 4 (0x4) */ 342 343 344 /** 345 * @brief CACHE_PROFILING [PROFILING] (Unspecified) 346 */ 347 typedef struct { 348 __IM uint32_t IHIT; /*!< (@ 0x00000000) Description cluster: Instruction fetch cache 349 hit counter for cache region n, where n=0 350 means Flash and n=1 means XIP. */ 351 __IM uint32_t IMISS; /*!< (@ 0x00000004) Description cluster: Instruction fetch cache 352 miss counter for cache region n, where n=0 353 means Flash and n=1 means XIP. */ 354 __IM uint32_t DHIT; /*!< (@ 0x00000008) Description cluster: Data fetch cache hit counter 355 for cache region n, where n=0 means Flash 356 and n=1 means XIP. */ 357 __IM uint32_t DMISS; /*!< (@ 0x0000000C) Description cluster: Data fetch cache miss counter 358 for cache region n, where n=0 means Flash 359 and n=1 means XIP. */ 360 __IM uint32_t RESERVED[4]; 361 } CACHE_PROFILING_Type; /*!< Size = 32 (0x20) */ 362 363 364 /** 365 * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) 366 */ 367 typedef struct { 368 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated 369 from the external domain n List capabilities 370 of the external domain n */ 371 } SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ 372 373 374 /** 375 * @brief SPU_DPPI [DPPI] (Unspecified) 376 */ 377 typedef struct { 378 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 379 non-secure attribute for the DPPI channels */ 380 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 381 of the corresponding PERM register */ 382 } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ 383 384 385 /** 386 * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) 387 */ 388 typedef struct { 389 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 390 non-secure attribute for pins 0 to 31 of 391 port n */ 392 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 393 of the corresponding PERM register */ 394 } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ 395 396 397 /** 398 * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) 399 */ 400 typedef struct { 401 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region 402 can contain the non-secure callable (NSC) 403 region n */ 404 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 405 callable (NSC) region n */ 406 } SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ 407 408 409 /** 410 * @brief SPU_RAMNSC [RAMNSC] (Unspecified) 411 */ 412 typedef struct { 413 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region 414 can contain the non-secure callable (NSC) 415 region n */ 416 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 417 callable (NSC) region n */ 418 } SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ 419 420 421 /** 422 * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) 423 */ 424 typedef struct { 425 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash 426 region n */ 427 } SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ 428 429 430 /** 431 * @brief SPU_RAMREGION [RAMREGION] (Unspecified) 432 */ 433 typedef struct { 434 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM 435 region n */ 436 } SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ 437 438 439 /** 440 * @brief SPU_PERIPHID [PERIPHID] (Unspecified) 441 */ 442 typedef struct { 443 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access 444 permissions for the peripheral with ID n */ 445 } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ 446 447 448 /** 449 * @brief OSCILLATORS_XOSC32KI [XOSC32KI] (Unspecified) 450 */ 451 typedef struct { 452 __IOM uint32_t BYPASS; /*!< (@ 0x00000000) Enable or disable bypass of LFCLK crystal oscillator 453 with external clock source */ 454 __IM uint32_t RESERVED[3]; 455 __IOM uint32_t INTCAP; /*!< (@ 0x00000010) Control usage of internal load capacitors */ 456 } OSCILLATORS_XOSC32KI_Type; /*!< Size = 20 (0x14) */ 457 458 459 /** 460 * @brief REGULATORS_VREGMAIN [VREGMAIN] (Unspecified) 461 */ 462 typedef struct { 463 __IOM uint32_t DCDCEN; /*!< (@ 0x00000000) DC/DC enable register for VREGMAIN */ 464 } REGULATORS_VREGMAIN_Type; /*!< Size = 4 (0x4) */ 465 466 467 /** 468 * @brief REGULATORS_VREGRADIO [VREGRADIO] (Unspecified) 469 */ 470 typedef struct { 471 __IM uint32_t RESERVED; 472 __IOM uint32_t DCDCEN; /*!< (@ 0x00000004) DC/DC enable register for VREGRADIO */ 473 } REGULATORS_VREGRADIO_Type; /*!< Size = 8 (0x8) */ 474 475 476 /** 477 * @brief REGULATORS_VREGH [VREGH] (Unspecified) 478 */ 479 typedef struct { 480 __IOM uint32_t DCDCEN; /*!< (@ 0x00000000) DC/DC enable register for VREGH */ 481 } REGULATORS_VREGH_Type; /*!< Size = 4 (0x4) */ 482 483 484 /** 485 * @brief CLOCK_HFCLKAUDIO [HFCLKAUDIO] (Unspecified) 486 */ 487 typedef struct { 488 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000000) Audio PLL frequency in 11.176 MHz - 11.402 MHz 489 or 12.165 MHz - 12.411 MHz frequency bands */ 490 } CLOCK_HFCLKAUDIO_Type; /*!< Size = 4 (0x4) */ 491 492 493 /** 494 * @brief RESET_NETWORK [NETWORK] (ULP network core control) 495 */ 496 typedef struct { 497 __IM uint32_t RESERVED; 498 __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force network core off */ 499 } RESET_NETWORK_Type; /*!< Size = 8 (0x8) */ 500 501 502 /** 503 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 504 */ 505 typedef struct { 506 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ 507 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if 508 data sent from the debugger to the CPU has 509 been read. */ 510 __IM uint32_t RESERVED[30]; 511 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ 512 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if 513 the data sent from the CPU to the debugger 514 has been read. */ 515 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 516 517 518 /** 519 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 520 */ 521 typedef struct { 522 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE 523 register from being written until next reset. */ 524 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register 525 and performs an ERASEALL operation. */ 526 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 527 528 529 /** 530 * @brief CTRLAPPERI_APPROTECT [APPROTECT] (Unspecified) 531 */ 532 typedef struct { 533 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the APPROTECT.DISABLE register 534 from being written to until next reset. */ 535 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the APPROTECT register 536 and enables debug access to non-secure mode. */ 537 } CTRLAPPERI_APPROTECT_Type; /*!< Size = 8 (0x8) */ 538 539 540 /** 541 * @brief CTRLAPPERI_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified) 542 */ 543 typedef struct { 544 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the SECUREAPPROTECT.DISABLE 545 register from being written until next reset. */ 546 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the SECUREAPPROTECT register 547 and enables debug access to secure mode. */ 548 } CTRLAPPERI_SECUREAPPROTECT_Type; /*!< Size = 8 (0x8) */ 549 550 551 /** 552 * @brief SPIM_PSEL [PSEL] (Unspecified) 553 */ 554 typedef struct { 555 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 556 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 557 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 558 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 559 } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 560 561 562 /** 563 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 564 */ 565 typedef struct { 566 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 567 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 568 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 569 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 570 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 571 572 573 /** 574 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 575 */ 576 typedef struct { 577 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 578 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 579 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 580 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 581 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 582 583 584 /** 585 * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 586 */ 587 typedef struct { 588 __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 589 __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 590 of SCK. When SHORTS.END_START is used, this 591 is also the minimum duration CSN must stay 592 high between transactions. */ 593 } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 594 595 596 /** 597 * @brief SPIS_PSEL [PSEL] (Unspecified) 598 */ 599 typedef struct { 600 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 601 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 602 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 603 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 604 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 605 606 607 /** 608 * @brief SPIS_RXD [RXD] (Unspecified) 609 */ 610 typedef struct { 611 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 612 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 613 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 614 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 615 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 616 617 618 /** 619 * @brief SPIS_TXD [TXD] (Unspecified) 620 */ 621 typedef struct { 622 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 623 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 624 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 625 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 626 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 627 628 629 /** 630 * @brief TWIM_PSEL [PSEL] (Unspecified) 631 */ 632 typedef struct { 633 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 634 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 635 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 636 637 638 /** 639 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 640 */ 641 typedef struct { 642 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 643 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 644 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 645 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 646 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 647 648 649 /** 650 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 651 */ 652 typedef struct { 653 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 654 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 655 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 656 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 657 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 658 659 660 /** 661 * @brief TWIS_PSEL [PSEL] (Unspecified) 662 */ 663 typedef struct { 664 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 665 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 666 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 667 668 669 /** 670 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 671 */ 672 typedef struct { 673 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 674 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 675 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 676 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 677 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 678 679 680 /** 681 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 682 */ 683 typedef struct { 684 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 685 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 686 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 687 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 688 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 689 690 691 /** 692 * @brief UARTE_PSEL [PSEL] (Unspecified) 693 */ 694 typedef struct { 695 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 696 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 697 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 698 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 699 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 700 701 702 /** 703 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 704 */ 705 typedef struct { 706 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 707 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 708 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 709 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 710 711 712 /** 713 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 714 */ 715 typedef struct { 716 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 717 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 718 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 719 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 720 721 722 /** 723 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 724 */ 725 typedef struct { 726 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 727 above CH[n].LIMIT.HIGH */ 728 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 729 below CH[n].LIMIT.LOW */ 730 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 731 732 733 /** 734 * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) 735 */ 736 typedef struct { 737 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for 738 event CH[n].LIMITH */ 739 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for 740 event CH[n].LIMITL */ 741 } SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ 742 743 744 /** 745 * @brief SAADC_CH [CH] (Unspecified) 746 */ 747 typedef struct { 748 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 749 for CH[n] */ 750 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 751 for CH[n] */ 752 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 753 CH[n] */ 754 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 755 monitoring a channel */ 756 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 757 758 759 /** 760 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 761 */ 762 typedef struct { 763 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 764 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 765 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 766 START */ 767 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 768 769 770 /** 771 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 772 */ 773 typedef struct { 774 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 775 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 776 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 777 778 779 /** 780 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 781 */ 782 typedef struct { 783 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 784 for task CHG[n].EN */ 785 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 786 for task CHG[n].DIS */ 787 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 788 789 790 /** 791 * @brief PWM_SEQ [SEQ] (Unspecified) 792 */ 793 typedef struct { 794 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 795 of this sequence */ 796 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 797 in this sequence */ 798 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 799 periods between samples loaded into compare 800 register */ 801 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 802 __IM uint32_t RESERVED[4]; 803 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 804 805 806 /** 807 * @brief PWM_PSEL [PSEL] (Unspecified) 808 */ 809 typedef struct { 810 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 811 PWM channel n */ 812 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 813 814 815 /** 816 * @brief PDM_PSEL [PSEL] (Unspecified) 817 */ 818 typedef struct { 819 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 820 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 821 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 822 823 824 /** 825 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 826 */ 827 typedef struct { 828 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 829 EasyDMA */ 830 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 831 mode */ 832 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 833 834 835 /** 836 * @brief I2S_CONFIG [CONFIG] (Unspecified) 837 */ 838 typedef struct { 839 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode */ 840 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable */ 841 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable */ 842 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable */ 843 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) I2S clock generator control */ 844 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio */ 845 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width */ 846 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame */ 847 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format */ 848 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels */ 849 __IOM uint32_t CLKCONFIG; /*!< (@ 0x00000028) Clock source selection for the I2S module */ 850 } I2S_CONFIG_Type; /*!< Size = 44 (0x2c) */ 851 852 853 /** 854 * @brief I2S_RXD [RXD] (Unspecified) 855 */ 856 typedef struct { 857 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 858 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 859 860 861 /** 862 * @brief I2S_TXD [TXD] (Unspecified) 863 */ 864 typedef struct { 865 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address */ 866 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 867 868 869 /** 870 * @brief I2S_RXTXD [RXTXD] (Unspecified) 871 */ 872 typedef struct { 873 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers */ 874 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 875 876 877 /** 878 * @brief I2S_PSEL [PSEL] (Unspecified) 879 */ 880 typedef struct { 881 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal */ 882 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal */ 883 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal */ 884 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal */ 885 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal */ 886 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 887 888 889 /** 890 * @brief QSPI_READ [READ] (Unspecified) 891 */ 892 typedef struct { 893 __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ 894 __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ 895 __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ 896 } QSPI_READ_Type; /*!< Size = 12 (0xc) */ 897 898 899 /** 900 * @brief QSPI_WRITE [WRITE] (Unspecified) 901 */ 902 typedef struct { 903 __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ 904 __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ 905 __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ 906 } QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ 907 908 909 /** 910 * @brief QSPI_ERASE [ERASE] (Unspecified) 911 */ 912 typedef struct { 913 __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ 914 __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ 915 } QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ 916 917 918 /** 919 * @brief QSPI_PSEL [PSEL] (Unspecified) 920 */ 921 typedef struct { 922 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ 923 __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ 924 __IM uint32_t RESERVED; 925 __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ 926 __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ 927 __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data WP/IO2. */ 928 __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data HOLD/IO3. */ 929 } QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ 930 931 932 /** 933 * @brief QSPI_XIP_ENC [XIP_ENC] (Unspecified) 934 */ 935 typedef struct { 936 __OM uint32_t KEY0; /*!< (@ 0x00000000) Bits 31:0 of XIP AES KEY */ 937 __OM uint32_t KEY1; /*!< (@ 0x00000004) Bits 63:32 of XIP AES KEY */ 938 __OM uint32_t KEY2; /*!< (@ 0x00000008) Bits 95:64 of XIP AES KEY */ 939 __OM uint32_t KEY3; /*!< (@ 0x0000000C) Bits 127:96 of XIP AES KEY */ 940 __OM uint32_t NONCE0; /*!< (@ 0x00000010) Bits 31:0 of XIP NONCE */ 941 __OM uint32_t NONCE1; /*!< (@ 0x00000014) Bits 63:32 of XIP NONCE */ 942 __OM uint32_t NONCE2; /*!< (@ 0x00000018) Bits 95:64 of XIP NONCE */ 943 __IOM uint32_t ENABLE; /*!< (@ 0x0000001C) Enable stream cipher for XIP */ 944 } QSPI_XIP_ENC_Type; /*!< Size = 32 (0x20) */ 945 946 947 /** 948 * @brief QSPI_DMA_ENC [DMA_ENC] (Unspecified) 949 */ 950 typedef struct { 951 __OM uint32_t KEY0; /*!< (@ 0x00000000) Bits 31:0 of DMA AES KEY */ 952 __OM uint32_t KEY1; /*!< (@ 0x00000004) Bits 63:32 of DMA AES KEY */ 953 __OM uint32_t KEY2; /*!< (@ 0x00000008) Bits 95:64 of DMA AES KEY */ 954 __OM uint32_t KEY3; /*!< (@ 0x0000000C) Bits 127:96 of DMA AES KEY */ 955 __OM uint32_t NONCE0; /*!< (@ 0x00000010) Bits 31:0 of DMA NONCE */ 956 __OM uint32_t NONCE1; /*!< (@ 0x00000014) Bits 63:32 of DMA NONCE */ 957 __OM uint32_t NONCE2; /*!< (@ 0x00000018) Bits 95:64 of DMA NONCE */ 958 __IOM uint32_t ENABLE; /*!< (@ 0x0000001C) Enable stream cipher for EasyDMA */ 959 } QSPI_DMA_ENC_Type; /*!< Size = 32 (0x20) */ 960 961 962 /** 963 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 964 */ 965 typedef struct { 966 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ 967 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 968 969 970 /** 971 * @brief NFCT_TXD [TXD] (Unspecified) 972 */ 973 typedef struct { 974 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 975 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 976 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 977 978 979 /** 980 * @brief NFCT_RXD [RXD] (Unspecified) 981 */ 982 typedef struct { 983 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 984 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 985 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 986 987 988 /** 989 * @brief QDEC_PSEL [PSEL] (Unspecified) 990 */ 991 typedef struct { 992 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 993 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 994 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 995 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 996 997 998 /** 999 * @brief USBD_HALTED [HALTED] (Unspecified) 1000 */ 1001 typedef struct { 1002 __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. 1003 Can be used as is as response to a GetStatus() 1004 request to endpoint. */ 1005 __IM uint32_t RESERVED; 1006 __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. 1007 Can be used as is as response to a GetStatus() 1008 request to endpoint. */ 1009 } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ 1010 1011 1012 /** 1013 * @brief USBD_SIZE [SIZE] (Unspecified) 1014 */ 1015 typedef struct { 1016 __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received 1017 last in the data stage of this OUT endpoint */ 1018 __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT 1019 data endpoint */ 1020 } USBD_SIZE_Type; /*!< Size = 36 (0x24) */ 1021 1022 1023 /** 1024 * @brief USBD_EPIN [EPIN] (Unspecified) 1025 */ 1026 typedef struct { 1027 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 1028 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 1029 to transfer */ 1030 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 1031 in the last transaction */ 1032 __IM uint32_t RESERVED[2]; 1033 } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ 1034 1035 1036 /** 1037 * @brief USBD_ISOIN [ISOIN] (Unspecified) 1038 */ 1039 typedef struct { 1040 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 1041 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 1042 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 1043 } USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ 1044 1045 1046 /** 1047 * @brief USBD_EPOUT [EPOUT] (Unspecified) 1048 */ 1049 typedef struct { 1050 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 1051 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 1052 to transfer */ 1053 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 1054 in the last transaction */ 1055 __IM uint32_t RESERVED[2]; 1056 } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ 1057 1058 1059 /** 1060 * @brief USBD_ISOOUT [ISOOUT] (Unspecified) 1061 */ 1062 typedef struct { 1063 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 1064 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 1065 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 1066 } USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ 1067 1068 1069 /** 1070 * @brief VMC_RAM [RAM] (Unspecified) 1071 */ 1072 typedef struct { 1073 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAM[n] power control register */ 1074 __IOM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAM[n] power control set 1075 register */ 1076 __IOM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAM[n] power control clear 1077 register */ 1078 __IM uint32_t RESERVED; 1079 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 1080 1081 1082 /** @} */ /* End of group Device_Peripheral_clusters */ 1083 1084 1085 /* =========================================================================================================================== */ 1086 /* ================ Device Specific Peripheral Section ================ */ 1087 /* =========================================================================================================================== */ 1088 1089 1090 /** @addtogroup Device_Peripheral_peripherals 1091 * @{ 1092 */ 1093 1094 1095 1096 /* =========================================================================================================================== */ 1097 /* ================ CACHEDATA_S ================ */ 1098 /* =========================================================================================================================== */ 1099 1100 1101 /** 1102 * @brief CACHEDATA (CACHEDATA_S) 1103 */ 1104 1105 typedef struct { /*!< (@ 0x00F00000) CACHEDATA_S Structure */ 1106 __IOM CACHEDATA_SET_Type SET[256]; /*!< (@ 0x00000000) Unspecified */ 1107 } NRF_CACHEDATA_Type; /*!< Size = 8192 (0x2000) */ 1108 1109 1110 1111 /* =========================================================================================================================== */ 1112 /* ================ CACHEINFO_S ================ */ 1113 /* =========================================================================================================================== */ 1114 1115 1116 /** 1117 * @brief CACHEINFO (CACHEINFO_S) 1118 */ 1119 1120 typedef struct { /*!< (@ 0x00F08000) CACHEINFO_S Structure */ 1121 __IOM CACHEINFO_SET_Type SET[256]; /*!< (@ 0x00000000) Unspecified */ 1122 } NRF_CACHEINFO_Type; /*!< Size = 2048 (0x800) */ 1123 1124 1125 1126 /* =========================================================================================================================== */ 1127 /* ================ FICR_S ================ */ 1128 /* =========================================================================================================================== */ 1129 1130 1131 /** 1132 * @brief Factory Information Configuration Registers (FICR_S) 1133 */ 1134 1135 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 1136 __IM uint32_t RESERVED[128]; 1137 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 1138 __IM uint32_t RESERVED1[53]; 1139 __IOM FICR_TRIMCNF_Type TRIMCNF[32]; /*!< (@ 0x00000300) Unspecified */ 1140 __IM uint32_t RESERVED2[20]; 1141 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 1142 __IM uint32_t RESERVED3[488]; 1143 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 1144 __IM uint32_t XOSC32MTRIM; /*!< (@ 0x00000C20) XOSC32M capacitor selection trim values */ 1145 } NRF_FICR_Type; /*!< Size = 3108 (0xc24) */ 1146 1147 1148 1149 /* =========================================================================================================================== */ 1150 /* ================ UICR_S ================ */ 1151 /* =========================================================================================================================== */ 1152 1153 1154 /** 1155 * @brief User Information Configuration Registers User information configuration registers (UICR_S) 1156 */ 1157 1158 typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ 1159 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 1160 __IM uint32_t RESERVED[3]; 1161 __IOM uint32_t VREGHVOUT; /*!< (@ 0x00000010) Output voltage from the high voltage (VREGH) 1162 regulator stage. The maximum output voltage 1163 from this stage is given as VDDH - VREGHDROP. */ 1164 __IOM uint32_t HFXOCNT; /*!< (@ 0x00000014) HFXO startup counter */ 1165 __IM uint32_t RESERVED1; 1166 __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000001C) Secure access port protection */ 1167 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000020) Erase protection */ 1168 __IOM uint32_t TINSTANCE; /*!< (@ 0x00000024) SW-DP Target instance */ 1169 __IOM uint32_t NFCPINS; /*!< (@ 0x00000028) Setting of pins dedicated to NFC functionality: 1170 NFC antenna or GPIO */ 1171 __IM uint32_t RESERVED2[53]; 1172 __IOM uint32_t OTP[192]; /*!< (@ 0x00000100) Description collection: One time programmable 1173 memory */ 1174 __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ 1175 } NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ 1176 1177 1178 1179 /* =========================================================================================================================== */ 1180 /* ================ CTI_S ================ */ 1181 /* =========================================================================================================================== */ 1182 1183 1184 /** 1185 * @brief Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. (CTI_S) 1186 */ 1187 1188 typedef struct { /*!< (@ 0xE0042000) CTI_S Structure */ 1189 __IOM uint32_t CTICONTROL; /*!< (@ 0x00000000) CTI Control register */ 1190 __IM uint32_t RESERVED[3]; 1191 __OM uint32_t CTIINTACK; /*!< (@ 0x00000010) CTI Interrupt Acknowledge register */ 1192 __IOM uint32_t CTIAPPSET; /*!< (@ 0x00000014) CTI Application Trigger Set register */ 1193 __OM uint32_t CTIAPPCLEAR; /*!< (@ 0x00000018) CTI Application Trigger Clear register */ 1194 __OM uint32_t CTIAPPPULSE; /*!< (@ 0x0000001C) CTI Application Pulse register */ 1195 __IOM uint32_t CTIINEN[8]; /*!< (@ 0x00000020) Description collection: CTI Trigger input */ 1196 __IM uint32_t RESERVED1[24]; 1197 __IOM uint32_t CTIOUTEN[8]; /*!< (@ 0x000000A0) Description collection: CTI Trigger output */ 1198 __IM uint32_t RESERVED2[28]; 1199 __IM uint32_t CTITRIGINSTATUS; /*!< (@ 0x00000130) CTI Trigger In Status register */ 1200 __IM uint32_t CTITRIGOUTSTATUS; /*!< (@ 0x00000134) CTI Trigger Out Status register */ 1201 __IM uint32_t CTICHINSTATUS; /*!< (@ 0x00000138) CTI Channel In Status register */ 1202 __IM uint32_t RESERVED3; 1203 __IOM uint32_t CTIGATE; /*!< (@ 0x00000140) Enable CTI Channel Gate register */ 1204 __IM uint32_t RESERVED4[926]; 1205 __IM uint32_t DEVARCH; /*!< (@ 0x00000FBC) Device Architecture register */ 1206 __IM uint32_t RESERVED5[2]; 1207 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration register */ 1208 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier register */ 1209 __IM uint32_t PIDR4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ 1210 __IM uint32_t PIDR5; /*!< (@ 0x00000FD4) Peripheral ID5 register */ 1211 __IM uint32_t PIDR6; /*!< (@ 0x00000FD8) Peripheral ID6 register */ 1212 __IM uint32_t PIDR7; /*!< (@ 0x00000FDC) Peripheral ID7 register */ 1213 __IM uint32_t PIDR0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ 1214 __IM uint32_t PIDR1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ 1215 __IM uint32_t PIDR2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ 1216 __IM uint32_t PIDR3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ 1217 __IM uint32_t CIDR0; /*!< (@ 0x00000FF0) Component ID0 Register */ 1218 __IM uint32_t CIDR1; /*!< (@ 0x00000FF4) Component ID1 Register */ 1219 __IM uint32_t CIDR2; /*!< (@ 0x00000FF8) Component ID2 Register */ 1220 __IM uint32_t CIDR3; /*!< (@ 0x00000FFC) Component ID3 Register */ 1221 } NRF_CTI_Type; /*!< Size = 4096 (0x1000) */ 1222 1223 1224 1225 /* =========================================================================================================================== */ 1226 /* ================ TAD_S ================ */ 1227 /* =========================================================================================================================== */ 1228 1229 1230 /** 1231 * @brief Trace and debug control (TAD_S) 1232 */ 1233 1234 typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ 1235 __IM uint32_t RESERVED; 1236 __OM uint32_t CLOCKSTART; /*!< (@ 0x00000004) Start all trace and debug clocks. */ 1237 __OM uint32_t CLOCKSTOP; /*!< (@ 0x00000008) Stop all trace and debug clocks. */ 1238 __IM uint32_t RESERVED1[317]; 1239 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ 1240 __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ 1241 __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface 1242 Reset behavior is the same as debug components */ 1243 } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ 1244 1245 1246 1247 /* =========================================================================================================================== */ 1248 /* ================ DCNF_NS ================ */ 1249 /* =========================================================================================================================== */ 1250 1251 1252 /** 1253 * @brief Domain configuration management 0 (DCNF_NS) 1254 */ 1255 1256 typedef struct { /*!< (@ 0x40000000) DCNF_NS Structure */ 1257 __IM uint32_t RESERVED[264]; 1258 __IM uint32_t CPUID; /*!< (@ 0x00000420) CPU ID of this subsystem */ 1259 __IM uint32_t RESERVED1[7]; 1260 __IOM DCNF_EXTPERI_Type EXTPERI[1]; /*!< (@ 0x00000440) Unspecified */ 1261 __IM uint32_t RESERVED2[7]; 1262 __IOM DCNF_EXTRAM_Type EXTRAM[1]; /*!< (@ 0x00000460) Unspecified */ 1263 __IM uint32_t RESERVED3[7]; 1264 __IOM DCNF_EXTCODE_Type EXTCODE[1]; /*!< (@ 0x00000480) Unspecified */ 1265 } NRF_DCNF_Type; /*!< Size = 1156 (0x484) */ 1266 1267 1268 1269 /* =========================================================================================================================== */ 1270 /* ================ FPU_NS ================ */ 1271 /* =========================================================================================================================== */ 1272 1273 1274 /** 1275 * @brief FPU control peripheral 0 (FPU_NS) 1276 */ 1277 1278 typedef struct { /*!< (@ 0x40000000) FPU_NS Structure */ 1279 __IM uint32_t RESERVED[64]; 1280 __IOM uint32_t EVENTS_INVALIDOPERATION; /*!< (@ 0x00000100) An FPUIOC exception triggered by an invalid operation 1281 has occurred in the FPU */ 1282 __IOM uint32_t EVENTS_DIVIDEBYZERO; /*!< (@ 0x00000104) An FPUDZC exception triggered by a floating-point 1283 divide-by-zero operation has occurred in 1284 the FPU */ 1285 __IOM uint32_t EVENTS_OVERFLOW; /*!< (@ 0x00000108) An FPUOFC exception triggered by a floating-point 1286 overflow has occurred in the FPU */ 1287 __IOM uint32_t EVENTS_UNDERFLOW; /*!< (@ 0x0000010C) An FPUUFC exception triggered by a floating-point 1288 underflow has occurred in the FPU */ 1289 __IOM uint32_t EVENTS_INEXACT; /*!< (@ 0x00000110) An FPUIXC exception triggered by an inexact floating-point 1290 operation has occurred in the FPU */ 1291 __IOM uint32_t EVENTS_DENORMALINPUT; /*!< (@ 0x00000114) An FPUIDC exception triggered by a denormal floating-point 1292 input has occurred in the FPU */ 1293 __IM uint32_t RESERVED1[122]; 1294 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1295 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1296 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1297 } NRF_FPU_Type; /*!< Size = 780 (0x30c) */ 1298 1299 1300 1301 /* =========================================================================================================================== */ 1302 /* ================ CACHE_S ================ */ 1303 /* =========================================================================================================================== */ 1304 1305 1306 /** 1307 * @brief Cache (CACHE_S) 1308 */ 1309 1310 typedef struct { /*!< (@ 0x50001000) CACHE_S Structure */ 1311 __IM uint32_t RESERVED[256]; 1312 __IOM CACHE_PROFILING_Type PROFILING[2]; /*!< (@ 0x00000400) Unspecified */ 1313 __IM uint32_t RESERVED1[48]; 1314 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable cache. */ 1315 __OM uint32_t INVALIDATE; /*!< (@ 0x00000504) Invalidate the cache. */ 1316 __OM uint32_t ERASE; /*!< (@ 0x00000508) Erase the cache. */ 1317 __IOM uint32_t PROFILINGENABLE; /*!< (@ 0x0000050C) Enable the profiling counters. */ 1318 __OM uint32_t PROFILINGCLEAR; /*!< (@ 0x00000510) Clear the profiling counters. */ 1319 __IOM uint32_t MODE; /*!< (@ 0x00000514) Cache mode. Switching from Cache to Ram mode 1320 causes the RAM to be cleared. Switching 1321 from RAM to Cache mode causes the cache 1322 to be invalidated. */ 1323 __IOM uint32_t DEBUGLOCK; /*!< (@ 0x00000518) Lock debug mode. */ 1324 __IOM uint32_t ERASESTATUS; /*!< (@ 0x0000051C) Cache erase status. */ 1325 __IOM uint32_t WRITELOCK; /*!< (@ 0x00000520) Lock cache updates. Prevents updating of cache 1326 content on cache misses, but will continue 1327 to lookup instruction/data fetches in content 1328 already present in the cache. Ignored in 1329 RAM mode. */ 1330 } NRF_CACHE_Type; /*!< Size = 1316 (0x524) */ 1331 1332 1333 1334 /* =========================================================================================================================== */ 1335 /* ================ SPU_S ================ */ 1336 /* =========================================================================================================================== */ 1337 1338 1339 /** 1340 * @brief System protection unit (SPU_S) 1341 */ 1342 1343 typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ 1344 __IM uint32_t RESERVED[64]; 1345 __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the 1346 RAM memory space */ 1347 __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the 1348 flash memory space */ 1349 __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one 1350 or several peripherals */ 1351 __IM uint32_t RESERVED1[29]; 1352 __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ 1353 __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ 1354 __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ 1355 __IM uint32_t RESERVED2[93]; 1356 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1357 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1358 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1359 __IM uint32_t RESERVED3[61]; 1360 __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ 1361 __IOM uint32_t CPULOCK; /*!< (@ 0x00000404) Configure bits to lock down CPU features at runtime */ 1362 __IM uint32_t RESERVED4[14]; 1363 __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ 1364 __IM uint32_t RESERVED5[15]; 1365 __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ 1366 __IM uint32_t RESERVED6[14]; 1367 __IOM SPU_GPIOPORT_Type GPIOPORT[2]; /*!< (@ 0x000004C0) Unspecified */ 1368 __IM uint32_t RESERVED7[12]; 1369 __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ 1370 __IM uint32_t RESERVED8[12]; 1371 __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ 1372 __IM uint32_t RESERVED9[44]; 1373 __IOM SPU_FLASHREGION_Type FLASHREGION[64]; /*!< (@ 0x00000600) Unspecified */ 1374 __IOM SPU_RAMREGION_Type RAMREGION[64]; /*!< (@ 0x00000700) Unspecified */ 1375 __IOM SPU_PERIPHID_Type PERIPHID[256]; /*!< (@ 0x00000800) Unspecified */ 1376 } NRF_SPU_Type; /*!< Size = 3072 (0xc00) */ 1377 1378 1379 1380 /* =========================================================================================================================== */ 1381 /* ================ OSCILLATORS_NS ================ */ 1382 /* =========================================================================================================================== */ 1383 1384 1385 /** 1386 * @brief Oscillator control 0 (OSCILLATORS_NS) 1387 */ 1388 1389 typedef struct { /*!< (@ 0x40004000) OSCILLATORS_NS Structure */ 1390 __IM uint32_t RESERVED[369]; 1391 __IOM uint32_t XOSC32MCAPS; /*!< (@ 0x000005C4) Programmable capacitance of XC1 and XC2 */ 1392 __IM uint32_t RESERVED1[62]; 1393 __IOM OSCILLATORS_XOSC32KI_Type XOSC32KI; /*!< (@ 0x000006C0) Unspecified */ 1394 } NRF_OSCILLATORS_Type; /*!< Size = 1748 (0x6d4) */ 1395 1396 1397 1398 /* =========================================================================================================================== */ 1399 /* ================ REGULATORS_NS ================ */ 1400 /* =========================================================================================================================== */ 1401 1402 1403 /** 1404 * @brief Voltage regulators 0 (REGULATORS_NS) 1405 */ 1406 1407 typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ 1408 __IM uint32_t RESERVED[266]; 1409 __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000428) Main supply status */ 1410 __IM uint32_t RESERVED1[53]; 1411 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1412 __IM uint32_t RESERVED2[3]; 1413 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 1414 __IM uint32_t RESERVED3[124]; 1415 __IOM REGULATORS_VREGMAIN_Type VREGMAIN; /*!< (@ 0x00000704) Unspecified */ 1416 __IM uint32_t RESERVED4[126]; 1417 __IOM REGULATORS_VREGRADIO_Type VREGRADIO; /*!< (@ 0x00000900) Unspecified */ 1418 __IM uint32_t RESERVED5[126]; 1419 __IOM REGULATORS_VREGH_Type VREGH; /*!< (@ 0x00000B00) Unspecified */ 1420 } NRF_REGULATORS_Type; /*!< Size = 2820 (0xb04) */ 1421 1422 1423 1424 /* =========================================================================================================================== */ 1425 /* ================ CLOCK_NS ================ */ 1426 /* =========================================================================================================================== */ 1427 1428 1429 /** 1430 * @brief Clock management 0 (CLOCK_NS) 1431 */ 1432 1433 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 1434 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK128M/HFCLK64M source as selected in 1435 HFCLKSRC */ 1436 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK128M/HFCLK64M source */ 1437 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source as selected in LFCLKSRC */ 1438 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 1439 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 1440 __IM uint32_t RESERVED; 1441 __OM uint32_t TASKS_HFCLKAUDIOSTART; /*!< (@ 0x00000018) Start HFCLKAUDIO source */ 1442 __OM uint32_t TASKS_HFCLKAUDIOSTOP; /*!< (@ 0x0000001C) Stop HFCLKAUDIO source */ 1443 __OM uint32_t TASKS_HFCLK192MSTART; /*!< (@ 0x00000020) Start HFCLK192M source as selected in HFCLK192MSRC */ 1444 __OM uint32_t TASKS_HFCLK192MSTOP; /*!< (@ 0x00000024) Stop HFCLK192M source */ 1445 __IM uint32_t RESERVED1[22]; 1446 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 1447 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 1448 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 1449 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 1450 __IOM uint32_t SUBSCRIBE_CAL; /*!< (@ 0x00000090) Subscribe configuration for task CAL */ 1451 __IM uint32_t RESERVED2; 1452 __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTART; /*!< (@ 0x00000098) Subscribe configuration for task HFCLKAUDIOSTART */ 1453 __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTOP; /*!< (@ 0x0000009C) Subscribe configuration for task HFCLKAUDIOSTOP */ 1454 __IOM uint32_t SUBSCRIBE_HFCLK192MSTART; /*!< (@ 0x000000A0) Subscribe configuration for task HFCLK192MSTART */ 1455 __IOM uint32_t SUBSCRIBE_HFCLK192MSTOP; /*!< (@ 0x000000A4) Subscribe configuration for task HFCLK192MSTOP */ 1456 __IM uint32_t RESERVED3[22]; 1457 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK128M/HFCLK64M source started */ 1458 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK source started */ 1459 __IM uint32_t RESERVED4[5]; 1460 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000011C) Calibration of LFRC oscillator complete event */ 1461 __IOM uint32_t EVENTS_HFCLKAUDIOSTARTED; /*!< (@ 0x00000120) HFCLKAUDIO source started */ 1462 __IOM uint32_t EVENTS_HFCLK192MSTARTED; /*!< (@ 0x00000124) HFCLK192M source started */ 1463 __IM uint32_t RESERVED5[22]; 1464 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 1465 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 1466 __IM uint32_t RESERVED6[5]; 1467 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x0000019C) Publish configuration for event DONE */ 1468 __IOM uint32_t PUBLISH_HFCLKAUDIOSTARTED; /*!< (@ 0x000001A0) Publish configuration for event HFCLKAUDIOSTARTED */ 1469 __IOM uint32_t PUBLISH_HFCLK192MSTARTED; /*!< (@ 0x000001A4) Publish configuration for event HFCLK192MSTARTED */ 1470 __IM uint32_t RESERVED7[86]; 1471 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1472 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1473 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1474 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1475 __IM uint32_t RESERVED8[62]; 1476 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 1477 triggered */ 1478 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) Status indicating which HFCLK128M/HFCLK64M source 1479 is running This register value in any CLOCK 1480 instance reflects status only due to configurations/action 1481 in that CLOCK instance. */ 1482 __IM uint32_t RESERVED9; 1483 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 1484 triggered */ 1485 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Status indicating which LFCLK source is running 1486 This register value in any CLOCK instance 1487 reflects status only due to configurations/actions 1488 in that CLOCK instance. */ 1489 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 1490 task was triggered */ 1491 __IM uint32_t RESERVED10[12]; 1492 __IM uint32_t HFCLKAUDIORUN; /*!< (@ 0x00000450) Status indicating that HFCLKAUDIOSTART task has 1493 been triggered */ 1494 __IM uint32_t HFCLKAUDIOSTAT; /*!< (@ 0x00000454) Status indicating which HFCLKAUDIO source is 1495 running */ 1496 __IM uint32_t HFCLK192MRUN; /*!< (@ 0x00000458) Status indicating that HFCLK192MSTART task has 1497 been triggered */ 1498 __IM uint32_t HFCLK192MSTAT; /*!< (@ 0x0000045C) Status indicating which HFCLK192M source is running */ 1499 __IM uint32_t RESERVED11[45]; 1500 __IOM uint32_t HFCLKSRC; /*!< (@ 0x00000514) Clock source for HFCLK128M/HFCLK64M */ 1501 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for LFCLK */ 1502 __IM uint32_t RESERVED12[15]; 1503 __IOM uint32_t HFCLKCTRL; /*!< (@ 0x00000558) HFCLK128M frequency configuration */ 1504 __IOM CLOCK_HFCLKAUDIO_Type HFCLKAUDIO; /*!< (@ 0x0000055C) Unspecified */ 1505 __IM uint32_t RESERVED13[4]; 1506 __IOM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ 1507 __IOM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ 1508 __IM uint32_t RESERVED14; 1509 __IOM uint32_t HFCLKAUDIOALWAYSRUN; /*!< (@ 0x0000057C) Automatic or manual control of HFCLKAUDIO */ 1510 __IOM uint32_t HFCLK192MSRC; /*!< (@ 0x00000580) Clock source for HFCLK192M */ 1511 __IOM uint32_t HFCLK192MALWAYSRUN; /*!< (@ 0x00000584) Automatic or manual control of HFCLK192M */ 1512 __IM uint32_t RESERVED15[12]; 1513 __IOM uint32_t HFCLK192MCTRL; /*!< (@ 0x000005B8) HFCLK192M frequency configuration */ 1514 } NRF_CLOCK_Type; /*!< Size = 1468 (0x5bc) */ 1515 1516 1517 1518 /* =========================================================================================================================== */ 1519 /* ================ POWER_NS ================ */ 1520 /* =========================================================================================================================== */ 1521 1522 1523 /** 1524 * @brief Power control 0 (POWER_NS) 1525 */ 1526 1527 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 1528 __IM uint32_t RESERVED[30]; 1529 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 1530 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-Power mode (variable latency) */ 1531 __IM uint32_t RESERVED1[30]; 1532 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 1533 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 1534 __IM uint32_t RESERVED2[2]; 1535 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1536 __IM uint32_t RESERVED3[2]; 1537 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1538 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1539 __IM uint32_t RESERVED4[27]; 1540 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 1541 __IM uint32_t RESERVED5[2]; 1542 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 1543 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 1544 __IM uint32_t RESERVED6[89]; 1545 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1546 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1547 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1548 __IM uint32_t RESERVED7[132]; 1549 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 1550 register */ 1551 } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ 1552 1553 1554 1555 /* =========================================================================================================================== */ 1556 /* ================ RESET_NS ================ */ 1557 /* =========================================================================================================================== */ 1558 1559 1560 /** 1561 * @brief Reset control 0 (RESET_NS) 1562 */ 1563 1564 typedef struct { /*!< (@ 0x40005000) RESET_NS Structure */ 1565 __IM uint32_t RESERVED[256]; 1566 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1567 __IM uint32_t RESERVED1[131]; 1568 __IOM RESET_NETWORK_Type NETWORK; /*!< (@ 0x00000610) ULP network core control */ 1569 } NRF_RESET_Type; /*!< Size = 1560 (0x618) */ 1570 1571 1572 1573 /* =========================================================================================================================== */ 1574 /* ================ CTRLAP_NS ================ */ 1575 /* =========================================================================================================================== */ 1576 1577 1578 /** 1579 * @brief Control access port 0 (CTRLAP_NS) 1580 */ 1581 1582 typedef struct { /*!< (@ 0x40006000) CTRLAP_NS Structure */ 1583 __IM uint32_t RESERVED[256]; 1584 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 1585 __IM uint32_t RESERVED1[30]; 1586 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 1587 __IM uint32_t RESERVED2[14]; 1588 __IOM CTRLAPPERI_APPROTECT_Type APPROTECT; /*!< (@ 0x00000540) Unspecified */ 1589 __IOM CTRLAPPERI_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000548) Unspecified */ 1590 __IM uint32_t RESERVED3[44]; 1591 __IM uint32_t STATUS; /*!< (@ 0x00000600) Status bits for CTRL-AP peripheral. */ 1592 } NRF_CTRLAPPERI_Type; /*!< Size = 1540 (0x604) */ 1593 1594 1595 1596 /* =========================================================================================================================== */ 1597 /* ================ SPIM0_NS ================ */ 1598 /* =========================================================================================================================== */ 1599 1600 1601 /** 1602 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) 1603 */ 1604 1605 typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ 1606 __IM uint32_t RESERVED[4]; 1607 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1608 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1609 __IM uint32_t RESERVED1; 1610 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1611 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1612 __IM uint32_t RESERVED2[27]; 1613 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 1614 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1615 __IM uint32_t RESERVED3; 1616 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1617 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1618 __IM uint32_t RESERVED4[24]; 1619 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1620 __IM uint32_t RESERVED5[2]; 1621 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1622 __IM uint32_t RESERVED6; 1623 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1624 __IM uint32_t RESERVED7; 1625 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1626 __IM uint32_t RESERVED8[10]; 1627 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1628 __IM uint32_t RESERVED9[13]; 1629 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1630 __IM uint32_t RESERVED10[2]; 1631 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1632 __IM uint32_t RESERVED11; 1633 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 1634 __IM uint32_t RESERVED12; 1635 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1636 __IM uint32_t RESERVED13[10]; 1637 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 1638 __IM uint32_t RESERVED14[12]; 1639 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1640 __IM uint32_t RESERVED15[64]; 1641 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1642 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1643 __IM uint32_t RESERVED16[61]; 1644 __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1645 in this register are set to STALL by hardware 1646 whenever a stall occurres and can be cleared 1647 (set to NOSTALL) by the CPU. */ 1648 __IM uint32_t RESERVED17[63]; 1649 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1650 __IM uint32_t RESERVED18; 1651 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1652 __IM uint32_t RESERVED19[3]; 1653 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1654 source selected. */ 1655 __IM uint32_t RESERVED20[3]; 1656 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1657 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1658 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1659 __IM uint32_t RESERVED21[2]; 1660 __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1661 __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1662 __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1663 __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1664 __IM uint32_t RESERVED22[19]; 1665 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1666 been transmitted in the case when RXD.MAXCNT 1667 is greater than TXD.MAXCNT */ 1668 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1669 1670 1671 1672 /* =========================================================================================================================== */ 1673 /* ================ SPIS0_NS ================ */ 1674 /* =========================================================================================================================== */ 1675 1676 1677 /** 1678 * @brief SPI Slave 0 (SPIS0_NS) 1679 */ 1680 1681 typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ 1682 __IM uint32_t RESERVED[9]; 1683 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1684 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1685 to acquire it */ 1686 __IM uint32_t RESERVED1[30]; 1687 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1688 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1689 __IM uint32_t RESERVED2[22]; 1690 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1691 __IM uint32_t RESERVED3[2]; 1692 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1693 __IM uint32_t RESERVED4[5]; 1694 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1695 __IM uint32_t RESERVED5[22]; 1696 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1697 __IM uint32_t RESERVED6[2]; 1698 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1699 __IM uint32_t RESERVED7[5]; 1700 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1701 __IM uint32_t RESERVED8[21]; 1702 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1703 __IM uint32_t RESERVED9[64]; 1704 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1705 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1706 __IM uint32_t RESERVED10[61]; 1707 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1708 __IM uint32_t RESERVED11[15]; 1709 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1710 __IM uint32_t RESERVED12[47]; 1711 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1712 __IM uint32_t RESERVED13; 1713 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1714 __IM uint32_t RESERVED14[7]; 1715 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1716 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1717 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1718 __IM uint32_t RESERVED15; 1719 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1720 of an ignored transaction. */ 1721 __IM uint32_t RESERVED16[24]; 1722 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1723 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1724 1725 1726 1727 /* =========================================================================================================================== */ 1728 /* ================ TWIM0_NS ================ */ 1729 /* =========================================================================================================================== */ 1730 1731 1732 /** 1733 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) 1734 */ 1735 1736 typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ 1737 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1738 __IM uint32_t RESERVED; 1739 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1740 __IM uint32_t RESERVED1[2]; 1741 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1742 TWI master is not suspended. */ 1743 __IM uint32_t RESERVED2; 1744 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1745 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1746 __IM uint32_t RESERVED3[23]; 1747 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1748 __IM uint32_t RESERVED4; 1749 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1750 __IM uint32_t RESERVED5[2]; 1751 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1752 __IM uint32_t RESERVED6; 1753 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1754 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1755 __IM uint32_t RESERVED7[24]; 1756 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1757 __IM uint32_t RESERVED8[7]; 1758 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1759 __IM uint32_t RESERVED9[8]; 1760 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1761 now suspended. */ 1762 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1763 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1764 __IM uint32_t RESERVED10[2]; 1765 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1766 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1767 byte */ 1768 __IM uint32_t RESERVED11[8]; 1769 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1770 __IM uint32_t RESERVED12[7]; 1771 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1772 __IM uint32_t RESERVED13[8]; 1773 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1774 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1775 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1776 __IM uint32_t RESERVED14[2]; 1777 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1778 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1779 __IM uint32_t RESERVED15[7]; 1780 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1781 __IM uint32_t RESERVED16[63]; 1782 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1783 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1784 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1785 __IM uint32_t RESERVED17[110]; 1786 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1787 __IM uint32_t RESERVED18[14]; 1788 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1789 __IM uint32_t RESERVED19; 1790 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1791 __IM uint32_t RESERVED20[5]; 1792 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1793 source selected. */ 1794 __IM uint32_t RESERVED21[3]; 1795 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1796 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1797 __IM uint32_t RESERVED22[13]; 1798 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1799 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1800 1801 1802 1803 /* =========================================================================================================================== */ 1804 /* ================ TWIS0_NS ================ */ 1805 /* =========================================================================================================================== */ 1806 1807 1808 /** 1809 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) 1810 */ 1811 1812 typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ 1813 __IM uint32_t RESERVED[5]; 1814 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1815 __IM uint32_t RESERVED1; 1816 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1817 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1818 __IM uint32_t RESERVED2[3]; 1819 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1820 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1821 __IM uint32_t RESERVED3[23]; 1822 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1823 __IM uint32_t RESERVED4; 1824 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1825 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1826 __IM uint32_t RESERVED5[3]; 1827 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1828 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1829 __IM uint32_t RESERVED6[19]; 1830 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1831 __IM uint32_t RESERVED7[7]; 1832 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1833 __IM uint32_t RESERVED8[9]; 1834 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1835 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1836 __IM uint32_t RESERVED9[4]; 1837 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1838 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1839 __IM uint32_t RESERVED10[6]; 1840 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1841 __IM uint32_t RESERVED11[7]; 1842 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1843 __IM uint32_t RESERVED12[9]; 1844 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1845 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1846 __IM uint32_t RESERVED13[4]; 1847 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1848 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1849 __IM uint32_t RESERVED14[5]; 1850 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1851 __IM uint32_t RESERVED15[63]; 1852 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1853 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1854 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1855 __IM uint32_t RESERVED16[113]; 1856 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1857 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1858 a match */ 1859 __IM uint32_t RESERVED17[10]; 1860 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1861 __IM uint32_t RESERVED18; 1862 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1863 __IM uint32_t RESERVED19[9]; 1864 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1865 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1866 __IM uint32_t RESERVED20[13]; 1867 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1868 __IM uint32_t RESERVED21; 1869 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1870 mechanism */ 1871 __IM uint32_t RESERVED22[10]; 1872 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1873 of an over-read of the transmit buffer. */ 1874 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1875 1876 1877 1878 /* =========================================================================================================================== */ 1879 /* ================ UARTE0_NS ================ */ 1880 /* =========================================================================================================================== */ 1881 1882 1883 /** 1884 * @brief UART with EasyDMA 0 (UARTE0_NS) 1885 */ 1886 1887 typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 1888 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1889 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1890 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1891 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1892 __IM uint32_t RESERVED[7]; 1893 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1894 __IM uint32_t RESERVED1[20]; 1895 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1896 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1897 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1898 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1899 __IM uint32_t RESERVED2[7]; 1900 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1901 __IM uint32_t RESERVED3[20]; 1902 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1903 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1904 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1905 transferred to Data RAM) */ 1906 __IM uint32_t RESERVED4; 1907 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1908 __IM uint32_t RESERVED5[2]; 1909 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1910 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1911 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1912 __IM uint32_t RESERVED6[7]; 1913 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1914 __IM uint32_t RESERVED7; 1915 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1916 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1917 __IM uint32_t RESERVED8; 1918 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1919 __IM uint32_t RESERVED9[9]; 1920 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1921 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1922 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1923 __IM uint32_t RESERVED10; 1924 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1925 __IM uint32_t RESERVED11[2]; 1926 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1927 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1928 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1929 __IM uint32_t RESERVED12[7]; 1930 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1931 __IM uint32_t RESERVED13; 1932 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1933 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1934 __IM uint32_t RESERVED14; 1935 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1936 __IM uint32_t RESERVED15[9]; 1937 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1938 __IM uint32_t RESERVED16[63]; 1939 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1940 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1941 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1942 __IM uint32_t RESERVED17[93]; 1943 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1944 __IM uint32_t RESERVED18[31]; 1945 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1946 __IM uint32_t RESERVED19; 1947 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1948 __IM uint32_t RESERVED20[3]; 1949 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1950 selected. */ 1951 __IM uint32_t RESERVED21[3]; 1952 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1953 __IM uint32_t RESERVED22; 1954 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1955 __IM uint32_t RESERVED23[7]; 1956 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1957 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1958 1959 1960 1961 /* =========================================================================================================================== */ 1962 /* ================ GPIOTE0_S ================ */ 1963 /* =========================================================================================================================== */ 1964 1965 1966 /** 1967 * @brief GPIO Tasks and Events 0 (GPIOTE0_S) 1968 */ 1969 1970 typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ 1971 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1972 specified in CONFIG[n].PSEL. Action on pin 1973 is configured in CONFIG[n].POLARITY. */ 1974 __IM uint32_t RESERVED[4]; 1975 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1976 specified in CONFIG[n].PSEL. Action on pin 1977 is to set it high. */ 1978 __IM uint32_t RESERVED1[4]; 1979 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1980 specified in CONFIG[n].PSEL. Action on pin 1981 is to set it low. */ 1982 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1983 for task OUT[n] */ 1984 __IM uint32_t RESERVED2[4]; 1985 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 1986 for task SET[n] */ 1987 __IM uint32_t RESERVED3[4]; 1988 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 1989 for task CLR[n] */ 1990 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1991 pin specified in CONFIG[n].PSEL */ 1992 __IM uint32_t RESERVED4[23]; 1993 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1994 with SENSE mechanism enabled */ 1995 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1996 for event IN[n] */ 1997 __IM uint32_t RESERVED5[23]; 1998 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 1999 __IM uint32_t RESERVED6[65]; 2000 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2001 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2002 __IM uint32_t RESERVED7[126]; 2003 __IOM uint32_t LATENCY; /*!< (@ 0x00000504) Latency selection for Event mode (MODE=Event) 2004 with rising or falling edge detection on 2005 the pin. */ 2006 __IM uint32_t RESERVED8[2]; 2007 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 2008 SET[n], and CLR[n] tasks and IN[n] event */ 2009 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 2010 2011 2012 2013 /* =========================================================================================================================== */ 2014 /* ================ SAADC_NS ================ */ 2015 /* =========================================================================================================================== */ 2016 2017 2018 /** 2019 * @brief Analog to Digital Converter 0 (SAADC_NS) 2020 */ 2021 2022 typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ 2023 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 2024 RAM */ 2025 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 2026 are sampled */ 2027 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any ongoing conversion */ 2028 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 2029 __IM uint32_t RESERVED[28]; 2030 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2031 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ 2032 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 2033 __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ 2034 __IM uint32_t RESERVED1[28]; 2035 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 2036 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 2037 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 2038 on the mode, multiple conversions might 2039 be needed for a result to be transferred 2040 to RAM. */ 2041 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM */ 2042 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 2043 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 2044 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 2045 __IM uint32_t RESERVED2[10]; 2046 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 2047 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 2048 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ 2049 __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ 2050 __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ 2051 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ 2052 __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ 2053 __IM uint32_t RESERVED3[74]; 2054 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2055 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2056 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2057 __IM uint32_t RESERVED4[61]; 2058 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 2059 __IM uint32_t RESERVED5[63]; 2060 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 2061 __IM uint32_t RESERVED6[3]; 2062 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 2063 __IM uint32_t RESERVED7[24]; 2064 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 2065 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 2066 not be combined with SCAN. The RESOLUTION 2067 is applied before averaging, thus for high 2068 OVERSAMPLE a higher RESOLUTION should be 2069 used. */ 2070 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 2071 __IM uint32_t RESERVED8[12]; 2072 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 2073 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 2074 2075 2076 2077 /* =========================================================================================================================== */ 2078 /* ================ TIMER0_NS ================ */ 2079 /* =========================================================================================================================== */ 2080 2081 2082 /** 2083 * @brief Timer/Counter 0 (TIMER0_NS) 2084 */ 2085 2086 typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ 2087 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 2088 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 2089 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 2090 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 2091 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 2092 __IM uint32_t RESERVED[11]; 2093 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 2094 CC[n] register */ 2095 __IM uint32_t RESERVED1[10]; 2096 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2097 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2098 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 2099 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 2100 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 2101 for task SHUTDOWN */ 2102 __IM uint32_t RESERVED2[11]; 2103 __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 2104 for task CAPTURE[n] */ 2105 __IM uint32_t RESERVED3[26]; 2106 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 2107 match */ 2108 __IM uint32_t RESERVED4[26]; 2109 __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration 2110 for event COMPARE[n] */ 2111 __IM uint32_t RESERVED5[10]; 2112 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2113 __IM uint32_t RESERVED6[63]; 2114 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2115 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2116 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2117 __IM uint32_t RESERVED7[126]; 2118 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 2119 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 2120 __IM uint32_t RESERVED8; 2121 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 2122 __IM uint32_t RESERVED9[11]; 2123 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 2124 n */ 2125 __IM uint32_t RESERVED10[10]; 2126 __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000580) Description collection: Enable one-shot operation 2127 for Capture/Compare channel n */ 2128 } NRF_TIMER_Type; /*!< Size = 1432 (0x598) */ 2129 2130 2131 2132 /* =========================================================================================================================== */ 2133 /* ================ RTC0_NS ================ */ 2134 /* =========================================================================================================================== */ 2135 2136 2137 /** 2138 * @brief Real-time counter 0 (RTC0_NS) 2139 */ 2140 2141 typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ 2142 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 2143 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 2144 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 2145 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 2146 __IM uint32_t RESERVED[12]; 2147 __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Description collection: Capture RTC counter to 2148 CC[n] register */ 2149 __IM uint32_t RESERVED1[12]; 2150 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2151 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2152 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 2153 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 2154 __IM uint32_t RESERVED2[12]; 2155 __IOM uint32_t SUBSCRIBE_CAPTURE[4]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 2156 for task CAPTURE[n] */ 2157 __IM uint32_t RESERVED3[12]; 2158 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 2159 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 2160 __IM uint32_t RESERVED4[14]; 2161 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 2162 match */ 2163 __IM uint32_t RESERVED5[12]; 2164 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 2165 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 2166 __IM uint32_t RESERVED6[14]; 2167 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 2168 for event COMPARE[n] */ 2169 __IM uint32_t RESERVED7[12]; 2170 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2171 __IM uint32_t RESERVED8[64]; 2172 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2173 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2174 __IM uint32_t RESERVED9[13]; 2175 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 2176 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 2177 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 2178 __IM uint32_t RESERVED10[110]; 2179 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 2180 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768 2181 / (PRESCALER + 1)). Must be written when 2182 RTC is stopped. */ 2183 __IM uint32_t RESERVED11[13]; 2184 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 2185 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 2186 2187 2188 2189 /* =========================================================================================================================== */ 2190 /* ================ DPPIC_NS ================ */ 2191 /* =========================================================================================================================== */ 2192 2193 2194 /** 2195 * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS) 2196 */ 2197 2198 typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ 2199 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2200 __IM uint32_t RESERVED[20]; 2201 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 2202 __IM uint32_t RESERVED1[276]; 2203 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2204 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2205 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2206 __IM uint32_t RESERVED2[189]; 2207 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 2208 Writes to this register are ignored if either 2209 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 2210 is enabled */ 2211 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 2212 2213 2214 2215 /* =========================================================================================================================== */ 2216 /* ================ WDT0_NS ================ */ 2217 /* =========================================================================================================================== */ 2218 2219 2220 /** 2221 * @brief Watchdog Timer 0 (WDT0_NS) 2222 */ 2223 2224 typedef struct { /*!< (@ 0x40018000) WDT0_NS Structure */ 2225 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start WDT */ 2226 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop WDT */ 2227 __IM uint32_t RESERVED[30]; 2228 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2229 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2230 __IM uint32_t RESERVED1[30]; 2231 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2232 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Watchdog stopped */ 2233 __IM uint32_t RESERVED2[30]; 2234 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 2235 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2236 __IM uint32_t RESERVED3[95]; 2237 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2238 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2239 __IM uint32_t RESERVED4[6]; 2240 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ 2241 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ 2242 __IM uint32_t RESERVED5[53]; 2243 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2244 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2245 __IM uint32_t RESERVED6[63]; 2246 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2247 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2248 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2249 __IM uint32_t RESERVED7[4]; 2250 __OM uint32_t TSEN; /*!< (@ 0x00000520) Task stop enable */ 2251 __IM uint32_t RESERVED8[55]; 2252 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 2253 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2254 2255 2256 2257 /* =========================================================================================================================== */ 2258 /* ================ COMP_NS ================ */ 2259 /* =========================================================================================================================== */ 2260 2261 2262 /** 2263 * @brief Comparator 0 (COMP_NS) 2264 */ 2265 2266 typedef struct { /*!< (@ 0x4001A000) COMP_NS Structure */ 2267 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2268 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2269 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2270 __IM uint32_t RESERVED[29]; 2271 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2272 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2273 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE */ 2274 __IM uint32_t RESERVED1[29]; 2275 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 2276 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2277 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2278 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2279 __IM uint32_t RESERVED2[28]; 2280 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2281 __IOM uint32_t PUBLISH_DOWN; /*!< (@ 0x00000184) Publish configuration for event DOWN */ 2282 __IOM uint32_t PUBLISH_UP; /*!< (@ 0x00000188) Publish configuration for event UP */ 2283 __IOM uint32_t PUBLISH_CROSS; /*!< (@ 0x0000018C) Publish configuration for event CROSS */ 2284 __IM uint32_t RESERVED3[28]; 2285 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2286 __IM uint32_t RESERVED4[63]; 2287 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2288 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2289 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2290 __IM uint32_t RESERVED5[61]; 2291 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2292 __IM uint32_t RESERVED6[63]; 2293 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 2294 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 2295 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 2296 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2297 __IM uint32_t RESERVED7[8]; 2298 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 2299 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 2300 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2301 __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ 2302 } NRF_COMP_Type; /*!< Size = 1344 (0x540) */ 2303 2304 2305 2306 /* =========================================================================================================================== */ 2307 /* ================ LPCOMP_NS ================ */ 2308 /* =========================================================================================================================== */ 2309 2310 2311 /** 2312 * @brief Low-power comparator 0 (LPCOMP_NS) 2313 */ 2314 2315 typedef struct { /*!< (@ 0x4001A000) LPCOMP_NS Structure */ 2316 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2317 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2318 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2319 __IM uint32_t RESERVED[29]; 2320 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2321 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2322 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE */ 2323 __IM uint32_t RESERVED1[29]; 2324 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 2325 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2326 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2327 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2328 __IM uint32_t RESERVED2[28]; 2329 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2330 __IOM uint32_t PUBLISH_DOWN; /*!< (@ 0x00000184) Publish configuration for event DOWN */ 2331 __IOM uint32_t PUBLISH_UP; /*!< (@ 0x00000188) Publish configuration for event UP */ 2332 __IOM uint32_t PUBLISH_CROSS; /*!< (@ 0x0000018C) Publish configuration for event CROSS */ 2333 __IM uint32_t RESERVED3[28]; 2334 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2335 __IM uint32_t RESERVED4[64]; 2336 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2337 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2338 __IM uint32_t RESERVED5[61]; 2339 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2340 __IM uint32_t RESERVED6[63]; 2341 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 2342 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 2343 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 2344 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2345 __IM uint32_t RESERVED7[4]; 2346 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 2347 __IM uint32_t RESERVED8[5]; 2348 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2349 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 2350 2351 2352 2353 /* =========================================================================================================================== */ 2354 /* ================ EGU0_NS ================ */ 2355 /* =========================================================================================================================== */ 2356 2357 2358 /** 2359 * @brief Event generator unit 0 (EGU0_NS) 2360 */ 2361 2362 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 2363 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 2364 the corresponding TRIGGERED[n] event */ 2365 __IM uint32_t RESERVED[16]; 2366 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 2367 for task TRIGGER[n] */ 2368 __IM uint32_t RESERVED1[16]; 2369 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 2370 by triggering the corresponding TRIGGER[n] 2371 task */ 2372 __IM uint32_t RESERVED2[16]; 2373 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 2374 for event TRIGGERED[n] */ 2375 __IM uint32_t RESERVED3[80]; 2376 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2377 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2378 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2379 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2380 2381 2382 2383 /* =========================================================================================================================== */ 2384 /* ================ PWM0_NS ================ */ 2385 /* =========================================================================================================================== */ 2386 2387 2388 /** 2389 * @brief Pulse width modulation unit 0 (PWM0_NS) 2390 */ 2391 2392 typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ 2393 __IM uint32_t RESERVED; 2394 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2395 the end of current PWM period, and stops 2396 sequence playback */ 2397 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 2398 on all enabled channels from sequence n, 2399 and starts playing that sequence at the 2400 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2401 Causes PWM generation to start if not running. */ 2402 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2403 all enabled channels if DECODER.MODE=NextStep. 2404 Does not cause PWM generation to start if 2405 not running. */ 2406 __IM uint32_t RESERVED1[28]; 2407 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2408 __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration 2409 for task SEQSTART[n] */ 2410 __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ 2411 __IM uint32_t RESERVED2[28]; 2412 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2413 are no longer generated */ 2414 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 2415 on sequence n */ 2416 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 2417 sequence n, when last value from RAM has 2418 been applied to wave counter */ 2419 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2420 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2421 of times defined in LOOP.CNT */ 2422 __IM uint32_t RESERVED3[25]; 2423 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2424 __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration 2425 for event SEQSTARTED[n] */ 2426 __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration 2427 for event SEQEND[n] */ 2428 __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ 2429 __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ 2430 __IM uint32_t RESERVED4[24]; 2431 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2432 __IM uint32_t RESERVED5[63]; 2433 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2434 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2435 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2436 __IM uint32_t RESERVED6[125]; 2437 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2438 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2439 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2440 counts */ 2441 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2442 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2443 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2444 __IM uint32_t RESERVED7[2]; 2445 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2446 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2447 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2448 2449 2450 2451 /* =========================================================================================================================== */ 2452 /* ================ PDM0_NS ================ */ 2453 /* =========================================================================================================================== */ 2454 2455 2456 /** 2457 * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM0_NS) 2458 */ 2459 2460 typedef struct { /*!< (@ 0x40026000) PDM0_NS Structure */ 2461 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2462 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2463 __IM uint32_t RESERVED[30]; 2464 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2465 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2466 __IM uint32_t RESERVED1[30]; 2467 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2468 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2469 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2470 by SAMPLE.MAXCNT (or the last sample after 2471 a STOP task has been received) to Data RAM */ 2472 __IM uint32_t RESERVED2[29]; 2473 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 2474 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2475 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ 2476 __IM uint32_t RESERVED3[93]; 2477 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2478 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2479 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2480 __IM uint32_t RESERVED4[125]; 2481 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2482 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2483 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2484 signals */ 2485 __IM uint32_t RESERVED5[3]; 2486 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2487 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2488 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2489 sample rate. Change PDMCLKCTRL accordingly. */ 2490 __IM uint32_t RESERVED6[7]; 2491 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2492 __IM uint32_t RESERVED7; 2493 __IOM uint32_t MCLKCONFIG; /*!< (@ 0x0000054C) Master clock generator configuration */ 2494 __IM uint32_t RESERVED8[4]; 2495 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2496 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2497 2498 2499 2500 /* =========================================================================================================================== */ 2501 /* ================ I2S0_NS ================ */ 2502 /* =========================================================================================================================== */ 2503 2504 2505 /** 2506 * @brief Inter-IC Sound 0 (I2S0_NS) 2507 */ 2508 2509 typedef struct { /*!< (@ 0x40028000) I2S0_NS Structure */ 2510 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2511 generator when this is enabled */ 2512 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer and MCK generator. Triggering 2513 this task will cause the event STOPPED to 2514 be generated. */ 2515 __IM uint32_t RESERVED[30]; 2516 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2517 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2518 __IM uint32_t RESERVED1[31]; 2519 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2520 double-buffers. When the I2S module is started 2521 and RX is enabled, this event will be generated 2522 for every RXTXD.MAXCNT words received on 2523 the SDIN pin. */ 2524 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2525 __IM uint32_t RESERVED2[2]; 2526 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2527 double-buffers. When the I2S module is started 2528 and TX is enabled, this event will be generated 2529 for every RXTXD.MAXCNT words that are sent 2530 on the SDOUT pin. */ 2531 __IM uint32_t RESERVED3; 2532 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x0000011C) Frame start event, generated on the active edge 2533 of LRCK */ 2534 __IM uint32_t RESERVED4[25]; 2535 __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ 2536 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ 2537 __IM uint32_t RESERVED5[2]; 2538 __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ 2539 __IM uint32_t RESERVED6; 2540 __IOM uint32_t PUBLISH_FRAMESTART; /*!< (@ 0x0000019C) Publish configuration for event FRAMESTART */ 2541 __IM uint32_t RESERVED7[88]; 2542 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2543 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2544 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2545 __IM uint32_t RESERVED8[125]; 2546 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module */ 2547 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2548 __IM uint32_t RESERVED9[2]; 2549 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2550 __IM uint32_t RESERVED10; 2551 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2552 __IM uint32_t RESERVED11[3]; 2553 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2554 __IM uint32_t RESERVED12[3]; 2555 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2556 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2557 2558 2559 2560 /* =========================================================================================================================== */ 2561 /* ================ IPC_NS ================ */ 2562 /* =========================================================================================================================== */ 2563 2564 2565 /** 2566 * @brief Interprocessor communication 0 (IPC_NS) 2567 */ 2568 2569 typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ 2570 __OM uint32_t TASKS_SEND[16]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC 2571 channel enabled in SEND_CNF[n] */ 2572 __IM uint32_t RESERVED[16]; 2573 __IOM uint32_t SUBSCRIBE_SEND[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 2574 for task SEND[n] */ 2575 __IM uint32_t RESERVED1[16]; 2576 __IOM uint32_t EVENTS_RECEIVE[16]; /*!< (@ 0x00000100) Description collection: Event received on one 2577 or more of the enabled IPC channels in RECEIVE_CNF[n] */ 2578 __IM uint32_t RESERVED2[16]; 2579 __IOM uint32_t PUBLISH_RECEIVE[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 2580 for event RECEIVE[n] */ 2581 __IM uint32_t RESERVED3[80]; 2582 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2583 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2584 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2585 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 2586 __IM uint32_t RESERVED4[128]; 2587 __IOM uint32_t SEND_CNF[16]; /*!< (@ 0x00000510) Description collection: Send event configuration 2588 for TASKS_SEND[n] */ 2589 __IM uint32_t RESERVED5[16]; 2590 __IOM uint32_t RECEIVE_CNF[16]; /*!< (@ 0x00000590) Description collection: Receive event configuration 2591 for EVENTS_RECEIVE[n] */ 2592 __IM uint32_t RESERVED6[16]; 2593 __IOM uint32_t GPMEM[2]; /*!< (@ 0x00000610) Description collection: General purpose memory */ 2594 } NRF_IPC_Type; /*!< Size = 1560 (0x618) */ 2595 2596 2597 2598 /* =========================================================================================================================== */ 2599 /* ================ QSPI_NS ================ */ 2600 /* =========================================================================================================================== */ 2601 2602 2603 /** 2604 * @brief External flash interface 0 (QSPI_NS) 2605 */ 2606 2607 typedef struct { /*!< (@ 0x4002B000) QSPI_NS Structure */ 2608 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ 2609 __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to 2610 internal RAM */ 2611 __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external 2612 flash memory */ 2613 __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ 2614 __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ 2615 __IM uint32_t RESERVED[27]; 2616 __IOM uint32_t SUBSCRIBE_ACTIVATE; /*!< (@ 0x00000080) Subscribe configuration for task ACTIVATE */ 2617 __IOM uint32_t SUBSCRIBE_READSTART; /*!< (@ 0x00000084) Subscribe configuration for task READSTART */ 2618 __IOM uint32_t SUBSCRIBE_WRITESTART; /*!< (@ 0x00000088) Subscribe configuration for task WRITESTART */ 2619 __IOM uint32_t SUBSCRIBE_ERASESTART; /*!< (@ 0x0000008C) Subscribe configuration for task ERASESTART */ 2620 __IOM uint32_t SUBSCRIBE_DEACTIVATE; /*!< (@ 0x00000090) Subscribe configuration for task DEACTIVATE */ 2621 __IM uint32_t RESERVED1[27]; 2622 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be 2623 generated as a response to all QSPI tasks 2624 except DEACTIVATE. */ 2625 __IM uint32_t RESERVED2[31]; 2626 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2627 __IM uint32_t RESERVED3[95]; 2628 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2629 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2630 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2631 __IM uint32_t RESERVED4[125]; 2632 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected 2633 in PSELn registers */ 2634 __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ 2635 __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ 2636 __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ 2637 __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ 2638 __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute 2639 in Place operation. */ 2640 __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ 2641 __IM uint32_t RESERVED5; 2642 __IOM uint32_t XIPEN; /*!< (@ 0x0000054C) Enable Execute in Place operation. */ 2643 __IM uint32_t RESERVED6[4]; 2644 __IOM QSPI_XIP_ENC_Type XIP_ENC; /*!< (@ 0x00000560) Unspecified */ 2645 __IOM QSPI_DMA_ENC_Type DMA_ENC; /*!< (@ 0x00000580) Unspecified */ 2646 __IM uint32_t RESERVED7[24]; 2647 __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ 2648 __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ 2649 __IM uint32_t RESERVED8[3]; 2650 __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep 2651 power-down mode (DPM). */ 2652 __IM uint32_t RESERVED9[3]; 2653 __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ 2654 __IM uint32_t RESERVED10[3]; 2655 __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ 2656 __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ 2657 __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ 2658 __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ 2659 } NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ 2660 2661 2662 2663 /* =========================================================================================================================== */ 2664 /* ================ NFCT_NS ================ */ 2665 /* =========================================================================================================================== */ 2666 2667 2668 /** 2669 * @brief NFC-A compatible radio 0 (NFCT_NS) 2670 */ 2671 2672 typedef struct { /*!< (@ 0x4002D000) NFCT_NS Structure */ 2673 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing 2674 frames, change state to activated */ 2675 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ 2676 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 2677 sense mode */ 2678 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change 2679 state to transmit */ 2680 __IM uint32_t RESERVED[3]; 2681 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 2682 __IM uint32_t RESERVED1; 2683 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 2684 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 2685 __IM uint32_t RESERVED2[21]; 2686 __IOM uint32_t SUBSCRIBE_ACTIVATE; /*!< (@ 0x00000080) Subscribe configuration for task ACTIVATE */ 2687 __IOM uint32_t SUBSCRIBE_DISABLE; /*!< (@ 0x00000084) Subscribe configuration for task DISABLE */ 2688 __IOM uint32_t SUBSCRIBE_SENSE; /*!< (@ 0x00000088) Subscribe configuration for task SENSE */ 2689 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x0000008C) Subscribe configuration for task STARTTX */ 2690 __IM uint32_t RESERVED3[3]; 2691 __IOM uint32_t SUBSCRIBE_ENABLERXDATA; /*!< (@ 0x0000009C) Subscribe configuration for task ENABLERXDATA */ 2692 __IM uint32_t RESERVED4; 2693 __IOM uint32_t SUBSCRIBE_GOIDLE; /*!< (@ 0x000000A4) Subscribe configuration for task GOIDLE */ 2694 __IOM uint32_t SUBSCRIBE_GOSLEEP; /*!< (@ 0x000000A8) Subscribe configuration for task GOSLEEP */ 2695 __IM uint32_t RESERVED5[21]; 2696 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send 2697 frames */ 2698 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 2699 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 2700 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 2701 frame */ 2702 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 2703 symbol of a frame */ 2704 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 2705 frame */ 2706 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) 2707 and transferred to RAM, and EasyDMA has 2708 ended accessing the RX buffer */ 2709 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 2710 contains details on the source of the error. */ 2711 __IM uint32_t RESERVED6[2]; 2712 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 2713 register contains details on the source 2714 of the error. */ 2715 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 2716 in Data RAM full. */ 2717 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 2718 has ended accessing the TX buffer */ 2719 __IM uint32_t RESERVED7; 2720 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 2721 __IM uint32_t RESERVED8[3]; 2722 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ 2723 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ 2724 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 2725 __IM uint32_t RESERVED9[11]; 2726 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2727 __IOM uint32_t PUBLISH_FIELDDETECTED; /*!< (@ 0x00000184) Publish configuration for event FIELDDETECTED */ 2728 __IOM uint32_t PUBLISH_FIELDLOST; /*!< (@ 0x00000188) Publish configuration for event FIELDLOST */ 2729 __IOM uint32_t PUBLISH_TXFRAMESTART; /*!< (@ 0x0000018C) Publish configuration for event TXFRAMESTART */ 2730 __IOM uint32_t PUBLISH_TXFRAMEEND; /*!< (@ 0x00000190) Publish configuration for event TXFRAMEEND */ 2731 __IOM uint32_t PUBLISH_RXFRAMESTART; /*!< (@ 0x00000194) Publish configuration for event RXFRAMESTART */ 2732 __IOM uint32_t PUBLISH_RXFRAMEEND; /*!< (@ 0x00000198) Publish configuration for event RXFRAMEEND */ 2733 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x0000019C) Publish configuration for event ERROR */ 2734 __IM uint32_t RESERVED10[2]; 2735 __IOM uint32_t PUBLISH_RXERROR; /*!< (@ 0x000001A8) Publish configuration for event RXERROR */ 2736 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x000001AC) Publish configuration for event ENDRX */ 2737 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001B0) Publish configuration for event ENDTX */ 2738 __IM uint32_t RESERVED11; 2739 __IOM uint32_t PUBLISH_AUTOCOLRESSTARTED; /*!< (@ 0x000001B8) Publish configuration for event AUTOCOLRESSTARTED */ 2740 __IM uint32_t RESERVED12[3]; 2741 __IOM uint32_t PUBLISH_COLLISION; /*!< (@ 0x000001C8) Publish configuration for event COLLISION */ 2742 __IOM uint32_t PUBLISH_SELECTED; /*!< (@ 0x000001CC) Publish configuration for event SELECTED */ 2743 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001D0) Publish configuration for event STARTED */ 2744 __IM uint32_t RESERVED13[11]; 2745 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2746 __IM uint32_t RESERVED14[63]; 2747 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2748 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2749 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2750 __IM uint32_t RESERVED15[62]; 2751 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 2752 __IM uint32_t RESERVED16; 2753 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 2754 __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) Current operating state of NFC tag */ 2755 __IM uint32_t RESERVED17[3]; 2756 __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ 2757 __IM uint32_t RESERVED18[6]; 2758 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 2759 __IM uint32_t RESERVED19[49]; 2760 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 2761 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 2762 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 2763 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 2764 Data RAM */ 2765 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD 2766 data storage each */ 2767 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 2768 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 2769 __IM uint32_t RESERVED20; 2770 __IOM uint32_t MODULATIONCTRL; /*!< (@ 0x0000052C) Enables the modulation output to a GPIO pin which 2771 can be connected to a second external antenna. */ 2772 __IM uint32_t RESERVED21[2]; 2773 __IOM uint32_t MODULATIONPSEL; /*!< (@ 0x00000538) Pin select for Modulation control */ 2774 __IM uint32_t RESERVED22[21]; 2775 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 2776 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 2777 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 2778 __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. 2779 This setting must be done before the NFCT 2780 peripheral is activated. */ 2781 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 2782 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 2783 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 2784 2785 2786 2787 /* =========================================================================================================================== */ 2788 /* ================ MUTEX_NS ================ */ 2789 /* =========================================================================================================================== */ 2790 2791 2792 /** 2793 * @brief MUTEX 0 (MUTEX_NS) 2794 */ 2795 2796 typedef struct { /*!< (@ 0x40030000) MUTEX_NS Structure */ 2797 __IM uint32_t RESERVED[256]; 2798 __IOM uint32_t MUTEX[16]; /*!< (@ 0x00000400) Description collection: Mutex register */ 2799 } NRF_MUTEX_Type; /*!< Size = 1088 (0x440) */ 2800 2801 2802 2803 /* =========================================================================================================================== */ 2804 /* ================ QDEC0_NS ================ */ 2805 /* =========================================================================================================================== */ 2806 2807 2808 /** 2809 * @brief Quadrature Decoder 0 (QDEC0_NS) 2810 */ 2811 2812 typedef struct { /*!< (@ 0x40033000) QDEC0_NS Structure */ 2813 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 2814 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 2815 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 2816 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 2817 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 2818 __IM uint32_t RESERVED[27]; 2819 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2820 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2821 __IOM uint32_t SUBSCRIBE_READCLRACC; /*!< (@ 0x00000088) Subscribe configuration for task READCLRACC */ 2822 __IOM uint32_t SUBSCRIBE_RDCLRACC; /*!< (@ 0x0000008C) Subscribe configuration for task RDCLRACC */ 2823 __IOM uint32_t SUBSCRIBE_RDCLRDBL; /*!< (@ 0x00000090) Subscribe configuration for task RDCLRDBL */ 2824 __IM uint32_t RESERVED1[27]; 2825 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 2826 written to the SAMPLE register */ 2827 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 2828 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 2829 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 2830 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 2831 __IM uint32_t RESERVED2[27]; 2832 __IOM uint32_t PUBLISH_SAMPLERDY; /*!< (@ 0x00000180) Publish configuration for event SAMPLERDY */ 2833 __IOM uint32_t PUBLISH_REPORTRDY; /*!< (@ 0x00000184) Publish configuration for event REPORTRDY */ 2834 __IOM uint32_t PUBLISH_ACCOF; /*!< (@ 0x00000188) Publish configuration for event ACCOF */ 2835 __IOM uint32_t PUBLISH_DBLRDY; /*!< (@ 0x0000018C) Publish configuration for event DBLRDY */ 2836 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000190) Publish configuration for event STOPPED */ 2837 __IM uint32_t RESERVED3[27]; 2838 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2839 __IM uint32_t RESERVED4[64]; 2840 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2841 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2842 __IM uint32_t RESERVED5[125]; 2843 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 2844 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 2845 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 2846 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 2847 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 2848 and DBLRDY events can be generated */ 2849 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 2850 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 2851 READCLRACC or RDCLRACC task */ 2852 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 2853 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 2854 __IM uint32_t RESERVED6[5]; 2855 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 2856 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 2857 double transitions */ 2858 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 2859 or RDCLRDBL task */ 2860 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 2861 2862 2863 2864 /* =========================================================================================================================== */ 2865 /* ================ USBD_NS ================ */ 2866 /* =========================================================================================================================== */ 2867 2868 2869 /** 2870 * @brief Universal serial bus device 0 (USBD_NS) 2871 */ 2872 2873 typedef struct { /*!< (@ 0x40036000) USBD_NS Structure */ 2874 __IM uint32_t RESERVED; 2875 __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR 2876 and EPIN[n].MAXCNT registers values, and 2877 enables endpoint IN n to respond to traffic 2878 from host */ 2879 __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers 2880 values, and enables sending data on ISO 2881 endpoint */ 2882 __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR 2883 and EPOUT[n].MAXCNT registers values, and 2884 enables endpoint n to respond to traffic 2885 from host */ 2886 __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers 2887 values, and enables receiving of data on 2888 ISO endpoint */ 2889 __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ 2890 __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ 2891 __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint 2892 0 */ 2893 __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined 2894 in the DPDMVALUE register */ 2895 __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state 2896 (USB engine takes control) */ 2897 __IM uint32_t RESERVED1[9]; 2898 __IOM uint32_t SUBSCRIBE_STARTEPIN[8]; /*!< (@ 0x00000084) Description collection: Subscribe configuration 2899 for task STARTEPIN[n] */ 2900 __IOM uint32_t SUBSCRIBE_STARTISOIN; /*!< (@ 0x000000A4) Subscribe configuration for task STARTISOIN */ 2901 __IOM uint32_t SUBSCRIBE_STARTEPOUT[8]; /*!< (@ 0x000000A8) Description collection: Subscribe configuration 2902 for task STARTEPOUT[n] */ 2903 __IOM uint32_t SUBSCRIBE_STARTISOOUT; /*!< (@ 0x000000C8) Subscribe configuration for task STARTISOOUT */ 2904 __IOM uint32_t SUBSCRIBE_EP0RCVOUT; /*!< (@ 0x000000CC) Subscribe configuration for task EP0RCVOUT */ 2905 __IOM uint32_t SUBSCRIBE_EP0STATUS; /*!< (@ 0x000000D0) Subscribe configuration for task EP0STATUS */ 2906 __IOM uint32_t SUBSCRIBE_EP0STALL; /*!< (@ 0x000000D4) Subscribe configuration for task EP0STALL */ 2907 __IOM uint32_t SUBSCRIBE_DPDMDRIVE; /*!< (@ 0x000000D8) Subscribe configuration for task DPDMDRIVE */ 2908 __IOM uint32_t SUBSCRIBE_DPDMNODRIVE; /*!< (@ 0x000000DC) Subscribe configuration for task DPDMNODRIVE */ 2909 __IM uint32_t RESERVED2[8]; 2910 __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected 2911 on USB lines */ 2912 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, 2913 or EPOUT[n].PTR and EPOUT[n].MAXCNT registers 2914 have been captured on all endpoints reported 2915 in the EPSTATUS register */ 2916 __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer 2917 has been consumed. The buffer can be accessed 2918 safely by software. */ 2919 __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place 2920 on the control endpoint */ 2921 __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The 2922 buffer can be accessed safely by software. */ 2923 __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer 2924 has been consumed. The buffer can be accessed 2925 safely by software. */ 2926 __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The 2927 buffer can be accessed safely by software. */ 2928 __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition 2929 has been detected on USB lines */ 2930 __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific 2931 events has occurred. Check EVENTCAUSE register 2932 to find the cause. */ 2933 __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) 2934 on the control endpoint */ 2935 __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, 2936 indicated by the EPDATASTATUS register */ 2937 __IM uint32_t RESERVED3[7]; 2938 __IOM uint32_t PUBLISH_USBRESET; /*!< (@ 0x00000180) Publish configuration for event USBRESET */ 2939 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000184) Publish configuration for event STARTED */ 2940 __IOM uint32_t PUBLISH_ENDEPIN[8]; /*!< (@ 0x00000188) Description collection: Publish configuration 2941 for event ENDEPIN[n] */ 2942 __IOM uint32_t PUBLISH_EP0DATADONE; /*!< (@ 0x000001A8) Publish configuration for event EP0DATADONE */ 2943 __IOM uint32_t PUBLISH_ENDISOIN; /*!< (@ 0x000001AC) Publish configuration for event ENDISOIN */ 2944 __IOM uint32_t PUBLISH_ENDEPOUT[8]; /*!< (@ 0x000001B0) Description collection: Publish configuration 2945 for event ENDEPOUT[n] */ 2946 __IOM uint32_t PUBLISH_ENDISOOUT; /*!< (@ 0x000001D0) Publish configuration for event ENDISOOUT */ 2947 __IOM uint32_t PUBLISH_SOF; /*!< (@ 0x000001D4) Publish configuration for event SOF */ 2948 __IOM uint32_t PUBLISH_USBEVENT; /*!< (@ 0x000001D8) Publish configuration for event USBEVENT */ 2949 __IOM uint32_t PUBLISH_EP0SETUP; /*!< (@ 0x000001DC) Publish configuration for event EP0SETUP */ 2950 __IOM uint32_t PUBLISH_EPDATA; /*!< (@ 0x000001E0) Publish configuration for event EPDATA */ 2951 __IM uint32_t RESERVED4[7]; 2952 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2953 __IM uint32_t RESERVED5[63]; 2954 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2955 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2956 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2957 __IM uint32_t RESERVED6[61]; 2958 __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ 2959 __IM uint32_t RESERVED7[7]; 2960 __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ 2961 __IM uint32_t RESERVED8; 2962 __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA 2963 registers have been captured */ 2964 __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an 2965 acknowledged data transfer has occurred 2966 (EPDATA event) */ 2967 __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ 2968 __IM uint32_t RESERVED9[3]; 2969 __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ 2970 __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ 2971 __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ 2972 __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ 2973 __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ 2974 __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ 2975 __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ 2976 __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ 2977 __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ 2978 __IM uint32_t RESERVED10[15]; 2979 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ 2980 __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ 2981 __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by 2982 the DPDMDRIVE task. The DPDMNODRIVE task 2983 reverts the control of the lines to MAC 2984 IP (no forcing). */ 2985 __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ 2986 __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ 2987 __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ 2988 __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ 2989 __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ 2990 __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame 2991 counter */ 2992 __IM uint32_t RESERVED11[2]; 2993 __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during 2994 USB suspend */ 2995 __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint 2996 to an IN token when no data is ready to 2997 be sent */ 2998 __IM uint32_t RESERVED12[51]; 2999 __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ 3000 __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ 3001 __IM uint32_t RESERVED13[21]; 3002 __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ 3003 __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ 3004 } NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ 3005 3006 3007 3008 /* =========================================================================================================================== */ 3009 /* ================ USBREGULATOR_NS ================ */ 3010 /* =========================================================================================================================== */ 3011 3012 3013 /** 3014 * @brief USB Regulator 0 (USBREGULATOR_NS) 3015 */ 3016 3017 typedef struct { /*!< (@ 0x40037000) USBREGULATOR_NS Structure */ 3018 __IM uint32_t RESERVED[64]; 3019 __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x00000100) Voltage supply detected on VBUS */ 3020 __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000104) Voltage supply removed from VBUS */ 3021 __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000108) USB 3.3 V supply ready */ 3022 __IM uint32_t RESERVED1[29]; 3023 __IOM uint32_t PUBLISH_USBDETECTED; /*!< (@ 0x00000180) Publish configuration for event USBDETECTED */ 3024 __IOM uint32_t PUBLISH_USBREMOVED; /*!< (@ 0x00000184) Publish configuration for event USBREMOVED */ 3025 __IOM uint32_t PUBLISH_USBPWRRDY; /*!< (@ 0x00000188) Publish configuration for event USBPWRRDY */ 3026 __IM uint32_t RESERVED2[93]; 3027 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 3028 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 3029 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 3030 __IM uint32_t RESERVED3[61]; 3031 __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000400) USB supply status */ 3032 } NRF_USBREG_Type; /*!< Size = 1028 (0x404) */ 3033 3034 3035 3036 /* =========================================================================================================================== */ 3037 /* ================ KMU_NS ================ */ 3038 /* =========================================================================================================================== */ 3039 3040 3041 /** 3042 * @brief Key management unit 0 (KMU_NS) 3043 */ 3044 3045 typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ 3046 __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ 3047 __IM uint32_t RESERVED[63]; 3048 __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */ 3049 __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked 3050 for selection */ 3051 __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address 3052 defined, or error during push operation */ 3053 __IM uint32_t RESERVED1[125]; 3054 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 3055 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 3056 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 3057 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 3058 __IM uint32_t RESERVED2[63]; 3059 __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ 3060 __IM uint32_t RESERVED3[60]; 3061 __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed 3062 over secure APB when TASKS_PUSH_KEYSLOT 3063 is started */ 3064 } NRF_KMU_Type; /*!< Size = 1284 (0x504) */ 3065 3066 3067 3068 /* =========================================================================================================================== */ 3069 /* ================ NVMC_NS ================ */ 3070 /* =========================================================================================================================== */ 3071 3072 3073 /** 3074 * @brief Non-volatile memory controller 0 (NVMC_NS) 3075 */ 3076 3077 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 3078 __IM uint32_t RESERVED[256]; 3079 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 3080 __IM uint32_t RESERVED1; 3081 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 3082 __IM uint32_t RESERVED2[62]; 3083 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 3084 __IM uint32_t RESERVED3; 3085 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 3086 __IM uint32_t RESERVED4[3]; 3087 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 3088 __IM uint32_t RESERVED5[25]; 3089 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Non-secure configuration register */ 3090 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 3091 } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ 3092 3093 3094 3095 /* =========================================================================================================================== */ 3096 /* ================ P0_NS ================ */ 3097 /* =========================================================================================================================== */ 3098 3099 3100 /** 3101 * @brief GPIO Port 0 (P0_NS) 3102 */ 3103 3104 typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ 3105 __IM uint32_t RESERVED; 3106 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 3107 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 3108 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 3109 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 3110 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 3111 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 3112 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 3113 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 3114 have met the criteria set in the PIN_CNF[n].SENSE 3115 registers */ 3116 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior 3117 and LDETECT mode (For non-secure pin only) */ 3118 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior 3119 and LDETECT mode (For secure pin only) */ 3120 __IM uint32_t RESERVED1[117]; 3121 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 3122 pins */ 3123 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 3124 3125 3126 3127 /* =========================================================================================================================== */ 3128 /* ================ CRYPTOCELL_S ================ */ 3129 /* =========================================================================================================================== */ 3130 3131 3132 /** 3133 * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL_S) 3134 */ 3135 3136 typedef struct { /*!< (@ 0x50844000) CRYPTOCELL_S Structure */ 3137 __IM uint32_t RESERVED[320]; 3138 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem. */ 3139 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 3140 3141 3142 3143 /* =========================================================================================================================== */ 3144 /* ================ VMC_NS ================ */ 3145 /* =========================================================================================================================== */ 3146 3147 3148 /** 3149 * @brief Volatile Memory controller 0 (VMC_NS) 3150 */ 3151 3152 typedef struct { /*!< (@ 0x40081000) VMC_NS Structure */ 3153 __IM uint32_t RESERVED[384]; 3154 __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ 3155 } NRF_VMC_Type; /*!< Size = 1664 (0x680) */ 3156 3157 3158 /** @} */ /* End of group Device_Peripheral_peripherals */ 3159 3160 3161 /* =========================================================================================================================== */ 3162 /* ================ Device Specific Peripheral Address Map ================ */ 3163 /* =========================================================================================================================== */ 3164 3165 3166 /** @addtogroup Device_Peripheral_peripheralAddr 3167 * @{ 3168 */ 3169 3170 #define NRF_CACHEDATA_S_BASE 0x00F00000UL 3171 #define NRF_CACHEINFO_S_BASE 0x00F08000UL 3172 #define NRF_FICR_S_BASE 0x00FF0000UL 3173 #define NRF_UICR_S_BASE 0x00FF8000UL 3174 #define NRF_CTI_S_BASE 0xE0042000UL 3175 #define NRF_TAD_S_BASE 0xE0080000UL 3176 #define NRF_DCNF_NS_BASE 0x40000000UL 3177 #define NRF_FPU_NS_BASE 0x40000000UL 3178 #define NRF_DCNF_S_BASE 0x50000000UL 3179 #define NRF_FPU_S_BASE 0x50000000UL 3180 #define NRF_CACHE_S_BASE 0x50001000UL 3181 #define NRF_SPU_S_BASE 0x50003000UL 3182 #define NRF_OSCILLATORS_NS_BASE 0x40004000UL 3183 #define NRF_REGULATORS_NS_BASE 0x40004000UL 3184 #define NRF_OSCILLATORS_S_BASE 0x50004000UL 3185 #define NRF_REGULATORS_S_BASE 0x50004000UL 3186 #define NRF_CLOCK_NS_BASE 0x40005000UL 3187 #define NRF_POWER_NS_BASE 0x40005000UL 3188 #define NRF_RESET_NS_BASE 0x40005000UL 3189 #define NRF_CLOCK_S_BASE 0x50005000UL 3190 #define NRF_POWER_S_BASE 0x50005000UL 3191 #define NRF_RESET_S_BASE 0x50005000UL 3192 #define NRF_CTRLAP_NS_BASE 0x40006000UL 3193 #define NRF_CTRLAP_S_BASE 0x50006000UL 3194 #define NRF_SPIM0_NS_BASE 0x40008000UL 3195 #define NRF_SPIS0_NS_BASE 0x40008000UL 3196 #define NRF_TWIM0_NS_BASE 0x40008000UL 3197 #define NRF_TWIS0_NS_BASE 0x40008000UL 3198 #define NRF_UARTE0_NS_BASE 0x40008000UL 3199 #define NRF_SPIM0_S_BASE 0x50008000UL 3200 #define NRF_SPIS0_S_BASE 0x50008000UL 3201 #define NRF_TWIM0_S_BASE 0x50008000UL 3202 #define NRF_TWIS0_S_BASE 0x50008000UL 3203 #define NRF_UARTE0_S_BASE 0x50008000UL 3204 #define NRF_SPIM1_NS_BASE 0x40009000UL 3205 #define NRF_SPIS1_NS_BASE 0x40009000UL 3206 #define NRF_TWIM1_NS_BASE 0x40009000UL 3207 #define NRF_TWIS1_NS_BASE 0x40009000UL 3208 #define NRF_UARTE1_NS_BASE 0x40009000UL 3209 #define NRF_SPIM1_S_BASE 0x50009000UL 3210 #define NRF_SPIS1_S_BASE 0x50009000UL 3211 #define NRF_TWIM1_S_BASE 0x50009000UL 3212 #define NRF_TWIS1_S_BASE 0x50009000UL 3213 #define NRF_UARTE1_S_BASE 0x50009000UL 3214 #define NRF_SPIM4_NS_BASE 0x4000A000UL 3215 #define NRF_SPIM4_S_BASE 0x5000A000UL 3216 #define NRF_SPIM2_NS_BASE 0x4000B000UL 3217 #define NRF_SPIS2_NS_BASE 0x4000B000UL 3218 #define NRF_TWIM2_NS_BASE 0x4000B000UL 3219 #define NRF_TWIS2_NS_BASE 0x4000B000UL 3220 #define NRF_UARTE2_NS_BASE 0x4000B000UL 3221 #define NRF_SPIM2_S_BASE 0x5000B000UL 3222 #define NRF_SPIS2_S_BASE 0x5000B000UL 3223 #define NRF_TWIM2_S_BASE 0x5000B000UL 3224 #define NRF_TWIS2_S_BASE 0x5000B000UL 3225 #define NRF_UARTE2_S_BASE 0x5000B000UL 3226 #define NRF_SPIM3_NS_BASE 0x4000C000UL 3227 #define NRF_SPIS3_NS_BASE 0x4000C000UL 3228 #define NRF_TWIM3_NS_BASE 0x4000C000UL 3229 #define NRF_TWIS3_NS_BASE 0x4000C000UL 3230 #define NRF_UARTE3_NS_BASE 0x4000C000UL 3231 #define NRF_SPIM3_S_BASE 0x5000C000UL 3232 #define NRF_SPIS3_S_BASE 0x5000C000UL 3233 #define NRF_TWIM3_S_BASE 0x5000C000UL 3234 #define NRF_TWIS3_S_BASE 0x5000C000UL 3235 #define NRF_UARTE3_S_BASE 0x5000C000UL 3236 #define NRF_GPIOTE0_S_BASE 0x5000D000UL 3237 #define NRF_SAADC_NS_BASE 0x4000E000UL 3238 #define NRF_SAADC_S_BASE 0x5000E000UL 3239 #define NRF_TIMER0_NS_BASE 0x4000F000UL 3240 #define NRF_TIMER0_S_BASE 0x5000F000UL 3241 #define NRF_TIMER1_NS_BASE 0x40010000UL 3242 #define NRF_TIMER1_S_BASE 0x50010000UL 3243 #define NRF_TIMER2_NS_BASE 0x40011000UL 3244 #define NRF_TIMER2_S_BASE 0x50011000UL 3245 #define NRF_RTC0_NS_BASE 0x40014000UL 3246 #define NRF_RTC0_S_BASE 0x50014000UL 3247 #define NRF_RTC1_NS_BASE 0x40015000UL 3248 #define NRF_RTC1_S_BASE 0x50015000UL 3249 #define NRF_DPPIC_NS_BASE 0x40017000UL 3250 #define NRF_DPPIC_S_BASE 0x50017000UL 3251 #define NRF_WDT0_NS_BASE 0x40018000UL 3252 #define NRF_WDT0_S_BASE 0x50018000UL 3253 #define NRF_WDT1_NS_BASE 0x40019000UL 3254 #define NRF_WDT1_S_BASE 0x50019000UL 3255 #define NRF_COMP_NS_BASE 0x4001A000UL 3256 #define NRF_LPCOMP_NS_BASE 0x4001A000UL 3257 #define NRF_COMP_S_BASE 0x5001A000UL 3258 #define NRF_LPCOMP_S_BASE 0x5001A000UL 3259 #define NRF_EGU0_NS_BASE 0x4001B000UL 3260 #define NRF_EGU0_S_BASE 0x5001B000UL 3261 #define NRF_EGU1_NS_BASE 0x4001C000UL 3262 #define NRF_EGU1_S_BASE 0x5001C000UL 3263 #define NRF_EGU2_NS_BASE 0x4001D000UL 3264 #define NRF_EGU2_S_BASE 0x5001D000UL 3265 #define NRF_EGU3_NS_BASE 0x4001E000UL 3266 #define NRF_EGU3_S_BASE 0x5001E000UL 3267 #define NRF_EGU4_NS_BASE 0x4001F000UL 3268 #define NRF_EGU4_S_BASE 0x5001F000UL 3269 #define NRF_EGU5_NS_BASE 0x40020000UL 3270 #define NRF_EGU5_S_BASE 0x50020000UL 3271 #define NRF_PWM0_NS_BASE 0x40021000UL 3272 #define NRF_PWM0_S_BASE 0x50021000UL 3273 #define NRF_PWM1_NS_BASE 0x40022000UL 3274 #define NRF_PWM1_S_BASE 0x50022000UL 3275 #define NRF_PWM2_NS_BASE 0x40023000UL 3276 #define NRF_PWM2_S_BASE 0x50023000UL 3277 #define NRF_PWM3_NS_BASE 0x40024000UL 3278 #define NRF_PWM3_S_BASE 0x50024000UL 3279 #define NRF_PDM0_NS_BASE 0x40026000UL 3280 #define NRF_PDM0_S_BASE 0x50026000UL 3281 #define NRF_I2S0_NS_BASE 0x40028000UL 3282 #define NRF_I2S0_S_BASE 0x50028000UL 3283 #define NRF_IPC_NS_BASE 0x4002A000UL 3284 #define NRF_IPC_S_BASE 0x5002A000UL 3285 #define NRF_QSPI_NS_BASE 0x4002B000UL 3286 #define NRF_QSPI_S_BASE 0x5002B000UL 3287 #define NRF_NFCT_NS_BASE 0x4002D000UL 3288 #define NRF_NFCT_S_BASE 0x5002D000UL 3289 #define NRF_GPIOTE1_NS_BASE 0x4002F000UL 3290 #define NRF_MUTEX_NS_BASE 0x40030000UL 3291 #define NRF_MUTEX_S_BASE 0x50030000UL 3292 #define NRF_QDEC0_NS_BASE 0x40033000UL 3293 #define NRF_QDEC0_S_BASE 0x50033000UL 3294 #define NRF_QDEC1_NS_BASE 0x40034000UL 3295 #define NRF_QDEC1_S_BASE 0x50034000UL 3296 #define NRF_USBD_NS_BASE 0x40036000UL 3297 #define NRF_USBD_S_BASE 0x50036000UL 3298 #define NRF_USBREGULATOR_NS_BASE 0x40037000UL 3299 #define NRF_USBREGULATOR_S_BASE 0x50037000UL 3300 #define NRF_KMU_NS_BASE 0x40039000UL 3301 #define NRF_NVMC_NS_BASE 0x40039000UL 3302 #define NRF_KMU_S_BASE 0x50039000UL 3303 #define NRF_NVMC_S_BASE 0x50039000UL 3304 #define NRF_P0_NS_BASE 0x40842500UL 3305 #define NRF_P1_NS_BASE 0x40842800UL 3306 #define NRF_P0_S_BASE 0x50842500UL 3307 #define NRF_P1_S_BASE 0x50842800UL 3308 #define NRF_CRYPTOCELL_S_BASE 0x50844000UL 3309 #define NRF_VMC_NS_BASE 0x40081000UL 3310 #define NRF_VMC_S_BASE 0x50081000UL 3311 3312 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 3313 3314 3315 /* =========================================================================================================================== */ 3316 /* ================ Peripheral declaration ================ */ 3317 /* =========================================================================================================================== */ 3318 3319 3320 /** @addtogroup Device_Peripheral_declaration 3321 * @{ 3322 */ 3323 3324 #define NRF_CACHEDATA_S ((NRF_CACHEDATA_Type*) NRF_CACHEDATA_S_BASE) 3325 #define NRF_CACHEINFO_S ((NRF_CACHEINFO_Type*) NRF_CACHEINFO_S_BASE) 3326 #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) 3327 #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) 3328 #define NRF_CTI_S ((NRF_CTI_Type*) NRF_CTI_S_BASE) 3329 #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) 3330 #define NRF_DCNF_NS ((NRF_DCNF_Type*) NRF_DCNF_NS_BASE) 3331 #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) 3332 #define NRF_DCNF_S ((NRF_DCNF_Type*) NRF_DCNF_S_BASE) 3333 #define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE) 3334 #define NRF_CACHE_S ((NRF_CACHE_Type*) NRF_CACHE_S_BASE) 3335 #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) 3336 #define NRF_OSCILLATORS_NS ((NRF_OSCILLATORS_Type*) NRF_OSCILLATORS_NS_BASE) 3337 #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) 3338 #define NRF_OSCILLATORS_S ((NRF_OSCILLATORS_Type*) NRF_OSCILLATORS_S_BASE) 3339 #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) 3340 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 3341 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 3342 #define NRF_RESET_NS ((NRF_RESET_Type*) NRF_RESET_NS_BASE) 3343 #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) 3344 #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) 3345 #define NRF_RESET_S ((NRF_RESET_Type*) NRF_RESET_S_BASE) 3346 #define NRF_CTRLAP_NS ((NRF_CTRLAPPERI_Type*) NRF_CTRLAP_NS_BASE) 3347 #define NRF_CTRLAP_S ((NRF_CTRLAPPERI_Type*) NRF_CTRLAP_S_BASE) 3348 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 3349 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 3350 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 3351 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 3352 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 3353 #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) 3354 #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) 3355 #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) 3356 #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) 3357 #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) 3358 #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) 3359 #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) 3360 #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) 3361 #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) 3362 #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) 3363 #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) 3364 #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) 3365 #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) 3366 #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) 3367 #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) 3368 #define NRF_SPIM4_NS ((NRF_SPIM_Type*) NRF_SPIM4_NS_BASE) 3369 #define NRF_SPIM4_S ((NRF_SPIM_Type*) NRF_SPIM4_S_BASE) 3370 #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) 3371 #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) 3372 #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) 3373 #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) 3374 #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) 3375 #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) 3376 #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) 3377 #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) 3378 #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) 3379 #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) 3380 #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) 3381 #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) 3382 #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) 3383 #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) 3384 #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) 3385 #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) 3386 #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) 3387 #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) 3388 #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) 3389 #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) 3390 #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) 3391 #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) 3392 #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) 3393 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 3394 #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) 3395 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 3396 #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) 3397 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 3398 #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) 3399 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 3400 #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) 3401 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 3402 #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) 3403 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 3404 #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) 3405 #define NRF_WDT0_NS ((NRF_WDT_Type*) NRF_WDT0_NS_BASE) 3406 #define NRF_WDT0_S ((NRF_WDT_Type*) NRF_WDT0_S_BASE) 3407 #define NRF_WDT1_NS ((NRF_WDT_Type*) NRF_WDT1_NS_BASE) 3408 #define NRF_WDT1_S ((NRF_WDT_Type*) NRF_WDT1_S_BASE) 3409 #define NRF_COMP_NS ((NRF_COMP_Type*) NRF_COMP_NS_BASE) 3410 #define NRF_LPCOMP_NS ((NRF_LPCOMP_Type*) NRF_LPCOMP_NS_BASE) 3411 #define NRF_COMP_S ((NRF_COMP_Type*) NRF_COMP_S_BASE) 3412 #define NRF_LPCOMP_S ((NRF_LPCOMP_Type*) NRF_LPCOMP_S_BASE) 3413 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 3414 #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) 3415 #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) 3416 #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) 3417 #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) 3418 #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) 3419 #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) 3420 #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) 3421 #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) 3422 #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) 3423 #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) 3424 #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) 3425 #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) 3426 #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) 3427 #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) 3428 #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) 3429 #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) 3430 #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) 3431 #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) 3432 #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) 3433 #define NRF_PDM0_NS ((NRF_PDM_Type*) NRF_PDM0_NS_BASE) 3434 #define NRF_PDM0_S ((NRF_PDM_Type*) NRF_PDM0_S_BASE) 3435 #define NRF_I2S0_NS ((NRF_I2S_Type*) NRF_I2S0_NS_BASE) 3436 #define NRF_I2S0_S ((NRF_I2S_Type*) NRF_I2S0_S_BASE) 3437 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 3438 #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) 3439 #define NRF_QSPI_NS ((NRF_QSPI_Type*) NRF_QSPI_NS_BASE) 3440 #define NRF_QSPI_S ((NRF_QSPI_Type*) NRF_QSPI_S_BASE) 3441 #define NRF_NFCT_NS ((NRF_NFCT_Type*) NRF_NFCT_NS_BASE) 3442 #define NRF_NFCT_S ((NRF_NFCT_Type*) NRF_NFCT_S_BASE) 3443 #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) 3444 #define NRF_MUTEX_NS ((NRF_MUTEX_Type*) NRF_MUTEX_NS_BASE) 3445 #define NRF_MUTEX_S ((NRF_MUTEX_Type*) NRF_MUTEX_S_BASE) 3446 #define NRF_QDEC0_NS ((NRF_QDEC_Type*) NRF_QDEC0_NS_BASE) 3447 #define NRF_QDEC0_S ((NRF_QDEC_Type*) NRF_QDEC0_S_BASE) 3448 #define NRF_QDEC1_NS ((NRF_QDEC_Type*) NRF_QDEC1_NS_BASE) 3449 #define NRF_QDEC1_S ((NRF_QDEC_Type*) NRF_QDEC1_S_BASE) 3450 #define NRF_USBD_NS ((NRF_USBD_Type*) NRF_USBD_NS_BASE) 3451 #define NRF_USBD_S ((NRF_USBD_Type*) NRF_USBD_S_BASE) 3452 #define NRF_USBREGULATOR_NS ((NRF_USBREG_Type*) NRF_USBREGULATOR_NS_BASE) 3453 #define NRF_USBREGULATOR_S ((NRF_USBREG_Type*) NRF_USBREGULATOR_S_BASE) 3454 #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) 3455 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 3456 #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) 3457 #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) 3458 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 3459 #define NRF_P1_NS ((NRF_GPIO_Type*) NRF_P1_NS_BASE) 3460 #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) 3461 #define NRF_P1_S ((NRF_GPIO_Type*) NRF_P1_S_BASE) 3462 #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) 3463 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 3464 #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) 3465 3466 /** @} */ /* End of group Device_Peripheral_declaration */ 3467 3468 3469 #ifdef __cplusplus 3470 } 3471 #endif 3472 3473 #endif /* NRF5340_APPLICATION_H */ 3474 3475 3476 /** @} */ /* End of group nrf5340_application */ 3477 3478 /** @} */ /* End of group Nordic Semiconductor */ 3479
