1 /* 2 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n 3 \n 4 SPDX-License-Identifier: BSD-3-Clause\n 5 \n 6 Redistribution and use in source and binary forms, with or without\n 7 modification, are permitted provided that the following conditions are met:\n 8 \n 9 1. Redistributions of source code must retain the above copyright notice, this\n 10 list of conditions and the following disclaimer.\n 11 \n 12 2. Redistributions in binary form must reproduce the above copyright\n 13 notice, this list of conditions and the following disclaimer in the\n 14 documentation and/or other materials provided with the distribution.\n 15 \n 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n 17 contributors may be used to endorse or promote products derived from this\n 18 software without specific prior written permission.\n 19 \n 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n 30 POSSIBILITY OF SUCH DAMAGE.\n 31 * 32 * @file nrf51.h 33 * @brief CMSIS HeaderFile 34 * @version 522 35 * @date 04. April 2023 36 * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:28 37 * from File 'nrf51.svd', 38 * last modified on Tuesday, 04.04.2023 09:57:13 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf51 49 * @{ 50 */ 51 52 53 #ifndef NRF51_H 54 #define NRF51_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 77 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 78 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 79 /* =========================================== nrf51 Specific Interrupt Numbers ============================================ */ 80 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 81 RADIO_IRQn = 1, /*!< 1 RADIO */ 82 UART0_IRQn = 2, /*!< 2 UART0 */ 83 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ 84 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ 85 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 86 ADC_IRQn = 7, /*!< 7 ADC */ 87 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 88 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 89 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 90 RTC0_IRQn = 11, /*!< 11 RTC0 */ 91 TEMP_IRQn = 12, /*!< 12 TEMP */ 92 RNG_IRQn = 13, /*!< 13 RNG */ 93 ECB_IRQn = 14, /*!< 14 ECB */ 94 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 95 WDT_IRQn = 16, /*!< 16 WDT */ 96 RTC1_IRQn = 17, /*!< 17 RTC1 */ 97 QDEC_IRQn = 18, /*!< 18 QDEC */ 98 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ 99 SWI0_IRQn = 20, /*!< 20 SWI0 */ 100 SWI1_IRQn = 21, /*!< 21 SWI1 */ 101 SWI2_IRQn = 22, /*!< 22 SWI2 */ 102 SWI3_IRQn = 23, /*!< 23 SWI3 */ 103 SWI4_IRQn = 24, /*!< 24 SWI4 */ 104 SWI5_IRQn = 25 /*!< 25 SWI5 */ 105 } IRQn_Type; 106 107 108 109 /* =========================================================================================================================== */ 110 /* ================ Processor and Core Peripheral Section ================ */ 111 /* =========================================================================================================================== */ 112 113 /* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ 114 #define __CM0_REV 0x0301U /*!< CM0 Core Revision */ 115 #define __INTERRUPTS_MAX 32 /*!< Top interrupt number */ 116 #define __DSP_PRESENT 0 /*!< DSP present or not */ 117 #define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 118 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 119 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 120 #define __MPU_PRESENT 0 /*!< MPU present */ 121 #define __FPU_PRESENT 0 /*!< FPU present */ 122 123 124 /** @} */ /* End of group Configuration_of_CMSIS */ 125 126 #include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ 127 #include "system_nrf51.h" /*!< nrf51 System */ 128 129 #ifndef __IM /*!< Fallback for older CMSIS versions */ 130 #define __IM __I 131 #endif 132 #ifndef __OM /*!< Fallback for older CMSIS versions */ 133 #define __OM __O 134 #endif 135 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 136 #define __IOM __IO 137 #endif 138 139 140 /* ======================================== Start of section using anonymous unions ======================================== */ 141 #if defined (__CC_ARM) 142 #pragma push 143 #pragma anon_unions 144 #elif defined (__ICCARM__) 145 #pragma language=extended 146 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 147 #pragma clang diagnostic push 148 #pragma clang diagnostic ignored "-Wc11-extensions" 149 #pragma clang diagnostic ignored "-Wreserved-id-macro" 150 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 151 #pragma clang diagnostic ignored "-Wnested-anon-types" 152 #elif defined (__GNUC__) 153 /* anonymous unions are enabled by default */ 154 #elif defined (__TMS470__) 155 /* anonymous unions are enabled by default */ 156 #elif defined (__TASKING__) 157 #pragma warning 586 158 #elif defined (__CSMC__) 159 /* anonymous unions are enabled by default */ 160 #else 161 #warning Not supported compiler type 162 #endif 163 164 165 /* =========================================================================================================================== */ 166 /* ================ Device Specific Cluster Section ================ */ 167 /* =========================================================================================================================== */ 168 169 170 /** @addtogroup Device_Peripheral_clusters 171 * @{ 172 */ 173 174 175 /** 176 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks.) 177 */ 178 typedef struct { 179 __OM uint32_t EN; /*!< (@ 0x00000000) Enable channel group. */ 180 __OM uint32_t DIS; /*!< (@ 0x00000004) Disable channel group. */ 181 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 182 183 184 /** 185 * @brief PPI_CH [CH] (PPI Channel.) 186 */ 187 typedef struct { 188 __IOM uint32_t EEP; /*!< (@ 0x00000000) Channel event end-point. */ 189 __IOM uint32_t TEP; /*!< (@ 0x00000004) Channel task end-point. */ 190 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 191 192 193 /** @} */ /* End of group Device_Peripheral_clusters */ 194 195 196 /* =========================================================================================================================== */ 197 /* ================ Device Specific Peripheral Section ================ */ 198 /* =========================================================================================================================== */ 199 200 201 /** @addtogroup Device_Peripheral_peripherals 202 * @{ 203 */ 204 205 206 207 /* =========================================================================================================================== */ 208 /* ================ POWER ================ */ 209 /* =========================================================================================================================== */ 210 211 212 /** 213 * @brief Power Control. (POWER) 214 */ 215 216 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 217 __IM uint32_t RESERVED[30]; 218 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 219 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency). */ 220 __IM uint32_t RESERVED1[34]; 221 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning. */ 222 __IM uint32_t RESERVED2[126]; 223 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 224 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 225 __IM uint32_t RESERVED3[61]; 226 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason. */ 227 __IM uint32_t RESERVED4[9]; 228 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Ram status register. */ 229 __IM uint32_t RESERVED5[53]; 230 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System off register. */ 231 __IM uint32_t RESERVED6[3]; 232 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure configuration. */ 233 __IM uint32_t RESERVED7[2]; 234 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register. This register 235 is a retained register. */ 236 __IM uint32_t RESERVED8; 237 __IOM uint32_t RAMON; /*!< (@ 0x00000524) Ram on/off. */ 238 __IM uint32_t RESERVED9[7]; 239 __IOM uint32_t RESET; /*!< (@ 0x00000544) Pin reset functionality configuration register. 240 This register is a retained register. */ 241 __IM uint32_t RESERVED10[3]; 242 __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Ram on/off. */ 243 __IM uint32_t RESERVED11[8]; 244 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DCDC converter enable configuration register. */ 245 __IM uint32_t RESERVED12[291]; 246 __IOM uint32_t DCDCFORCE; /*!< (@ 0x00000A08) DCDC power-up force register. */ 247 } NRF_POWER_Type; /*!< Size = 2572 (0xa0c) */ 248 249 250 251 /* =========================================================================================================================== */ 252 /* ================ CLOCK ================ */ 253 /* =========================================================================================================================== */ 254 255 256 /** 257 * @brief Clock control. (CLOCK) 258 */ 259 260 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 261 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK clock source. */ 262 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK clock source. */ 263 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK clock source. */ 264 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK clock source. */ 265 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFCLK RC oscillator. */ 266 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer. */ 267 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer. */ 268 __IM uint32_t RESERVED[57]; 269 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started. */ 270 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK oscillator started. */ 271 __IM uint32_t RESERVED1; 272 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator completed. */ 273 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout. */ 274 __IM uint32_t RESERVED2[124]; 275 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 276 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 277 __IM uint32_t RESERVED3[63]; 278 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Task HFCLKSTART trigger status. */ 279 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) High frequency clock status. */ 280 __IM uint32_t RESERVED4; 281 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Task LFCLKSTART triggered status. */ 282 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Low frequency clock status. */ 283 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Clock source for the LFCLK clock, set when task 284 LKCLKSTART is triggered. */ 285 __IM uint32_t RESERVED5[62]; 286 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK clock. */ 287 __IM uint32_t RESERVED6[7]; 288 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval. */ 289 __IM uint32_t RESERVED7[5]; 290 __IOM uint32_t XTALFREQ; /*!< (@ 0x00000550) Crystal frequency. */ 291 } NRF_CLOCK_Type; /*!< Size = 1364 (0x554) */ 292 293 294 295 /* =========================================================================================================================== */ 296 /* ================ MPU ================ */ 297 /* =========================================================================================================================== */ 298 299 300 /** 301 * @brief Memory Protection Unit. (MPU) 302 */ 303 304 typedef struct { /*!< (@ 0x40000000) MPU Structure */ 305 __IM uint32_t RESERVED[330]; 306 __IOM uint32_t PERR0; /*!< (@ 0x00000528) Configuration of peripherals in mpu regions. */ 307 __IOM uint32_t RLENR0; /*!< (@ 0x0000052C) Length of RAM region 0. */ 308 __IM uint32_t RESERVED1[52]; 309 __IOM uint32_t PROTENSET0; /*!< (@ 0x00000600) Erase and write protection bit enable set register. */ 310 __IOM uint32_t PROTENSET1; /*!< (@ 0x00000604) Erase and write protection bit enable set register. */ 311 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable erase and write protection mechanism 312 in debug mode. */ 313 __IOM uint32_t PROTBLOCKSIZE; /*!< (@ 0x0000060C) Erase and write protection block size. */ 314 } NRF_MPU_Type; /*!< Size = 1552 (0x610) */ 315 316 317 318 /* =========================================================================================================================== */ 319 /* ================ RADIO ================ */ 320 /* =========================================================================================================================== */ 321 322 323 /** 324 * @brief The radio. (RADIO) 325 */ 326 327 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 328 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable radio in TX mode. */ 329 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable radio in RX mode. */ 330 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start radio. */ 331 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop radio. */ 332 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable radio. */ 333 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sample of the receive 334 signal strength. */ 335 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement. */ 336 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter. */ 337 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter. */ 338 __IM uint32_t RESERVED[55]; 339 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) Ready event. */ 340 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address event. */ 341 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Payload event. */ 342 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) End event. */ 343 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) Disable event. */ 344 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 345 packet. */ 346 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 347 received packet. */ 348 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of the receive signal strength complete. 349 A new RSSI sample is ready for readout at 350 the RSSISAMPLE register. */ 351 __IM uint32_t RESERVED1[2]; 352 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value specified 353 in BCC register. */ 354 __IM uint32_t RESERVED2[53]; 355 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the radio. */ 356 __IM uint32_t RESERVED3[64]; 357 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 358 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 359 __IM uint32_t RESERVED4[61]; 360 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status of received packet. */ 361 __IM uint32_t RESERVED5; 362 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address. */ 363 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) Received CRC. */ 364 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index. */ 365 __IM uint32_t RESERVED6[60]; 366 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer. Decision point: START task. */ 367 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency. */ 368 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power. */ 369 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation. */ 370 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration 0. */ 371 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration 1. */ 372 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Radio base address 0. Decision point: START task. */ 373 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Radio base address 1. Decision point: START task. */ 374 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0 to 3. */ 375 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4 to 7. */ 376 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select. */ 377 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select. */ 378 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration. */ 379 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial. */ 380 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value. */ 381 __IOM uint32_t TEST; /*!< (@ 0x00000540) Test features enable register. */ 382 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in microseconds. */ 383 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample. */ 384 __IM uint32_t RESERVED7; 385 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state. */ 386 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value. */ 387 __IM uint32_t RESERVED8[2]; 388 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare. */ 389 __IM uint32_t RESERVED9[39]; 390 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Device address base segment. */ 391 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Device address prefix. */ 392 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration. */ 393 __IM uint32_t RESERVED10[56]; 394 __IOM uint32_t OVERRIDE0; /*!< (@ 0x00000724) Trim value override register 0. */ 395 __IOM uint32_t OVERRIDE1; /*!< (@ 0x00000728) Trim value override register 1. */ 396 __IOM uint32_t OVERRIDE2; /*!< (@ 0x0000072C) Trim value override register 2. */ 397 __IOM uint32_t OVERRIDE3; /*!< (@ 0x00000730) Trim value override register 3. */ 398 __IOM uint32_t OVERRIDE4; /*!< (@ 0x00000734) Trim value override register 4. */ 399 __IM uint32_t RESERVED11[561]; 400 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 401 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 402 403 404 405 /* =========================================================================================================================== */ 406 /* ================ UART0 ================ */ 407 /* =========================================================================================================================== */ 408 409 410 /** 411 * @brief Universal Asynchronous Receiver/Transmitter. (UART0) 412 */ 413 414 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 415 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver. */ 416 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver. */ 417 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter. */ 418 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter. */ 419 __IM uint32_t RESERVED[3]; 420 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART. */ 421 __IM uint32_t RESERVED1[56]; 422 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS activated. */ 423 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS deactivated. */ 424 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD. */ 425 __IM uint32_t RESERVED2[4]; 426 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD. */ 427 __IM uint32_t RESERVED3; 428 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected. */ 429 __IM uint32_t RESERVED4[7]; 430 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout. */ 431 __IM uint32_t RESERVED5[46]; 432 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for UART. */ 433 __IM uint32_t RESERVED6[64]; 434 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 435 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 436 __IM uint32_t RESERVED7[93]; 437 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source. Write error field to 1 to clear 438 error. */ 439 __IM uint32_t RESERVED8[31]; 440 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART and acquire IOs. */ 441 __IM uint32_t RESERVED9; 442 __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS. */ 443 __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD. */ 444 __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS. */ 445 __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD. */ 446 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register. On read action the buffer pointer 447 is displaced. Once read the character is 448 consumed. If read when no character available, 449 the UART will stop working. */ 450 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register. */ 451 __IM uint32_t RESERVED10; 452 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) UART Baudrate. */ 453 __IM uint32_t RESERVED11[17]; 454 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control 455 register. */ 456 __IM uint32_t RESERVED12[675]; 457 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 458 } NRF_UART_Type; /*!< Size = 4096 (0x1000) */ 459 460 461 462 /* =========================================================================================================================== */ 463 /* ================ SPI0 ================ */ 464 /* =========================================================================================================================== */ 465 466 467 /** 468 * @brief SPI master 0. (SPI0) 469 */ 470 471 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 472 __IM uint32_t RESERVED[66]; 473 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received. */ 474 __IM uint32_t RESERVED1[126]; 475 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 476 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 477 __IM uint32_t RESERVED2[125]; 478 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI. */ 479 __IM uint32_t RESERVED3; 480 __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ 481 __IOM uint32_t PSELMOSI; /*!< (@ 0x0000050C) Pin select for MOSI. */ 482 __IOM uint32_t PSELMISO; /*!< (@ 0x00000510) Pin select for MISO. */ 483 __IM uint32_t RESERVED4; 484 __IM uint32_t RXD; /*!< (@ 0x00000518) RX data. */ 485 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data. */ 486 __IM uint32_t RESERVED5; 487 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ 488 __IM uint32_t RESERVED6[11]; 489 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ 490 __IM uint32_t RESERVED7[681]; 491 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 492 } NRF_SPI_Type; /*!< Size = 4096 (0x1000) */ 493 494 495 496 /* =========================================================================================================================== */ 497 /* ================ TWI0 ================ */ 498 /* =========================================================================================================================== */ 499 500 501 /** 502 * @brief Two-wire interface master 0. (TWI0) 503 */ 504 505 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 506 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start 2-Wire master receive sequence. */ 507 __IM uint32_t RESERVED; 508 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start 2-Wire master transmit sequence. */ 509 __IM uint32_t RESERVED1[2]; 510 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop 2-Wire transaction. */ 511 __IM uint32_t RESERVED2; 512 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend 2-Wire transaction. */ 513 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume 2-Wire transaction. */ 514 __IM uint32_t RESERVED3[56]; 515 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Two-wire stopped. */ 516 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) Two-wire ready to deliver new RXD byte received. */ 517 __IM uint32_t RESERVED4[4]; 518 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) Two-wire finished sending last TXD byte. */ 519 __IM uint32_t RESERVED5; 520 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Two-wire error detected. */ 521 __IM uint32_t RESERVED6[4]; 522 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) Two-wire byte boundary. */ 523 __IM uint32_t RESERVED7[3]; 524 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Two-wire suspended. */ 525 __IM uint32_t RESERVED8[45]; 526 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for TWI. */ 527 __IM uint32_t RESERVED9[64]; 528 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 529 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 530 __IM uint32_t RESERVED10[110]; 531 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Two-wire error source. Write error field to 1 532 to clear error. */ 533 __IM uint32_t RESERVED11[14]; 534 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable two-wire master. */ 535 __IM uint32_t RESERVED12; 536 __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL. */ 537 __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA. */ 538 __IM uint32_t RESERVED13[2]; 539 __IM uint32_t RXD; /*!< (@ 0x00000518) RX data register. */ 540 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data register. */ 541 __IM uint32_t RESERVED14; 542 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) Two-wire frequency. */ 543 __IM uint32_t RESERVED15[24]; 544 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the two-wire transfer. */ 545 __IM uint32_t RESERVED16[668]; 546 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 547 } NRF_TWI_Type; /*!< Size = 4096 (0x1000) */ 548 549 550 551 /* =========================================================================================================================== */ 552 /* ================ SPIS1 ================ */ 553 /* =========================================================================================================================== */ 554 555 556 /** 557 * @brief SPI slave 1. (SPIS1) 558 */ 559 560 typedef struct { /*!< (@ 0x40004000) SPIS1 Structure */ 561 __IM uint32_t RESERVED[9]; 562 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore. */ 563 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore. */ 564 __IM uint32_t RESERVED1[54]; 565 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed. */ 566 __IM uint32_t RESERVED2[2]; 567 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 568 __IM uint32_t RESERVED3[5]; 569 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired. */ 570 __IM uint32_t RESERVED4[53]; 571 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for SPIS. */ 572 __IM uint32_t RESERVED5[64]; 573 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 574 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 575 __IM uint32_t RESERVED6[61]; 576 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status. */ 577 __IM uint32_t RESERVED7[15]; 578 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction. */ 579 __IM uint32_t RESERVED8[47]; 580 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIS. */ 581 __IM uint32_t RESERVED9; 582 __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ 583 __IOM uint32_t PSELMISO; /*!< (@ 0x0000050C) Pin select for MISO. */ 584 __IOM uint32_t PSELMOSI; /*!< (@ 0x00000510) Pin select for MOSI. */ 585 __IOM uint32_t PSELCSN; /*!< (@ 0x00000514) Pin select for CSN. */ 586 __IM uint32_t RESERVED10[7]; 587 __IOM uint32_t RXDPTR; /*!< (@ 0x00000534) RX data pointer. */ 588 __IOM uint32_t MAXRX; /*!< (@ 0x00000538) Maximum number of bytes in the receive buffer. */ 589 __IM uint32_t AMOUNTRX; /*!< (@ 0x0000053C) Number of bytes received in last granted transaction. */ 590 __IM uint32_t RESERVED11; 591 __IOM uint32_t TXDPTR; /*!< (@ 0x00000544) TX data pointer. */ 592 __IOM uint32_t MAXTX; /*!< (@ 0x00000548) Maximum number of bytes in the transmit buffer. */ 593 __IM uint32_t AMOUNTTX; /*!< (@ 0x0000054C) Number of bytes transmitted in last granted transaction. */ 594 __IM uint32_t RESERVED12; 595 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ 596 __IM uint32_t RESERVED13; 597 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. */ 598 __IM uint32_t RESERVED14[24]; 599 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. */ 600 __IM uint32_t RESERVED15[654]; 601 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 602 } NRF_SPIS_Type; /*!< Size = 4096 (0x1000) */ 603 604 605 606 /* =========================================================================================================================== */ 607 /* ================ GPIOTE ================ */ 608 /* =========================================================================================================================== */ 609 610 611 /** 612 * @brief GPIO tasks and events. (GPIOTE) 613 */ 614 615 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 616 __OM uint32_t TASKS_OUT[4]; /*!< (@ 0x00000000) Tasks asssociated with GPIOTE channels. */ 617 __IM uint32_t RESERVED[60]; 618 __IOM uint32_t EVENTS_IN[4]; /*!< (@ 0x00000100) Tasks asssociated with GPIOTE channels. */ 619 __IM uint32_t RESERVED1[27]; 620 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple pins. */ 621 __IM uint32_t RESERVED2[97]; 622 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 623 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 624 __IM uint32_t RESERVED3[129]; 625 __IOM uint32_t CONFIG[4]; /*!< (@ 0x00000510) Channel configuration registers. */ 626 __IM uint32_t RESERVED4[695]; 627 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 628 } NRF_GPIOTE_Type; /*!< Size = 4096 (0x1000) */ 629 630 631 632 /* =========================================================================================================================== */ 633 /* ================ ADC ================ */ 634 /* =========================================================================================================================== */ 635 636 637 /** 638 * @brief Analog to digital converter. (ADC) 639 */ 640 641 typedef struct { /*!< (@ 0x40007000) ADC Structure */ 642 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start an ADC conversion. */ 643 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop ADC. */ 644 __IM uint32_t RESERVED[62]; 645 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) ADC conversion complete. */ 646 __IM uint32_t RESERVED1[128]; 647 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 648 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 649 __IM uint32_t RESERVED2[61]; 650 __IM uint32_t BUSY; /*!< (@ 0x00000400) ADC busy register. */ 651 __IM uint32_t RESERVED3[63]; 652 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) ADC enable. */ 653 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) ADC configuration register. */ 654 __IM uint32_t RESULT; /*!< (@ 0x00000508) Result of ADC conversion. */ 655 __IM uint32_t RESERVED4[700]; 656 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 657 } NRF_ADC_Type; /*!< Size = 4096 (0x1000) */ 658 659 660 661 /* =========================================================================================================================== */ 662 /* ================ TIMER0 ================ */ 663 /* =========================================================================================================================== */ 664 665 666 /** 667 * @brief Timer 0. (TIMER0) 668 */ 669 670 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 671 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer. */ 672 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer. */ 673 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (In counter mode). */ 674 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear timer. */ 675 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Shutdown timer. */ 676 __IM uint32_t RESERVED[11]; 677 __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Capture Timer value to CC[n] registers. */ 678 __IM uint32_t RESERVED1[60]; 679 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ 680 __IM uint32_t RESERVED2[44]; 681 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for Timer. */ 682 __IM uint32_t RESERVED3[64]; 683 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 684 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 685 __IM uint32_t RESERVED4[126]; 686 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer Mode selection. */ 687 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Sets timer behaviour. */ 688 __IM uint32_t RESERVED5; 689 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) 4-bit prescaler to source clock frequency (max 690 value 9). Source clock frequency is divided 691 by 2^SCALE. */ 692 __IM uint32_t RESERVED6[11]; 693 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ 694 __IM uint32_t RESERVED7[683]; 695 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 696 } NRF_TIMER_Type; /*!< Size = 4096 (0x1000) */ 697 698 699 700 /* =========================================================================================================================== */ 701 /* ================ RTC0 ================ */ 702 /* =========================================================================================================================== */ 703 704 705 /** 706 * @brief Real time counter 0. (RTC0) 707 */ 708 709 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 710 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC Counter. */ 711 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC Counter. */ 712 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC Counter. */ 713 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFFFF0. */ 714 __IM uint32_t RESERVED[60]; 715 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment. */ 716 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow. */ 717 __IM uint32_t RESERVED1[14]; 718 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ 719 __IM uint32_t RESERVED2[109]; 720 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 721 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 722 __IM uint32_t RESERVED3[13]; 723 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Configures event enable routing to PPI for each 724 RTC event. */ 725 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable events routing to PPI. The reading of 726 this register gives the value of EVTEN. */ 727 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable events routing to PPI. The reading of 728 this register gives the value of EVTEN. */ 729 __IM uint32_t RESERVED4[110]; 730 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value. */ 731 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 732 Must be written when RTC is STOPed. */ 733 __IM uint32_t RESERVED5[13]; 734 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ 735 __IM uint32_t RESERVED6[683]; 736 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 737 } NRF_RTC_Type; /*!< Size = 4096 (0x1000) */ 738 739 740 741 /* =========================================================================================================================== */ 742 /* ================ TEMP ================ */ 743 /* =========================================================================================================================== */ 744 745 746 /** 747 * @brief Temperature Sensor. (TEMP) 748 */ 749 750 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 751 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement. */ 752 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement. */ 753 __IM uint32_t RESERVED[62]; 754 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready 755 event. */ 756 __IM uint32_t RESERVED1[128]; 757 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 758 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 759 __IM uint32_t RESERVED2[127]; 760 __IM int32_t TEMP; /*!< (@ 0x00000508) Die temperature in degC, 2's complement format, 761 0.25 degC pecision. */ 762 __IM uint32_t RESERVED3[700]; 763 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 764 } NRF_TEMP_Type; /*!< Size = 4096 (0x1000) */ 765 766 767 768 /* =========================================================================================================================== */ 769 /* ================ RNG ================ */ 770 /* =========================================================================================================================== */ 771 772 773 /** 774 * @brief Random Number Generator. (RNG) 775 */ 776 777 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 778 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the random number generator. */ 779 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the random number generator. */ 780 __IM uint32_t RESERVED[62]; 781 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) New random number generated and written to VALUE 782 register. */ 783 __IM uint32_t RESERVED1[63]; 784 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the RNG. */ 785 __IM uint32_t RESERVED2[64]; 786 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register */ 787 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register */ 788 __IM uint32_t RESERVED3[126]; 789 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ 790 __IM uint32_t VALUE; /*!< (@ 0x00000508) RNG random number. */ 791 __IM uint32_t RESERVED4[700]; 792 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 793 } NRF_RNG_Type; /*!< Size = 4096 (0x1000) */ 794 795 796 797 /* =========================================================================================================================== */ 798 /* ================ ECB ================ */ 799 /* =========================================================================================================================== */ 800 801 802 /** 803 * @brief AES ECB Mode Encryption. (ECB) 804 */ 805 806 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 807 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt. If a crypto operation 808 is running, this will not initiate a new 809 encryption and the ERRORECB event will be 810 triggered. */ 811 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Stop current ECB encryption. If a crypto operation 812 is running, this will will trigger the ERRORECB 813 event. */ 814 __IM uint32_t RESERVED[62]; 815 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete. */ 816 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted due to a STOPECB task 817 or due to an error. */ 818 __IM uint32_t RESERVED1[127]; 819 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 820 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 821 __IM uint32_t RESERVED2[126]; 822 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointer. */ 823 __IM uint32_t RESERVED3[701]; 824 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 825 } NRF_ECB_Type; /*!< Size = 4096 (0x1000) */ 826 827 828 829 /* =========================================================================================================================== */ 830 /* ================ AAR ================ */ 831 /* =========================================================================================================================== */ 832 833 834 /** 835 * @brief Accelerated Address Resolver. (AAR) 836 */ 837 838 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 839 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 840 in the IRK data structure. */ 841 __IM uint32_t RESERVED; 842 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses. */ 843 __IM uint32_t RESERVED1[61]; 844 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure completed. */ 845 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved. */ 846 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved. */ 847 __IM uint32_t RESERVED2[126]; 848 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 849 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 850 __IM uint32_t RESERVED3[61]; 851 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status. */ 852 __IM uint32_t RESERVED4[63]; 853 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR. */ 854 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of Identity root Keys in the IRK data 855 structure. */ 856 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to the IRK data structure. */ 857 __IM uint32_t RESERVED5; 858 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address (6 bytes). */ 859 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary 860 storage during resolution. A minimum of 861 3 bytes must be reserved. */ 862 __IM uint32_t RESERVED6[697]; 863 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 864 } NRF_AAR_Type; /*!< Size = 4096 (0x1000) */ 865 866 867 868 /* =========================================================================================================================== */ 869 /* ================ CCM ================ */ 870 /* =========================================================================================================================== */ 871 872 873 /** 874 * @brief AES CCM Mode Encryption. (CCM) 875 */ 876 877 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 878 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 879 will stop by itself when completed. */ 880 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encrypt/decrypt. This operation will stop 881 by itself when completed. */ 882 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encrypt/decrypt. */ 883 __IM uint32_t RESERVED[61]; 884 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation completed. */ 885 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt completed. */ 886 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Error happened. */ 887 __IM uint32_t RESERVED1[61]; 888 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the CCM. */ 889 __IM uint32_t RESERVED2[64]; 890 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 891 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 892 __IM uint32_t RESERVED3[61]; 893 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) CCM RX MIC check result. */ 894 __IM uint32_t RESERVED4[63]; 895 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) CCM enable. */ 896 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode. */ 897 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to a data structure holding AES key and 898 NONCE vector. */ 899 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Pointer to the input packet. */ 900 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Pointer to the output packet. */ 901 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary 902 storage during resolution. A minimum of 903 43 bytes must be reserved. */ 904 __IM uint32_t RESERVED5[697]; 905 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 906 } NRF_CCM_Type; /*!< Size = 4096 (0x1000) */ 907 908 909 910 /* =========================================================================================================================== */ 911 /* ================ WDT ================ */ 912 /* =========================================================================================================================== */ 913 914 915 /** 916 * @brief Watchdog Timer. (WDT) 917 */ 918 919 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 920 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog. */ 921 __IM uint32_t RESERVED[63]; 922 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout. */ 923 __IM uint32_t RESERVED1[128]; 924 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 925 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 926 __IM uint32_t RESERVED2[61]; 927 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Watchdog running status. */ 928 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status. */ 929 __IM uint32_t RESERVED3[63]; 930 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value in number of 32kiHz clock 931 cycles. */ 932 __IOM uint32_t RREN; /*!< (@ 0x00000508) Reload request enable. */ 933 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register. */ 934 __IM uint32_t RESERVED4[60]; 935 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Reload requests registers. */ 936 __IM uint32_t RESERVED5[631]; 937 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 938 } NRF_WDT_Type; /*!< Size = 4096 (0x1000) */ 939 940 941 942 /* =========================================================================================================================== */ 943 /* ================ QDEC ================ */ 944 /* =========================================================================================================================== */ 945 946 947 /** 948 * @brief Rotary decoder. (QDEC) 949 */ 950 951 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 952 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the quadrature decoder. */ 953 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the quadrature decoder. */ 954 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Transfers the content from ACC registers to ACCREAD 955 registers, and clears the ACC registers. */ 956 __IM uint32_t RESERVED[61]; 957 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) A new sample is written to the sample register. */ 958 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) REPORTPER number of samples accumulated in ACC 959 register, and ACC register different than 960 zero. */ 961 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow. */ 962 __IM uint32_t RESERVED1[61]; 963 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the QDEC. */ 964 __IM uint32_t RESERVED2[64]; 965 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 966 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 967 __IM uint32_t RESERVED3[125]; 968 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the QDEC. */ 969 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity. */ 970 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period. */ 971 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value. */ 972 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to generate an EVENT_REPORTRDY. */ 973 __IM int32_t ACC; /*!< (@ 0x00000514) Accumulated valid transitions register. */ 974 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of ACC register. Value generated by 975 the TASKS_READCLEACC task. */ 976 __IOM uint32_t PSELLED; /*!< (@ 0x0000051C) Pin select for LED output. */ 977 __IOM uint32_t PSELA; /*!< (@ 0x00000520) Pin select for phase A input. */ 978 __IOM uint32_t PSELB; /*!< (@ 0x00000524) Pin select for phase B input. */ 979 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable debouncer input filters. */ 980 __IM uint32_t RESERVED4[5]; 981 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time LED is switched ON before the sample. */ 982 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Accumulated double (error) transitions register. */ 983 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of ACCDBL register. Value generated 984 by the TASKS_READCLEACC task. */ 985 __IM uint32_t RESERVED5[684]; 986 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 987 } NRF_QDEC_Type; /*!< Size = 4096 (0x1000) */ 988 989 990 991 /* =========================================================================================================================== */ 992 /* ================ LPCOMP ================ */ 993 /* =========================================================================================================================== */ 994 995 996 /** 997 * @brief Low power comparator. (LPCOMP) 998 */ 999 1000 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 1001 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the comparator. */ 1002 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the comparator. */ 1003 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value. */ 1004 __IM uint32_t RESERVED[61]; 1005 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid. */ 1006 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Input voltage crossed the threshold going down. */ 1007 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Input voltage crossed the threshold going up. */ 1008 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Input voltage crossed the threshold in any direction. */ 1009 __IM uint32_t RESERVED1[60]; 1010 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the LPCOMP. */ 1011 __IM uint32_t RESERVED2[64]; 1012 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 1013 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 1014 __IM uint32_t RESERVED3[61]; 1015 __IM uint32_t RESULT; /*!< (@ 0x00000400) Result of last compare. */ 1016 __IM uint32_t RESERVED4[63]; 1017 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the LPCOMP. */ 1018 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select. */ 1019 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select. */ 1020 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select. */ 1021 __IM uint32_t RESERVED5[4]; 1022 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration. */ 1023 __IM uint32_t RESERVED6[694]; 1024 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 1025 } NRF_LPCOMP_Type; /*!< Size = 4096 (0x1000) */ 1026 1027 1028 1029 /* =========================================================================================================================== */ 1030 /* ================ SWI ================ */ 1031 /* =========================================================================================================================== */ 1032 1033 1034 /** 1035 * @brief SW Interrupts. (SWI) 1036 */ 1037 1038 typedef struct { /*!< (@ 0x40014000) SWI Structure */ 1039 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1040 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1041 1042 1043 1044 /* =========================================================================================================================== */ 1045 /* ================ NVMC ================ */ 1046 /* =========================================================================================================================== */ 1047 1048 1049 /** 1050 * @brief Non Volatile Memory Controller. (NVMC) 1051 */ 1052 1053 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1054 __IM uint32_t RESERVED[256]; 1055 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag. */ 1056 __IM uint32_t RESERVED1[64]; 1057 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ 1058 1059 union { 1060 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile 1061 memory page. */ 1062 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile 1063 memory page. */ 1064 }; 1065 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory. */ 1066 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Register for erasing a protected non-volatile 1067 memory page. */ 1068 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for start erasing User Information Congfiguration 1069 Registers. */ 1070 } NRF_NVMC_Type; /*!< Size = 1304 (0x518) */ 1071 1072 1073 1074 /* =========================================================================================================================== */ 1075 /* ================ PPI ================ */ 1076 /* =========================================================================================================================== */ 1077 1078 1079 /** 1080 * @brief PPI controller. (PPI) 1081 */ 1082 1083 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1084 __IOM PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< (@ 0x00000000) Channel group tasks. */ 1085 __IM uint32_t RESERVED[312]; 1086 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable. */ 1087 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set. */ 1088 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear. */ 1089 __IM uint32_t RESERVED1; 1090 __IOM PPI_CH_Type CH[16]; /*!< (@ 0x00000510) PPI Channel. */ 1091 __IM uint32_t RESERVED2[156]; 1092 __IOM uint32_t CHG[4]; /*!< (@ 0x00000800) Channel group configuration. */ 1093 } NRF_PPI_Type; /*!< Size = 2064 (0x810) */ 1094 1095 1096 1097 /* =========================================================================================================================== */ 1098 /* ================ FICR ================ */ 1099 /* =========================================================================================================================== */ 1100 1101 1102 /** 1103 * @brief Factory Information Configuration. (FICR) 1104 */ 1105 1106 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 1107 __IM uint32_t RESERVED[4]; 1108 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size in bytes. */ 1109 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size in pages. */ 1110 __IM uint32_t RESERVED1[4]; 1111 __IM uint32_t CLENR0; /*!< (@ 0x00000028) Length of code region 0 in bytes. */ 1112 __IM uint32_t PPFC; /*!< (@ 0x0000002C) Pre-programmed factory code present. */ 1113 __IM uint32_t RESERVED2; 1114 __IM uint32_t NUMRAMBLOCK; /*!< (@ 0x00000034) Number of individualy controllable RAM blocks. */ 1115 1116 union { 1117 __IM uint32_t SIZERAMBLOCKS; /*!< (@ 0x00000038) Size of RAM blocks in bytes. */ 1118 __IM uint32_t SIZERAMBLOCK[4]; /*!< (@ 0x00000038) Deprecated array of size of RAM block in bytes. 1119 This name is kept for backward compatinility 1120 purposes. Use SIZERAMBLOCKS instead. */ 1121 }; 1122 __IM uint32_t RESERVED3[5]; 1123 __IM uint32_t CONFIGID; /*!< (@ 0x0000005C) Configuration identifier. */ 1124 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Device identifier. */ 1125 __IM uint32_t RESERVED4[6]; 1126 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Encryption root. */ 1127 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Identity root. */ 1128 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type. */ 1129 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Device address. */ 1130 __IM uint32_t OVERRIDEEN; /*!< (@ 0x000000AC) Radio calibration override enable. */ 1131 __IM uint32_t NRF_1MBIT[5]; /*!< (@ 0x000000B0) Override values for the OVERRIDEn registers in 1132 RADIO for NRF_1Mbit mode. */ 1133 __IM uint32_t RESERVED5[10]; 1134 __IM uint32_t BLE_1MBIT[5]; /*!< (@ 0x000000EC) Override values for the OVERRIDEn registers in 1135 RADIO for BLE_1Mbit mode. */ 1136 } NRF_FICR_Type; /*!< Size = 256 (0x100) */ 1137 1138 1139 1140 /* =========================================================================================================================== */ 1141 /* ================ UICR ================ */ 1142 /* =========================================================================================================================== */ 1143 1144 1145 /** 1146 * @brief User Information Configuration. (UICR) 1147 */ 1148 1149 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 1150 __IOM uint32_t CLENR0; /*!< (@ 0x00000000) Length of code region 0. */ 1151 __IOM uint32_t RBPCONF; /*!< (@ 0x00000004) Readback protection configuration. */ 1152 __IOM uint32_t XTALFREQ; /*!< (@ 0x00000008) Reset value for CLOCK XTALFREQ register. */ 1153 __IM uint32_t RESERVED; 1154 __IM uint32_t FWID; /*!< (@ 0x00000010) Firmware ID. */ 1155 1156 union { 1157 __IOM uint32_t BOOTLOADERADDR; /*!< (@ 0x00000014) Bootloader start address. */ 1158 __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Reserved for Nordic firmware design. */ 1159 }; 1160 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Reserved for Nordic hardware design. */ 1161 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Reserved for customer. */ 1162 } NRF_UICR_Type; /*!< Size = 256 (0x100) */ 1163 1164 1165 1166 /* =========================================================================================================================== */ 1167 /* ================ GPIO ================ */ 1168 /* =========================================================================================================================== */ 1169 1170 1171 /** 1172 * @brief General purpose input and output. (GPIO) 1173 */ 1174 1175 typedef struct { /*!< (@ 0x50000000) GPIO Structure */ 1176 __IM uint32_t RESERVED[321]; 1177 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port. */ 1178 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port. */ 1179 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port. */ 1180 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port. */ 1181 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins. */ 1182 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register. */ 1183 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register. */ 1184 __IM uint32_t RESERVED1[120]; 1185 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Configuration of GPIO pins. */ 1186 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 1187 1188 1189 /** @} */ /* End of group Device_Peripheral_peripherals */ 1190 1191 1192 /* =========================================================================================================================== */ 1193 /* ================ Device Specific Peripheral Address Map ================ */ 1194 /* =========================================================================================================================== */ 1195 1196 1197 /** @addtogroup Device_Peripheral_peripheralAddr 1198 * @{ 1199 */ 1200 1201 #define NRF_POWER_BASE 0x40000000UL 1202 #define NRF_CLOCK_BASE 0x40000000UL 1203 #define NRF_MPU_BASE 0x40000000UL 1204 #define NRF_RADIO_BASE 0x40001000UL 1205 #define NRF_UART0_BASE 0x40002000UL 1206 #define NRF_SPI0_BASE 0x40003000UL 1207 #define NRF_TWI0_BASE 0x40003000UL 1208 #define NRF_SPI1_BASE 0x40004000UL 1209 #define NRF_TWI1_BASE 0x40004000UL 1210 #define NRF_SPIS1_BASE 0x40004000UL 1211 #define NRF_GPIOTE_BASE 0x40006000UL 1212 #define NRF_ADC_BASE 0x40007000UL 1213 #define NRF_TIMER0_BASE 0x40008000UL 1214 #define NRF_TIMER1_BASE 0x40009000UL 1215 #define NRF_TIMER2_BASE 0x4000A000UL 1216 #define NRF_RTC0_BASE 0x4000B000UL 1217 #define NRF_TEMP_BASE 0x4000C000UL 1218 #define NRF_RNG_BASE 0x4000D000UL 1219 #define NRF_ECB_BASE 0x4000E000UL 1220 #define NRF_AAR_BASE 0x4000F000UL 1221 #define NRF_CCM_BASE 0x4000F000UL 1222 #define NRF_WDT_BASE 0x40010000UL 1223 #define NRF_RTC1_BASE 0x40011000UL 1224 #define NRF_QDEC_BASE 0x40012000UL 1225 #define NRF_LPCOMP_BASE 0x40013000UL 1226 #define NRF_SWI_BASE 0x40014000UL 1227 #define NRF_NVMC_BASE 0x4001E000UL 1228 #define NRF_PPI_BASE 0x4001F000UL 1229 #define NRF_FICR_BASE 0x10000000UL 1230 #define NRF_UICR_BASE 0x10001000UL 1231 #define NRF_GPIO_BASE 0x50000000UL 1232 1233 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1234 1235 1236 /* =========================================================================================================================== */ 1237 /* ================ Peripheral declaration ================ */ 1238 /* =========================================================================================================================== */ 1239 1240 1241 /** @addtogroup Device_Peripheral_declaration 1242 * @{ 1243 */ 1244 1245 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 1246 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 1247 #define NRF_MPU ((NRF_MPU_Type*) NRF_MPU_BASE) 1248 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 1249 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 1250 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 1251 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 1252 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 1253 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 1254 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 1255 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 1256 #define NRF_ADC ((NRF_ADC_Type*) NRF_ADC_BASE) 1257 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 1258 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 1259 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 1260 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 1261 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 1262 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 1263 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 1264 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 1265 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 1266 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 1267 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 1268 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 1269 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 1270 #define NRF_SWI ((NRF_SWI_Type*) NRF_SWI_BASE) 1271 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 1272 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 1273 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 1274 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 1275 #define NRF_GPIO ((NRF_GPIO_Type*) NRF_GPIO_BASE) 1276 1277 /** @} */ /* End of group Device_Peripheral_declaration */ 1278 1279 1280 /* ========================================= End of section using anonymous unions ========================================= */ 1281 #if defined (__CC_ARM) 1282 #pragma pop 1283 #elif defined (__ICCARM__) 1284 /* leave anonymous unions enabled */ 1285 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 1286 #pragma clang diagnostic pop 1287 #elif defined (__GNUC__) 1288 /* anonymous unions are enabled by default */ 1289 #elif defined (__TMS470__) 1290 /* anonymous unions are enabled by default */ 1291 #elif defined (__TASKING__) 1292 #pragma warning restore 1293 #elif defined (__CSMC__) 1294 /* anonymous unions are enabled by default */ 1295 #endif 1296 1297 1298 #ifdef __cplusplus 1299 } 1300 #endif 1301 1302 #endif /* NRF51_H */ 1303 1304 1305 /** @} */ /* End of group nrf51 */ 1306 1307 /** @} */ /* End of group Nordic Semiconductor */ 1308
