1 /*
2 * Copyright (c) 2019 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_FPU_H__
35 #define NRF_FPU_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_fpu_hal FPU HAL
45 * @{
46 * @ingroup nrf_fpu
47 * @brief Hardware access layer (HAL) for managing the Floating Point Unit configuration.
48 */
49
50 /** @brief FPU events. */
51 typedef enum
52 {
53 NRF_FPU_EVENT_INVALIDOPERATION = offsetof(NRF_FPU_Type, EVENTS_INVALIDOPERATION), /**< An FPUIOC exception triggered by an invalid operation has occurred in the FPU. */
54 NRF_FPU_EVENT_DIVIDEBYZERO = offsetof(NRF_FPU_Type, EVENTS_DIVIDEBYZERO), /**< An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU. */
55 NRF_FPU_EVENT_OVERFLOW = offsetof(NRF_FPU_Type, EVENTS_OVERFLOW), /**< An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU. */
56 NRF_FPU_EVENT_UNDERFLOW = offsetof(NRF_FPU_Type, EVENTS_UNDERFLOW), /**< An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU. */
57 NRF_FPU_EVENT_INEXACT = offsetof(NRF_FPU_Type, EVENTS_INEXACT), /**< An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU. */
58 NRF_FPU_EVENT_DENORMALINPUT = offsetof(NRF_FPU_Type, EVENTS_DENORMALINPUT), /**< An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU. */
59 } nrf_fpu_event_t;
60
61
62
63 /** @brief FPU interrupts. */
64 typedef enum
65 {
66 NRF_FPU_INT_INVALIDOPERATION = FPU_INTEN_INVALIDOPERATION_Msk, /**< Interrupt on event INVALIDOPERATION. */
67 NRF_FPU_INT_DIVIDEBYZERO = FPU_INTEN_DIVIDEBYZERO_Msk, /**< Interrupt on event DIVIDEBYZERO. */
68 NRF_FPU_INT_OVERFLOW = FPU_INTEN_OVERFLOW_Msk, /**< Interrupt on event OVERFLOW. */
69 NRF_FPU_INT_UNDERFLOW = FPU_INTEN_UNDERFLOW_Msk, /**< Interrupt on event UNDERFLOW. */
70 NRF_FPU_INT_INEXACT = FPU_INTEN_INEXACT_Msk, /**< Interrupt on event INEXACT. */
71 NRF_FPU_INT_DENORMALINPUT = FPU_INTEN_DENORMALINPUT_Msk, /**< Interrupt on event DENORMALINPUT. */
72 } nrf_fpu_int_mask_t;
73
74 /**
75 * @brief Function for clearing the specified FPU event.
76 *
77 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
78 * @param[in] event Event to be cleared.
79 */
80 NRF_STATIC_INLINE void nrf_fpu_event_clear(NRF_FPU_Type * p_reg,
81 nrf_fpu_event_t event);
82
83 /**
84 * @brief Function for retrieving the state of the FPU event.
85 *
86 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
87 * @param[in] event Event to be checked.
88 *
89 * @retval true The event has been generated.
90 * @retval false The event has not been generated.
91 */
92 NRF_STATIC_INLINE bool nrf_fpu_event_check(NRF_FPU_Type const * p_reg,
93 nrf_fpu_event_t event);
94
95 /**
96 * @brief Function for enabling specified interrupts.
97 *
98 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
99 * @param[in] mask Mask of interrupts to be enabled.
100 */
101 NRF_STATIC_INLINE void nrf_fpu_int_enable(NRF_FPU_Type * p_reg, uint32_t mask);
102
103 /**
104 * @brief Function for disabling specified interrupts.
105 *
106 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
107 * @param[in] mask Mask of interrupts to be disabled.
108 */
109 NRF_STATIC_INLINE void nrf_fpu_int_disable(NRF_FPU_Type * p_reg, uint32_t mask);
110
111 /**
112 * @brief Function for checking if the specified interrupts are enabled.
113 *
114 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
115 * @param[in] mask Mask of interrupts to be checked.
116 *
117 * @return Mask of enabled interrupts.
118 */
119 NRF_STATIC_INLINE uint32_t nrf_fpu_int_enable_check(NRF_FPU_Type const * p_reg, uint32_t mask);
120
121 #ifndef NRF_DECLARE_ONLY
122
nrf_fpu_event_clear(NRF_FPU_Type * p_reg,nrf_fpu_event_t event)123 NRF_STATIC_INLINE void nrf_fpu_event_clear(NRF_FPU_Type * p_reg,
124 nrf_fpu_event_t event)
125 {
126 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
127 }
128
nrf_fpu_event_check(NRF_FPU_Type const * p_reg,nrf_fpu_event_t event)129 NRF_STATIC_INLINE bool nrf_fpu_event_check(NRF_FPU_Type const * p_reg,
130 nrf_fpu_event_t event)
131 {
132 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
133 }
134
nrf_fpu_int_enable(NRF_FPU_Type * p_reg,uint32_t mask)135 NRF_STATIC_INLINE void nrf_fpu_int_enable(NRF_FPU_Type * p_reg, uint32_t mask)
136 {
137 p_reg->INTENSET = mask;
138 }
139
nrf_fpu_int_disable(NRF_FPU_Type * p_reg,uint32_t mask)140 NRF_STATIC_INLINE void nrf_fpu_int_disable(NRF_FPU_Type * p_reg, uint32_t mask)
141 {
142 p_reg->INTENCLR = mask;
143 }
144
nrf_fpu_int_enable_check(NRF_FPU_Type const * p_reg,uint32_t mask)145 NRF_STATIC_INLINE uint32_t nrf_fpu_int_enable_check(NRF_FPU_Type const * p_reg, uint32_t mask)
146 {
147 return p_reg->INTENSET & mask;
148 }
149
150 #endif // NRF_DECLARE_ONLY
151
152 /** @} */
153
154 #ifdef __cplusplus
155 }
156 #endif
157
158 #endif // NRF_FPU_H__
159
