1 /*
2 
3 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF52_BITS_H
36 #define __NRF52_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: AAR */
41 /* Description: Accelerated Address Resolver */
42 
43 /* Register: AAR_TASKS_START */
44 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
45 
46 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
47 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
48 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
49 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
50 
51 /* Register: AAR_TASKS_STOP */
52 /* Description: Stop resolving addresses */
53 
54 /* Bit 0 : Stop resolving addresses */
55 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
56 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
57 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
58 
59 /* Register: AAR_EVENTS_END */
60 /* Description: Address resolution procedure complete */
61 
62 /* Bit 0 : Address resolution procedure complete */
63 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
64 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
65 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
66 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
67 
68 /* Register: AAR_EVENTS_RESOLVED */
69 /* Description: Address resolved */
70 
71 /* Bit 0 : Address resolved */
72 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
73 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
74 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
75 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
76 
77 /* Register: AAR_EVENTS_NOTRESOLVED */
78 /* Description: Address not resolved */
79 
80 /* Bit 0 : Address not resolved */
81 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
82 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
83 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
84 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
85 
86 /* Register: AAR_INTENSET */
87 /* Description: Enable interrupt */
88 
89 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
90 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
91 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
92 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
93 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
94 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
95 
96 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
97 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
98 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
99 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
100 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
101 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
102 
103 /* Bit 0 : Write '1' to enable interrupt for event END */
104 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
105 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
106 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
107 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
108 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
109 
110 /* Register: AAR_INTENCLR */
111 /* Description: Disable interrupt */
112 
113 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
114 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
115 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
116 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
117 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
118 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
119 
120 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
121 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
122 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
123 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
124 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
125 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
126 
127 /* Bit 0 : Write '1' to disable interrupt for event END */
128 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
129 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
130 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
131 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
132 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
133 
134 /* Register: AAR_STATUS */
135 /* Description: Resolution status */
136 
137 /* Bits 3..0 : The IRK that was used last time an address was resolved */
138 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
139 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
140 
141 /* Register: AAR_ENABLE */
142 /* Description: Enable AAR */
143 
144 /* Bits 1..0 : Enable or disable AAR */
145 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
146 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
147 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
148 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
149 
150 /* Register: AAR_NIRK */
151 /* Description: Number of IRKs */
152 
153 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
154 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
155 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
156 
157 /* Register: AAR_IRKPTR */
158 /* Description: Pointer to IRK data structure */
159 
160 /* Bits 31..0 : Pointer to the IRK data structure */
161 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
162 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
163 
164 /* Register: AAR_ADDRPTR */
165 /* Description: Pointer to the resolvable address */
166 
167 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
168 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
169 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
170 
171 /* Register: AAR_SCRATCHPTR */
172 /* Description: Pointer to data area used for temporary storage */
173 
174 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
175 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
176 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
177 
178 
179 /* Peripheral: APPROTECT */
180 /* Description: Access Port Protection */
181 
182 /* Register: APPROTECT_FORCEPROTECT */
183 /* Description: Software force enable APPROTECT mechanism until next reset. This register can only be written once. */
184 
185 /* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */
186 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */
187 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
188 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */
189 
190 /* Register: APPROTECT_DISABLE */
191 /* Description: Software disable APPROTECT mechanism */
192 
193 /* Bits 7..0 : Software disable APPROTECT mechanism */
194 #define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
195 #define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
196 #define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */
197 
198 
199 /* Peripheral: BPROT */
200 /* Description: Block Protect */
201 
202 /* Register: BPROT_CONFIG0 */
203 /* Description: Block protect configuration register 0 */
204 
205 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
206 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
207 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
208 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
209 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
210 
211 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
212 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
213 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
214 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
215 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
216 
217 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
218 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
219 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
220 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
221 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
222 
223 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
224 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
225 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
226 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
227 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
228 
229 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
230 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
231 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
232 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
233 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
234 
235 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
236 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
237 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
238 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
239 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
240 
241 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
242 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
243 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
244 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
245 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
246 
247 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
248 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
249 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
250 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
251 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
252 
253 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
254 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
255 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
256 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
257 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
258 
259 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
260 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
261 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
262 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
263 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
264 
265 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
266 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
267 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
268 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
269 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
270 
271 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
272 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
273 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
274 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
275 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
276 
277 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
278 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
279 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
280 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
281 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
282 
283 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
284 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
285 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
286 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
287 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
288 
289 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
290 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
291 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
292 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
293 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
294 
295 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
296 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
297 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
298 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
299 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
300 
301 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
302 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
303 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
304 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
305 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
306 
307 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
308 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
309 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
310 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
311 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
312 
313 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
314 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
315 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
316 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
317 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
318 
319 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
320 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
321 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
322 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
323 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
324 
325 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
326 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
327 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
328 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
329 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
330 
331 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
332 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
333 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
334 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
335 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
336 
337 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
338 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
339 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
340 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
341 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
342 
343 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
344 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
345 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
346 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
347 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
348 
349 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
350 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
351 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
352 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
353 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
354 
355 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
356 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
357 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
358 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
359 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
360 
361 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
362 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
363 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
364 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
365 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
366 
367 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
368 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
369 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
370 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
371 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
372 
373 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
374 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
375 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
376 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
377 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
378 
379 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
380 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
381 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
382 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
383 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
384 
385 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
386 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
387 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
388 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
389 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
390 
391 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
392 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
393 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
394 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
395 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
396 
397 /* Register: BPROT_CONFIG1 */
398 /* Description: Block protect configuration register 1 */
399 
400 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
401 #define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
402 #define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
403 #define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
404 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
405 
406 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
407 #define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
408 #define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
409 #define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
410 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
411 
412 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
413 #define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
414 #define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
415 #define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
416 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
417 
418 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
419 #define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
420 #define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
421 #define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
422 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
423 
424 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
425 #define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
426 #define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
427 #define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
428 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
429 
430 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
431 #define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
432 #define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
433 #define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
434 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
435 
436 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
437 #define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
438 #define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
439 #define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
440 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
441 
442 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
443 #define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
444 #define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
445 #define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
446 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
447 
448 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
449 #define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
450 #define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
451 #define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
452 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
453 
454 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
455 #define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
456 #define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
457 #define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
458 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
459 
460 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
461 #define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
462 #define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
463 #define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
464 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
465 
466 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
467 #define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
468 #define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
469 #define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
470 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
471 
472 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
473 #define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
474 #define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
475 #define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
476 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
477 
478 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
479 #define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
480 #define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
481 #define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
482 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
483 
484 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
485 #define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
486 #define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
487 #define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
488 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
489 
490 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
491 #define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
492 #define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
493 #define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
494 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
495 
496 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
497 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
498 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
499 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
500 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
501 
502 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
503 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
504 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
505 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
506 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
507 
508 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
509 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
510 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
511 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
512 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
513 
514 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
515 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
516 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
517 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
518 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
519 
520 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
521 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
522 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
523 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
524 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
525 
526 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
527 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
528 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
529 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
530 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
531 
532 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
533 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
534 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
535 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
536 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
537 
538 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
539 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
540 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
541 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
542 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
543 
544 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
545 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
546 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
547 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
548 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
549 
550 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
551 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
552 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
553 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
554 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
555 
556 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
557 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
558 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
559 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
560 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
561 
562 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
563 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
564 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
565 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
566 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
567 
568 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
569 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
570 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
571 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
572 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
573 
574 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
575 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
576 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
577 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
578 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
579 
580 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
581 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
582 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
583 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
584 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
585 
586 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
587 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
588 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
589 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
590 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
591 
592 /* Register: BPROT_DISABLEINDEBUG */
593 /* Description: Disable protection mechanism in debug interface mode */
594 
595 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
596 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
597 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
598 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
599 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
600 
601 /* Register: BPROT_CONFIG2 */
602 /* Description: Block protect configuration register 2 */
603 
604 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
605 #define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
606 #define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
607 #define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
608 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
609 
610 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
611 #define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
612 #define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
613 #define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
614 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
615 
616 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
617 #define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
618 #define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
619 #define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
620 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
621 
622 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
623 #define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
624 #define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
625 #define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
626 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
627 
628 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
629 #define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
630 #define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
631 #define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
632 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
633 
634 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
635 #define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
636 #define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
637 #define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
638 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
639 
640 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
641 #define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
642 #define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
643 #define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
644 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
645 
646 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
647 #define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
648 #define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
649 #define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
650 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
651 
652 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
653 #define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
654 #define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
655 #define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
656 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
657 
658 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
659 #define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
660 #define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
661 #define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
662 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
663 
664 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
665 #define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
666 #define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
667 #define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
668 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
669 
670 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
671 #define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
672 #define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
673 #define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
674 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
675 
676 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
677 #define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
678 #define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
679 #define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
680 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
681 
682 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
683 #define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
684 #define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
685 #define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
686 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
687 
688 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
689 #define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
690 #define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
691 #define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
692 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
693 
694 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
695 #define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
696 #define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
697 #define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
698 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
699 
700 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
701 #define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
702 #define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
703 #define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
704 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
705 
706 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
707 #define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
708 #define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
709 #define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
710 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
711 
712 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
713 #define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
714 #define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
715 #define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
716 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
717 
718 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
719 #define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
720 #define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
721 #define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
722 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
723 
724 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
725 #define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
726 #define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
727 #define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
728 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
729 
730 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
731 #define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
732 #define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
733 #define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
734 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
735 
736 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
737 #define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
738 #define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
739 #define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
740 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
741 
742 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
743 #define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
744 #define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
745 #define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
746 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
747 
748 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
749 #define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
750 #define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
751 #define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
752 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
753 
754 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
755 #define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
756 #define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
757 #define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
758 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
759 
760 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
761 #define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
762 #define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
763 #define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
764 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
765 
766 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
767 #define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
768 #define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
769 #define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
770 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
771 
772 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
773 #define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
774 #define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
775 #define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
776 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
777 
778 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
779 #define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
780 #define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
781 #define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
782 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
783 
784 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
785 #define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
786 #define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
787 #define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
788 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
789 
790 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
791 #define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
792 #define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
793 #define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
794 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
795 
796 /* Register: BPROT_CONFIG3 */
797 /* Description: Block protect configuration register 3 */
798 
799 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
800 #define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
801 #define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
802 #define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
803 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
804 
805 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
806 #define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
807 #define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
808 #define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
809 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
810 
811 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
812 #define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
813 #define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
814 #define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
815 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
816 
817 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
818 #define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
819 #define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
820 #define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
821 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
822 
823 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
824 #define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
825 #define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
826 #define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
827 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
828 
829 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
830 #define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
831 #define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
832 #define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
833 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
834 
835 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
836 #define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
837 #define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
838 #define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
839 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
840 
841 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
842 #define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
843 #define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
844 #define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
845 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
846 
847 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
848 #define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
849 #define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
850 #define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
851 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
852 
853 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
854 #define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
855 #define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
856 #define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
857 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
858 
859 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
860 #define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
861 #define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
862 #define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
863 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
864 
865 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
866 #define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
867 #define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
868 #define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
869 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
870 
871 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
872 #define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
873 #define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
874 #define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
875 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
876 
877 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
878 #define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
879 #define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
880 #define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
881 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
882 
883 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
884 #define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
885 #define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
886 #define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
887 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
888 
889 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
890 #define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
891 #define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
892 #define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
893 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
894 
895 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
896 #define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
897 #define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
898 #define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
899 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
900 
901 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
902 #define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
903 #define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
904 #define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
905 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
906 
907 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
908 #define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
909 #define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
910 #define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
911 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
912 
913 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
914 #define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
915 #define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
916 #define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
917 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
918 
919 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
920 #define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
921 #define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
922 #define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
923 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
924 
925 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
926 #define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
927 #define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
928 #define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
929 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
930 
931 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
932 #define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
933 #define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
934 #define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
935 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
936 
937 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
938 #define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
939 #define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
940 #define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
941 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
942 
943 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
944 #define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
945 #define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
946 #define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
947 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
948 
949 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
950 #define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
951 #define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
952 #define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
953 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
954 
955 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
956 #define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
957 #define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
958 #define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
959 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
960 
961 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
962 #define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
963 #define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
964 #define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
965 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
966 
967 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
968 #define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
969 #define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
970 #define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
971 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
972 
973 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
974 #define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
975 #define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
976 #define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
977 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
978 
979 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
980 #define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
981 #define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
982 #define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
983 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
984 
985 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
986 #define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
987 #define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
988 #define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
989 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
990 
991 
992 /* Peripheral: CCM */
993 /* Description: AES CCM Mode Encryption */
994 
995 /* Register: CCM_TASKS_KSGEN */
996 /* Description: Start generation of key-stream. This operation will stop by itself when completed. */
997 
998 /* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */
999 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
1000 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
1001 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
1002 
1003 /* Register: CCM_TASKS_CRYPT */
1004 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
1005 
1006 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
1007 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
1008 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
1009 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
1010 
1011 /* Register: CCM_TASKS_STOP */
1012 /* Description: Stop encryption/decryption */
1013 
1014 /* Bit 0 : Stop encryption/decryption */
1015 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
1016 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
1017 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
1018 
1019 /* Register: CCM_EVENTS_ENDKSGEN */
1020 /* Description: Key-stream generation complete */
1021 
1022 /* Bit 0 : Key-stream generation complete */
1023 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
1024 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
1025 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
1026 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
1027 
1028 /* Register: CCM_EVENTS_ENDCRYPT */
1029 /* Description: Encrypt/decrypt complete */
1030 
1031 /* Bit 0 : Encrypt/decrypt complete */
1032 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
1033 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
1034 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
1035 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
1036 
1037 /* Register: CCM_EVENTS_ERROR */
1038 /* Description: CCM error event */
1039 
1040 /* Bit 0 : CCM error event */
1041 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
1042 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
1043 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
1044 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
1045 
1046 /* Register: CCM_SHORTS */
1047 /* Description: Shortcuts between local events and tasks */
1048 
1049 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
1050 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
1051 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
1052 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
1053 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
1054 
1055 /* Register: CCM_INTENSET */
1056 /* Description: Enable interrupt */
1057 
1058 /* Bit 2 : Write '1' to enable interrupt for event ERROR */
1059 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
1060 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
1061 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
1062 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
1063 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
1064 
1065 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
1066 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
1067 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
1068 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
1069 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
1070 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
1071 
1072 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
1073 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
1074 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
1075 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
1076 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
1077 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
1078 
1079 /* Register: CCM_INTENCLR */
1080 /* Description: Disable interrupt */
1081 
1082 /* Bit 2 : Write '1' to disable interrupt for event ERROR */
1083 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
1084 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
1085 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
1086 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
1087 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
1088 
1089 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
1090 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
1091 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
1092 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
1093 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
1094 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
1095 
1096 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
1097 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
1098 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
1099 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
1100 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
1101 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
1102 
1103 /* Register: CCM_MICSTATUS */
1104 /* Description: MIC check result */
1105 
1106 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
1107 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
1108 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
1109 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
1110 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
1111 
1112 /* Register: CCM_ENABLE */
1113 /* Description: Enable */
1114 
1115 /* Bits 1..0 : Enable or disable CCM */
1116 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1117 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1118 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1119 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1120 
1121 /* Register: CCM_MODE */
1122 /* Description: Operation mode */
1123 
1124 /* Bit 24 : Packet length configuration */
1125 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
1126 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
1127 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
1128 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
1129 
1130 /* Bit 16 : Data rate that the CCM shall run in synch with */
1131 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
1132 #define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
1133 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
1134 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
1135 
1136 /* Bit 0 : The mode of operation to be used */
1137 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
1138 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
1139 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
1140 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
1141 
1142 /* Register: CCM_CNFPTR */
1143 /* Description: Pointer to data structure holding AES key and NONCE vector */
1144 
1145 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
1146 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
1147 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
1148 
1149 /* Register: CCM_INPTR */
1150 /* Description: Input pointer */
1151 
1152 /* Bits 31..0 : Input pointer */
1153 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
1154 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
1155 
1156 /* Register: CCM_OUTPTR */
1157 /* Description: Output pointer */
1158 
1159 /* Bits 31..0 : Output pointer */
1160 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
1161 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
1162 
1163 /* Register: CCM_SCRATCHPTR */
1164 /* Description: Pointer to data area used for temporary storage */
1165 
1166 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation,
1167         MIC generation and encryption/decryption. */
1168 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
1169 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
1170 
1171 
1172 /* Peripheral: CLOCK */
1173 /* Description: Clock control */
1174 
1175 /* Register: CLOCK_TASKS_HFCLKSTART */
1176 /* Description: Start HFCLK crystal oscillator */
1177 
1178 /* Bit 0 : Start HFCLK crystal oscillator */
1179 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
1180 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
1181 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
1182 
1183 /* Register: CLOCK_TASKS_HFCLKSTOP */
1184 /* Description: Stop HFCLK crystal oscillator */
1185 
1186 /* Bit 0 : Stop HFCLK crystal oscillator */
1187 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
1188 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
1189 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
1190 
1191 /* Register: CLOCK_TASKS_LFCLKSTART */
1192 /* Description: Start LFCLK source */
1193 
1194 /* Bit 0 : Start LFCLK source */
1195 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
1196 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
1197 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
1198 
1199 /* Register: CLOCK_TASKS_LFCLKSTOP */
1200 /* Description: Stop LFCLK source */
1201 
1202 /* Bit 0 : Stop LFCLK source */
1203 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
1204 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
1205 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
1206 
1207 /* Register: CLOCK_TASKS_CAL */
1208 /* Description: Start calibration of LFRC oscillator */
1209 
1210 /* Bit 0 : Start calibration of LFRC oscillator */
1211 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
1212 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
1213 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
1214 
1215 /* Register: CLOCK_TASKS_CTSTART */
1216 /* Description: Start calibration timer */
1217 
1218 /* Bit 0 : Start calibration timer */
1219 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */
1220 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */
1221 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */
1222 
1223 /* Register: CLOCK_TASKS_CTSTOP */
1224 /* Description: Stop calibration timer */
1225 
1226 /* Bit 0 : Stop calibration timer */
1227 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */
1228 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */
1229 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */
1230 
1231 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
1232 /* Description: HFCLK oscillator started */
1233 
1234 /* Bit 0 : HFCLK oscillator started */
1235 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
1236 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
1237 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
1238 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
1239 
1240 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
1241 /* Description: LFCLK started */
1242 
1243 /* Bit 0 : LFCLK started */
1244 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
1245 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
1246 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
1247 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
1248 
1249 /* Register: CLOCK_EVENTS_DONE */
1250 /* Description: Calibration of LFCLK RC oscillator complete event */
1251 
1252 /* Bit 0 : Calibration of LFCLK RC oscillator complete event */
1253 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
1254 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
1255 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
1256 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
1257 
1258 /* Register: CLOCK_EVENTS_CTTO */
1259 /* Description: Calibration timer timeout */
1260 
1261 /* Bit 0 : Calibration timer timeout */
1262 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */
1263 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */
1264 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */
1265 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */
1266 
1267 /* Register: CLOCK_INTENSET */
1268 /* Description: Enable interrupt */
1269 
1270 /* Bit 4 : Write '1' to enable interrupt for event CTTO */
1271 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
1272 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
1273 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
1274 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
1275 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
1276 
1277 /* Bit 3 : Write '1' to enable interrupt for event DONE */
1278 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
1279 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
1280 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
1281 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
1282 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
1283 
1284 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
1285 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1286 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1287 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1288 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1289 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
1290 
1291 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
1292 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1293 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1294 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1295 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1296 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
1297 
1298 /* Register: CLOCK_INTENCLR */
1299 /* Description: Disable interrupt */
1300 
1301 /* Bit 4 : Write '1' to disable interrupt for event CTTO */
1302 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
1303 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
1304 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
1305 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
1306 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
1307 
1308 /* Bit 3 : Write '1' to disable interrupt for event DONE */
1309 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
1310 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
1311 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
1312 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
1313 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
1314 
1315 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
1316 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1317 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1318 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1319 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1320 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
1321 
1322 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
1323 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1324 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1325 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1326 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1327 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
1328 
1329 /* Register: CLOCK_HFCLKRUN */
1330 /* Description: Status indicating that HFCLKSTART task has been triggered */
1331 
1332 /* Bit 0 : HFCLKSTART task triggered or not */
1333 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1334 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1335 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1336 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1337 
1338 /* Register: CLOCK_HFCLKSTAT */
1339 /* Description: HFCLK status */
1340 
1341 /* Bit 16 : HFCLK state */
1342 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1343 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1344 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
1345 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
1346 
1347 /* Bit 0 : Source of HFCLK */
1348 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1349 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1350 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
1351 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
1352 
1353 /* Register: CLOCK_LFCLKRUN */
1354 /* Description: Status indicating that LFCLKSTART task has been triggered */
1355 
1356 /* Bit 0 : LFCLKSTART task triggered or not */
1357 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1358 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1359 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1360 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1361 
1362 /* Register: CLOCK_LFCLKSTAT */
1363 /* Description: LFCLK status */
1364 
1365 /* Bit 16 : LFCLK state */
1366 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1367 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1368 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
1369 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
1370 
1371 /* Bits 1..0 : Source of LFCLK */
1372 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1373 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1374 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1375 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1376 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1377 
1378 /* Register: CLOCK_LFCLKSRCCOPY */
1379 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
1380 
1381 /* Bits 1..0 : Clock source */
1382 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
1383 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
1384 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1385 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1386 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1387 
1388 /* Register: CLOCK_LFCLKSRC */
1389 /* Description: Clock source for the LFCLK */
1390 
1391 /* Bit 17 : Enable or disable external source for LFCLK */
1392 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
1393 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
1394 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
1395 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
1396 
1397 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
1398 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
1399 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
1400 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
1401 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
1402 
1403 /* Bits 1..0 : Clock source */
1404 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
1405 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
1406 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1407 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1408 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1409 
1410 /* Register: CLOCK_CTIV */
1411 /* Description: Calibration timer interval */
1412 
1413 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
1414 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
1415 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
1416 
1417 /* Register: CLOCK_TRACECONFIG */
1418 /* Description: Clocking options for the Trace Port debug interface */
1419 
1420 /* Bits 17..16 : Pin multiplexing of trace signals. */
1421 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
1422 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
1423 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
1424 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
1425 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
1426 
1427 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
1428 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
1429 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
1430 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
1431 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
1432 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
1433 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
1434 
1435 
1436 /* Peripheral: COMP */
1437 /* Description: Comparator */
1438 
1439 /* Register: COMP_TASKS_START */
1440 /* Description: Start comparator */
1441 
1442 /* Bit 0 : Start comparator */
1443 #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
1444 #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
1445 #define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
1446 
1447 /* Register: COMP_TASKS_STOP */
1448 /* Description: Stop comparator */
1449 
1450 /* Bit 0 : Stop comparator */
1451 #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
1452 #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
1453 #define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
1454 
1455 /* Register: COMP_TASKS_SAMPLE */
1456 /* Description: Sample comparator value */
1457 
1458 /* Bit 0 : Sample comparator value */
1459 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
1460 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
1461 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
1462 
1463 /* Register: COMP_EVENTS_READY */
1464 /* Description: COMP is ready and output is valid */
1465 
1466 /* Bit 0 : COMP is ready and output is valid */
1467 #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
1468 #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
1469 #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
1470 #define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
1471 
1472 /* Register: COMP_EVENTS_DOWN */
1473 /* Description: Downward crossing */
1474 
1475 /* Bit 0 : Downward crossing */
1476 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
1477 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
1478 #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
1479 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
1480 
1481 /* Register: COMP_EVENTS_UP */
1482 /* Description: Upward crossing */
1483 
1484 /* Bit 0 : Upward crossing */
1485 #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
1486 #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
1487 #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
1488 #define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
1489 
1490 /* Register: COMP_EVENTS_CROSS */
1491 /* Description: Downward or upward crossing */
1492 
1493 /* Bit 0 : Downward or upward crossing */
1494 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
1495 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
1496 #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
1497 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
1498 
1499 /* Register: COMP_SHORTS */
1500 /* Description: Shortcuts between local events and tasks */
1501 
1502 /* Bit 4 : Shortcut between event CROSS and task STOP */
1503 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
1504 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
1505 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
1506 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
1507 
1508 /* Bit 3 : Shortcut between event UP and task STOP */
1509 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
1510 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
1511 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
1512 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
1513 
1514 /* Bit 2 : Shortcut between event DOWN and task STOP */
1515 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
1516 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
1517 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
1518 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
1519 
1520 /* Bit 1 : Shortcut between event READY and task STOP */
1521 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
1522 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
1523 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
1524 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
1525 
1526 /* Bit 0 : Shortcut between event READY and task SAMPLE */
1527 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
1528 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
1529 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
1530 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
1531 
1532 /* Register: COMP_INTEN */
1533 /* Description: Enable or disable interrupt */
1534 
1535 /* Bit 3 : Enable or disable interrupt for event CROSS */
1536 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1537 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
1538 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
1539 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
1540 
1541 /* Bit 2 : Enable or disable interrupt for event UP */
1542 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
1543 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
1544 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
1545 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
1546 
1547 /* Bit 1 : Enable or disable interrupt for event DOWN */
1548 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1549 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
1550 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
1551 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
1552 
1553 /* Bit 0 : Enable or disable interrupt for event READY */
1554 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
1555 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
1556 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
1557 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
1558 
1559 /* Register: COMP_INTENSET */
1560 /* Description: Enable interrupt */
1561 
1562 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
1563 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1564 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
1565 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1566 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1567 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
1568 
1569 /* Bit 2 : Write '1' to enable interrupt for event UP */
1570 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
1571 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
1572 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1573 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1574 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
1575 
1576 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
1577 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1578 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
1579 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1580 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1581 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
1582 
1583 /* Bit 0 : Write '1' to enable interrupt for event READY */
1584 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
1585 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
1586 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1587 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1588 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
1589 
1590 /* Register: COMP_INTENCLR */
1591 /* Description: Disable interrupt */
1592 
1593 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
1594 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1595 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
1596 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1597 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1598 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1599 
1600 /* Bit 2 : Write '1' to disable interrupt for event UP */
1601 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
1602 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
1603 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1604 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1605 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1606 
1607 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
1608 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1609 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
1610 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1611 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1612 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1613 
1614 /* Bit 0 : Write '1' to disable interrupt for event READY */
1615 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
1616 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
1617 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1618 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1619 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1620 
1621 /* Register: COMP_RESULT */
1622 /* Description: Compare result */
1623 
1624 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
1625 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
1626 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
1627 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
1628 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
1629 
1630 /* Register: COMP_ENABLE */
1631 /* Description: COMP enable */
1632 
1633 /* Bits 1..0 : Enable or disable COMP */
1634 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1635 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1636 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1637 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1638 
1639 /* Register: COMP_PSEL */
1640 /* Description: Pin select */
1641 
1642 /* Bits 2..0 : Analog pin select */
1643 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
1644 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
1645 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
1646 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
1647 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
1648 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
1649 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
1650 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
1651 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
1652 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
1653 
1654 /* Register: COMP_REFSEL */
1655 /* Description: Reference source select for single-ended mode */
1656 
1657 /* Bits 2..0 : Reference select */
1658 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
1659 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
1660 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
1661 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
1662 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
1663 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
1664 #define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
1665 
1666 /* Register: COMP_EXTREFSEL */
1667 /* Description: External reference select */
1668 
1669 /* Bits 2..0 : External analog reference select */
1670 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
1671 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
1672 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
1673 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
1674 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
1675 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
1676 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */
1677 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */
1678 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */
1679 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */
1680 
1681 /* Register: COMP_TH */
1682 /* Description: Threshold configuration for hysteresis unit */
1683 
1684 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
1685 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
1686 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
1687 
1688 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1689 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
1690 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
1691 
1692 /* Register: COMP_MODE */
1693 /* Description: Mode configuration */
1694 
1695 /* Bit 8 : Main operation modes */
1696 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
1697 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
1698 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1699 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1700 
1701 /* Bits 1..0 : Speed and power modes */
1702 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
1703 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
1704 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1705 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1706 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1707 
1708 /* Register: COMP_HYST */
1709 /* Description: Comparator hysteresis enable */
1710 
1711 /* Bit 0 : Comparator hysteresis */
1712 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
1713 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
1714 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1715 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1716 
1717 /* Register: COMP_ISOURCE */
1718 /* Description: Current source select on analog input */
1719 
1720 /* Bits 1..0 : Comparator hysteresis */
1721 #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
1722 #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
1723 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
1724 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
1725 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
1726 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
1727 
1728 
1729 /* Peripheral: ECB */
1730 /* Description: AES ECB Mode Encryption */
1731 
1732 /* Register: ECB_TASKS_STARTECB */
1733 /* Description: Start ECB block encrypt */
1734 
1735 /* Bit 0 : Start ECB block encrypt */
1736 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
1737 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
1738 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
1739 
1740 /* Register: ECB_TASKS_STOPECB */
1741 /* Description: Abort a possible executing ECB operation */
1742 
1743 /* Bit 0 : Abort a possible executing ECB operation */
1744 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
1745 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
1746 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
1747 
1748 /* Register: ECB_EVENTS_ENDECB */
1749 /* Description: ECB block encrypt complete */
1750 
1751 /* Bit 0 : ECB block encrypt complete */
1752 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
1753 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
1754 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
1755 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
1756 
1757 /* Register: ECB_EVENTS_ERRORECB */
1758 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
1759 
1760 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
1761 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
1762 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
1763 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
1764 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
1765 
1766 /* Register: ECB_INTENSET */
1767 /* Description: Enable interrupt */
1768 
1769 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
1770 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1771 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1772 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1773 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1774 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1775 
1776 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */
1777 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1778 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1779 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1780 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1781 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1782 
1783 /* Register: ECB_INTENCLR */
1784 /* Description: Disable interrupt */
1785 
1786 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
1787 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1788 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1789 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1790 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1791 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1792 
1793 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */
1794 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1795 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1796 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1797 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1798 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1799 
1800 /* Register: ECB_ECBDATAPTR */
1801 /* Description: ECB block encrypt memory pointers */
1802 
1803 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1804 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
1805 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
1806 
1807 
1808 /* Peripheral: EGU */
1809 /* Description: Event Generator Unit 0 */
1810 
1811 /* Register: EGU_TASKS_TRIGGER */
1812 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
1813 
1814 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
1815 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
1816 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
1817 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
1818 
1819 /* Register: EGU_EVENTS_TRIGGERED */
1820 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
1821 
1822 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
1823 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
1824 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
1825 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
1826 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
1827 
1828 /* Register: EGU_INTEN */
1829 /* Description: Enable or disable interrupt */
1830 
1831 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
1832 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1833 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1834 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1835 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1836 
1837 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
1838 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1839 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1840 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1841 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1842 
1843 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
1844 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1845 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1846 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1847 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1848 
1849 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
1850 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1851 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1852 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1853 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1854 
1855 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
1856 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1857 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1858 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1859 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1860 
1861 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
1862 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1863 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1864 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1865 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1866 
1867 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
1868 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1869 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1870 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1871 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1872 
1873 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
1874 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1875 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1876 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1877 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1878 
1879 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
1880 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1881 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1882 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1883 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1884 
1885 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
1886 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1887 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1888 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1889 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1890 
1891 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
1892 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1893 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1894 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1895 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1896 
1897 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
1898 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1899 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1900 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1901 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1902 
1903 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
1904 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1905 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1906 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1907 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1908 
1909 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
1910 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1911 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1912 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1913 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1914 
1915 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
1916 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1917 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1918 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1919 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1920 
1921 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
1922 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1923 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1924 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1925 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1926 
1927 /* Register: EGU_INTENSET */
1928 /* Description: Enable interrupt */
1929 
1930 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
1931 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1932 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1933 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1934 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1935 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1936 
1937 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
1938 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1939 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1940 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1941 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1942 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1943 
1944 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
1945 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1946 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1947 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1948 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1949 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1950 
1951 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
1952 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1953 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1954 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1955 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1956 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1957 
1958 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
1959 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1960 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1961 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1962 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1963 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1964 
1965 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
1966 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1967 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1968 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1969 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1970 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1971 
1972 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
1973 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1974 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1975 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1976 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1977 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1978 
1979 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
1980 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1981 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1982 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1983 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1984 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1985 
1986 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
1987 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1988 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1989 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1990 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1991 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1992 
1993 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
1994 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1995 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1996 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1997 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1998 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1999 
2000 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
2001 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
2002 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
2003 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
2004 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
2005 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
2006 
2007 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
2008 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
2009 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
2010 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
2011 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
2012 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
2013 
2014 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
2015 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
2016 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
2017 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
2018 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
2019 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
2020 
2021 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
2022 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
2023 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
2024 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
2025 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
2026 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
2027 
2028 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
2029 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
2030 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
2031 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
2032 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
2033 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
2034 
2035 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
2036 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
2037 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
2038 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
2039 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
2040 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
2041 
2042 /* Register: EGU_INTENCLR */
2043 /* Description: Disable interrupt */
2044 
2045 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
2046 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
2047 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
2048 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
2049 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
2050 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
2051 
2052 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
2053 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
2054 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
2055 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
2056 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
2057 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
2058 
2059 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
2060 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
2061 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
2062 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
2063 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
2064 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
2065 
2066 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
2067 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
2068 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
2069 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
2070 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
2071 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
2072 
2073 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
2074 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
2075 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
2076 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
2077 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
2078 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
2079 
2080 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
2081 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
2082 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
2083 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
2084 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
2085 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
2086 
2087 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
2088 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
2089 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
2090 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
2091 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
2092 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
2093 
2094 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
2095 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
2096 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
2097 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
2098 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
2099 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
2100 
2101 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
2102 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
2103 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
2104 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
2105 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
2106 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
2107 
2108 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
2109 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
2110 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
2111 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
2112 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
2113 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
2114 
2115 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
2116 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
2117 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
2118 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
2119 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
2120 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
2121 
2122 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
2123 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
2124 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
2125 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
2126 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
2127 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
2128 
2129 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
2130 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
2131 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
2132 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
2133 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
2134 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
2135 
2136 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
2137 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
2138 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
2139 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
2140 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
2141 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
2142 
2143 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
2144 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
2145 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
2146 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
2147 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
2148 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
2149 
2150 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
2151 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
2152 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
2153 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
2154 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
2155 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
2156 
2157 
2158 /* Peripheral: FICR */
2159 /* Description: Factory Information Configuration Registers */
2160 
2161 /* Register: FICR_CODEPAGESIZE */
2162 /* Description: Code memory page size */
2163 
2164 /* Bits 31..0 : Code memory page size */
2165 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
2166 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
2167 
2168 /* Register: FICR_CODESIZE */
2169 /* Description: Code memory size */
2170 
2171 /* Bits 31..0 : Code memory size in number of pages */
2172 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
2173 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
2174 
2175 /* Register: FICR_DEVICEID */
2176 /* Description: Description collection: Device identifier */
2177 
2178 /* Bits 31..0 : 64 bit unique device identifier */
2179 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
2180 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
2181 
2182 /* Register: FICR_ER */
2183 /* Description: Description collection: Encryption Root, word n */
2184 
2185 /* Bits 31..0 : Encryption Root, word n */
2186 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
2187 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
2188 
2189 /* Register: FICR_IR */
2190 /* Description: Description collection: Identity Root, word n */
2191 
2192 /* Bits 31..0 : Identity Root, word n */
2193 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
2194 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
2195 
2196 /* Register: FICR_DEVICEADDRTYPE */
2197 /* Description: Device address type */
2198 
2199 /* Bit 0 : Device address type */
2200 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
2201 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
2202 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
2203 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
2204 
2205 /* Register: FICR_DEVICEADDR */
2206 /* Description: Description collection: Device address n */
2207 
2208 /* Bits 31..0 : 48 bit device address */
2209 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
2210 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
2211 
2212 /* Register: FICR_INFO_PART */
2213 /* Description: Part code */
2214 
2215 /* Bits 31..0 : Part code */
2216 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
2217 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
2218 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
2219 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
2220 
2221 /* Register: FICR_INFO_VARIANT */
2222 /* Description: Part Variant, Hardware version and Production configuration */
2223 
2224 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
2225 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
2226 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
2227 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
2228 #define FICR_INFO_VARIANT_VARIANT_AAAC (0x41414143UL) /*!< AAAC */
2229 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
2230 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
2231 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
2232 #define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */
2233 #define FICR_INFO_VARIANT_VARIANT_AAG0 (0x41414730UL) /*!< AAG0 */
2234 #define FICR_INFO_VARIANT_VARIANT_AAGB (0x41414742UL) /*!< AAGB */
2235 #define FICR_INFO_VARIANT_VARIANT_ABB0 (0x41424230UL) /*!< ABB0 */
2236 #define FICR_INFO_VARIANT_VARIANT_ABE0 (0x41424530UL) /*!< ABE0 */
2237 #define FICR_INFO_VARIANT_VARIANT_ABG0 (0x41424730UL) /*!< ABG0 */
2238 #define FICR_INFO_VARIANT_VARIANT_ABGB (0x41424742UL) /*!< ABGB */
2239 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
2240 
2241 /* Register: FICR_INFO_PACKAGE */
2242 /* Description: Package option */
2243 
2244 /* Bits 31..0 : Package option */
2245 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
2246 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
2247 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
2248 #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
2249 #define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */
2250 #define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */
2251 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
2252 
2253 /* Register: FICR_INFO_RAM */
2254 /* Description: RAM variant */
2255 
2256 /* Bits 31..0 : RAM variant */
2257 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
2258 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
2259 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
2260 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
2261 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
2262 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
2263 
2264 /* Register: FICR_INFO_FLASH */
2265 /* Description: Flash variant */
2266 
2267 /* Bits 31..0 : Flash variant */
2268 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
2269 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
2270 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
2271 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
2272 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
2273 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
2274 
2275 /* Register: FICR_TEMP_A0 */
2276 /* Description: Slope definition A0. */
2277 
2278 /* Bits 11..0 : A (slope definition) register. */
2279 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
2280 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
2281 
2282 /* Register: FICR_TEMP_A1 */
2283 /* Description: Slope definition A1. */
2284 
2285 /* Bits 11..0 : A (slope definition) register. */
2286 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
2287 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
2288 
2289 /* Register: FICR_TEMP_A2 */
2290 /* Description: Slope definition A2. */
2291 
2292 /* Bits 11..0 : A (slope definition) register. */
2293 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
2294 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
2295 
2296 /* Register: FICR_TEMP_A3 */
2297 /* Description: Slope definition A3. */
2298 
2299 /* Bits 11..0 : A (slope definition) register. */
2300 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
2301 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
2302 
2303 /* Register: FICR_TEMP_A4 */
2304 /* Description: Slope definition A4. */
2305 
2306 /* Bits 11..0 : A (slope definition) register. */
2307 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
2308 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
2309 
2310 /* Register: FICR_TEMP_A5 */
2311 /* Description: Slope definition A5. */
2312 
2313 /* Bits 11..0 : A (slope definition) register. */
2314 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
2315 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
2316 
2317 /* Register: FICR_TEMP_B0 */
2318 /* Description: y-intercept B0. */
2319 
2320 /* Bits 13..0 : B (y-intercept) */
2321 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
2322 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
2323 
2324 /* Register: FICR_TEMP_B1 */
2325 /* Description: y-intercept B1. */
2326 
2327 /* Bits 13..0 : B (y-intercept) */
2328 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
2329 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
2330 
2331 /* Register: FICR_TEMP_B2 */
2332 /* Description: y-intercept B2. */
2333 
2334 /* Bits 13..0 : B (y-intercept) */
2335 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
2336 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
2337 
2338 /* Register: FICR_TEMP_B3 */
2339 /* Description: y-intercept B3. */
2340 
2341 /* Bits 13..0 : B (y-intercept) */
2342 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
2343 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
2344 
2345 /* Register: FICR_TEMP_B4 */
2346 /* Description: y-intercept B4. */
2347 
2348 /* Bits 13..0 : B (y-intercept) */
2349 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
2350 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
2351 
2352 /* Register: FICR_TEMP_B5 */
2353 /* Description: y-intercept B5. */
2354 
2355 /* Bits 13..0 : B (y-intercept) */
2356 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
2357 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
2358 
2359 /* Register: FICR_TEMP_T0 */
2360 /* Description: Segment end T0. */
2361 
2362 /* Bits 7..0 : T (segment end)register. */
2363 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
2364 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
2365 
2366 /* Register: FICR_TEMP_T1 */
2367 /* Description: Segment end T1. */
2368 
2369 /* Bits 7..0 : T (segment end)register. */
2370 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
2371 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
2372 
2373 /* Register: FICR_TEMP_T2 */
2374 /* Description: Segment end T2. */
2375 
2376 /* Bits 7..0 : T (segment end)register. */
2377 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
2378 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
2379 
2380 /* Register: FICR_TEMP_T3 */
2381 /* Description: Segment end T3. */
2382 
2383 /* Bits 7..0 : T (segment end)register. */
2384 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
2385 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
2386 
2387 /* Register: FICR_TEMP_T4 */
2388 /* Description: Segment end T4. */
2389 
2390 /* Bits 7..0 : T (segment end)register. */
2391 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
2392 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
2393 
2394 /* Register: FICR_NFC_TAGHEADER0 */
2395 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2396 
2397 /* Bits 31..24 : Unique identifier byte 3 */
2398 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
2399 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
2400 
2401 /* Bits 23..16 : Unique identifier byte 2 */
2402 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
2403 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
2404 
2405 /* Bits 15..8 : Unique identifier byte 1 */
2406 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
2407 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
2408 
2409 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
2410 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
2411 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
2412 
2413 /* Register: FICR_NFC_TAGHEADER1 */
2414 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2415 
2416 /* Bits 31..24 : Unique identifier byte 7 */
2417 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
2418 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
2419 
2420 /* Bits 23..16 : Unique identifier byte 6 */
2421 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
2422 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
2423 
2424 /* Bits 15..8 : Unique identifier byte 5 */
2425 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
2426 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
2427 
2428 /* Bits 7..0 : Unique identifier byte 4 */
2429 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
2430 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
2431 
2432 /* Register: FICR_NFC_TAGHEADER2 */
2433 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2434 
2435 /* Bits 31..24 : Unique identifier byte 11 */
2436 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
2437 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
2438 
2439 /* Bits 23..16 : Unique identifier byte 10 */
2440 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
2441 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
2442 
2443 /* Bits 15..8 : Unique identifier byte 9 */
2444 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
2445 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
2446 
2447 /* Bits 7..0 : Unique identifier byte 8 */
2448 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
2449 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
2450 
2451 /* Register: FICR_NFC_TAGHEADER3 */
2452 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2453 
2454 /* Bits 31..24 : Unique identifier byte 15 */
2455 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
2456 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
2457 
2458 /* Bits 23..16 : Unique identifier byte 14 */
2459 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
2460 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
2461 
2462 /* Bits 15..8 : Unique identifier byte 13 */
2463 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
2464 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
2465 
2466 /* Bits 7..0 : Unique identifier byte 12 */
2467 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
2468 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
2469 
2470 
2471 /* Peripheral: GPIOTE */
2472 /* Description: GPIO Tasks and Events */
2473 
2474 /* Register: GPIOTE_TASKS_OUT */
2475 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
2476 
2477 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
2478 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
2479 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
2480 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
2481 
2482 /* Register: GPIOTE_TASKS_SET */
2483 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
2484 
2485 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
2486 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
2487 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
2488 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
2489 
2490 /* Register: GPIOTE_TASKS_CLR */
2491 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
2492 
2493 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
2494 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
2495 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
2496 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
2497 
2498 /* Register: GPIOTE_EVENTS_IN */
2499 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
2500 
2501 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
2502 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
2503 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
2504 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
2505 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
2506 
2507 /* Register: GPIOTE_EVENTS_PORT */
2508 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
2509 
2510 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
2511 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
2512 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
2513 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
2514 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
2515 
2516 /* Register: GPIOTE_INTENSET */
2517 /* Description: Enable interrupt */
2518 
2519 /* Bit 31 : Write '1' to enable interrupt for event PORT */
2520 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
2521 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
2522 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
2523 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
2524 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
2525 
2526 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
2527 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
2528 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
2529 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
2530 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
2531 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
2532 
2533 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
2534 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
2535 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
2536 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
2537 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
2538 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
2539 
2540 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
2541 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
2542 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
2543 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
2544 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
2545 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
2546 
2547 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
2548 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
2549 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
2550 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
2551 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
2552 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
2553 
2554 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
2555 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
2556 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
2557 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
2558 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
2559 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
2560 
2561 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
2562 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
2563 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
2564 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
2565 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
2566 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
2567 
2568 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
2569 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
2570 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
2571 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
2572 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
2573 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
2574 
2575 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
2576 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
2577 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
2578 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
2579 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
2580 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
2581 
2582 /* Register: GPIOTE_INTENCLR */
2583 /* Description: Disable interrupt */
2584 
2585 /* Bit 31 : Write '1' to disable interrupt for event PORT */
2586 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
2587 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
2588 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
2589 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2590 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
2591 
2592 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
2593 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
2594 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
2595 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
2596 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
2597 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
2598 
2599 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
2600 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
2601 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
2602 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
2603 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
2604 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
2605 
2606 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
2607 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
2608 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
2609 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
2610 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
2611 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
2612 
2613 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
2614 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
2615 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
2616 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
2617 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2618 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
2619 
2620 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
2621 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
2622 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
2623 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2624 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2625 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
2626 
2627 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
2628 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2629 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
2630 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2631 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2632 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
2633 
2634 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
2635 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
2636 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
2637 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2638 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2639 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
2640 
2641 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
2642 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
2643 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
2644 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2645 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2646 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
2647 
2648 /* Register: GPIOTE_CONFIG */
2649 /* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
2650 
2651 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
2652 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
2653 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
2654 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
2655 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
2656 
2657 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
2658 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
2659 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
2660 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
2661 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
2662 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
2663 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
2664 
2665 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
2666 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
2667 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
2668 
2669 /* Bits 1..0 : Mode */
2670 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
2671 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
2672 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
2673 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
2674 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
2675 
2676 
2677 /* Peripheral: I2S */
2678 /* Description: Inter-IC Sound */
2679 
2680 /* Register: I2S_TASKS_START */
2681 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
2682 
2683 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
2684 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
2685 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
2686 #define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
2687 
2688 /* Register: I2S_TASKS_STOP */
2689 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. */
2690 
2691 /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. */
2692 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
2693 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
2694 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
2695 
2696 /* Register: I2S_EVENTS_RXPTRUPD */
2697 /* Description: The RXD.PTR register has been copied to internal double-buffers.
2698       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
2699 
2700 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
2701       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
2702 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
2703 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
2704 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
2705 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
2706 
2707 /* Register: I2S_EVENTS_STOPPED */
2708 /* Description: I2S transfer stopped. */
2709 
2710 /* Bit 0 : I2S transfer stopped. */
2711 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
2712 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
2713 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
2714 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
2715 
2716 /* Register: I2S_EVENTS_TXPTRUPD */
2717 /* Description: The TDX.PTR register has been copied to internal double-buffers.
2718       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
2719 
2720 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
2721       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
2722 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
2723 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
2724 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
2725 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
2726 
2727 /* Register: I2S_INTEN */
2728 /* Description: Enable or disable interrupt */
2729 
2730 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
2731 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2732 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2733 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
2734 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
2735 
2736 /* Bit 2 : Enable or disable interrupt for event STOPPED */
2737 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2738 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2739 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
2740 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
2741 
2742 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
2743 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2744 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2745 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
2746 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
2747 
2748 /* Register: I2S_INTENSET */
2749 /* Description: Enable interrupt */
2750 
2751 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
2752 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2753 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2754 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2755 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2756 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
2757 
2758 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
2759 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2760 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2761 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2762 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2763 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
2764 
2765 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
2766 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2767 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2768 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2769 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2770 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
2771 
2772 /* Register: I2S_INTENCLR */
2773 /* Description: Disable interrupt */
2774 
2775 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
2776 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2777 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2778 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2779 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2780 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
2781 
2782 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
2783 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2784 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2785 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2786 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2787 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
2788 
2789 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
2790 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2791 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2792 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2793 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2794 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
2795 
2796 /* Register: I2S_ENABLE */
2797 /* Description: Enable I2S module. */
2798 
2799 /* Bit 0 : Enable I2S module. */
2800 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2801 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2802 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2803 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2804 
2805 /* Register: I2S_CONFIG_MODE */
2806 /* Description: I2S mode. */
2807 
2808 /* Bit 0 : I2S mode. */
2809 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
2810 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
2811 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
2812 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
2813 
2814 /* Register: I2S_CONFIG_RXEN */
2815 /* Description: Reception (RX) enable. */
2816 
2817 /* Bit 0 : Reception (RX) enable. */
2818 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
2819 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
2820 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
2821 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
2822 
2823 /* Register: I2S_CONFIG_TXEN */
2824 /* Description: Transmission (TX) enable. */
2825 
2826 /* Bit 0 : Transmission (TX) enable. */
2827 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
2828 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
2829 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
2830 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2831 
2832 /* Register: I2S_CONFIG_MCKEN */
2833 /* Description: Master clock generator enable. */
2834 
2835 /* Bit 0 : Master clock generator enable. */
2836 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
2837 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
2838 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
2839 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
2840 
2841 /* Register: I2S_CONFIG_MCKFREQ */
2842 /* Description: Master clock generator frequency. */
2843 
2844 /* Bits 31..0 : Master clock generator frequency. */
2845 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
2846 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
2847 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
2848 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
2849 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
2850 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
2851 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
2852 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
2853 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
2854 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
2855 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
2856 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
2857 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
2858 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
2859 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
2860 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
2861 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
2862 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
2863 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
2864 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
2865 
2866 /* Register: I2S_CONFIG_RATIO */
2867 /* Description: MCK / LRCK ratio. */
2868 
2869 /* Bits 3..0 : MCK / LRCK ratio. */
2870 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
2871 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
2872 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
2873 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
2874 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
2875 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
2876 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
2877 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
2878 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
2879 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
2880 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
2881 
2882 /* Register: I2S_CONFIG_SWIDTH */
2883 /* Description: Sample width. */
2884 
2885 /* Bits 1..0 : Sample width. */
2886 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
2887 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
2888 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
2889 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
2890 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
2891 
2892 /* Register: I2S_CONFIG_ALIGN */
2893 /* Description: Alignment of sample within a frame. */
2894 
2895 /* Bit 0 : Alignment of sample within a frame. */
2896 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
2897 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
2898 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
2899 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2900 
2901 /* Register: I2S_CONFIG_FORMAT */
2902 /* Description: Frame format. */
2903 
2904 /* Bit 0 : Frame format. */
2905 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
2906 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
2907 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
2908 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2909 
2910 /* Register: I2S_CONFIG_CHANNELS */
2911 /* Description: Enable channels. */
2912 
2913 /* Bits 1..0 : Enable channels. */
2914 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
2915 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
2916 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
2917 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
2918 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2919 
2920 /* Register: I2S_RXD_PTR */
2921 /* Description: Receive buffer RAM start address. */
2922 
2923 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
2924 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2925 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2926 
2927 /* Register: I2S_TXD_PTR */
2928 /* Description: Transmit buffer RAM start address. */
2929 
2930 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
2931 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2932 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2933 
2934 /* Register: I2S_RXTXD_MAXCNT */
2935 /* Description: Size of RXD and TXD buffers. */
2936 
2937 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
2938 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
2939 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
2940 
2941 /* Register: I2S_PSEL_MCK */
2942 /* Description: Pin select for MCK signal. */
2943 
2944 /* Bit 31 : Connection */
2945 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2946 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2947 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
2948 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2949 
2950 /* Bits 4..0 : Pin number */
2951 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2952 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
2953 
2954 /* Register: I2S_PSEL_SCK */
2955 /* Description: Pin select for SCK signal. */
2956 
2957 /* Bit 31 : Connection */
2958 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2959 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2960 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
2961 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2962 
2963 /* Bits 4..0 : Pin number */
2964 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2965 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
2966 
2967 /* Register: I2S_PSEL_LRCK */
2968 /* Description: Pin select for LRCK signal. */
2969 
2970 /* Bit 31 : Connection */
2971 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2972 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2973 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
2974 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2975 
2976 /* Bits 4..0 : Pin number */
2977 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2978 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
2979 
2980 /* Register: I2S_PSEL_SDIN */
2981 /* Description: Pin select for SDIN signal. */
2982 
2983 /* Bit 31 : Connection */
2984 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2985 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2986 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
2987 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2988 
2989 /* Bits 4..0 : Pin number */
2990 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
2991 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
2992 
2993 /* Register: I2S_PSEL_SDOUT */
2994 /* Description: Pin select for SDOUT signal. */
2995 
2996 /* Bit 31 : Connection */
2997 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2998 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2999 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
3000 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
3001 
3002 /* Bits 4..0 : Pin number */
3003 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
3004 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
3005 
3006 
3007 /* Peripheral: LPCOMP */
3008 /* Description: Low Power Comparator */
3009 
3010 /* Register: LPCOMP_TASKS_START */
3011 /* Description: Start comparator */
3012 
3013 /* Bit 0 : Start comparator */
3014 #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
3015 #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
3016 #define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
3017 
3018 /* Register: LPCOMP_TASKS_STOP */
3019 /* Description: Stop comparator */
3020 
3021 /* Bit 0 : Stop comparator */
3022 #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
3023 #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
3024 #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
3025 
3026 /* Register: LPCOMP_TASKS_SAMPLE */
3027 /* Description: Sample comparator value */
3028 
3029 /* Bit 0 : Sample comparator value */
3030 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
3031 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
3032 #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
3033 
3034 /* Register: LPCOMP_EVENTS_READY */
3035 /* Description: LPCOMP is ready and output is valid */
3036 
3037 /* Bit 0 : LPCOMP is ready and output is valid */
3038 #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
3039 #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
3040 #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
3041 #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
3042 
3043 /* Register: LPCOMP_EVENTS_DOWN */
3044 /* Description: Downward crossing */
3045 
3046 /* Bit 0 : Downward crossing */
3047 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
3048 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
3049 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
3050 #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
3051 
3052 /* Register: LPCOMP_EVENTS_UP */
3053 /* Description: Upward crossing */
3054 
3055 /* Bit 0 : Upward crossing */
3056 #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
3057 #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
3058 #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
3059 #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
3060 
3061 /* Register: LPCOMP_EVENTS_CROSS */
3062 /* Description: Downward or upward crossing */
3063 
3064 /* Bit 0 : Downward or upward crossing */
3065 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
3066 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
3067 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
3068 #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
3069 
3070 /* Register: LPCOMP_SHORTS */
3071 /* Description: Shortcuts between local events and tasks */
3072 
3073 /* Bit 4 : Shortcut between event CROSS and task STOP */
3074 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
3075 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
3076 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
3077 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
3078 
3079 /* Bit 3 : Shortcut between event UP and task STOP */
3080 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
3081 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
3082 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
3083 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
3084 
3085 /* Bit 2 : Shortcut between event DOWN and task STOP */
3086 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
3087 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
3088 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
3089 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
3090 
3091 /* Bit 1 : Shortcut between event READY and task STOP */
3092 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
3093 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
3094 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
3095 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
3096 
3097 /* Bit 0 : Shortcut between event READY and task SAMPLE */
3098 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
3099 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
3100 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
3101 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
3102 
3103 /* Register: LPCOMP_INTENSET */
3104 /* Description: Enable interrupt */
3105 
3106 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
3107 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
3108 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
3109 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
3110 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
3111 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
3112 
3113 /* Bit 2 : Write '1' to enable interrupt for event UP */
3114 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
3115 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
3116 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
3117 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
3118 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
3119 
3120 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
3121 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
3122 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
3123 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
3124 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
3125 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
3126 
3127 /* Bit 0 : Write '1' to enable interrupt for event READY */
3128 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
3129 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
3130 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
3131 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
3132 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
3133 
3134 /* Register: LPCOMP_INTENCLR */
3135 /* Description: Disable interrupt */
3136 
3137 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
3138 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
3139 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
3140 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
3141 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
3142 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
3143 
3144 /* Bit 2 : Write '1' to disable interrupt for event UP */
3145 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
3146 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
3147 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
3148 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
3149 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
3150 
3151 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
3152 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
3153 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
3154 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
3155 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
3156 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
3157 
3158 /* Bit 0 : Write '1' to disable interrupt for event READY */
3159 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
3160 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
3161 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
3162 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
3163 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
3164 
3165 /* Register: LPCOMP_RESULT */
3166 /* Description: Compare result */
3167 
3168 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
3169 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
3170 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
3171 #define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
3172 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
3173 
3174 /* Register: LPCOMP_ENABLE */
3175 /* Description: Enable LPCOMP */
3176 
3177 /* Bits 1..0 : Enable or disable LPCOMP */
3178 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
3179 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
3180 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
3181 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
3182 
3183 /* Register: LPCOMP_PSEL */
3184 /* Description: Input pin select */
3185 
3186 /* Bits 2..0 : Analog pin select */
3187 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
3188 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
3189 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
3190 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
3191 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
3192 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
3193 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
3194 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
3195 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
3196 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
3197 
3198 /* Register: LPCOMP_REFSEL */
3199 /* Description: Reference select */
3200 
3201 /* Bits 3..0 : Reference select */
3202 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
3203 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
3204 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
3205 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
3206 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
3207 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
3208 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
3209 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
3210 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
3211 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
3212 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
3213 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
3214 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
3215 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
3216 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
3217 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
3218 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
3219 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
3220 
3221 /* Register: LPCOMP_EXTREFSEL */
3222 /* Description: External reference select */
3223 
3224 /* Bit 0 : External analog reference select */
3225 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
3226 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
3227 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
3228 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
3229 
3230 /* Register: LPCOMP_ANADETECT */
3231 /* Description: Analog detect configuration */
3232 
3233 /* Bits 1..0 : Analog detect configuration */
3234 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
3235 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
3236 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
3237 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
3238 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
3239 
3240 /* Register: LPCOMP_HYST */
3241 /* Description: Comparator hysteresis enable */
3242 
3243 /* Bit 0 : Comparator hysteresis enable */
3244 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
3245 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
3246 #define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
3247 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
3248 
3249 
3250 /* Peripheral: MWU */
3251 /* Description: Memory Watch Unit */
3252 
3253 /* Register: MWU_EVENTS_REGION_WA */
3254 /* Description: Description cluster: Write access to region n detected */
3255 
3256 /* Bit 0 : Write access to region n detected */
3257 #define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
3258 #define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */
3259 #define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
3260 #define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */
3261 
3262 /* Register: MWU_EVENTS_REGION_RA */
3263 /* Description: Description cluster: Read access to region n detected */
3264 
3265 /* Bit 0 : Read access to region n detected */
3266 #define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
3267 #define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */
3268 #define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
3269 #define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */
3270 
3271 /* Register: MWU_EVENTS_PREGION_WA */
3272 /* Description: Description cluster: Write access to peripheral region n detected */
3273 
3274 /* Bit 0 : Write access to peripheral region n detected */
3275 #define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */
3276 #define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */
3277 #define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */
3278 #define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */
3279 
3280 /* Register: MWU_EVENTS_PREGION_RA */
3281 /* Description: Description cluster: Read access to peripheral region n detected */
3282 
3283 /* Bit 0 : Read access to peripheral region n detected */
3284 #define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */
3285 #define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */
3286 #define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */
3287 #define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */
3288 
3289 /* Register: MWU_INTEN */
3290 /* Description: Enable or disable interrupt */
3291 
3292 /* Bit 27 : Enable or disable interrupt for event PREGION1RA */
3293 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3294 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3295 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
3296 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
3297 
3298 /* Bit 26 : Enable or disable interrupt for event PREGION1WA */
3299 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3300 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3301 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
3302 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
3303 
3304 /* Bit 25 : Enable or disable interrupt for event PREGION0RA */
3305 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3306 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3307 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
3308 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
3309 
3310 /* Bit 24 : Enable or disable interrupt for event PREGION0WA */
3311 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3312 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3313 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
3314 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
3315 
3316 /* Bit 7 : Enable or disable interrupt for event REGION3RA */
3317 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3318 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3319 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
3320 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
3321 
3322 /* Bit 6 : Enable or disable interrupt for event REGION3WA */
3323 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3324 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3325 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
3326 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
3327 
3328 /* Bit 5 : Enable or disable interrupt for event REGION2RA */
3329 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3330 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3331 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
3332 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
3333 
3334 /* Bit 4 : Enable or disable interrupt for event REGION2WA */
3335 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3336 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3337 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
3338 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
3339 
3340 /* Bit 3 : Enable or disable interrupt for event REGION1RA */
3341 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3342 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3343 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
3344 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
3345 
3346 /* Bit 2 : Enable or disable interrupt for event REGION1WA */
3347 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3348 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3349 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
3350 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
3351 
3352 /* Bit 1 : Enable or disable interrupt for event REGION0RA */
3353 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3354 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3355 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
3356 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
3357 
3358 /* Bit 0 : Enable or disable interrupt for event REGION0WA */
3359 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3360 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3361 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
3362 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
3363 
3364 /* Register: MWU_INTENSET */
3365 /* Description: Enable interrupt */
3366 
3367 /* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
3368 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3369 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3370 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3371 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3372 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
3373 
3374 /* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
3375 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3376 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3377 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3378 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3379 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
3380 
3381 /* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
3382 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3383 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3384 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3385 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3386 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
3387 
3388 /* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
3389 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3390 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3391 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3392 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3393 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
3394 
3395 /* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
3396 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3397 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3398 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3399 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3400 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
3401 
3402 /* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
3403 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3404 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3405 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3406 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3407 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
3408 
3409 /* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
3410 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3411 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3412 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3413 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3414 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
3415 
3416 /* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
3417 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3418 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3419 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3420 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3421 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
3422 
3423 /* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
3424 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3425 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3426 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3427 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3428 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
3429 
3430 /* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
3431 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3432 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3433 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3434 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3435 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
3436 
3437 /* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
3438 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3439 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3440 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3441 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3442 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
3443 
3444 /* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
3445 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3446 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3447 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3448 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3449 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
3450 
3451 /* Register: MWU_INTENCLR */
3452 /* Description: Disable interrupt */
3453 
3454 /* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
3455 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3456 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3457 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3458 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3459 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3460 
3461 /* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
3462 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3463 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3464 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3465 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3466 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3467 
3468 /* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
3469 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3470 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3471 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3472 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3473 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3474 
3475 /* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
3476 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3477 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3478 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3479 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3480 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3481 
3482 /* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
3483 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3484 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3485 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3486 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3487 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3488 
3489 /* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
3490 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3491 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3492 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3493 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3494 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3495 
3496 /* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
3497 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3498 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3499 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3500 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3501 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3502 
3503 /* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
3504 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3505 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3506 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3507 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3508 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3509 
3510 /* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
3511 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3512 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3513 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3514 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3515 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3516 
3517 /* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
3518 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3519 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3520 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3521 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3522 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3523 
3524 /* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
3525 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3526 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3527 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3528 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3529 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3530 
3531 /* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
3532 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3533 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3534 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3535 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3536 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3537 
3538 /* Register: MWU_NMIEN */
3539 /* Description: Enable or disable interrupt */
3540 
3541 /* Bit 27 : Enable or disable interrupt for event PREGION1RA */
3542 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3543 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3544 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
3545 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
3546 
3547 /* Bit 26 : Enable or disable interrupt for event PREGION1WA */
3548 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3549 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3550 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
3551 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
3552 
3553 /* Bit 25 : Enable or disable interrupt for event PREGION0RA */
3554 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3555 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3556 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
3557 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
3558 
3559 /* Bit 24 : Enable or disable interrupt for event PREGION0WA */
3560 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3561 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3562 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
3563 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
3564 
3565 /* Bit 7 : Enable or disable interrupt for event REGION3RA */
3566 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3567 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3568 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
3569 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
3570 
3571 /* Bit 6 : Enable or disable interrupt for event REGION3WA */
3572 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3573 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3574 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
3575 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
3576 
3577 /* Bit 5 : Enable or disable interrupt for event REGION2RA */
3578 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3579 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3580 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
3581 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
3582 
3583 /* Bit 4 : Enable or disable interrupt for event REGION2WA */
3584 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3585 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3586 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
3587 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
3588 
3589 /* Bit 3 : Enable or disable interrupt for event REGION1RA */
3590 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3591 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3592 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
3593 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
3594 
3595 /* Bit 2 : Enable or disable interrupt for event REGION1WA */
3596 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3597 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3598 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
3599 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
3600 
3601 /* Bit 1 : Enable or disable interrupt for event REGION0RA */
3602 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3603 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3604 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
3605 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
3606 
3607 /* Bit 0 : Enable or disable interrupt for event REGION0WA */
3608 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3609 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3610 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
3611 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
3612 
3613 /* Register: MWU_NMIENSET */
3614 /* Description: Enable interrupt */
3615 
3616 /* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */
3617 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3618 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3619 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3620 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3621 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
3622 
3623 /* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */
3624 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3625 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3626 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3627 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3628 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
3629 
3630 /* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */
3631 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3632 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3633 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3634 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3635 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
3636 
3637 /* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */
3638 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3639 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3640 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3641 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3642 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
3643 
3644 /* Bit 7 : Write '1' to enable interrupt for event REGION3RA */
3645 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3646 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3647 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3648 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3649 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
3650 
3651 /* Bit 6 : Write '1' to enable interrupt for event REGION3WA */
3652 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3653 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3654 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3655 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3656 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
3657 
3658 /* Bit 5 : Write '1' to enable interrupt for event REGION2RA */
3659 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3660 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3661 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3662 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3663 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
3664 
3665 /* Bit 4 : Write '1' to enable interrupt for event REGION2WA */
3666 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3667 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3668 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3669 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3670 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
3671 
3672 /* Bit 3 : Write '1' to enable interrupt for event REGION1RA */
3673 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3674 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3675 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3676 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3677 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
3678 
3679 /* Bit 2 : Write '1' to enable interrupt for event REGION1WA */
3680 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3681 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3682 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3683 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3684 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
3685 
3686 /* Bit 1 : Write '1' to enable interrupt for event REGION0RA */
3687 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3688 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3689 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3690 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3691 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
3692 
3693 /* Bit 0 : Write '1' to enable interrupt for event REGION0WA */
3694 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3695 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3696 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3697 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3698 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
3699 
3700 /* Register: MWU_NMIENCLR */
3701 /* Description: Disable interrupt */
3702 
3703 /* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */
3704 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3705 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3706 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3707 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3708 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3709 
3710 /* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */
3711 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3712 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3713 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3714 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3715 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3716 
3717 /* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */
3718 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3719 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3720 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3721 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3722 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3723 
3724 /* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */
3725 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3726 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3727 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3728 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3729 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3730 
3731 /* Bit 7 : Write '1' to disable interrupt for event REGION3RA */
3732 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3733 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3734 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3735 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3736 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3737 
3738 /* Bit 6 : Write '1' to disable interrupt for event REGION3WA */
3739 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3740 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3741 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3742 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3743 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3744 
3745 /* Bit 5 : Write '1' to disable interrupt for event REGION2RA */
3746 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3747 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3748 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3749 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3750 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3751 
3752 /* Bit 4 : Write '1' to disable interrupt for event REGION2WA */
3753 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3754 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3755 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3756 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3757 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3758 
3759 /* Bit 3 : Write '1' to disable interrupt for event REGION1RA */
3760 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3761 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3762 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3763 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3764 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3765 
3766 /* Bit 2 : Write '1' to disable interrupt for event REGION1WA */
3767 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3768 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3769 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3770 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3771 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3772 
3773 /* Bit 1 : Write '1' to disable interrupt for event REGION0RA */
3774 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3775 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3776 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3777 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3778 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3779 
3780 /* Bit 0 : Write '1' to disable interrupt for event REGION0WA */
3781 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3782 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3783 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3784 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3785 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3786 
3787 /* Register: MWU_PERREGION_SUBSTATWA */
3788 /* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */
3789 
3790 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
3791 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3792 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
3793 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
3794 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
3795 
3796 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
3797 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3798 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
3799 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
3800 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
3801 
3802 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
3803 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3804 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
3805 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
3806 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
3807 
3808 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
3809 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3810 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
3811 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
3812 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
3813 
3814 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
3815 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3816 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
3817 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
3818 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
3819 
3820 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
3821 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3822 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
3823 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
3824 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
3825 
3826 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
3827 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3828 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
3829 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
3830 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
3831 
3832 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
3833 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3834 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
3835 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
3836 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
3837 
3838 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
3839 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3840 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
3841 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
3842 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
3843 
3844 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
3845 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3846 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
3847 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
3848 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
3849 
3850 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
3851 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3852 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
3853 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
3854 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
3855 
3856 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
3857 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3858 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
3859 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
3860 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
3861 
3862 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
3863 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3864 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
3865 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
3866 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
3867 
3868 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
3869 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3870 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
3871 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
3872 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
3873 
3874 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
3875 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3876 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
3877 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
3878 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
3879 
3880 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
3881 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3882 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
3883 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
3884 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
3885 
3886 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
3887 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3888 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
3889 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
3890 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
3891 
3892 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
3893 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3894 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
3895 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
3896 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
3897 
3898 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
3899 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3900 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
3901 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
3902 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
3903 
3904 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
3905 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3906 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
3907 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
3908 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
3909 
3910 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
3911 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3912 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
3913 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
3914 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
3915 
3916 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
3917 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3918 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
3919 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
3920 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
3921 
3922 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
3923 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3924 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
3925 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
3926 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
3927 
3928 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
3929 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3930 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
3931 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
3932 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
3933 
3934 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
3935 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3936 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
3937 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
3938 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
3939 
3940 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
3941 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3942 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
3943 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
3944 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
3945 
3946 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
3947 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3948 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
3949 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
3950 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
3951 
3952 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
3953 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3954 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
3955 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
3956 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
3957 
3958 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
3959 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3960 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
3961 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
3962 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
3963 
3964 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
3965 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3966 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
3967 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
3968 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
3969 
3970 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
3971 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3972 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
3973 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
3974 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
3975 
3976 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
3977 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3978 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
3979 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
3980 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
3981 
3982 /* Register: MWU_PERREGION_SUBSTATRA */
3983 /* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */
3984 
3985 /* Bit 31 : Subregion 31 in region n (write '1' to clear) */
3986 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3987 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
3988 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
3989 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
3990 
3991 /* Bit 30 : Subregion 30 in region n (write '1' to clear) */
3992 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3993 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
3994 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
3995 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
3996 
3997 /* Bit 29 : Subregion 29 in region n (write '1' to clear) */
3998 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3999 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
4000 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
4001 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
4002 
4003 /* Bit 28 : Subregion 28 in region n (write '1' to clear) */
4004 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
4005 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
4006 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
4007 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
4008 
4009 /* Bit 27 : Subregion 27 in region n (write '1' to clear) */
4010 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
4011 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
4012 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
4013 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
4014 
4015 /* Bit 26 : Subregion 26 in region n (write '1' to clear) */
4016 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
4017 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
4018 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
4019 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
4020 
4021 /* Bit 25 : Subregion 25 in region n (write '1' to clear) */
4022 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
4023 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
4024 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
4025 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
4026 
4027 /* Bit 24 : Subregion 24 in region n (write '1' to clear) */
4028 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
4029 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
4030 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
4031 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
4032 
4033 /* Bit 23 : Subregion 23 in region n (write '1' to clear) */
4034 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
4035 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
4036 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
4037 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
4038 
4039 /* Bit 22 : Subregion 22 in region n (write '1' to clear) */
4040 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
4041 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
4042 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
4043 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
4044 
4045 /* Bit 21 : Subregion 21 in region n (write '1' to clear) */
4046 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
4047 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
4048 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
4049 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
4050 
4051 /* Bit 20 : Subregion 20 in region n (write '1' to clear) */
4052 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
4053 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
4054 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
4055 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
4056 
4057 /* Bit 19 : Subregion 19 in region n (write '1' to clear) */
4058 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
4059 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
4060 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
4061 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
4062 
4063 /* Bit 18 : Subregion 18 in region n (write '1' to clear) */
4064 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
4065 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
4066 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
4067 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
4068 
4069 /* Bit 17 : Subregion 17 in region n (write '1' to clear) */
4070 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
4071 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
4072 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
4073 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
4074 
4075 /* Bit 16 : Subregion 16 in region n (write '1' to clear) */
4076 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
4077 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
4078 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
4079 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
4080 
4081 /* Bit 15 : Subregion 15 in region n (write '1' to clear) */
4082 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
4083 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
4084 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
4085 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
4086 
4087 /* Bit 14 : Subregion 14 in region n (write '1' to clear) */
4088 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
4089 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
4090 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
4091 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
4092 
4093 /* Bit 13 : Subregion 13 in region n (write '1' to clear) */
4094 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
4095 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
4096 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
4097 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
4098 
4099 /* Bit 12 : Subregion 12 in region n (write '1' to clear) */
4100 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
4101 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
4102 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
4103 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
4104 
4105 /* Bit 11 : Subregion 11 in region n (write '1' to clear) */
4106 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
4107 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
4108 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
4109 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
4110 
4111 /* Bit 10 : Subregion 10 in region n (write '1' to clear) */
4112 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
4113 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
4114 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
4115 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
4116 
4117 /* Bit 9 : Subregion 9 in region n (write '1' to clear) */
4118 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
4119 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
4120 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
4121 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
4122 
4123 /* Bit 8 : Subregion 8 in region n (write '1' to clear) */
4124 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
4125 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
4126 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
4127 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
4128 
4129 /* Bit 7 : Subregion 7 in region n (write '1' to clear) */
4130 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
4131 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
4132 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
4133 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
4134 
4135 /* Bit 6 : Subregion 6 in region n (write '1' to clear) */
4136 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
4137 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
4138 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
4139 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
4140 
4141 /* Bit 5 : Subregion 5 in region n (write '1' to clear) */
4142 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
4143 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
4144 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
4145 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
4146 
4147 /* Bit 4 : Subregion 4 in region n (write '1' to clear) */
4148 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
4149 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
4150 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
4151 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
4152 
4153 /* Bit 3 : Subregion 3 in region n (write '1' to clear) */
4154 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
4155 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
4156 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
4157 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
4158 
4159 /* Bit 2 : Subregion 2 in region n (write '1' to clear) */
4160 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
4161 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
4162 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
4163 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
4164 
4165 /* Bit 1 : Subregion 1 in region n (write '1' to clear) */
4166 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
4167 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
4168 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
4169 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
4170 
4171 /* Bit 0 : Subregion 0 in region n (write '1' to clear) */
4172 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
4173 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
4174 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
4175 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
4176 
4177 /* Register: MWU_REGIONEN */
4178 /* Description: Enable/disable regions watch */
4179 
4180 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
4181 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
4182 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
4183 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
4184 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
4185 
4186 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
4187 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
4188 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
4189 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
4190 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
4191 
4192 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
4193 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
4194 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
4195 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
4196 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
4197 
4198 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
4199 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
4200 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
4201 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
4202 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
4203 
4204 /* Bit 7 : Enable/disable read access watch in region[3] */
4205 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
4206 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
4207 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
4208 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
4209 
4210 /* Bit 6 : Enable/disable write access watch in region[3] */
4211 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
4212 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
4213 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
4214 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
4215 
4216 /* Bit 5 : Enable/disable read access watch in region[2] */
4217 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
4218 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
4219 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
4220 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
4221 
4222 /* Bit 4 : Enable/disable write access watch in region[2] */
4223 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
4224 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
4225 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
4226 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
4227 
4228 /* Bit 3 : Enable/disable read access watch in region[1] */
4229 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
4230 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
4231 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
4232 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
4233 
4234 /* Bit 2 : Enable/disable write access watch in region[1] */
4235 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
4236 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
4237 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
4238 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
4239 
4240 /* Bit 1 : Enable/disable read access watch in region[0] */
4241 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
4242 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
4243 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
4244 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
4245 
4246 /* Bit 0 : Enable/disable write access watch in region[0] */
4247 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
4248 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
4249 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
4250 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
4251 
4252 /* Register: MWU_REGIONENSET */
4253 /* Description: Enable regions watch */
4254 
4255 /* Bit 27 : Enable read access watch in PREGION[1] */
4256 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
4257 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
4258 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
4259 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
4260 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
4261 
4262 /* Bit 26 : Enable write access watch in PREGION[1] */
4263 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
4264 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
4265 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
4266 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
4267 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
4268 
4269 /* Bit 25 : Enable read access watch in PREGION[0] */
4270 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
4271 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
4272 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
4273 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
4274 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
4275 
4276 /* Bit 24 : Enable write access watch in PREGION[0] */
4277 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
4278 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
4279 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
4280 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
4281 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
4282 
4283 /* Bit 7 : Enable read access watch in region[3] */
4284 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
4285 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
4286 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
4287 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
4288 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
4289 
4290 /* Bit 6 : Enable write access watch in region[3] */
4291 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
4292 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
4293 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4294 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4295 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
4296 
4297 /* Bit 5 : Enable read access watch in region[2] */
4298 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
4299 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
4300 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
4301 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
4302 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
4303 
4304 /* Bit 4 : Enable write access watch in region[2] */
4305 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
4306 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
4307 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4308 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4309 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
4310 
4311 /* Bit 3 : Enable read access watch in region[1] */
4312 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
4313 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
4314 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
4315 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
4316 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
4317 
4318 /* Bit 2 : Enable write access watch in region[1] */
4319 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
4320 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
4321 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4322 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4323 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
4324 
4325 /* Bit 1 : Enable read access watch in region[0] */
4326 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
4327 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
4328 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
4329 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
4330 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
4331 
4332 /* Bit 0 : Enable write access watch in region[0] */
4333 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
4334 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
4335 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4336 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4337 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
4338 
4339 /* Register: MWU_REGIONENCLR */
4340 /* Description: Disable regions watch */
4341 
4342 /* Bit 27 : Disable read access watch in PREGION[1] */
4343 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
4344 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
4345 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
4346 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
4347 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
4348 
4349 /* Bit 26 : Disable write access watch in PREGION[1] */
4350 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
4351 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
4352 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
4353 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
4354 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
4355 
4356 /* Bit 25 : Disable read access watch in PREGION[0] */
4357 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
4358 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
4359 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
4360 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
4361 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
4362 
4363 /* Bit 24 : Disable write access watch in PREGION[0] */
4364 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
4365 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
4366 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
4367 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
4368 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
4369 
4370 /* Bit 7 : Disable read access watch in region[3] */
4371 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
4372 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
4373 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
4374 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
4375 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
4376 
4377 /* Bit 6 : Disable write access watch in region[3] */
4378 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
4379 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
4380 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4381 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4382 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
4383 
4384 /* Bit 5 : Disable read access watch in region[2] */
4385 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
4386 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
4387 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
4388 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
4389 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
4390 
4391 /* Bit 4 : Disable write access watch in region[2] */
4392 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
4393 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
4394 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4395 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4396 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
4397 
4398 /* Bit 3 : Disable read access watch in region[1] */
4399 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
4400 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
4401 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
4402 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
4403 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
4404 
4405 /* Bit 2 : Disable write access watch in region[1] */
4406 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
4407 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
4408 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4409 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4410 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
4411 
4412 /* Bit 1 : Disable read access watch in region[0] */
4413 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
4414 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
4415 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
4416 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
4417 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
4418 
4419 /* Bit 0 : Disable write access watch in region[0] */
4420 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
4421 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
4422 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4423 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4424 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
4425 
4426 /* Register: MWU_REGION_START */
4427 /* Description: Description cluster: Start address for region n */
4428 
4429 /* Bits 31..0 : Start address for region */
4430 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
4431 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
4432 
4433 /* Register: MWU_REGION_END */
4434 /* Description: Description cluster: End address of region n */
4435 
4436 /* Bits 31..0 : End address of region. */
4437 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
4438 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
4439 
4440 /* Register: MWU_PREGION_START */
4441 /* Description: Description cluster: Reserved for future use */
4442 
4443 /* Bits 31..0 : Reserved for future use */
4444 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
4445 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
4446 
4447 /* Register: MWU_PREGION_END */
4448 /* Description: Description cluster: Reserved for future use */
4449 
4450 /* Bits 31..0 : Reserved for future use */
4451 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
4452 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
4453 
4454 /* Register: MWU_PREGION_SUBS */
4455 /* Description: Description cluster: Subregions of region n */
4456 
4457 /* Bit 31 : Include or exclude subregion 31 in region */
4458 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
4459 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
4460 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
4461 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
4462 
4463 /* Bit 30 : Include or exclude subregion 30 in region */
4464 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
4465 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
4466 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
4467 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
4468 
4469 /* Bit 29 : Include or exclude subregion 29 in region */
4470 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
4471 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
4472 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
4473 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
4474 
4475 /* Bit 28 : Include or exclude subregion 28 in region */
4476 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
4477 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
4478 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
4479 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
4480 
4481 /* Bit 27 : Include or exclude subregion 27 in region */
4482 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
4483 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
4484 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
4485 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
4486 
4487 /* Bit 26 : Include or exclude subregion 26 in region */
4488 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
4489 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
4490 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
4491 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
4492 
4493 /* Bit 25 : Include or exclude subregion 25 in region */
4494 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
4495 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
4496 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
4497 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
4498 
4499 /* Bit 24 : Include or exclude subregion 24 in region */
4500 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
4501 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
4502 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
4503 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
4504 
4505 /* Bit 23 : Include or exclude subregion 23 in region */
4506 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
4507 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
4508 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
4509 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
4510 
4511 /* Bit 22 : Include or exclude subregion 22 in region */
4512 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
4513 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
4514 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
4515 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
4516 
4517 /* Bit 21 : Include or exclude subregion 21 in region */
4518 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
4519 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
4520 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
4521 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
4522 
4523 /* Bit 20 : Include or exclude subregion 20 in region */
4524 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
4525 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
4526 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
4527 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
4528 
4529 /* Bit 19 : Include or exclude subregion 19 in region */
4530 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
4531 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
4532 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
4533 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
4534 
4535 /* Bit 18 : Include or exclude subregion 18 in region */
4536 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
4537 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
4538 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
4539 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
4540 
4541 /* Bit 17 : Include or exclude subregion 17 in region */
4542 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
4543 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
4544 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
4545 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
4546 
4547 /* Bit 16 : Include or exclude subregion 16 in region */
4548 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
4549 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
4550 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
4551 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
4552 
4553 /* Bit 15 : Include or exclude subregion 15 in region */
4554 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
4555 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
4556 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
4557 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
4558 
4559 /* Bit 14 : Include or exclude subregion 14 in region */
4560 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
4561 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
4562 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
4563 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
4564 
4565 /* Bit 13 : Include or exclude subregion 13 in region */
4566 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
4567 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
4568 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
4569 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
4570 
4571 /* Bit 12 : Include or exclude subregion 12 in region */
4572 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
4573 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
4574 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
4575 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
4576 
4577 /* Bit 11 : Include or exclude subregion 11 in region */
4578 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
4579 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
4580 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
4581 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
4582 
4583 /* Bit 10 : Include or exclude subregion 10 in region */
4584 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
4585 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
4586 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
4587 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
4588 
4589 /* Bit 9 : Include or exclude subregion 9 in region */
4590 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
4591 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
4592 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
4593 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
4594 
4595 /* Bit 8 : Include or exclude subregion 8 in region */
4596 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
4597 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
4598 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
4599 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
4600 
4601 /* Bit 7 : Include or exclude subregion 7 in region */
4602 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
4603 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
4604 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
4605 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
4606 
4607 /* Bit 6 : Include or exclude subregion 6 in region */
4608 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
4609 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
4610 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
4611 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
4612 
4613 /* Bit 5 : Include or exclude subregion 5 in region */
4614 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
4615 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
4616 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
4617 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
4618 
4619 /* Bit 4 : Include or exclude subregion 4 in region */
4620 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
4621 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
4622 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
4623 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
4624 
4625 /* Bit 3 : Include or exclude subregion 3 in region */
4626 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
4627 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
4628 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
4629 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
4630 
4631 /* Bit 2 : Include or exclude subregion 2 in region */
4632 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
4633 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
4634 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
4635 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
4636 
4637 /* Bit 1 : Include or exclude subregion 1 in region */
4638 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
4639 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
4640 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
4641 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
4642 
4643 /* Bit 0 : Include or exclude subregion 0 in region */
4644 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
4645 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
4646 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
4647 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
4648 
4649 
4650 /* Peripheral: NFCT */
4651 /* Description: NFC-A compatible radio */
4652 
4653 /* Register: NFCT_TASKS_ACTIVATE */
4654 /* Description: Activate NFC peripheral for incoming and outgoing frames, change state to activated */
4655 
4656 /* Bit 0 : Activate NFC peripheral for incoming and outgoing frames, change state to activated */
4657 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */
4658 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */
4659 #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */
4660 
4661 /* Register: NFCT_TASKS_DISABLE */
4662 /* Description: Disable NFC peripheral */
4663 
4664 /* Bit 0 : Disable NFC peripheral */
4665 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
4666 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
4667 #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
4668 
4669 /* Register: NFCT_TASKS_SENSE */
4670 /* Description: Enable NFC sense field mode, change state to sense mode */
4671 
4672 /* Bit 0 : Enable NFC sense field mode, change state to sense mode */
4673 #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */
4674 #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */
4675 #define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */
4676 
4677 /* Register: NFCT_TASKS_STARTTX */
4678 /* Description: Start transmission of a outgoing frame, change state to transmit */
4679 
4680 /* Bit 0 : Start transmission of a outgoing frame, change state to transmit */
4681 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
4682 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
4683 #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
4684 
4685 /* Register: NFCT_TASKS_ENABLERXDATA */
4686 /* Description: Initializes the EasyDMA for receive. */
4687 
4688 /* Bit 0 : Initializes the EasyDMA for receive. */
4689 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */
4690 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */
4691 #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */
4692 
4693 /* Register: NFCT_TASKS_GOIDLE */
4694 /* Description: Force state machine to IDLE state */
4695 
4696 /* Bit 0 : Force state machine to IDLE state */
4697 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */
4698 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */
4699 #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */
4700 
4701 /* Register: NFCT_TASKS_GOSLEEP */
4702 /* Description: Force state machine to SLEEP_A state */
4703 
4704 /* Bit 0 : Force state machine to SLEEP_A state */
4705 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */
4706 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */
4707 #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */
4708 
4709 /* Register: NFCT_EVENTS_READY */
4710 /* Description: The NFC peripheral is ready to receive and send frames */
4711 
4712 /* Bit 0 : The NFC peripheral is ready to receive and send frames */
4713 #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
4714 #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
4715 #define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
4716 #define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
4717 
4718 /* Register: NFCT_EVENTS_FIELDDETECTED */
4719 /* Description: Remote NFC field detected */
4720 
4721 /* Bit 0 : Remote NFC field detected */
4722 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */
4723 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */
4724 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */
4725 #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */
4726 
4727 /* Register: NFCT_EVENTS_FIELDLOST */
4728 /* Description: Remote NFC field lost */
4729 
4730 /* Bit 0 : Remote NFC field lost */
4731 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */
4732 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */
4733 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */
4734 #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */
4735 
4736 /* Register: NFCT_EVENTS_TXFRAMESTART */
4737 /* Description: Marks the start of the first symbol of a transmitted frame */
4738 
4739 /* Bit 0 : Marks the start of the first symbol of a transmitted frame */
4740 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */
4741 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */
4742 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
4743 #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */
4744 
4745 /* Register: NFCT_EVENTS_TXFRAMEEND */
4746 /* Description: Marks the end of the last transmitted on-air symbol of a frame */
4747 
4748 /* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
4749 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */
4750 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */
4751 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
4752 #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */
4753 
4754 /* Register: NFCT_EVENTS_RXFRAMESTART */
4755 /* Description: Marks the end of the first symbol of a received frame */
4756 
4757 /* Bit 0 : Marks the end of the first symbol of a received frame */
4758 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */
4759 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */
4760 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */
4761 #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */
4762 
4763 /* Register: NFCT_EVENTS_RXFRAMEEND */
4764 /* Description: Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
4765 
4766 /* Bit 0 : Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */
4767 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */
4768 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */
4769 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */
4770 #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */
4771 
4772 /* Register: NFCT_EVENTS_ERROR */
4773 /* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
4774 
4775 /* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
4776 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
4777 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
4778 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
4779 #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
4780 
4781 /* Register: NFCT_EVENTS_RXERROR */
4782 /* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
4783 
4784 /* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
4785 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */
4786 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */
4787 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */
4788 #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */
4789 
4790 /* Register: NFCT_EVENTS_ENDRX */
4791 /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
4792 
4793 /* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
4794 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
4795 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
4796 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
4797 #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
4798 
4799 /* Register: NFCT_EVENTS_ENDTX */
4800 /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
4801 
4802 /* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
4803 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
4804 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
4805 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
4806 #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
4807 
4808 /* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */
4809 /* Description: Auto collision resolution process has started */
4810 
4811 /* Bit 0 : Auto collision resolution process has started */
4812 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */
4813 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */
4814 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */
4815 #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */
4816 
4817 /* Register: NFCT_EVENTS_COLLISION */
4818 /* Description: NFC Auto collision resolution error reported. */
4819 
4820 /* Bit 0 : NFC Auto collision resolution error reported. */
4821 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */
4822 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */
4823 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */
4824 #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */
4825 
4826 /* Register: NFCT_EVENTS_SELECTED */
4827 /* Description: NFC Auto collision resolution successfully completed */
4828 
4829 /* Bit 0 : NFC Auto collision resolution successfully completed */
4830 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */
4831 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */
4832 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */
4833 #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */
4834 
4835 /* Register: NFCT_EVENTS_STARTED */
4836 /* Description: EasyDMA is ready to receive or send frames. */
4837 
4838 /* Bit 0 : EasyDMA is ready to receive or send frames. */
4839 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
4840 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
4841 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
4842 #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
4843 
4844 /* Register: NFCT_SHORTS */
4845 /* Description: Shortcuts between local events and tasks */
4846 
4847 /* Bit 1 : Shortcut between event FIELDLOST and task SENSE */
4848 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
4849 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
4850 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
4851 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
4852 
4853 /* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
4854 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
4855 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
4856 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
4857 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
4858 
4859 /* Register: NFCT_INTEN */
4860 /* Description: Enable or disable interrupt */
4861 
4862 /* Bit 20 : Enable or disable interrupt for event STARTED */
4863 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4864 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
4865 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4866 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4867 
4868 /* Bit 19 : Enable or disable interrupt for event SELECTED */
4869 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4870 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4871 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
4872 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
4873 
4874 /* Bit 18 : Enable or disable interrupt for event COLLISION */
4875 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4876 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4877 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
4878 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
4879 
4880 /* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
4881 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4882 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4883 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
4884 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
4885 
4886 /* Bit 12 : Enable or disable interrupt for event ENDTX */
4887 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4888 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4889 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
4890 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
4891 
4892 /* Bit 11 : Enable or disable interrupt for event ENDRX */
4893 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4894 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4895 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
4896 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
4897 
4898 /* Bit 10 : Enable or disable interrupt for event RXERROR */
4899 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4900 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4901 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
4902 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
4903 
4904 /* Bit 7 : Enable or disable interrupt for event ERROR */
4905 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4906 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
4907 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
4908 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
4909 
4910 /* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
4911 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4912 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4913 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
4914 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
4915 
4916 /* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
4917 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4918 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4919 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
4920 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
4921 
4922 /* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
4923 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4924 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4925 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
4926 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
4927 
4928 /* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
4929 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4930 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4931 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
4932 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
4933 
4934 /* Bit 2 : Enable or disable interrupt for event FIELDLOST */
4935 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4936 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4937 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
4938 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
4939 
4940 /* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
4941 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4942 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4943 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
4944 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
4945 
4946 /* Bit 0 : Enable or disable interrupt for event READY */
4947 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
4948 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
4949 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
4950 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
4951 
4952 /* Register: NFCT_INTENSET */
4953 /* Description: Enable interrupt */
4954 
4955 /* Bit 20 : Write '1' to enable interrupt for event STARTED */
4956 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4957 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
4958 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4959 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4960 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
4961 
4962 /* Bit 19 : Write '1' to enable interrupt for event SELECTED */
4963 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4964 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4965 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4966 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4967 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
4968 
4969 /* Bit 18 : Write '1' to enable interrupt for event COLLISION */
4970 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4971 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4972 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4973 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4974 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
4975 
4976 /* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
4977 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4978 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4979 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4980 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4981 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
4982 
4983 /* Bit 12 : Write '1' to enable interrupt for event ENDTX */
4984 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4985 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4986 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4987 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4988 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
4989 
4990 /* Bit 11 : Write '1' to enable interrupt for event ENDRX */
4991 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4992 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4993 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4994 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4995 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
4996 
4997 /* Bit 10 : Write '1' to enable interrupt for event RXERROR */
4998 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4999 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
5000 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
5001 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
5002 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
5003 
5004 /* Bit 7 : Write '1' to enable interrupt for event ERROR */
5005 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
5006 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
5007 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
5008 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
5009 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
5010 
5011 /* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
5012 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
5013 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
5014 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
5015 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
5016 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
5017 
5018 /* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
5019 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
5020 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
5021 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
5022 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
5023 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
5024 
5025 /* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
5026 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
5027 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
5028 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
5029 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
5030 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
5031 
5032 /* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
5033 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
5034 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
5035 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
5036 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
5037 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
5038 
5039 /* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
5040 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
5041 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
5042 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
5043 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
5044 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
5045 
5046 /* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
5047 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
5048 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
5049 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
5050 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
5051 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
5052 
5053 /* Bit 0 : Write '1' to enable interrupt for event READY */
5054 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
5055 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
5056 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
5057 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
5058 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
5059 
5060 /* Register: NFCT_INTENCLR */
5061 /* Description: Disable interrupt */
5062 
5063 /* Bit 20 : Write '1' to disable interrupt for event STARTED */
5064 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
5065 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
5066 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
5067 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
5068 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
5069 
5070 /* Bit 19 : Write '1' to disable interrupt for event SELECTED */
5071 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
5072 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
5073 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
5074 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
5075 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
5076 
5077 /* Bit 18 : Write '1' to disable interrupt for event COLLISION */
5078 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
5079 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
5080 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
5081 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
5082 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
5083 
5084 /* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
5085 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
5086 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
5087 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
5088 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
5089 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
5090 
5091 /* Bit 12 : Write '1' to disable interrupt for event ENDTX */
5092 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
5093 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
5094 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
5095 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
5096 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
5097 
5098 /* Bit 11 : Write '1' to disable interrupt for event ENDRX */
5099 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
5100 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
5101 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
5102 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
5103 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
5104 
5105 /* Bit 10 : Write '1' to disable interrupt for event RXERROR */
5106 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
5107 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
5108 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
5109 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
5110 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
5111 
5112 /* Bit 7 : Write '1' to disable interrupt for event ERROR */
5113 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
5114 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
5115 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
5116 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
5117 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
5118 
5119 /* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
5120 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
5121 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
5122 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
5123 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
5124 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
5125 
5126 /* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
5127 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
5128 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
5129 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
5130 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
5131 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
5132 
5133 /* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
5134 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
5135 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
5136 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
5137 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
5138 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
5139 
5140 /* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
5141 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
5142 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
5143 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
5144 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
5145 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
5146 
5147 /* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
5148 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
5149 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
5150 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
5151 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
5152 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
5153 
5154 /* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
5155 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
5156 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
5157 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
5158 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
5159 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
5160 
5161 /* Bit 0 : Write '1' to disable interrupt for event READY */
5162 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
5163 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
5164 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
5165 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
5166 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
5167 
5168 /* Register: NFCT_ERRORSTATUS */
5169 /* Description: NFC Error Status register */
5170 
5171 /* Bit 3 : Field level is too low at min load resistance */
5172 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
5173 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
5174 
5175 /* Bit 2 : Field level is too high at max load resistance */
5176 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
5177 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
5178 
5179 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
5180 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
5181 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
5182 
5183 /* Register: NFCT_FRAMESTATUS_RX */
5184 /* Description: Result of last incoming frames */
5185 
5186 /* Bit 3 : Overrun detected */
5187 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
5188 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
5189 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
5190 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
5191 
5192 /* Bit 2 : Parity status of received frame */
5193 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
5194 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
5195 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
5196 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
5197 
5198 /* Bit 0 : No valid End of Frame detected */
5199 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
5200 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
5201 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
5202 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
5203 
5204 /* Register: NFCT_CURRENTLOADCTRL */
5205 /* Description: Current value driven to the NFC Load Control */
5206 
5207 /* Bits 5..0 : Current value driven to the NFC Load Control */
5208 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
5209 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
5210 
5211 /* Register: NFCT_FIELDPRESENT */
5212 /* Description: Indicates the presence or not of a valid field */
5213 
5214 /* Bit 1 : Indicates if the low level has locked to the field */
5215 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
5216 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
5217 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
5218 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
5219 
5220 /* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
5221 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
5222 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
5223 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
5224 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
5225 
5226 /* Register: NFCT_FRAMEDELAYMIN */
5227 /* Description: Minimum frame delay */
5228 
5229 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
5230 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
5231 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
5232 
5233 /* Register: NFCT_FRAMEDELAYMAX */
5234 /* Description: Maximum frame delay */
5235 
5236 /* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
5237 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
5238 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
5239 
5240 /* Register: NFCT_FRAMEDELAYMODE */
5241 /* Description: Configuration register for the Frame Delay Timer */
5242 
5243 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
5244 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
5245 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
5246 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
5247 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
5248 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
5249 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
5250 
5251 /* Register: NFCT_PACKETPTR */
5252 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
5253 
5254 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
5255 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
5256 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
5257 
5258 /* Register: NFCT_MAXLEN */
5259 /* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
5260 
5261 /* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
5262 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
5263 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
5264 
5265 /* Register: NFCT_TXD_FRAMECONFIG */
5266 /* Description: Configuration of outgoing frames */
5267 
5268 /* Bit 4 : CRC mode for outgoing frames */
5269 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
5270 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
5271 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
5272 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
5273 
5274 /* Bit 2 : Adding SoF or not in TX frames */
5275 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
5276 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
5277 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
5278 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
5279 
5280 /* Bit 1 : Discarding unused bits in start or at end of a Frame */
5281 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
5282 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
5283 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
5284 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
5285 
5286 /* Bit 0 : Adding parity or not in the frame */
5287 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
5288 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
5289 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
5290 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
5291 
5292 /* Register: NFCT_TXD_AMOUNT */
5293 /* Description: Size of outgoing frame */
5294 
5295 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
5296 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
5297 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
5298 
5299 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
5300 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
5301 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
5302 
5303 /* Register: NFCT_RXD_FRAMECONFIG */
5304 /* Description: Configuration of incoming frames */
5305 
5306 /* Bit 4 : CRC mode for incoming frames */
5307 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
5308 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
5309 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
5310 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
5311 
5312 /* Bit 2 : SoF expected or not in RX frames */
5313 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
5314 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
5315 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
5316 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
5317 
5318 /* Bit 0 : Parity expected or not in RX frame */
5319 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
5320 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
5321 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
5322 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
5323 
5324 /* Register: NFCT_RXD_AMOUNT */
5325 /* Description: Size of last incoming frame */
5326 
5327 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
5328 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
5329 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
5330 
5331 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
5332 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
5333 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
5334 
5335 /* Register: NFCT_NFCID1_LAST */
5336 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
5337 
5338 /* Bits 31..24 : NFCID1 byte W */
5339 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
5340 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
5341 
5342 /* Bits 23..16 : NFCID1 byte X */
5343 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
5344 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
5345 
5346 /* Bits 15..8 : NFCID1 byte Y */
5347 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
5348 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
5349 
5350 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
5351 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
5352 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
5353 
5354 /* Register: NFCT_NFCID1_2ND_LAST */
5355 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
5356 
5357 /* Bits 23..16 : NFCID1 byte T */
5358 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
5359 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
5360 
5361 /* Bits 15..8 : NFCID1 byte U */
5362 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
5363 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
5364 
5365 /* Bits 7..0 : NFCID1 byte V */
5366 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
5367 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
5368 
5369 /* Register: NFCT_NFCID1_3RD_LAST */
5370 /* Description: Third last NFCID1 part (10 bytes ID) */
5371 
5372 /* Bits 23..16 : NFCID1 byte Q */
5373 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
5374 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
5375 
5376 /* Bits 15..8 : NFCID1 byte R */
5377 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
5378 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
5379 
5380 /* Bits 7..0 : NFCID1 byte S */
5381 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
5382 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
5383 
5384 /* Register: NFCT_SENSRES */
5385 /* Description: NFC-A SENS_RES auto-response settings */
5386 
5387 /* Bits 15..12 : Reserved for future use. Shall be 0. */
5388 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
5389 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
5390 
5391 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
5392 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
5393 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
5394 
5395 /* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
5396 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
5397 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
5398 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
5399 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
5400 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
5401 
5402 /* Bit 5 : Reserved for future use. Shall be 0. */
5403 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
5404 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
5405 
5406 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
5407 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
5408 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
5409 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
5410 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
5411 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
5412 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
5413 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
5414 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
5415 
5416 /* Register: NFCT_SELRES */
5417 /* Description: NFC-A SEL_RES auto-response settings */
5418 
5419 /* Bit 7 : Reserved for future use. Shall be 0. */
5420 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
5421 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
5422 
5423 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
5424 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
5425 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
5426 
5427 /* Bits 4..3 : Reserved for future use. Shall be 0. */
5428 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
5429 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
5430 
5431 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
5432 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
5433 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
5434 #define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
5435 #define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
5436 
5437 /* Bits 1..0 : Reserved for future use. Shall be 0. */
5438 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
5439 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
5440 
5441 
5442 /* Peripheral: NVMC */
5443 /* Description: Non Volatile Memory Controller */
5444 
5445 /* Register: NVMC_READY */
5446 /* Description: Ready flag */
5447 
5448 /* Bit 0 : NVMC is ready or busy */
5449 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
5450 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
5451 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
5452 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
5453 
5454 /* Register: NVMC_CONFIG */
5455 /* Description: Configuration register */
5456 
5457 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
5458 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
5459 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
5460 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
5461 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
5462 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
5463 
5464 /* Register: NVMC_ERASEPAGE */
5465 /* Description: Register for erasing a page in Code area */
5466 
5467 /* Bits 31..0 : Register for starting erase of a page in Code area */
5468 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
5469 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
5470 
5471 /* Register: NVMC_ERASEPCR1 */
5472 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
5473 
5474 /* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
5475 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
5476 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
5477 
5478 /* Register: NVMC_ERASEALL */
5479 /* Description: Register for erasing all non-volatile user memory */
5480 
5481 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
5482 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
5483 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
5484 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
5485 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
5486 
5487 /* Register: NVMC_ERASEPCR0 */
5488 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
5489 
5490 /* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
5491 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
5492 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
5493 
5494 /* Register: NVMC_ERASEUICR */
5495 /* Description: Register for erasing User Information Configuration Registers */
5496 
5497 /* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
5498 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
5499 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
5500 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
5501 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
5502 
5503 /* Register: NVMC_ICACHECNF */
5504 /* Description: I-Code cache configuration register. */
5505 
5506 /* Bit 8 : Cache profiling enable */
5507 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
5508 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
5509 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
5510 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
5511 
5512 /* Bit 0 : Cache enable */
5513 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
5514 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
5515 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
5516 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
5517 
5518 /* Register: NVMC_IHIT */
5519 /* Description: I-Code cache hit counter. */
5520 
5521 /* Bits 31..0 : Number of cache hits */
5522 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
5523 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
5524 
5525 /* Register: NVMC_IMISS */
5526 /* Description: I-Code cache miss counter. */
5527 
5528 /* Bits 31..0 : Number of cache misses */
5529 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
5530 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
5531 
5532 
5533 /* Peripheral: GPIO */
5534 /* Description: GPIO Port 1 */
5535 
5536 /* Register: GPIO_OUT */
5537 /* Description: Write GPIO port */
5538 
5539 /* Bit 31 : Pin 31 */
5540 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5541 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5542 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
5543 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
5544 
5545 /* Bit 30 : Pin 30 */
5546 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5547 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5548 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
5549 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
5550 
5551 /* Bit 29 : Pin 29 */
5552 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5553 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5554 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
5555 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
5556 
5557 /* Bit 28 : Pin 28 */
5558 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5559 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5560 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
5561 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
5562 
5563 /* Bit 27 : Pin 27 */
5564 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5565 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5566 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
5567 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
5568 
5569 /* Bit 26 : Pin 26 */
5570 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5571 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5572 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
5573 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
5574 
5575 /* Bit 25 : Pin 25 */
5576 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5577 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5578 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
5579 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
5580 
5581 /* Bit 24 : Pin 24 */
5582 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5583 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5584 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
5585 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
5586 
5587 /* Bit 23 : Pin 23 */
5588 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5589 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5590 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
5591 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
5592 
5593 /* Bit 22 : Pin 22 */
5594 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5595 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5596 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
5597 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
5598 
5599 /* Bit 21 : Pin 21 */
5600 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5601 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5602 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
5603 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
5604 
5605 /* Bit 20 : Pin 20 */
5606 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5607 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5608 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
5609 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
5610 
5611 /* Bit 19 : Pin 19 */
5612 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5613 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5614 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
5615 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
5616 
5617 /* Bit 18 : Pin 18 */
5618 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5619 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5620 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
5621 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
5622 
5623 /* Bit 17 : Pin 17 */
5624 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5625 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5626 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
5627 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
5628 
5629 /* Bit 16 : Pin 16 */
5630 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5631 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5632 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
5633 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
5634 
5635 /* Bit 15 : Pin 15 */
5636 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5637 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5638 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
5639 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
5640 
5641 /* Bit 14 : Pin 14 */
5642 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5643 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5644 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
5645 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
5646 
5647 /* Bit 13 : Pin 13 */
5648 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5649 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5650 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
5651 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
5652 
5653 /* Bit 12 : Pin 12 */
5654 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5655 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5656 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
5657 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
5658 
5659 /* Bit 11 : Pin 11 */
5660 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5661 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5662 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
5663 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
5664 
5665 /* Bit 10 : Pin 10 */
5666 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5667 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5668 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
5669 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
5670 
5671 /* Bit 9 : Pin 9 */
5672 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5673 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5674 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
5675 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
5676 
5677 /* Bit 8 : Pin 8 */
5678 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5679 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5680 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
5681 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
5682 
5683 /* Bit 7 : Pin 7 */
5684 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5685 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5686 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
5687 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
5688 
5689 /* Bit 6 : Pin 6 */
5690 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5691 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5692 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
5693 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
5694 
5695 /* Bit 5 : Pin 5 */
5696 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5697 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5698 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
5699 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
5700 
5701 /* Bit 4 : Pin 4 */
5702 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5703 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5704 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
5705 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
5706 
5707 /* Bit 3 : Pin 3 */
5708 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5709 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5710 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
5711 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
5712 
5713 /* Bit 2 : Pin 2 */
5714 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5715 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5716 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
5717 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
5718 
5719 /* Bit 1 : Pin 1 */
5720 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5721 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5722 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
5723 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
5724 
5725 /* Bit 0 : Pin 0 */
5726 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5727 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5728 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
5729 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
5730 
5731 /* Register: GPIO_OUTSET */
5732 /* Description: Set individual bits in GPIO port */
5733 
5734 /* Bit 31 : Pin 31 */
5735 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5736 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5737 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
5738 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5739 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5740 
5741 /* Bit 30 : Pin 30 */
5742 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5743 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5744 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
5745 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5746 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5747 
5748 /* Bit 29 : Pin 29 */
5749 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5750 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5751 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
5752 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5753 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5754 
5755 /* Bit 28 : Pin 28 */
5756 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5757 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5758 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
5759 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5760 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5761 
5762 /* Bit 27 : Pin 27 */
5763 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5764 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5765 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
5766 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5767 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5768 
5769 /* Bit 26 : Pin 26 */
5770 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5771 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5772 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
5773 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5774 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5775 
5776 /* Bit 25 : Pin 25 */
5777 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5778 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5779 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
5780 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5781 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5782 
5783 /* Bit 24 : Pin 24 */
5784 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5785 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5786 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
5787 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5788 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5789 
5790 /* Bit 23 : Pin 23 */
5791 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5792 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5793 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
5794 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5795 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5796 
5797 /* Bit 22 : Pin 22 */
5798 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5799 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5800 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
5801 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5802 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5803 
5804 /* Bit 21 : Pin 21 */
5805 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5806 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5807 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
5808 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5809 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5810 
5811 /* Bit 20 : Pin 20 */
5812 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5813 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5814 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
5815 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5816 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5817 
5818 /* Bit 19 : Pin 19 */
5819 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5820 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5821 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
5822 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5823 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5824 
5825 /* Bit 18 : Pin 18 */
5826 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5827 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5828 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
5829 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5830 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5831 
5832 /* Bit 17 : Pin 17 */
5833 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5834 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5835 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
5836 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5837 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5838 
5839 /* Bit 16 : Pin 16 */
5840 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5841 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5842 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
5843 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5844 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5845 
5846 /* Bit 15 : Pin 15 */
5847 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5848 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5849 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
5850 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5851 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5852 
5853 /* Bit 14 : Pin 14 */
5854 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5855 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5856 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
5857 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5858 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5859 
5860 /* Bit 13 : Pin 13 */
5861 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5862 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5863 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
5864 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5865 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5866 
5867 /* Bit 12 : Pin 12 */
5868 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5869 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5870 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
5871 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5872 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5873 
5874 /* Bit 11 : Pin 11 */
5875 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5876 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5877 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
5878 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5879 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5880 
5881 /* Bit 10 : Pin 10 */
5882 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5883 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5884 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
5885 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5886 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5887 
5888 /* Bit 9 : Pin 9 */
5889 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5890 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5891 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
5892 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5893 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5894 
5895 /* Bit 8 : Pin 8 */
5896 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5897 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5898 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
5899 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5900 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5901 
5902 /* Bit 7 : Pin 7 */
5903 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5904 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5905 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
5906 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5907 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5908 
5909 /* Bit 6 : Pin 6 */
5910 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5911 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5912 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
5913 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5914 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5915 
5916 /* Bit 5 : Pin 5 */
5917 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5918 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5919 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
5920 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5921 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5922 
5923 /* Bit 4 : Pin 4 */
5924 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5925 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5926 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
5927 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5928 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5929 
5930 /* Bit 3 : Pin 3 */
5931 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5932 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5933 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
5934 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5935 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5936 
5937 /* Bit 2 : Pin 2 */
5938 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5939 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5940 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
5941 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5942 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5943 
5944 /* Bit 1 : Pin 1 */
5945 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5946 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5947 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
5948 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5949 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5950 
5951 /* Bit 0 : Pin 0 */
5952 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5953 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5954 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
5955 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5956 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5957 
5958 /* Register: GPIO_OUTCLR */
5959 /* Description: Clear individual bits in GPIO port */
5960 
5961 /* Bit 31 : Pin 31 */
5962 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5963 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5964 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
5965 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5966 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5967 
5968 /* Bit 30 : Pin 30 */
5969 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5970 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5971 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
5972 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5973 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5974 
5975 /* Bit 29 : Pin 29 */
5976 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5977 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5978 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
5979 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5980 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5981 
5982 /* Bit 28 : Pin 28 */
5983 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5984 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5985 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
5986 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5987 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5988 
5989 /* Bit 27 : Pin 27 */
5990 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5991 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5992 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
5993 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5994 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5995 
5996 /* Bit 26 : Pin 26 */
5997 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5998 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5999 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
6000 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
6001 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6002 
6003 /* Bit 25 : Pin 25 */
6004 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6005 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6006 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
6007 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
6008 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6009 
6010 /* Bit 24 : Pin 24 */
6011 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6012 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6013 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
6014 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
6015 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6016 
6017 /* Bit 23 : Pin 23 */
6018 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6019 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6020 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
6021 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
6022 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6023 
6024 /* Bit 22 : Pin 22 */
6025 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6026 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6027 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
6028 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
6029 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6030 
6031 /* Bit 21 : Pin 21 */
6032 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6033 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6034 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
6035 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
6036 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6037 
6038 /* Bit 20 : Pin 20 */
6039 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6040 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6041 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
6042 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
6043 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6044 
6045 /* Bit 19 : Pin 19 */
6046 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6047 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6048 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
6049 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
6050 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6051 
6052 /* Bit 18 : Pin 18 */
6053 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6054 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6055 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
6056 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
6057 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6058 
6059 /* Bit 17 : Pin 17 */
6060 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6061 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6062 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
6063 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
6064 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6065 
6066 /* Bit 16 : Pin 16 */
6067 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6068 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6069 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
6070 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
6071 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6072 
6073 /* Bit 15 : Pin 15 */
6074 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6075 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6076 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
6077 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
6078 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6079 
6080 /* Bit 14 : Pin 14 */
6081 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6082 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6083 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
6084 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
6085 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6086 
6087 /* Bit 13 : Pin 13 */
6088 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6089 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6090 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
6091 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
6092 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6093 
6094 /* Bit 12 : Pin 12 */
6095 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6096 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6097 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
6098 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
6099 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6100 
6101 /* Bit 11 : Pin 11 */
6102 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6103 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6104 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
6105 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
6106 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6107 
6108 /* Bit 10 : Pin 10 */
6109 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6110 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6111 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
6112 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
6113 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6114 
6115 /* Bit 9 : Pin 9 */
6116 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6117 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6118 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
6119 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
6120 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6121 
6122 /* Bit 8 : Pin 8 */
6123 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6124 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6125 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
6126 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
6127 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6128 
6129 /* Bit 7 : Pin 7 */
6130 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6131 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6132 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
6133 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
6134 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6135 
6136 /* Bit 6 : Pin 6 */
6137 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6138 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6139 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
6140 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
6141 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6142 
6143 /* Bit 5 : Pin 5 */
6144 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6145 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6146 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
6147 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
6148 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6149 
6150 /* Bit 4 : Pin 4 */
6151 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6152 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6153 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
6154 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
6155 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6156 
6157 /* Bit 3 : Pin 3 */
6158 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6159 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6160 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
6161 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
6162 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6163 
6164 /* Bit 2 : Pin 2 */
6165 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6166 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6167 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
6168 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
6169 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6170 
6171 /* Bit 1 : Pin 1 */
6172 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6173 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6174 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
6175 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
6176 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6177 
6178 /* Bit 0 : Pin 0 */
6179 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6180 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6181 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
6182 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
6183 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
6184 
6185 /* Register: GPIO_IN */
6186 /* Description: Read GPIO port */
6187 
6188 /* Bit 31 : Pin 31 */
6189 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6190 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6191 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
6192 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
6193 
6194 /* Bit 30 : Pin 30 */
6195 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6196 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6197 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
6198 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
6199 
6200 /* Bit 29 : Pin 29 */
6201 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6202 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6203 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
6204 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
6205 
6206 /* Bit 28 : Pin 28 */
6207 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6208 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6209 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
6210 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
6211 
6212 /* Bit 27 : Pin 27 */
6213 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6214 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6215 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
6216 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
6217 
6218 /* Bit 26 : Pin 26 */
6219 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6220 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6221 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
6222 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
6223 
6224 /* Bit 25 : Pin 25 */
6225 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6226 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6227 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
6228 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
6229 
6230 /* Bit 24 : Pin 24 */
6231 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6232 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6233 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
6234 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
6235 
6236 /* Bit 23 : Pin 23 */
6237 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6238 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6239 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
6240 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
6241 
6242 /* Bit 22 : Pin 22 */
6243 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6244 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6245 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
6246 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
6247 
6248 /* Bit 21 : Pin 21 */
6249 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6250 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6251 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
6252 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
6253 
6254 /* Bit 20 : Pin 20 */
6255 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6256 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6257 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
6258 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
6259 
6260 /* Bit 19 : Pin 19 */
6261 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6262 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6263 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
6264 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
6265 
6266 /* Bit 18 : Pin 18 */
6267 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6268 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6269 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
6270 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
6271 
6272 /* Bit 17 : Pin 17 */
6273 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6274 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6275 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
6276 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
6277 
6278 /* Bit 16 : Pin 16 */
6279 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6280 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6281 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
6282 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
6283 
6284 /* Bit 15 : Pin 15 */
6285 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6286 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6287 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
6288 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
6289 
6290 /* Bit 14 : Pin 14 */
6291 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6292 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6293 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
6294 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
6295 
6296 /* Bit 13 : Pin 13 */
6297 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6298 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6299 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
6300 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
6301 
6302 /* Bit 12 : Pin 12 */
6303 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6304 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6305 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
6306 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
6307 
6308 /* Bit 11 : Pin 11 */
6309 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6310 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6311 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
6312 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
6313 
6314 /* Bit 10 : Pin 10 */
6315 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6316 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6317 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
6318 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
6319 
6320 /* Bit 9 : Pin 9 */
6321 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6322 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6323 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
6324 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
6325 
6326 /* Bit 8 : Pin 8 */
6327 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6328 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6329 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
6330 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
6331 
6332 /* Bit 7 : Pin 7 */
6333 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6334 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6335 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
6336 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
6337 
6338 /* Bit 6 : Pin 6 */
6339 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6340 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6341 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
6342 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
6343 
6344 /* Bit 5 : Pin 5 */
6345 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6346 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6347 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
6348 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
6349 
6350 /* Bit 4 : Pin 4 */
6351 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6352 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6353 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
6354 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
6355 
6356 /* Bit 3 : Pin 3 */
6357 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6358 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6359 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
6360 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
6361 
6362 /* Bit 2 : Pin 2 */
6363 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6364 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6365 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
6366 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
6367 
6368 /* Bit 1 : Pin 1 */
6369 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6370 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6371 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
6372 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
6373 
6374 /* Bit 0 : Pin 0 */
6375 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6376 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6377 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
6378 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
6379 
6380 /* Register: GPIO_DIR */
6381 /* Description: Direction of GPIO pins */
6382 
6383 /* Bit 31 : Pin 31 */
6384 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6385 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6386 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
6387 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
6388 
6389 /* Bit 30 : Pin 30 */
6390 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6391 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6392 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
6393 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
6394 
6395 /* Bit 29 : Pin 29 */
6396 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6397 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6398 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
6399 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
6400 
6401 /* Bit 28 : Pin 28 */
6402 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6403 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6404 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
6405 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
6406 
6407 /* Bit 27 : Pin 27 */
6408 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6409 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6410 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
6411 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
6412 
6413 /* Bit 26 : Pin 26 */
6414 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6415 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6416 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
6417 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
6418 
6419 /* Bit 25 : Pin 25 */
6420 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6421 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6422 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
6423 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
6424 
6425 /* Bit 24 : Pin 24 */
6426 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6427 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6428 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
6429 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
6430 
6431 /* Bit 23 : Pin 23 */
6432 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6433 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6434 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
6435 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
6436 
6437 /* Bit 22 : Pin 22 */
6438 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6439 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6440 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
6441 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
6442 
6443 /* Bit 21 : Pin 21 */
6444 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6445 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6446 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
6447 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
6448 
6449 /* Bit 20 : Pin 20 */
6450 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6451 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6452 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
6453 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
6454 
6455 /* Bit 19 : Pin 19 */
6456 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6457 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6458 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
6459 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
6460 
6461 /* Bit 18 : Pin 18 */
6462 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6463 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6464 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
6465 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
6466 
6467 /* Bit 17 : Pin 17 */
6468 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6469 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6470 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
6471 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
6472 
6473 /* Bit 16 : Pin 16 */
6474 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6475 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6476 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
6477 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
6478 
6479 /* Bit 15 : Pin 15 */
6480 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6481 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6482 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
6483 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
6484 
6485 /* Bit 14 : Pin 14 */
6486 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6487 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6488 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
6489 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
6490 
6491 /* Bit 13 : Pin 13 */
6492 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6493 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6494 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
6495 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
6496 
6497 /* Bit 12 : Pin 12 */
6498 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6499 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6500 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
6501 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
6502 
6503 /* Bit 11 : Pin 11 */
6504 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6505 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6506 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
6507 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
6508 
6509 /* Bit 10 : Pin 10 */
6510 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6511 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6512 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
6513 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
6514 
6515 /* Bit 9 : Pin 9 */
6516 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6517 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6518 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
6519 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
6520 
6521 /* Bit 8 : Pin 8 */
6522 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6523 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6524 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
6525 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
6526 
6527 /* Bit 7 : Pin 7 */
6528 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6529 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6530 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
6531 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
6532 
6533 /* Bit 6 : Pin 6 */
6534 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6535 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6536 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
6537 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
6538 
6539 /* Bit 5 : Pin 5 */
6540 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6541 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6542 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
6543 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
6544 
6545 /* Bit 4 : Pin 4 */
6546 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6547 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6548 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
6549 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
6550 
6551 /* Bit 3 : Pin 3 */
6552 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6553 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6554 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
6555 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
6556 
6557 /* Bit 2 : Pin 2 */
6558 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6559 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6560 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
6561 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
6562 
6563 /* Bit 1 : Pin 1 */
6564 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6565 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6566 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
6567 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
6568 
6569 /* Bit 0 : Pin 0 */
6570 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6571 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6572 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
6573 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
6574 
6575 /* Register: GPIO_DIRSET */
6576 /* Description: DIR set register */
6577 
6578 /* Bit 31 : Set as output pin 31 */
6579 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6580 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6581 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
6582 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
6583 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6584 
6585 /* Bit 30 : Set as output pin 30 */
6586 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6587 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6588 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
6589 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
6590 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6591 
6592 /* Bit 29 : Set as output pin 29 */
6593 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6594 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6595 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
6596 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
6597 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6598 
6599 /* Bit 28 : Set as output pin 28 */
6600 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6601 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6602 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
6603 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
6604 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6605 
6606 /* Bit 27 : Set as output pin 27 */
6607 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6608 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6609 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
6610 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
6611 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6612 
6613 /* Bit 26 : Set as output pin 26 */
6614 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6615 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6616 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
6617 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
6618 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6619 
6620 /* Bit 25 : Set as output pin 25 */
6621 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6622 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6623 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
6624 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
6625 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6626 
6627 /* Bit 24 : Set as output pin 24 */
6628 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6629 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6630 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
6631 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
6632 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6633 
6634 /* Bit 23 : Set as output pin 23 */
6635 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6636 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6637 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
6638 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
6639 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6640 
6641 /* Bit 22 : Set as output pin 22 */
6642 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6643 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6644 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
6645 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
6646 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6647 
6648 /* Bit 21 : Set as output pin 21 */
6649 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6650 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6651 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
6652 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
6653 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6654 
6655 /* Bit 20 : Set as output pin 20 */
6656 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6657 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6658 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
6659 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
6660 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6661 
6662 /* Bit 19 : Set as output pin 19 */
6663 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6664 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6665 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
6666 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
6667 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6668 
6669 /* Bit 18 : Set as output pin 18 */
6670 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6671 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6672 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
6673 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
6674 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6675 
6676 /* Bit 17 : Set as output pin 17 */
6677 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6678 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6679 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
6680 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
6681 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6682 
6683 /* Bit 16 : Set as output pin 16 */
6684 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6685 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6686 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
6687 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
6688 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6689 
6690 /* Bit 15 : Set as output pin 15 */
6691 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6692 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6693 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
6694 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
6695 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6696 
6697 /* Bit 14 : Set as output pin 14 */
6698 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6699 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6700 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
6701 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
6702 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6703 
6704 /* Bit 13 : Set as output pin 13 */
6705 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6706 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6707 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
6708 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
6709 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6710 
6711 /* Bit 12 : Set as output pin 12 */
6712 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6713 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6714 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
6715 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
6716 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6717 
6718 /* Bit 11 : Set as output pin 11 */
6719 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6720 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6721 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
6722 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
6723 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6724 
6725 /* Bit 10 : Set as output pin 10 */
6726 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6727 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6728 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
6729 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
6730 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6731 
6732 /* Bit 9 : Set as output pin 9 */
6733 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6734 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6735 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
6736 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
6737 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6738 
6739 /* Bit 8 : Set as output pin 8 */
6740 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6741 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6742 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
6743 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
6744 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6745 
6746 /* Bit 7 : Set as output pin 7 */
6747 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6748 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6749 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
6750 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
6751 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6752 
6753 /* Bit 6 : Set as output pin 6 */
6754 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6755 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6756 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
6757 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
6758 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6759 
6760 /* Bit 5 : Set as output pin 5 */
6761 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6762 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6763 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
6764 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
6765 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6766 
6767 /* Bit 4 : Set as output pin 4 */
6768 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6769 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6770 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
6771 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
6772 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6773 
6774 /* Bit 3 : Set as output pin 3 */
6775 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6776 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6777 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
6778 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
6779 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6780 
6781 /* Bit 2 : Set as output pin 2 */
6782 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6783 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6784 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
6785 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
6786 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6787 
6788 /* Bit 1 : Set as output pin 1 */
6789 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6790 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6791 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
6792 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
6793 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6794 
6795 /* Bit 0 : Set as output pin 0 */
6796 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6797 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6798 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
6799 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
6800 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6801 
6802 /* Register: GPIO_DIRCLR */
6803 /* Description: DIR clear register */
6804 
6805 /* Bit 31 : Set as input pin 31 */
6806 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6807 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6808 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
6809 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
6810 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6811 
6812 /* Bit 30 : Set as input pin 30 */
6813 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6814 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6815 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
6816 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
6817 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6818 
6819 /* Bit 29 : Set as input pin 29 */
6820 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6821 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6822 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
6823 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
6824 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6825 
6826 /* Bit 28 : Set as input pin 28 */
6827 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6828 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6829 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
6830 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
6831 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6832 
6833 /* Bit 27 : Set as input pin 27 */
6834 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6835 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6836 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
6837 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
6838 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6839 
6840 /* Bit 26 : Set as input pin 26 */
6841 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6842 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6843 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
6844 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
6845 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6846 
6847 /* Bit 25 : Set as input pin 25 */
6848 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6849 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6850 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
6851 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
6852 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6853 
6854 /* Bit 24 : Set as input pin 24 */
6855 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6856 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6857 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
6858 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
6859 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6860 
6861 /* Bit 23 : Set as input pin 23 */
6862 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6863 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6864 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
6865 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
6866 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6867 
6868 /* Bit 22 : Set as input pin 22 */
6869 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6870 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6871 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
6872 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
6873 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6874 
6875 /* Bit 21 : Set as input pin 21 */
6876 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6877 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6878 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
6879 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
6880 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6881 
6882 /* Bit 20 : Set as input pin 20 */
6883 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6884 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6885 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
6886 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
6887 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6888 
6889 /* Bit 19 : Set as input pin 19 */
6890 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6891 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6892 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
6893 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
6894 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6895 
6896 /* Bit 18 : Set as input pin 18 */
6897 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6898 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6899 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
6900 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
6901 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6902 
6903 /* Bit 17 : Set as input pin 17 */
6904 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6905 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6906 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
6907 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
6908 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6909 
6910 /* Bit 16 : Set as input pin 16 */
6911 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6912 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6913 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
6914 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
6915 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6916 
6917 /* Bit 15 : Set as input pin 15 */
6918 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6919 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6920 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
6921 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
6922 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6923 
6924 /* Bit 14 : Set as input pin 14 */
6925 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6926 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6927 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
6928 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
6929 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6930 
6931 /* Bit 13 : Set as input pin 13 */
6932 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6933 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6934 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
6935 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
6936 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6937 
6938 /* Bit 12 : Set as input pin 12 */
6939 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6940 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6941 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
6942 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
6943 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6944 
6945 /* Bit 11 : Set as input pin 11 */
6946 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6947 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6948 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
6949 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
6950 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6951 
6952 /* Bit 10 : Set as input pin 10 */
6953 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6954 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6955 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
6956 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
6957 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6958 
6959 /* Bit 9 : Set as input pin 9 */
6960 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6961 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6962 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
6963 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
6964 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6965 
6966 /* Bit 8 : Set as input pin 8 */
6967 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6968 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6969 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
6970 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
6971 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6972 
6973 /* Bit 7 : Set as input pin 7 */
6974 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6975 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6976 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
6977 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
6978 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6979 
6980 /* Bit 6 : Set as input pin 6 */
6981 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6982 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6983 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
6984 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
6985 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6986 
6987 /* Bit 5 : Set as input pin 5 */
6988 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6989 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6990 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
6991 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
6992 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6993 
6994 /* Bit 4 : Set as input pin 4 */
6995 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6996 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6997 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
6998 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
6999 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
7000 
7001 /* Bit 3 : Set as input pin 3 */
7002 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7003 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7004 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
7005 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
7006 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
7007 
7008 /* Bit 2 : Set as input pin 2 */
7009 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7010 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7011 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
7012 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
7013 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
7014 
7015 /* Bit 1 : Set as input pin 1 */
7016 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7017 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7018 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
7019 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
7020 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
7021 
7022 /* Bit 0 : Set as input pin 0 */
7023 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7024 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7025 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
7026 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
7027 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
7028 
7029 /* Register: GPIO_LATCH */
7030 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
7031 
7032 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
7033 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7034 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7035 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
7036 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
7037 
7038 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
7039 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7040 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7041 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
7042 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
7043 
7044 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
7045 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7046 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7047 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
7048 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
7049 
7050 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
7051 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7052 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7053 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
7054 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
7055 
7056 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
7057 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7058 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7059 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
7060 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
7061 
7062 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
7063 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7064 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7065 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
7066 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
7067 
7068 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
7069 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7070 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7071 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
7072 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
7073 
7074 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
7075 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7076 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7077 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
7078 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
7079 
7080 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
7081 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7082 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7083 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
7084 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
7085 
7086 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
7087 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7088 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7089 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
7090 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
7091 
7092 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
7093 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7094 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7095 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
7096 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
7097 
7098 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
7099 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7100 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7101 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
7102 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
7103 
7104 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
7105 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7106 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7107 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
7108 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
7109 
7110 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
7111 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7112 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7113 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
7114 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
7115 
7116 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
7117 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7118 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7119 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
7120 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
7121 
7122 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
7123 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7124 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7125 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
7126 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
7127 
7128 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
7129 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7130 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7131 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
7132 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
7133 
7134 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
7135 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7136 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7137 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
7138 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
7139 
7140 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
7141 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7142 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7143 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
7144 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
7145 
7146 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
7147 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7148 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7149 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
7150 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
7151 
7152 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
7153 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7154 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7155 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
7156 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
7157 
7158 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
7159 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7160 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7161 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
7162 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
7163 
7164 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
7165 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7166 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7167 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
7168 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
7169 
7170 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
7171 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7172 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7173 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
7174 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
7175 
7176 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
7177 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7178 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7179 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
7180 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
7181 
7182 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
7183 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7184 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7185 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
7186 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
7187 
7188 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
7189 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7190 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7191 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
7192 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
7193 
7194 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
7195 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7196 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7197 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
7198 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
7199 
7200 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
7201 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7202 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7203 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
7204 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
7205 
7206 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
7207 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7208 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7209 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
7210 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
7211 
7212 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
7213 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7214 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7215 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
7216 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
7217 
7218 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
7219 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7220 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7221 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
7222 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
7223 
7224 /* Register: GPIO_DETECTMODE */
7225 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
7226 
7227 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
7228 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
7229 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
7230 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
7231 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
7232 
7233 /* Register: GPIO_PIN_CNF */
7234 /* Description: Description collection: Configuration of GPIO pins */
7235 
7236 /* Bits 17..16 : Pin sensing mechanism */
7237 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
7238 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
7239 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
7240 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
7241 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
7242 
7243 /* Bits 10..8 : Drive configuration */
7244 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
7245 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
7246 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
7247 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
7248 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
7249 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
7250 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
7251 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
7252 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
7253 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
7254 
7255 /* Bits 3..2 : Pull configuration */
7256 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
7257 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
7258 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
7259 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
7260 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
7261 
7262 /* Bit 1 : Connect or disconnect input buffer */
7263 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
7264 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
7265 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
7266 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
7267 
7268 /* Bit 0 : Pin direction. Same physical register as DIR register */
7269 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
7270 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
7271 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
7272 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
7273 
7274 
7275 /* Peripheral: PDM */
7276 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
7277 
7278 /* Register: PDM_TASKS_START */
7279 /* Description: Starts continuous PDM transfer */
7280 
7281 /* Bit 0 : Starts continuous PDM transfer */
7282 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
7283 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
7284 #define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
7285 
7286 /* Register: PDM_TASKS_STOP */
7287 /* Description: Stops PDM transfer */
7288 
7289 /* Bit 0 : Stops PDM transfer */
7290 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
7291 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
7292 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
7293 
7294 /* Register: PDM_EVENTS_STARTED */
7295 /* Description: PDM transfer has started */
7296 
7297 /* Bit 0 : PDM transfer has started */
7298 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
7299 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
7300 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
7301 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
7302 
7303 /* Register: PDM_EVENTS_STOPPED */
7304 /* Description: PDM transfer has finished */
7305 
7306 /* Bit 0 : PDM transfer has finished */
7307 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
7308 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
7309 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
7310 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
7311 
7312 /* Register: PDM_EVENTS_END */
7313 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
7314 
7315 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
7316 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
7317 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
7318 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
7319 #define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
7320 
7321 /* Register: PDM_INTEN */
7322 /* Description: Enable or disable interrupt */
7323 
7324 /* Bit 2 : Enable or disable interrupt for event END */
7325 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
7326 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
7327 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
7328 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
7329 
7330 /* Bit 1 : Enable or disable interrupt for event STOPPED */
7331 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7332 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7333 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
7334 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
7335 
7336 /* Bit 0 : Enable or disable interrupt for event STARTED */
7337 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
7338 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
7339 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
7340 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
7341 
7342 /* Register: PDM_INTENSET */
7343 /* Description: Enable interrupt */
7344 
7345 /* Bit 2 : Write '1' to enable interrupt for event END */
7346 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
7347 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
7348 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7349 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7350 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
7351 
7352 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
7353 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7354 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7355 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7356 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7357 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
7358 
7359 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
7360 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
7361 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
7362 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
7363 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
7364 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
7365 
7366 /* Register: PDM_INTENCLR */
7367 /* Description: Disable interrupt */
7368 
7369 /* Bit 2 : Write '1' to disable interrupt for event END */
7370 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
7371 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
7372 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7373 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7374 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
7375 
7376 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
7377 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7378 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7379 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7380 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7381 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
7382 
7383 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
7384 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
7385 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
7386 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7387 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7388 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
7389 
7390 /* Register: PDM_ENABLE */
7391 /* Description: PDM module enable register */
7392 
7393 /* Bit 0 : Enable or disable PDM module */
7394 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7395 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7396 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
7397 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
7398 
7399 /* Register: PDM_PDMCLKCTRL */
7400 /* Description: PDM clock generator control */
7401 
7402 /* Bits 31..0 : PDM_CLK frequency */
7403 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
7404 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
7405 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
7406 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
7407 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
7408 
7409 /* Register: PDM_MODE */
7410 /* Description: Defines the routing of the connected PDM microphones' signals */
7411 
7412 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
7413 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
7414 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
7415 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
7416 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
7417 
7418 /* Bit 0 : Mono or stereo operation */
7419 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
7420 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
7421 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
7422 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
7423 
7424 /* Register: PDM_GAINL */
7425 /* Description: Left output gain adjustment */
7426 
7427 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
7428 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
7429 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
7430 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
7431 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
7432 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
7433 
7434 /* Register: PDM_GAINR */
7435 /* Description: Right output gain adjustment */
7436 
7437 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
7438 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
7439 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
7440 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
7441 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
7442 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
7443 
7444 /* Register: PDM_PSEL_CLK */
7445 /* Description: Pin number configuration for PDM CLK signal */
7446 
7447 /* Bit 31 : Connection */
7448 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7449 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7450 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
7451 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7452 
7453 /* Bits 4..0 : Pin number */
7454 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
7455 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
7456 
7457 /* Register: PDM_PSEL_DIN */
7458 /* Description: Pin number configuration for PDM DIN signal */
7459 
7460 /* Bit 31 : Connection */
7461 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7462 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7463 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
7464 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
7465 
7466 /* Bits 4..0 : Pin number */
7467 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
7468 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
7469 
7470 /* Register: PDM_SAMPLE_PTR */
7471 /* Description: RAM address pointer to write samples to with EasyDMA */
7472 
7473 /* Bits 31..0 : Address to write PDM samples to over DMA */
7474 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
7475 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
7476 
7477 /* Register: PDM_SAMPLE_MAXCNT */
7478 /* Description: Number of samples to allocate memory for in EasyDMA mode */
7479 
7480 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
7481 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
7482 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
7483 
7484 
7485 /* Peripheral: POWER */
7486 /* Description: Power control */
7487 
7488 /* Register: POWER_TASKS_CONSTLAT */
7489 /* Description: Enable constant latency mode */
7490 
7491 /* Bit 0 : Enable constant latency mode */
7492 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
7493 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
7494 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
7495 
7496 /* Register: POWER_TASKS_LOWPWR */
7497 /* Description: Enable low power mode (variable latency) */
7498 
7499 /* Bit 0 : Enable low power mode (variable latency) */
7500 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
7501 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
7502 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
7503 
7504 /* Register: POWER_EVENTS_POFWARN */
7505 /* Description: Power failure warning */
7506 
7507 /* Bit 0 : Power failure warning */
7508 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
7509 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
7510 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
7511 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
7512 
7513 /* Register: POWER_EVENTS_SLEEPENTER */
7514 /* Description: CPU entered WFI/WFE sleep */
7515 
7516 /* Bit 0 : CPU entered WFI/WFE sleep */
7517 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
7518 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
7519 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
7520 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
7521 
7522 /* Register: POWER_EVENTS_SLEEPEXIT */
7523 /* Description: CPU exited WFI/WFE sleep */
7524 
7525 /* Bit 0 : CPU exited WFI/WFE sleep */
7526 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
7527 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
7528 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
7529 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
7530 
7531 /* Register: POWER_INTENSET */
7532 /* Description: Enable interrupt */
7533 
7534 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
7535 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
7536 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
7537 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
7538 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
7539 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
7540 
7541 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
7542 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
7543 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
7544 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
7545 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
7546 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
7547 
7548 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
7549 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
7550 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
7551 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
7552 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7553 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
7554 
7555 /* Register: POWER_INTENCLR */
7556 /* Description: Disable interrupt */
7557 
7558 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
7559 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
7560 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
7561 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
7562 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
7563 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
7564 
7565 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
7566 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
7567 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
7568 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
7569 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
7570 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
7571 
7572 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
7573 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
7574 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
7575 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
7576 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7577 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
7578 
7579 /* Register: POWER_RESETREAS */
7580 /* Description: Reset reason */
7581 
7582 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
7583 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
7584 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
7585 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
7586 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
7587 
7588 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
7589 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
7590 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
7591 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
7592 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
7593 
7594 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
7595 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
7596 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
7597 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
7598 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
7599 
7600 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
7601 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
7602 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
7603 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
7604 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
7605 
7606 /* Bit 3 : Reset from CPU lock-up detected */
7607 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
7608 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
7609 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
7610 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
7611 
7612 /* Bit 2 : Reset from soft reset detected */
7613 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
7614 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
7615 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
7616 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
7617 
7618 /* Bit 1 : Reset from watchdog detected */
7619 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
7620 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
7621 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
7622 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
7623 
7624 /* Bit 0 : Reset from pin-reset detected */
7625 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
7626 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
7627 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
7628 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
7629 
7630 /* Register: POWER_RAMSTATUS */
7631 /* Description: Deprecated register - RAM status register */
7632 
7633 /* Bit 3 : RAM block 3 is on or off/powering up */
7634 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
7635 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
7636 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
7637 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
7638 
7639 /* Bit 2 : RAM block 2 is on or off/powering up */
7640 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
7641 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
7642 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
7643 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
7644 
7645 /* Bit 1 : RAM block 1 is on or off/powering up */
7646 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
7647 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
7648 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
7649 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
7650 
7651 /* Bit 0 : RAM block 0 is on or off/powering up */
7652 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
7653 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
7654 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
7655 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
7656 
7657 /* Register: POWER_SYSTEMOFF */
7658 /* Description: System OFF register */
7659 
7660 /* Bit 0 : Enable System OFF mode */
7661 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
7662 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
7663 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
7664 
7665 /* Register: POWER_POFCON */
7666 /* Description: Power failure comparator configuration */
7667 
7668 /* Bits 4..1 : Power failure comparator threshold setting */
7669 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
7670 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
7671 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
7672 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
7673 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
7674 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
7675 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
7676 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
7677 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
7678 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
7679 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
7680 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
7681 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
7682 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
7683 
7684 /* Bit 0 : Enable or disable power failure comparator */
7685 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
7686 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
7687 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
7688 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
7689 
7690 /* Register: POWER_GPREGRET */
7691 /* Description: General purpose retention register */
7692 
7693 /* Bits 7..0 : General purpose retention register */
7694 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
7695 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
7696 
7697 /* Register: POWER_GPREGRET2 */
7698 /* Description: General purpose retention register */
7699 
7700 /* Bits 7..0 : General purpose retention register */
7701 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
7702 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
7703 
7704 /* Register: POWER_RAMON */
7705 /* Description: Deprecated register - RAM on/off register (this register is retained) */
7706 
7707 /* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
7708 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
7709 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
7710 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
7711 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
7712 
7713 /* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
7714 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
7715 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
7716 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
7717 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
7718 
7719 /* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
7720 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
7721 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
7722 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
7723 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
7724 
7725 /* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
7726 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
7727 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
7728 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
7729 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
7730 
7731 /* Register: POWER_RAMONB */
7732 /* Description: Deprecated register - RAM on/off register (this register is retained) */
7733 
7734 /* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
7735 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
7736 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
7737 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
7738 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
7739 
7740 /* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
7741 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
7742 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
7743 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
7744 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
7745 
7746 /* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
7747 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
7748 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
7749 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
7750 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
7751 
7752 /* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
7753 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
7754 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
7755 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
7756 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
7757 
7758 /* Register: POWER_DCDCEN */
7759 /* Description: DC/DC enable register */
7760 
7761 /* Bit 0 : Enable or disable DC/DC converter */
7762 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
7763 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
7764 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
7765 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
7766 
7767 /* Register: POWER_RAM_POWER */
7768 /* Description: Description cluster: RAMn power control register */
7769 
7770 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
7771 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7772 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7773 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
7774 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
7775 
7776 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
7777 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7778 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7779 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
7780 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
7781 
7782 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
7783 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7784 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7785 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
7786 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
7787 
7788 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
7789 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7790 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7791 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
7792 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
7793 
7794 /* Register: POWER_RAM_POWERSET */
7795 /* Description: Description cluster: RAMn power control set register */
7796 
7797 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7798 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7799 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7800 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
7801 
7802 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7803 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7804 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7805 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
7806 
7807 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
7808 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7809 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7810 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
7811 
7812 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
7813 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7814 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7815 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
7816 
7817 /* Register: POWER_RAM_POWERCLR */
7818 /* Description: Description cluster: RAMn power control clear register */
7819 
7820 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7821 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7822 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7823 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
7824 
7825 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7826 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7827 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7828 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
7829 
7830 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
7831 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7832 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7833 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
7834 
7835 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
7836 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7837 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7838 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
7839 
7840 
7841 /* Peripheral: PPI */
7842 /* Description: Programmable Peripheral Interconnect */
7843 
7844 /* Register: PPI_TASKS_CHG_EN */
7845 /* Description: Description cluster: Enable channel group n */
7846 
7847 /* Bit 0 : Enable channel group n */
7848 #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
7849 #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
7850 #define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
7851 
7852 /* Register: PPI_TASKS_CHG_DIS */
7853 /* Description: Description cluster: Disable channel group n */
7854 
7855 /* Bit 0 : Disable channel group n */
7856 #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
7857 #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
7858 #define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
7859 
7860 /* Register: PPI_CHEN */
7861 /* Description: Channel enable register */
7862 
7863 /* Bit 31 : Enable or disable channel 31 */
7864 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
7865 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
7866 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
7867 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
7868 
7869 /* Bit 30 : Enable or disable channel 30 */
7870 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
7871 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
7872 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
7873 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
7874 
7875 /* Bit 29 : Enable or disable channel 29 */
7876 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
7877 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
7878 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
7879 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
7880 
7881 /* Bit 28 : Enable or disable channel 28 */
7882 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
7883 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
7884 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
7885 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
7886 
7887 /* Bit 27 : Enable or disable channel 27 */
7888 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
7889 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
7890 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
7891 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
7892 
7893 /* Bit 26 : Enable or disable channel 26 */
7894 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
7895 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
7896 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
7897 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
7898 
7899 /* Bit 25 : Enable or disable channel 25 */
7900 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
7901 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
7902 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
7903 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
7904 
7905 /* Bit 24 : Enable or disable channel 24 */
7906 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
7907 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
7908 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
7909 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
7910 
7911 /* Bit 23 : Enable or disable channel 23 */
7912 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
7913 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
7914 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
7915 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
7916 
7917 /* Bit 22 : Enable or disable channel 22 */
7918 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
7919 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
7920 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
7921 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
7922 
7923 /* Bit 21 : Enable or disable channel 21 */
7924 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
7925 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
7926 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
7927 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
7928 
7929 /* Bit 20 : Enable or disable channel 20 */
7930 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
7931 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
7932 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
7933 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
7934 
7935 /* Bit 19 : Enable or disable channel 19 */
7936 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
7937 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
7938 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
7939 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
7940 
7941 /* Bit 18 : Enable or disable channel 18 */
7942 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
7943 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
7944 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
7945 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
7946 
7947 /* Bit 17 : Enable or disable channel 17 */
7948 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
7949 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
7950 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
7951 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
7952 
7953 /* Bit 16 : Enable or disable channel 16 */
7954 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
7955 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
7956 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
7957 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
7958 
7959 /* Bit 15 : Enable or disable channel 15 */
7960 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
7961 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
7962 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
7963 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
7964 
7965 /* Bit 14 : Enable or disable channel 14 */
7966 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
7967 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
7968 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
7969 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
7970 
7971 /* Bit 13 : Enable or disable channel 13 */
7972 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
7973 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
7974 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
7975 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
7976 
7977 /* Bit 12 : Enable or disable channel 12 */
7978 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
7979 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
7980 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
7981 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
7982 
7983 /* Bit 11 : Enable or disable channel 11 */
7984 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
7985 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
7986 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
7987 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
7988 
7989 /* Bit 10 : Enable or disable channel 10 */
7990 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
7991 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
7992 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
7993 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
7994 
7995 /* Bit 9 : Enable or disable channel 9 */
7996 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
7997 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
7998 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
7999 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
8000 
8001 /* Bit 8 : Enable or disable channel 8 */
8002 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
8003 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
8004 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
8005 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
8006 
8007 /* Bit 7 : Enable or disable channel 7 */
8008 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
8009 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
8010 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
8011 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
8012 
8013 /* Bit 6 : Enable or disable channel 6 */
8014 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
8015 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
8016 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
8017 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
8018 
8019 /* Bit 5 : Enable or disable channel 5 */
8020 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
8021 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
8022 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
8023 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
8024 
8025 /* Bit 4 : Enable or disable channel 4 */
8026 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
8027 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
8028 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
8029 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
8030 
8031 /* Bit 3 : Enable or disable channel 3 */
8032 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
8033 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
8034 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
8035 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
8036 
8037 /* Bit 2 : Enable or disable channel 2 */
8038 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
8039 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
8040 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
8041 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
8042 
8043 /* Bit 1 : Enable or disable channel 1 */
8044 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
8045 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
8046 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
8047 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
8048 
8049 /* Bit 0 : Enable or disable channel 0 */
8050 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
8051 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
8052 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
8053 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
8054 
8055 /* Register: PPI_CHENSET */
8056 /* Description: Channel enable set register */
8057 
8058 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
8059 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
8060 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
8061 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
8062 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
8063 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
8064 
8065 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
8066 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
8067 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
8068 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
8069 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
8070 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
8071 
8072 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
8073 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
8074 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
8075 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
8076 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
8077 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
8078 
8079 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
8080 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
8081 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
8082 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
8083 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
8084 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
8085 
8086 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
8087 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
8088 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
8089 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
8090 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
8091 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
8092 
8093 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
8094 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
8095 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
8096 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
8097 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
8098 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
8099 
8100 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
8101 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
8102 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
8103 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
8104 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
8105 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
8106 
8107 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
8108 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
8109 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
8110 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
8111 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
8112 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
8113 
8114 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
8115 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
8116 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
8117 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
8118 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
8119 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
8120 
8121 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
8122 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
8123 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
8124 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
8125 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
8126 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
8127 
8128 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
8129 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
8130 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
8131 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
8132 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
8133 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
8134 
8135 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
8136 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
8137 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
8138 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
8139 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
8140 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
8141 
8142 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
8143 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
8144 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
8145 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
8146 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
8147 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
8148 
8149 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
8150 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
8151 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
8152 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
8153 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
8154 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
8155 
8156 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
8157 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
8158 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
8159 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
8160 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
8161 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
8162 
8163 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
8164 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
8165 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
8166 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
8167 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
8168 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
8169 
8170 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
8171 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
8172 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
8173 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
8174 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
8175 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
8176 
8177 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
8178 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
8179 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
8180 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
8181 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
8182 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
8183 
8184 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
8185 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
8186 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
8187 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
8188 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
8189 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
8190 
8191 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
8192 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
8193 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
8194 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
8195 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
8196 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
8197 
8198 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
8199 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
8200 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
8201 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
8202 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
8203 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
8204 
8205 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
8206 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
8207 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
8208 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
8209 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
8210 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
8211 
8212 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
8213 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
8214 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
8215 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
8216 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
8217 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
8218 
8219 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
8220 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
8221 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
8222 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
8223 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
8224 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
8225 
8226 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
8227 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
8228 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
8229 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
8230 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
8231 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
8232 
8233 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
8234 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
8235 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
8236 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
8237 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
8238 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
8239 
8240 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
8241 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
8242 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
8243 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
8244 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
8245 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
8246 
8247 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
8248 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
8249 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
8250 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
8251 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
8252 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
8253 
8254 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
8255 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
8256 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
8257 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
8258 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
8259 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
8260 
8261 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
8262 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
8263 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
8264 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
8265 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
8266 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
8267 
8268 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
8269 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
8270 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
8271 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
8272 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
8273 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
8274 
8275 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
8276 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
8277 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
8278 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
8279 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
8280 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
8281 
8282 /* Register: PPI_CHENCLR */
8283 /* Description: Channel enable clear register */
8284 
8285 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
8286 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
8287 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
8288 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
8289 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
8290 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
8291 
8292 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
8293 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
8294 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
8295 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
8296 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
8297 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
8298 
8299 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
8300 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
8301 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
8302 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
8303 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
8304 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
8305 
8306 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
8307 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
8308 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
8309 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
8310 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
8311 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
8312 
8313 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
8314 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
8315 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
8316 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
8317 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
8318 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
8319 
8320 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
8321 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
8322 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
8323 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
8324 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
8325 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
8326 
8327 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
8328 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
8329 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
8330 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
8331 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
8332 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
8333 
8334 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
8335 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
8336 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
8337 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
8338 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
8339 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
8340 
8341 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
8342 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
8343 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
8344 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
8345 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
8346 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
8347 
8348 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
8349 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
8350 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
8351 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
8352 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
8353 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
8354 
8355 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
8356 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
8357 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
8358 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
8359 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
8360 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
8361 
8362 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
8363 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
8364 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
8365 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
8366 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
8367 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
8368 
8369 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
8370 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
8371 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
8372 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
8373 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
8374 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
8375 
8376 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
8377 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
8378 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
8379 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
8380 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
8381 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
8382 
8383 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
8384 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
8385 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
8386 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
8387 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
8388 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
8389 
8390 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
8391 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
8392 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
8393 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
8394 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
8395 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
8396 
8397 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
8398 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
8399 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
8400 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
8401 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
8402 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
8403 
8404 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
8405 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
8406 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
8407 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
8408 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
8409 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
8410 
8411 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
8412 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
8413 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
8414 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
8415 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
8416 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
8417 
8418 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
8419 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
8420 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
8421 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
8422 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
8423 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
8424 
8425 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
8426 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
8427 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
8428 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
8429 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
8430 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
8431 
8432 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
8433 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
8434 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
8435 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
8436 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
8437 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
8438 
8439 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
8440 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
8441 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
8442 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
8443 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
8444 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
8445 
8446 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
8447 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
8448 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
8449 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
8450 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
8451 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
8452 
8453 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
8454 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
8455 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
8456 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
8457 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
8458 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
8459 
8460 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
8461 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
8462 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
8463 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
8464 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
8465 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
8466 
8467 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
8468 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
8469 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
8470 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
8471 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
8472 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
8473 
8474 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
8475 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
8476 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
8477 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
8478 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
8479 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
8480 
8481 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
8482 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
8483 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
8484 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
8485 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
8486 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
8487 
8488 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
8489 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
8490 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
8491 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
8492 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
8493 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
8494 
8495 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
8496 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
8497 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
8498 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
8499 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
8500 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
8501 
8502 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
8503 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
8504 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
8505 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
8506 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
8507 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
8508 
8509 /* Register: PPI_CH_EEP */
8510 /* Description: Description cluster: Channel n event end-point */
8511 
8512 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
8513 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
8514 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
8515 
8516 /* Register: PPI_CH_TEP */
8517 /* Description: Description cluster: Channel n task end-point */
8518 
8519 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
8520 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
8521 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
8522 
8523 /* Register: PPI_CHG */
8524 /* Description: Description collection: Channel group n */
8525 
8526 /* Bit 31 : Include or exclude channel 31 */
8527 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
8528 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
8529 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
8530 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
8531 
8532 /* Bit 30 : Include or exclude channel 30 */
8533 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
8534 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
8535 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
8536 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
8537 
8538 /* Bit 29 : Include or exclude channel 29 */
8539 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
8540 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
8541 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
8542 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
8543 
8544 /* Bit 28 : Include or exclude channel 28 */
8545 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
8546 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
8547 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
8548 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
8549 
8550 /* Bit 27 : Include or exclude channel 27 */
8551 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
8552 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
8553 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
8554 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
8555 
8556 /* Bit 26 : Include or exclude channel 26 */
8557 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
8558 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
8559 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
8560 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
8561 
8562 /* Bit 25 : Include or exclude channel 25 */
8563 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
8564 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
8565 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
8566 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
8567 
8568 /* Bit 24 : Include or exclude channel 24 */
8569 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
8570 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
8571 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
8572 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
8573 
8574 /* Bit 23 : Include or exclude channel 23 */
8575 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
8576 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
8577 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
8578 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
8579 
8580 /* Bit 22 : Include or exclude channel 22 */
8581 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
8582 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
8583 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
8584 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
8585 
8586 /* Bit 21 : Include or exclude channel 21 */
8587 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
8588 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
8589 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
8590 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
8591 
8592 /* Bit 20 : Include or exclude channel 20 */
8593 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
8594 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
8595 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
8596 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
8597 
8598 /* Bit 19 : Include or exclude channel 19 */
8599 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
8600 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
8601 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
8602 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
8603 
8604 /* Bit 18 : Include or exclude channel 18 */
8605 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
8606 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
8607 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
8608 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
8609 
8610 /* Bit 17 : Include or exclude channel 17 */
8611 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
8612 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
8613 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
8614 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
8615 
8616 /* Bit 16 : Include or exclude channel 16 */
8617 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
8618 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
8619 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
8620 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
8621 
8622 /* Bit 15 : Include or exclude channel 15 */
8623 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
8624 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
8625 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
8626 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
8627 
8628 /* Bit 14 : Include or exclude channel 14 */
8629 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
8630 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
8631 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
8632 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
8633 
8634 /* Bit 13 : Include or exclude channel 13 */
8635 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
8636 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
8637 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
8638 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
8639 
8640 /* Bit 12 : Include or exclude channel 12 */
8641 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
8642 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
8643 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
8644 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
8645 
8646 /* Bit 11 : Include or exclude channel 11 */
8647 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
8648 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
8649 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
8650 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
8651 
8652 /* Bit 10 : Include or exclude channel 10 */
8653 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
8654 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
8655 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
8656 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
8657 
8658 /* Bit 9 : Include or exclude channel 9 */
8659 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
8660 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
8661 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
8662 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
8663 
8664 /* Bit 8 : Include or exclude channel 8 */
8665 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
8666 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
8667 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
8668 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
8669 
8670 /* Bit 7 : Include or exclude channel 7 */
8671 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
8672 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
8673 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
8674 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
8675 
8676 /* Bit 6 : Include or exclude channel 6 */
8677 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
8678 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
8679 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
8680 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
8681 
8682 /* Bit 5 : Include or exclude channel 5 */
8683 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
8684 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
8685 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
8686 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
8687 
8688 /* Bit 4 : Include or exclude channel 4 */
8689 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
8690 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
8691 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
8692 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
8693 
8694 /* Bit 3 : Include or exclude channel 3 */
8695 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
8696 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
8697 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
8698 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
8699 
8700 /* Bit 2 : Include or exclude channel 2 */
8701 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
8702 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
8703 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
8704 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
8705 
8706 /* Bit 1 : Include or exclude channel 1 */
8707 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
8708 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
8709 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
8710 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
8711 
8712 /* Bit 0 : Include or exclude channel 0 */
8713 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
8714 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
8715 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
8716 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
8717 
8718 /* Register: PPI_FORK_TEP */
8719 /* Description: Description cluster: Channel n task end-point */
8720 
8721 /* Bits 31..0 : Pointer to task register */
8722 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
8723 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
8724 
8725 
8726 /* Peripheral: PWM */
8727 /* Description: Pulse Width Modulation Unit 0 */
8728 
8729 /* Register: PWM_TASKS_STOP */
8730 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
8731 
8732 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
8733 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8734 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8735 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8736 
8737 /* Register: PWM_TASKS_SEQSTART */
8738 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. */
8739 
8740 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running. */
8741 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
8742 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
8743 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
8744 
8745 /* Register: PWM_TASKS_NEXTSTEP */
8746 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running. */
8747 
8748 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running. */
8749 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
8750 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
8751 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
8752 
8753 /* Register: PWM_EVENTS_STOPPED */
8754 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
8755 
8756 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
8757 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8758 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8759 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8760 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8761 
8762 /* Register: PWM_EVENTS_SEQSTARTED */
8763 /* Description: Description collection: First PWM period started on sequence n */
8764 
8765 /* Bit 0 : First PWM period started on sequence n */
8766 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
8767 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
8768 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
8769 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
8770 
8771 /* Register: PWM_EVENTS_SEQEND */
8772 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
8773 
8774 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
8775 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
8776 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
8777 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
8778 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
8779 
8780 /* Register: PWM_EVENTS_PWMPERIODEND */
8781 /* Description: Emitted at the end of each PWM period */
8782 
8783 /* Bit 0 : Emitted at the end of each PWM period */
8784 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
8785 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
8786 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
8787 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
8788 
8789 /* Register: PWM_EVENTS_LOOPSDONE */
8790 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
8791 
8792 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
8793 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
8794 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
8795 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
8796 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
8797 
8798 /* Register: PWM_SHORTS */
8799 /* Description: Shortcuts between local events and tasks */
8800 
8801 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
8802 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
8803 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
8804 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
8805 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
8806 
8807 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
8808 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
8809 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
8810 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
8811 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
8812 
8813 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
8814 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
8815 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
8816 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
8817 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
8818 
8819 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
8820 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
8821 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
8822 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
8823 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
8824 
8825 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
8826 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
8827 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
8828 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
8829 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
8830 
8831 /* Register: PWM_INTEN */
8832 /* Description: Enable or disable interrupt */
8833 
8834 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
8835 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8836 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8837 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
8838 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
8839 
8840 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
8841 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8842 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8843 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
8844 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
8845 
8846 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
8847 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8848 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8849 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
8850 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
8851 
8852 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
8853 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8854 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8855 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
8856 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
8857 
8858 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
8859 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8860 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8861 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
8862 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
8863 
8864 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
8865 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8866 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8867 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
8868 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
8869 
8870 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8871 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8872 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8873 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8874 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8875 
8876 /* Register: PWM_INTENSET */
8877 /* Description: Enable interrupt */
8878 
8879 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
8880 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8881 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8882 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8883 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8884 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
8885 
8886 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
8887 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8888 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8889 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8890 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8891 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
8892 
8893 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
8894 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8895 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8896 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8897 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8898 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
8899 
8900 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
8901 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8902 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8903 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8904 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8905 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
8906 
8907 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
8908 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8909 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8910 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8911 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8912 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
8913 
8914 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
8915 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8916 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8917 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8918 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8919 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
8920 
8921 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
8922 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8923 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8924 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8925 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8926 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8927 
8928 /* Register: PWM_INTENCLR */
8929 /* Description: Disable interrupt */
8930 
8931 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
8932 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8933 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8934 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8935 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8936 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
8937 
8938 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
8939 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8940 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8941 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8942 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8943 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
8944 
8945 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
8946 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8947 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8948 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8949 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8950 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
8951 
8952 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
8953 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8954 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8955 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8956 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8957 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
8958 
8959 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
8960 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8961 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8962 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8963 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8964 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
8965 
8966 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
8967 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8968 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8969 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8970 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8971 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
8972 
8973 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
8974 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8975 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8976 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8977 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8978 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8979 
8980 /* Register: PWM_ENABLE */
8981 /* Description: PWM module enable register */
8982 
8983 /* Bit 0 : Enable or disable PWM module */
8984 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8985 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8986 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
8987 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8988 
8989 /* Register: PWM_MODE */
8990 /* Description: Selects operating mode of the wave counter */
8991 
8992 /* Bit 0 : Selects up or up and down as wave counter mode */
8993 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
8994 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
8995 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
8996 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
8997 
8998 /* Register: PWM_COUNTERTOP */
8999 /* Description: Value up to which the pulse generator counter counts */
9000 
9001 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
9002 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
9003 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
9004 
9005 /* Register: PWM_PRESCALER */
9006 /* Description: Configuration for PWM_CLK */
9007 
9008 /* Bits 2..0 : Pre-scaler of PWM_CLK */
9009 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
9010 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
9011 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */
9012 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
9013 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */
9014 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */
9015 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */
9016 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by  32 ( 500kHz) */
9017 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by  64 ( 250kHz) */
9018 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
9019 
9020 /* Register: PWM_DECODER */
9021 /* Description: Configuration of the decoder */
9022 
9023 /* Bit 8 : Selects source for advancing the active sequence */
9024 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
9025 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
9026 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
9027 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
9028 
9029 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
9030 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
9031 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
9032 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
9033 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
9034 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
9035 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
9036 
9037 /* Register: PWM_LOOP */
9038 /* Description: Amount of playback of a loop */
9039 
9040 /* Bits 15..0 : Amount of playback of pattern cycles */
9041 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
9042 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
9043 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
9044 
9045 /* Register: PWM_SEQ_PTR */
9046 /* Description: Description cluster: Beginning address in Data RAM of this sequence */
9047 
9048 /* Bits 31..0 : Beginning address in Data RAM of this sequence */
9049 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9050 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9051 
9052 /* Register: PWM_SEQ_CNT */
9053 /* Description: Description cluster: Amount of values (duty cycles) in this sequence */
9054 
9055 /* Bits 14..0 : Amount of values (duty cycles) in this sequence */
9056 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
9057 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
9058 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
9059 
9060 /* Register: PWM_SEQ_REFRESH */
9061 /* Description: Description cluster: Amount of additional PWM periods between samples loaded into compare register */
9062 
9063 /* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
9064 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
9065 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
9066 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
9067 
9068 /* Register: PWM_SEQ_ENDDELAY */
9069 /* Description: Description cluster: Time added after the sequence */
9070 
9071 /* Bits 23..0 : Time added after the sequence in PWM periods */
9072 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
9073 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
9074 
9075 /* Register: PWM_PSEL_OUT */
9076 /* Description: Description collection: Output pin select for PWM channel n */
9077 
9078 /* Bit 31 : Connection */
9079 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9080 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9081 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
9082 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
9083 
9084 /* Bits 4..0 : Pin number */
9085 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
9086 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
9087 
9088 
9089 /* Peripheral: QDEC */
9090 /* Description: Quadrature Decoder */
9091 
9092 /* Register: QDEC_TASKS_START */
9093 /* Description: Task starting the quadrature decoder */
9094 
9095 /* Bit 0 : Task starting the quadrature decoder */
9096 #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
9097 #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
9098 #define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
9099 
9100 /* Register: QDEC_TASKS_STOP */
9101 /* Description: Task stopping the quadrature decoder */
9102 
9103 /* Bit 0 : Task stopping the quadrature decoder */
9104 #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9105 #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9106 #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9107 
9108 /* Register: QDEC_TASKS_READCLRACC */
9109 /* Description: Read and clear ACC and ACCDBL */
9110 
9111 /* Bit 0 : Read and clear ACC and ACCDBL */
9112 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
9113 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
9114 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */
9115 
9116 /* Register: QDEC_TASKS_RDCLRACC */
9117 /* Description: Read and clear ACC */
9118 
9119 /* Bit 0 : Read and clear ACC */
9120 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
9121 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
9122 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */
9123 
9124 /* Register: QDEC_TASKS_RDCLRDBL */
9125 /* Description: Read and clear ACCDBL */
9126 
9127 /* Bit 0 : Read and clear ACCDBL */
9128 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
9129 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
9130 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */
9131 
9132 /* Register: QDEC_EVENTS_SAMPLERDY */
9133 /* Description: Event being generated for every new sample value written to the SAMPLE register */
9134 
9135 /* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
9136 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
9137 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
9138 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */
9139 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */
9140 
9141 /* Register: QDEC_EVENTS_REPORTRDY */
9142 /* Description: Non-null report ready */
9143 
9144 /* Bit 0 : Non-null report ready */
9145 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
9146 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
9147 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */
9148 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */
9149 
9150 /* Register: QDEC_EVENTS_ACCOF */
9151 /* Description: ACC or ACCDBL register overflow */
9152 
9153 /* Bit 0 : ACC or ACCDBL register overflow */
9154 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
9155 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
9156 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */
9157 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */
9158 
9159 /* Register: QDEC_EVENTS_DBLRDY */
9160 /* Description: Double displacement(s) detected */
9161 
9162 /* Bit 0 : Double displacement(s) detected */
9163 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
9164 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
9165 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */
9166 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */
9167 
9168 /* Register: QDEC_EVENTS_STOPPED */
9169 /* Description: QDEC has been stopped */
9170 
9171 /* Bit 0 : QDEC has been stopped */
9172 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9173 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9174 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9175 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9176 
9177 /* Register: QDEC_SHORTS */
9178 /* Description: Shortcuts between local events and tasks */
9179 
9180 /* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
9181 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
9182 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
9183 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9184 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9185 
9186 /* Bit 5 : Shortcut between event DBLRDY and task STOP */
9187 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
9188 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
9189 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9190 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9191 
9192 /* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
9193 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
9194 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
9195 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
9196 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
9197 
9198 /* Bit 3 : Shortcut between event REPORTRDY and task STOP */
9199 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
9200 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
9201 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9202 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9203 
9204 /* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
9205 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
9206 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
9207 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
9208 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
9209 
9210 /* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
9211 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
9212 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
9213 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9214 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9215 
9216 /* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
9217 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
9218 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
9219 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
9220 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
9221 
9222 /* Register: QDEC_INTENSET */
9223 /* Description: Enable interrupt */
9224 
9225 /* Bit 4 : Write '1' to enable interrupt for event STOPPED */
9226 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
9227 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9228 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9229 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9230 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9231 
9232 /* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
9233 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
9234 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
9235 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9236 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9237 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
9238 
9239 /* Bit 2 : Write '1' to enable interrupt for event ACCOF */
9240 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9241 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
9242 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9243 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9244 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
9245 
9246 /* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
9247 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
9248 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
9249 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9250 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9251 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
9252 
9253 /* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
9254 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
9255 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
9256 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9257 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9258 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
9259 
9260 /* Register: QDEC_INTENCLR */
9261 /* Description: Disable interrupt */
9262 
9263 /* Bit 4 : Write '1' to disable interrupt for event STOPPED */
9264 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
9265 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9266 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9267 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9268 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9269 
9270 /* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
9271 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
9272 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
9273 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9274 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9275 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
9276 
9277 /* Bit 2 : Write '1' to disable interrupt for event ACCOF */
9278 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
9279 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
9280 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9281 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9282 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
9283 
9284 /* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
9285 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
9286 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
9287 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9288 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9289 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
9290 
9291 /* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
9292 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
9293 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
9294 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9295 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9296 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
9297 
9298 /* Register: QDEC_ENABLE */
9299 /* Description: Enable the quadrature decoder */
9300 
9301 /* Bit 0 : Enable or disable the quadrature decoder */
9302 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9303 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9304 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
9305 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
9306 
9307 /* Register: QDEC_LEDPOL */
9308 /* Description: LED output pin polarity */
9309 
9310 /* Bit 0 : LED output pin polarity */
9311 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
9312 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
9313 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
9314 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
9315 
9316 /* Register: QDEC_SAMPLEPER */
9317 /* Description: Sample period */
9318 
9319 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
9320 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
9321 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
9322 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
9323 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
9324 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
9325 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
9326 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
9327 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
9328 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
9329 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
9330 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
9331 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
9332 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
9333 
9334 /* Register: QDEC_SAMPLE */
9335 /* Description: Motion sample value */
9336 
9337 /* Bits 31..0 : Last motion sample */
9338 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
9339 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
9340 
9341 /* Register: QDEC_REPORTPER */
9342 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
9343 
9344 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
9345 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
9346 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
9347 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
9348 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
9349 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
9350 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
9351 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
9352 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
9353 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
9354 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
9355 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
9356 
9357 /* Register: QDEC_ACC */
9358 /* Description: Register accumulating the valid transitions */
9359 
9360 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
9361 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
9362 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
9363 
9364 /* Register: QDEC_ACCREAD */
9365 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
9366 
9367 /* Bits 31..0 : Snapshot of the ACC register. */
9368 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
9369 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
9370 
9371 /* Register: QDEC_PSEL_LED */
9372 /* Description: Pin select for LED signal */
9373 
9374 /* Bit 31 : Connection */
9375 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9376 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9377 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
9378 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
9379 
9380 /* Bits 4..0 : Pin number */
9381 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
9382 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
9383 
9384 /* Register: QDEC_PSEL_A */
9385 /* Description: Pin select for A signal */
9386 
9387 /* Bit 31 : Connection */
9388 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9389 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9390 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
9391 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
9392 
9393 /* Bits 4..0 : Pin number */
9394 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
9395 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
9396 
9397 /* Register: QDEC_PSEL_B */
9398 /* Description: Pin select for B signal */
9399 
9400 /* Bit 31 : Connection */
9401 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9402 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9403 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
9404 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
9405 
9406 /* Bits 4..0 : Pin number */
9407 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
9408 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
9409 
9410 /* Register: QDEC_DBFEN */
9411 /* Description: Enable input debounce filters */
9412 
9413 /* Bit 0 : Enable input debounce filters */
9414 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
9415 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
9416 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
9417 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
9418 
9419 /* Register: QDEC_LEDPRE */
9420 /* Description: Time period the LED is switched ON prior to sampling */
9421 
9422 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
9423 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
9424 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
9425 
9426 /* Register: QDEC_ACCDBL */
9427 /* Description: Register accumulating the number of detected double transitions */
9428 
9429 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
9430 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
9431 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
9432 
9433 /* Register: QDEC_ACCDBLREAD */
9434 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
9435 
9436 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
9437 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
9438 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
9439 
9440 
9441 /* Peripheral: RADIO */
9442 /* Description: 2.4 GHz Radio */
9443 
9444 /* Register: RADIO_TASKS_TXEN */
9445 /* Description: Enable RADIO in TX mode */
9446 
9447 /* Bit 0 : Enable RADIO in TX mode */
9448 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
9449 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
9450 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
9451 
9452 /* Register: RADIO_TASKS_RXEN */
9453 /* Description: Enable RADIO in RX mode */
9454 
9455 /* Bit 0 : Enable RADIO in RX mode */
9456 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
9457 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
9458 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
9459 
9460 /* Register: RADIO_TASKS_START */
9461 /* Description: Start RADIO */
9462 
9463 /* Bit 0 : Start RADIO */
9464 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
9465 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
9466 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
9467 
9468 /* Register: RADIO_TASKS_STOP */
9469 /* Description: Stop RADIO */
9470 
9471 /* Bit 0 : Stop RADIO */
9472 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9473 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9474 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9475 
9476 /* Register: RADIO_TASKS_DISABLE */
9477 /* Description: Disable RADIO */
9478 
9479 /* Bit 0 : Disable RADIO */
9480 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
9481 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
9482 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
9483 
9484 /* Register: RADIO_TASKS_RSSISTART */
9485 /* Description: Start the RSSI and take one single sample of the receive signal strength. */
9486 
9487 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength. */
9488 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
9489 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
9490 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
9491 
9492 /* Register: RADIO_TASKS_RSSISTOP */
9493 /* Description: Stop the RSSI measurement */
9494 
9495 /* Bit 0 : Stop the RSSI measurement */
9496 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
9497 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
9498 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
9499 
9500 /* Register: RADIO_TASKS_BCSTART */
9501 /* Description: Start the bit counter */
9502 
9503 /* Bit 0 : Start the bit counter */
9504 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
9505 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
9506 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
9507 
9508 /* Register: RADIO_TASKS_BCSTOP */
9509 /* Description: Stop the bit counter */
9510 
9511 /* Bit 0 : Stop the bit counter */
9512 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
9513 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
9514 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
9515 
9516 /* Register: RADIO_EVENTS_READY */
9517 /* Description: RADIO has ramped up and is ready to be started */
9518 
9519 /* Bit 0 : RADIO has ramped up and is ready to be started */
9520 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
9521 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
9522 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
9523 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
9524 
9525 /* Register: RADIO_EVENTS_ADDRESS */
9526 /* Description: Address sent or received */
9527 
9528 /* Bit 0 : Address sent or received */
9529 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
9530 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
9531 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
9532 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
9533 
9534 /* Register: RADIO_EVENTS_PAYLOAD */
9535 /* Description: Packet payload sent or received */
9536 
9537 /* Bit 0 : Packet payload sent or received */
9538 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
9539 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
9540 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
9541 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
9542 
9543 /* Register: RADIO_EVENTS_END */
9544 /* Description: Packet sent or received */
9545 
9546 /* Bit 0 : Packet sent or received */
9547 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
9548 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
9549 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
9550 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
9551 
9552 /* Register: RADIO_EVENTS_DISABLED */
9553 /* Description: RADIO has been disabled */
9554 
9555 /* Bit 0 : RADIO has been disabled */
9556 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
9557 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
9558 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
9559 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
9560 
9561 /* Register: RADIO_EVENTS_DEVMATCH */
9562 /* Description: A device address match occurred on the last received packet */
9563 
9564 /* Bit 0 : A device address match occurred on the last received packet */
9565 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
9566 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
9567 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
9568 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
9569 
9570 /* Register: RADIO_EVENTS_DEVMISS */
9571 /* Description: No device address match occurred on the last received packet */
9572 
9573 /* Bit 0 : No device address match occurred on the last received packet */
9574 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
9575 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
9576 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
9577 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
9578 
9579 /* Register: RADIO_EVENTS_RSSIEND */
9580 /* Description: Sampling of receive signal strength complete. */
9581 
9582 /* Bit 0 : Sampling of receive signal strength complete. */
9583 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
9584 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
9585 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
9586 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
9587 
9588 /* Register: RADIO_EVENTS_BCMATCH */
9589 /* Description: Bit counter reached bit count value. */
9590 
9591 /* Bit 0 : Bit counter reached bit count value. */
9592 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
9593 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
9594 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
9595 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
9596 
9597 /* Register: RADIO_EVENTS_CRCOK */
9598 /* Description: Packet received with CRC ok */
9599 
9600 /* Bit 0 : Packet received with CRC ok */
9601 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
9602 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
9603 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
9604 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
9605 
9606 /* Register: RADIO_EVENTS_CRCERROR */
9607 /* Description: Packet received with CRC error */
9608 
9609 /* Bit 0 : Packet received with CRC error */
9610 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
9611 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
9612 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
9613 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
9614 
9615 /* Register: RADIO_SHORTS */
9616 /* Description: Shortcuts between local events and tasks */
9617 
9618 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
9619 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
9620 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
9621 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
9622 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
9623 
9624 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
9625 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
9626 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
9627 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
9628 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
9629 
9630 /* Bit 5 : Shortcut between event END and task START */
9631 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
9632 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
9633 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
9634 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
9635 
9636 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
9637 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
9638 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
9639 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
9640 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
9641 
9642 /* Bit 3 : Shortcut between event DISABLED and task RXEN */
9643 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
9644 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
9645 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
9646 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
9647 
9648 /* Bit 2 : Shortcut between event DISABLED and task TXEN */
9649 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
9650 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
9651 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
9652 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
9653 
9654 /* Bit 1 : Shortcut between event END and task DISABLE */
9655 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
9656 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
9657 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
9658 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
9659 
9660 /* Bit 0 : Shortcut between event READY and task START */
9661 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
9662 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
9663 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
9664 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
9665 
9666 /* Register: RADIO_INTENSET */
9667 /* Description: Enable interrupt */
9668 
9669 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
9670 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
9671 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
9672 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
9673 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
9674 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
9675 
9676 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */
9677 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
9678 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
9679 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
9680 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
9681 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
9682 
9683 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
9684 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
9685 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
9686 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
9687 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
9688 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
9689 
9690 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
9691 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
9692 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
9693 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
9694 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
9695 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
9696 
9697 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
9698 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
9699 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
9700 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
9701 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
9702 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
9703 
9704 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
9705 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
9706 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
9707 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
9708 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
9709 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
9710 
9711 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */
9712 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
9713 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
9714 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
9715 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
9716 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
9717 
9718 /* Bit 3 : Write '1' to enable interrupt for event END */
9719 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
9720 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
9721 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
9722 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
9723 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
9724 
9725 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
9726 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
9727 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
9728 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
9729 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
9730 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
9731 
9732 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
9733 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
9734 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9735 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
9736 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
9737 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
9738 
9739 /* Bit 0 : Write '1' to enable interrupt for event READY */
9740 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
9741 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
9742 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
9743 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
9744 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
9745 
9746 /* Register: RADIO_INTENCLR */
9747 /* Description: Disable interrupt */
9748 
9749 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
9750 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
9751 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
9752 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
9753 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
9754 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
9755 
9756 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */
9757 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
9758 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
9759 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
9760 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
9761 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
9762 
9763 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
9764 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
9765 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
9766 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
9767 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
9768 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
9769 
9770 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
9771 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
9772 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
9773 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
9774 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
9775 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
9776 
9777 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
9778 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
9779 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
9780 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
9781 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
9782 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
9783 
9784 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
9785 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
9786 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
9787 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
9788 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
9789 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
9790 
9791 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */
9792 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
9793 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
9794 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
9795 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
9796 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
9797 
9798 /* Bit 3 : Write '1' to disable interrupt for event END */
9799 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
9800 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
9801 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
9802 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
9803 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
9804 
9805 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
9806 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
9807 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
9808 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
9809 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
9810 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
9811 
9812 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
9813 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
9814 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9815 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
9816 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
9817 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
9818 
9819 /* Bit 0 : Write '1' to disable interrupt for event READY */
9820 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
9821 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
9822 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
9823 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
9824 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
9825 
9826 /* Register: RADIO_CRCSTATUS */
9827 /* Description: CRC status */
9828 
9829 /* Bit 0 : CRC status of packet received */
9830 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
9831 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
9832 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
9833 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
9834 
9835 /* Register: RADIO_RXMATCH */
9836 /* Description: Received address */
9837 
9838 /* Bits 2..0 : Received address */
9839 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
9840 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
9841 
9842 /* Register: RADIO_RXCRC */
9843 /* Description: CRC field of previously received packet */
9844 
9845 /* Bits 23..0 : CRC field of previously received packet */
9846 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
9847 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
9848 
9849 /* Register: RADIO_DAI */
9850 /* Description: Device address match index */
9851 
9852 /* Bits 2..0 : Device address match index */
9853 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
9854 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
9855 
9856 /* Register: RADIO_PACKETPTR */
9857 /* Description: Packet pointer */
9858 
9859 /* Bits 31..0 : Packet pointer */
9860 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
9861 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
9862 
9863 /* Register: RADIO_FREQUENCY */
9864 /* Description: Frequency */
9865 
9866 /* Bit 8 : Channel map selection. */
9867 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
9868 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
9869 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
9870 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
9871 
9872 /* Bits 6..0 : Radio channel frequency */
9873 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
9874 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
9875 
9876 /* Register: RADIO_TXPOWER */
9877 /* Description: Output power */
9878 
9879 /* Bits 7..0 : RADIO output power. */
9880 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
9881 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
9882 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
9883 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
9884 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
9885 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
9886 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
9887 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
9888 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
9889 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
9890 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
9891 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator -  -40 dBm */
9892 
9893 /* Register: RADIO_MODE */
9894 /* Description: Data rate and modulation */
9895 
9896 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
9897 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
9898 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
9899 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
9900 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
9901 #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode */
9902 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
9903 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */
9904 
9905 /* Register: RADIO_PCNF0 */
9906 /* Description: Packet configuration register 0 */
9907 
9908 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
9909 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
9910 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
9911 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
9912 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
9913 
9914 /* Bit 20 : Include or exclude S1 field in RAM */
9915 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
9916 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
9917 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
9918 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
9919 
9920 /* Bits 19..16 : Length on air of S1 field in number of bits. */
9921 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
9922 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
9923 
9924 /* Bit 8 : Length on air of S0 field in number of bytes. */
9925 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
9926 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
9927 
9928 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
9929 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
9930 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
9931 
9932 /* Register: RADIO_PCNF1 */
9933 /* Description: Packet configuration register 1 */
9934 
9935 /* Bit 25 : Enable or disable packet whitening */
9936 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
9937 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
9938 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
9939 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
9940 
9941 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
9942 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
9943 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
9944 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
9945 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
9946 
9947 /* Bits 18..16 : Base address length in number of bytes */
9948 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
9949 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
9950 
9951 /* Bits 15..8 : Static length in number of bytes */
9952 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
9953 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
9954 
9955 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
9956 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
9957 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
9958 
9959 /* Register: RADIO_BASE0 */
9960 /* Description: Base address 0 */
9961 
9962 /* Bits 31..0 : Base address 0 */
9963 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
9964 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
9965 
9966 /* Register: RADIO_BASE1 */
9967 /* Description: Base address 1 */
9968 
9969 /* Bits 31..0 : Base address 1 */
9970 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
9971 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
9972 
9973 /* Register: RADIO_PREFIX0 */
9974 /* Description: Prefixes bytes for logical addresses 0-3 */
9975 
9976 /* Bits 31..24 : Address prefix 3. */
9977 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
9978 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
9979 
9980 /* Bits 23..16 : Address prefix 2. */
9981 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
9982 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
9983 
9984 /* Bits 15..8 : Address prefix 1. */
9985 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
9986 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
9987 
9988 /* Bits 7..0 : Address prefix 0. */
9989 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
9990 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
9991 
9992 /* Register: RADIO_PREFIX1 */
9993 /* Description: Prefixes bytes for logical addresses 4-7 */
9994 
9995 /* Bits 31..24 : Address prefix 7. */
9996 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
9997 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
9998 
9999 /* Bits 23..16 : Address prefix 6. */
10000 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
10001 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
10002 
10003 /* Bits 15..8 : Address prefix 5. */
10004 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
10005 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
10006 
10007 /* Bits 7..0 : Address prefix 4. */
10008 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
10009 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
10010 
10011 /* Register: RADIO_TXADDRESS */
10012 /* Description: Transmit address select */
10013 
10014 /* Bits 2..0 : Transmit address select */
10015 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
10016 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
10017 
10018 /* Register: RADIO_RXADDRESSES */
10019 /* Description: Receive address select */
10020 
10021 /* Bit 7 : Enable or disable reception on logical address 7. */
10022 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
10023 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
10024 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
10025 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
10026 
10027 /* Bit 6 : Enable or disable reception on logical address 6. */
10028 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
10029 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
10030 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
10031 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
10032 
10033 /* Bit 5 : Enable or disable reception on logical address 5. */
10034 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
10035 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
10036 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
10037 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
10038 
10039 /* Bit 4 : Enable or disable reception on logical address 4. */
10040 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
10041 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
10042 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
10043 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
10044 
10045 /* Bit 3 : Enable or disable reception on logical address 3. */
10046 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
10047 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
10048 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
10049 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
10050 
10051 /* Bit 2 : Enable or disable reception on logical address 2. */
10052 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
10053 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
10054 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
10055 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
10056 
10057 /* Bit 1 : Enable or disable reception on logical address 1. */
10058 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
10059 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
10060 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
10061 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
10062 
10063 /* Bit 0 : Enable or disable reception on logical address 0. */
10064 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
10065 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
10066 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
10067 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
10068 
10069 /* Register: RADIO_CRCCNF */
10070 /* Description: CRC configuration */
10071 
10072 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */
10073 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
10074 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
10075 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
10076 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
10077 
10078 /* Bits 1..0 : CRC length in number of bytes. */
10079 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
10080 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
10081 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
10082 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
10083 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
10084 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
10085 
10086 /* Register: RADIO_CRCPOLY */
10087 /* Description: CRC polynomial */
10088 
10089 /* Bits 23..0 : CRC polynomial */
10090 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
10091 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
10092 
10093 /* Register: RADIO_CRCINIT */
10094 /* Description: CRC initial value */
10095 
10096 /* Bits 23..0 : CRC initial value */
10097 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
10098 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
10099 
10100 /* Register: RADIO_TIFS */
10101 /* Description: Inter Frame Spacing in us */
10102 
10103 /* Bits 7..0 : Inter Frame Spacing in us */
10104 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
10105 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
10106 
10107 /* Register: RADIO_RSSISAMPLE */
10108 /* Description: RSSI sample */
10109 
10110 /* Bits 6..0 : RSSI sample */
10111 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
10112 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
10113 
10114 /* Register: RADIO_STATE */
10115 /* Description: Current radio state */
10116 
10117 /* Bits 3..0 : Current radio state */
10118 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
10119 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
10120 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
10121 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
10122 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
10123 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
10124 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
10125 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
10126 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
10127 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
10128 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
10129 
10130 /* Register: RADIO_DATAWHITEIV */
10131 /* Description: Data whitening initial value */
10132 
10133 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
10134 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
10135 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
10136 
10137 /* Register: RADIO_BCC */
10138 /* Description: Bit counter compare */
10139 
10140 /* Bits 31..0 : Bit counter compare */
10141 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
10142 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
10143 
10144 /* Register: RADIO_DAB */
10145 /* Description: Description collection: Device address base segment n */
10146 
10147 /* Bits 31..0 : Device address base segment n */
10148 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
10149 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
10150 
10151 /* Register: RADIO_DAP */
10152 /* Description: Description collection: Device address prefix n */
10153 
10154 /* Bits 15..0 : Device address prefix n */
10155 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
10156 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
10157 
10158 /* Register: RADIO_DACNF */
10159 /* Description: Device address match configuration */
10160 
10161 /* Bit 15 : TxAdd for device address 7 */
10162 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
10163 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
10164 
10165 /* Bit 14 : TxAdd for device address 6 */
10166 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
10167 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
10168 
10169 /* Bit 13 : TxAdd for device address 5 */
10170 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
10171 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
10172 
10173 /* Bit 12 : TxAdd for device address 4 */
10174 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
10175 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
10176 
10177 /* Bit 11 : TxAdd for device address 3 */
10178 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
10179 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
10180 
10181 /* Bit 10 : TxAdd for device address 2 */
10182 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
10183 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
10184 
10185 /* Bit 9 : TxAdd for device address 1 */
10186 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
10187 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
10188 
10189 /* Bit 8 : TxAdd for device address 0 */
10190 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
10191 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
10192 
10193 /* Bit 7 : Enable or disable device address matching using device address 7 */
10194 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
10195 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
10196 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
10197 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
10198 
10199 /* Bit 6 : Enable or disable device address matching using device address 6 */
10200 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
10201 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
10202 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
10203 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
10204 
10205 /* Bit 5 : Enable or disable device address matching using device address 5 */
10206 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
10207 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
10208 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
10209 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
10210 
10211 /* Bit 4 : Enable or disable device address matching using device address 4 */
10212 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
10213 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
10214 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
10215 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
10216 
10217 /* Bit 3 : Enable or disable device address matching using device address 3 */
10218 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
10219 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
10220 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
10221 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
10222 
10223 /* Bit 2 : Enable or disable device address matching using device address 2 */
10224 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
10225 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
10226 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
10227 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
10228 
10229 /* Bit 1 : Enable or disable device address matching using device address 1 */
10230 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
10231 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
10232 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
10233 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
10234 
10235 /* Bit 0 : Enable or disable device address matching using device address 0 */
10236 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
10237 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
10238 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
10239 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
10240 
10241 /* Register: RADIO_MODECNF0 */
10242 /* Description: Radio mode configuration register 0 */
10243 
10244 /* Bits 9..8 : Default TX value */
10245 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
10246 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
10247 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
10248 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
10249 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
10250 
10251 /* Bit 0 : Radio ramp-up time */
10252 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
10253 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
10254 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
10255 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
10256 
10257 /* Register: RADIO_POWER */
10258 /* Description: Peripheral power control */
10259 
10260 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
10261 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
10262 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
10263 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
10264 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
10265 
10266 
10267 /* Peripheral: RNG */
10268 /* Description: Random Number Generator */
10269 
10270 /* Register: RNG_TASKS_START */
10271 /* Description: Task starting the random number generator */
10272 
10273 /* Bit 0 : Task starting the random number generator */
10274 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10275 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10276 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
10277 
10278 /* Register: RNG_TASKS_STOP */
10279 /* Description: Task stopping the random number generator */
10280 
10281 /* Bit 0 : Task stopping the random number generator */
10282 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10283 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10284 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
10285 
10286 /* Register: RNG_EVENTS_VALRDY */
10287 /* Description: Event being generated for every new random number written to the VALUE register */
10288 
10289 /* Bit 0 : Event being generated for every new random number written to the VALUE register */
10290 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
10291 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
10292 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
10293 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
10294 
10295 /* Register: RNG_SHORTS */
10296 /* Description: Shortcuts between local events and tasks */
10297 
10298 /* Bit 0 : Shortcut between event VALRDY and task STOP */
10299 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
10300 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
10301 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
10302 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
10303 
10304 /* Register: RNG_INTENSET */
10305 /* Description: Enable interrupt */
10306 
10307 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */
10308 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
10309 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
10310 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
10311 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
10312 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
10313 
10314 /* Register: RNG_INTENCLR */
10315 /* Description: Disable interrupt */
10316 
10317 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */
10318 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
10319 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
10320 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
10321 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
10322 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
10323 
10324 /* Register: RNG_CONFIG */
10325 /* Description: Configuration register */
10326 
10327 /* Bit 0 : Bias correction */
10328 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
10329 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
10330 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
10331 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
10332 
10333 /* Register: RNG_VALUE */
10334 /* Description: Output random number */
10335 
10336 /* Bits 7..0 : Generated random number */
10337 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
10338 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
10339 
10340 
10341 /* Peripheral: RTC */
10342 /* Description: Real time counter 0 */
10343 
10344 /* Register: RTC_TASKS_START */
10345 /* Description: Start RTC COUNTER */
10346 
10347 /* Bit 0 : Start RTC COUNTER */
10348 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10349 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10350 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
10351 
10352 /* Register: RTC_TASKS_STOP */
10353 /* Description: Stop RTC COUNTER */
10354 
10355 /* Bit 0 : Stop RTC COUNTER */
10356 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10357 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10358 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
10359 
10360 /* Register: RTC_TASKS_CLEAR */
10361 /* Description: Clear RTC COUNTER */
10362 
10363 /* Bit 0 : Clear RTC COUNTER */
10364 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
10365 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
10366 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
10367 
10368 /* Register: RTC_TASKS_TRIGOVRFLW */
10369 /* Description: Set COUNTER to 0xFFFFF0 */
10370 
10371 /* Bit 0 : Set COUNTER to 0xFFFFF0 */
10372 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
10373 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
10374 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
10375 
10376 /* Register: RTC_EVENTS_TICK */
10377 /* Description: Event on COUNTER increment */
10378 
10379 /* Bit 0 : Event on COUNTER increment */
10380 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
10381 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
10382 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
10383 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
10384 
10385 /* Register: RTC_EVENTS_OVRFLW */
10386 /* Description: Event on COUNTER overflow */
10387 
10388 /* Bit 0 : Event on COUNTER overflow */
10389 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
10390 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
10391 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
10392 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
10393 
10394 /* Register: RTC_EVENTS_COMPARE */
10395 /* Description: Description collection: Compare event on CC[n] match */
10396 
10397 /* Bit 0 : Compare event on CC[n] match */
10398 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
10399 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
10400 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
10401 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
10402 
10403 /* Register: RTC_INTENSET */
10404 /* Description: Enable interrupt */
10405 
10406 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
10407 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10408 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10409 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10410 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10411 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
10412 
10413 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
10414 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10415 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10416 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10417 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10418 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
10419 
10420 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
10421 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10422 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10423 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10424 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10425 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
10426 
10427 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
10428 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10429 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10430 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10431 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10432 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
10433 
10434 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
10435 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10436 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10437 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
10438 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
10439 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
10440 
10441 /* Bit 0 : Write '1' to enable interrupt for event TICK */
10442 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
10443 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
10444 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
10445 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
10446 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
10447 
10448 /* Register: RTC_INTENCLR */
10449 /* Description: Disable interrupt */
10450 
10451 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
10452 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10453 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10454 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10455 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10456 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
10457 
10458 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
10459 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10460 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10461 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10462 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10463 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
10464 
10465 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
10466 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10467 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10468 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10469 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10470 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
10471 
10472 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
10473 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10474 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10475 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10476 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10477 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
10478 
10479 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
10480 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10481 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10482 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
10483 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
10484 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
10485 
10486 /* Bit 0 : Write '1' to disable interrupt for event TICK */
10487 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
10488 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
10489 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
10490 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
10491 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
10492 
10493 /* Register: RTC_EVTEN */
10494 /* Description: Enable or disable event routing */
10495 
10496 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
10497 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10498 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10499 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
10500 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
10501 
10502 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
10503 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10504 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10505 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
10506 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
10507 
10508 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
10509 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10510 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10511 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
10512 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
10513 
10514 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
10515 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10516 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10517 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
10518 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
10519 
10520 /* Bit 1 : Enable or disable event routing for event OVRFLW */
10521 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10522 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10523 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
10524 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
10525 
10526 /* Bit 0 : Enable or disable event routing for event TICK */
10527 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
10528 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
10529 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
10530 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
10531 
10532 /* Register: RTC_EVTENSET */
10533 /* Description: Enable event routing */
10534 
10535 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
10536 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10537 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10538 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10539 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10540 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
10541 
10542 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
10543 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10544 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10545 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10546 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10547 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
10548 
10549 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
10550 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10551 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10552 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10553 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10554 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
10555 
10556 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
10557 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10558 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10559 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10560 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10561 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
10562 
10563 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
10564 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10565 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10566 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
10567 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
10568 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
10569 
10570 /* Bit 0 : Write '1' to enable event routing for event TICK */
10571 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
10572 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
10573 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
10574 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
10575 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
10576 
10577 /* Register: RTC_EVTENCLR */
10578 /* Description: Disable event routing */
10579 
10580 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
10581 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10582 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10583 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10584 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10585 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
10586 
10587 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
10588 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10589 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10590 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10591 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10592 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
10593 
10594 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
10595 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10596 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10597 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10598 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10599 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
10600 
10601 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
10602 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10603 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10604 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10605 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10606 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
10607 
10608 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
10609 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
10610 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
10611 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
10612 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
10613 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
10614 
10615 /* Bit 0 : Write '1' to disable event routing for event TICK */
10616 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
10617 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
10618 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
10619 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
10620 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
10621 
10622 /* Register: RTC_COUNTER */
10623 /* Description: Current COUNTER value */
10624 
10625 /* Bits 23..0 : Counter value */
10626 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
10627 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
10628 
10629 /* Register: RTC_PRESCALER */
10630 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
10631 
10632 /* Bits 11..0 : Prescaler value */
10633 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
10634 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
10635 
10636 /* Register: RTC_CC */
10637 /* Description: Description collection: Compare register n */
10638 
10639 /* Bits 23..0 : Compare value */
10640 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
10641 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
10642 
10643 
10644 /* Peripheral: SAADC */
10645 /* Description: Analog to Digital Converter */
10646 
10647 /* Register: SAADC_TASKS_START */
10648 /* Description: Start the ADC and prepare the result buffer in RAM */
10649 
10650 /* Bit 0 : Start the ADC and prepare the result buffer in RAM */
10651 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10652 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10653 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
10654 
10655 /* Register: SAADC_TASKS_SAMPLE */
10656 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */
10657 
10658 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
10659 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
10660 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
10661 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
10662 
10663 /* Register: SAADC_TASKS_STOP */
10664 /* Description: Stop the ADC and terminate any on-going conversion */
10665 
10666 /* Bit 0 : Stop the ADC and terminate any on-going conversion */
10667 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
10668 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
10669 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
10670 
10671 /* Register: SAADC_TASKS_CALIBRATEOFFSET */
10672 /* Description: Starts offset auto-calibration */
10673 
10674 /* Bit 0 : Starts offset auto-calibration */
10675 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
10676 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
10677 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
10678 
10679 /* Register: SAADC_EVENTS_STARTED */
10680 /* Description: The ADC has started */
10681 
10682 /* Bit 0 : The ADC has started */
10683 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
10684 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
10685 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
10686 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
10687 
10688 /* Register: SAADC_EVENTS_END */
10689 /* Description: The ADC has filled up the Result buffer */
10690 
10691 /* Bit 0 : The ADC has filled up the Result buffer */
10692 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
10693 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
10694 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
10695 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
10696 
10697 /* Register: SAADC_EVENTS_DONE */
10698 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
10699 
10700 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
10701 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
10702 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
10703 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
10704 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
10705 
10706 /* Register: SAADC_EVENTS_RESULTDONE */
10707 /* Description: A result is ready to get transferred to RAM. */
10708 
10709 /* Bit 0 : A result is ready to get transferred to RAM. */
10710 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
10711 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
10712 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
10713 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
10714 
10715 /* Register: SAADC_EVENTS_CALIBRATEDONE */
10716 /* Description: Calibration is complete */
10717 
10718 /* Bit 0 : Calibration is complete */
10719 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
10720 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
10721 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
10722 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
10723 
10724 /* Register: SAADC_EVENTS_STOPPED */
10725 /* Description: The ADC has stopped */
10726 
10727 /* Bit 0 : The ADC has stopped */
10728 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
10729 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
10730 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
10731 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
10732 
10733 /* Register: SAADC_EVENTS_CH_LIMITH */
10734 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
10735 
10736 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
10737 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
10738 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
10739 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
10740 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
10741 
10742 /* Register: SAADC_EVENTS_CH_LIMITL */
10743 /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */
10744 
10745 /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
10746 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
10747 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
10748 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
10749 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
10750 
10751 /* Register: SAADC_INTEN */
10752 /* Description: Enable or disable interrupt */
10753 
10754 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
10755 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
10756 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
10757 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
10758 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
10759 
10760 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
10761 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
10762 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
10763 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
10764 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
10765 
10766 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
10767 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
10768 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
10769 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
10770 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
10771 
10772 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
10773 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
10774 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
10775 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
10776 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
10777 
10778 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
10779 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
10780 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
10781 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
10782 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
10783 
10784 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
10785 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
10786 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
10787 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
10788 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
10789 
10790 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
10791 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
10792 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
10793 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
10794 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
10795 
10796 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
10797 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
10798 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
10799 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
10800 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
10801 
10802 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
10803 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
10804 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
10805 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
10806 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
10807 
10808 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
10809 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
10810 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
10811 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
10812 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
10813 
10814 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
10815 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
10816 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
10817 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
10818 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
10819 
10820 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
10821 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
10822 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
10823 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
10824 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
10825 
10826 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
10827 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
10828 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
10829 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
10830 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
10831 
10832 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
10833 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
10834 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
10835 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
10836 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
10837 
10838 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
10839 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
10840 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
10841 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
10842 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
10843 
10844 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
10845 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
10846 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
10847 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
10848 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
10849 
10850 /* Bit 5 : Enable or disable interrupt for event STOPPED */
10851 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
10852 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10853 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
10854 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
10855 
10856 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
10857 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
10858 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
10859 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
10860 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
10861 
10862 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
10863 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
10864 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
10865 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
10866 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
10867 
10868 /* Bit 2 : Enable or disable interrupt for event DONE */
10869 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
10870 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
10871 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
10872 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
10873 
10874 /* Bit 1 : Enable or disable interrupt for event END */
10875 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
10876 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
10877 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
10878 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
10879 
10880 /* Bit 0 : Enable or disable interrupt for event STARTED */
10881 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
10882 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
10883 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
10884 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
10885 
10886 /* Register: SAADC_INTENSET */
10887 /* Description: Enable interrupt */
10888 
10889 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
10890 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
10891 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
10892 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
10893 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
10894 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
10895 
10896 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
10897 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
10898 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
10899 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
10900 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
10901 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
10902 
10903 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
10904 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
10905 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
10906 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
10907 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
10908 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
10909 
10910 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
10911 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
10912 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
10913 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
10914 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
10915 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
10916 
10917 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
10918 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
10919 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
10920 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
10921 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
10922 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
10923 
10924 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
10925 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
10926 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
10927 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
10928 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
10929 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
10930 
10931 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
10932 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
10933 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
10934 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
10935 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
10936 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
10937 
10938 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
10939 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
10940 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
10941 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
10942 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
10943 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
10944 
10945 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
10946 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
10947 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
10948 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
10949 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
10950 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
10951 
10952 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
10953 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
10954 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
10955 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
10956 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
10957 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
10958 
10959 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
10960 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
10961 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
10962 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
10963 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
10964 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
10965 
10966 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
10967 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
10968 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
10969 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
10970 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
10971 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
10972 
10973 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
10974 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
10975 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
10976 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
10977 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
10978 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
10979 
10980 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
10981 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
10982 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
10983 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
10984 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
10985 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
10986 
10987 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
10988 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
10989 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
10990 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
10991 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
10992 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
10993 
10994 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
10995 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
10996 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
10997 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
10998 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
10999 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
11000 
11001 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
11002 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
11003 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11004 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11005 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11006 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11007 
11008 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
11009 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
11010 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
11011 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
11012 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
11013 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
11014 
11015 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
11016 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
11017 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
11018 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
11019 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
11020 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
11021 
11022 /* Bit 2 : Write '1' to enable interrupt for event DONE */
11023 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
11024 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
11025 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
11026 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
11027 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
11028 
11029 /* Bit 1 : Write '1' to enable interrupt for event END */
11030 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
11031 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
11032 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
11033 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
11034 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
11035 
11036 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
11037 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
11038 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
11039 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
11040 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
11041 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
11042 
11043 /* Register: SAADC_INTENCLR */
11044 /* Description: Disable interrupt */
11045 
11046 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
11047 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
11048 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
11049 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11050 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11051 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
11052 
11053 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
11054 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
11055 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
11056 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11057 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11058 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
11059 
11060 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
11061 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
11062 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
11063 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11064 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11065 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
11066 
11067 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
11068 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
11069 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
11070 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11071 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11072 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
11073 
11074 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
11075 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
11076 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
11077 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11078 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11079 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
11080 
11081 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
11082 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
11083 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
11084 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11085 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11086 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
11087 
11088 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
11089 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
11090 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
11091 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11092 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11093 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
11094 
11095 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
11096 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
11097 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
11098 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11099 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11100 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
11101 
11102 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
11103 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
11104 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
11105 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
11106 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
11107 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
11108 
11109 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
11110 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
11111 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
11112 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
11113 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
11114 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
11115 
11116 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
11117 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
11118 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
11119 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
11120 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
11121 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
11122 
11123 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
11124 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
11125 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
11126 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
11127 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
11128 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
11129 
11130 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
11131 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
11132 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
11133 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
11134 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
11135 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
11136 
11137 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
11138 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
11139 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
11140 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
11141 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
11142 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
11143 
11144 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
11145 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
11146 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
11147 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
11148 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
11149 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
11150 
11151 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
11152 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
11153 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
11154 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
11155 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
11156 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
11157 
11158 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
11159 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
11160 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11161 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11162 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11163 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11164 
11165 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
11166 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
11167 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
11168 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
11169 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
11170 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
11171 
11172 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
11173 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
11174 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
11175 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
11176 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
11177 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
11178 
11179 /* Bit 2 : Write '1' to disable interrupt for event DONE */
11180 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
11181 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
11182 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
11183 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
11184 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
11185 
11186 /* Bit 1 : Write '1' to disable interrupt for event END */
11187 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
11188 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
11189 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
11190 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
11191 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
11192 
11193 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
11194 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
11195 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
11196 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
11197 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
11198 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
11199 
11200 /* Register: SAADC_STATUS */
11201 /* Description: Status */
11202 
11203 /* Bit 0 : Status */
11204 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
11205 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
11206 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
11207 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
11208 
11209 /* Register: SAADC_ENABLE */
11210 /* Description: Enable or disable ADC */
11211 
11212 /* Bit 0 : Enable or disable ADC */
11213 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11214 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11215 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
11216 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
11217 
11218 /* Register: SAADC_CH_PSELP */
11219 /* Description: Description cluster: Input positive pin selection for CH[n] */
11220 
11221 /* Bits 4..0 : Analog positive input channel */
11222 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
11223 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
11224 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
11225 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
11226 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
11227 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
11228 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
11229 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
11230 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
11231 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
11232 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
11233 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
11234 
11235 /* Register: SAADC_CH_PSELN */
11236 /* Description: Description cluster: Input negative pin selection for CH[n] */
11237 
11238 /* Bits 4..0 : Analog negative input, enables differential channel */
11239 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
11240 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
11241 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
11242 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
11243 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
11244 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
11245 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
11246 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
11247 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
11248 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
11249 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
11250 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
11251 
11252 /* Register: SAADC_CH_CONFIG */
11253 /* Description: Description cluster: Input configuration for CH[n] */
11254 
11255 /* Bit 24 : Enable burst mode */
11256 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
11257 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
11258 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
11259 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
11260 
11261 /* Bit 20 : Enable differential mode */
11262 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
11263 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
11264 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
11265 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
11266 
11267 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
11268 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
11269 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
11270 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
11271 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
11272 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
11273 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
11274 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
11275 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
11276 
11277 /* Bit 12 : Reference control */
11278 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
11279 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
11280 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
11281 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
11282 
11283 /* Bits 10..8 : Gain control */
11284 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
11285 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
11286 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
11287 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
11288 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
11289 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
11290 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
11291 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
11292 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
11293 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
11294 
11295 /* Bits 5..4 : Negative channel resistor control */
11296 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
11297 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
11298 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
11299 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
11300 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
11301 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
11302 
11303 /* Bits 1..0 : Positive channel resistor control */
11304 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
11305 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
11306 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
11307 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
11308 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
11309 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
11310 
11311 /* Register: SAADC_CH_LIMIT */
11312 /* Description: Description cluster: High/low limits for event monitoring a channel */
11313 
11314 /* Bits 31..16 : High level limit */
11315 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
11316 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
11317 
11318 /* Bits 15..0 : Low level limit */
11319 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
11320 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
11321 
11322 /* Register: SAADC_RESOLUTION */
11323 /* Description: Resolution configuration */
11324 
11325 /* Bits 2..0 : Set the resolution */
11326 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
11327 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
11328 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
11329 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
11330 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
11331 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
11332 
11333 /* Register: SAADC_OVERSAMPLE */
11334 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
11335 
11336 /* Bits 3..0 : Oversample control */
11337 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
11338 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
11339 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
11340 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
11341 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
11342 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
11343 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
11344 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
11345 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
11346 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
11347 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
11348 
11349 /* Register: SAADC_SAMPLERATE */
11350 /* Description: Controls normal or continuous sample rate */
11351 
11352 /* Bit 12 : Select mode for sample rate control */
11353 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
11354 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
11355 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
11356 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
11357 
11358 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
11359 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
11360 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
11361 
11362 /* Register: SAADC_RESULT_PTR */
11363 /* Description: Data pointer */
11364 
11365 /* Bits 31..0 : Data pointer */
11366 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11367 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11368 
11369 /* Register: SAADC_RESULT_MAXCNT */
11370 /* Description: Maximum number of buffer words to transfer */
11371 
11372 /* Bits 14..0 : Maximum number of buffer words to transfer */
11373 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11374 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11375 
11376 /* Register: SAADC_RESULT_AMOUNT */
11377 /* Description: Number of buffer words transferred since last START */
11378 
11379 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
11380 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11381 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11382 
11383 
11384 /* Peripheral: SPI */
11385 /* Description: Serial Peripheral Interface 0 */
11386 
11387 /* Register: SPI_EVENTS_READY */
11388 /* Description: TXD byte sent and RXD byte received */
11389 
11390 /* Bit 0 : TXD byte sent and RXD byte received */
11391 #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
11392 #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
11393 #define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
11394 #define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
11395 
11396 /* Register: SPI_INTENSET */
11397 /* Description: Enable interrupt */
11398 
11399 /* Bit 2 : Write '1' to enable interrupt for event READY */
11400 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
11401 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
11402 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
11403 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
11404 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
11405 
11406 /* Register: SPI_INTENCLR */
11407 /* Description: Disable interrupt */
11408 
11409 /* Bit 2 : Write '1' to disable interrupt for event READY */
11410 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
11411 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
11412 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
11413 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
11414 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
11415 
11416 /* Register: SPI_ENABLE */
11417 /* Description: Enable SPI */
11418 
11419 /* Bits 3..0 : Enable or disable SPI */
11420 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11421 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11422 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
11423 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
11424 
11425 /* Register: SPI_PSEL_SCK */
11426 /* Description: Pin select for SCK */
11427 
11428 /* Bits 31..0 : Pin number configuration for SPI SCK signal */
11429 #define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
11430 #define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
11431 #define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11432 
11433 /* Register: SPI_PSEL_MOSI */
11434 /* Description: Pin select for MOSI */
11435 
11436 /* Bits 31..0 : Pin number configuration for SPI MOSI signal */
11437 #define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
11438 #define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
11439 #define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11440 
11441 /* Register: SPI_PSEL_MISO */
11442 /* Description: Pin select for MISO */
11443 
11444 /* Bits 31..0 : Pin number configuration for SPI MISO signal */
11445 #define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
11446 #define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
11447 #define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11448 
11449 /* Register: SPI_RXD */
11450 /* Description: RXD register */
11451 
11452 /* Bits 7..0 : RX data received. Double buffered */
11453 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
11454 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
11455 
11456 /* Register: SPI_TXD */
11457 /* Description: TXD register */
11458 
11459 /* Bits 7..0 : TX data to send. Double buffered */
11460 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
11461 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
11462 
11463 /* Register: SPI_FREQUENCY */
11464 /* Description: SPI frequency */
11465 
11466 /* Bits 31..0 : SPI master data rate */
11467 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
11468 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
11469 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
11470 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
11471 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
11472 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
11473 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
11474 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
11475 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
11476 
11477 /* Register: SPI_CONFIG */
11478 /* Description: Configuration register */
11479 
11480 /* Bit 2 : Serial clock (SCK) polarity */
11481 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
11482 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
11483 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
11484 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
11485 
11486 /* Bit 1 : Serial clock (SCK) phase */
11487 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
11488 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
11489 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
11490 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
11491 
11492 /* Bit 0 : Bit order */
11493 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
11494 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
11495 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
11496 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
11497 
11498 
11499 /* Peripheral: SPIM */
11500 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
11501 
11502 /* Register: SPIM_TASKS_START */
11503 /* Description: Start SPI transaction */
11504 
11505 /* Bit 0 : Start SPI transaction */
11506 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11507 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11508 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
11509 
11510 /* Register: SPIM_TASKS_STOP */
11511 /* Description: Stop SPI transaction */
11512 
11513 /* Bit 0 : Stop SPI transaction */
11514 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
11515 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
11516 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
11517 
11518 /* Register: SPIM_TASKS_SUSPEND */
11519 /* Description: Suspend SPI transaction */
11520 
11521 /* Bit 0 : Suspend SPI transaction */
11522 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
11523 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
11524 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
11525 
11526 /* Register: SPIM_TASKS_RESUME */
11527 /* Description: Resume SPI transaction */
11528 
11529 /* Bit 0 : Resume SPI transaction */
11530 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
11531 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
11532 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
11533 
11534 /* Register: SPIM_EVENTS_STOPPED */
11535 /* Description: SPI transaction has stopped */
11536 
11537 /* Bit 0 : SPI transaction has stopped */
11538 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
11539 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
11540 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
11541 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
11542 
11543 /* Register: SPIM_EVENTS_ENDRX */
11544 /* Description: End of RXD buffer reached */
11545 
11546 /* Bit 0 : End of RXD buffer reached */
11547 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
11548 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
11549 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
11550 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
11551 
11552 /* Register: SPIM_EVENTS_END */
11553 /* Description: End of RXD buffer and TXD buffer reached */
11554 
11555 /* Bit 0 : End of RXD buffer and TXD buffer reached */
11556 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
11557 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
11558 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
11559 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
11560 
11561 /* Register: SPIM_EVENTS_ENDTX */
11562 /* Description: End of TXD buffer reached */
11563 
11564 /* Bit 0 : End of TXD buffer reached */
11565 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
11566 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
11567 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
11568 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
11569 
11570 /* Register: SPIM_EVENTS_STARTED */
11571 /* Description: Transaction started */
11572 
11573 /* Bit 0 : Transaction started */
11574 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
11575 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
11576 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
11577 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
11578 
11579 /* Register: SPIM_SHORTS */
11580 /* Description: Shortcuts between local events and tasks */
11581 
11582 /* Bit 17 : Shortcut between event END and task START */
11583 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
11584 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
11585 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
11586 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
11587 
11588 /* Register: SPIM_INTENSET */
11589 /* Description: Enable interrupt */
11590 
11591 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
11592 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
11593 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
11594 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
11595 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
11596 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
11597 
11598 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
11599 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
11600 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
11601 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
11602 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
11603 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
11604 
11605 /* Bit 6 : Write '1' to enable interrupt for event END */
11606 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
11607 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
11608 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
11609 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
11610 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
11611 
11612 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
11613 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11614 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11615 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
11616 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
11617 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
11618 
11619 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
11620 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11621 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11622 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11623 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11624 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11625 
11626 /* Register: SPIM_INTENCLR */
11627 /* Description: Disable interrupt */
11628 
11629 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
11630 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
11631 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
11632 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
11633 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
11634 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
11635 
11636 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
11637 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
11638 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
11639 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
11640 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
11641 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
11642 
11643 /* Bit 6 : Write '1' to disable interrupt for event END */
11644 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
11645 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
11646 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
11647 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
11648 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
11649 
11650 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
11651 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11652 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11653 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
11654 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
11655 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
11656 
11657 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
11658 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11659 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11660 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11661 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11662 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11663 
11664 /* Register: SPIM_ENABLE */
11665 /* Description: Enable SPIM */
11666 
11667 /* Bits 3..0 : Enable or disable SPIM */
11668 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11669 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11670 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
11671 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
11672 
11673 /* Register: SPIM_PSEL_SCK */
11674 /* Description: Pin select for SCK */
11675 
11676 /* Bit 31 : Connection */
11677 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11678 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11679 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
11680 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
11681 
11682 /* Bits 4..0 : Pin number */
11683 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
11684 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
11685 
11686 /* Register: SPIM_PSEL_MOSI */
11687 /* Description: Pin select for MOSI signal */
11688 
11689 /* Bit 31 : Connection */
11690 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11691 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11692 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
11693 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
11694 
11695 /* Bits 4..0 : Pin number */
11696 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
11697 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
11698 
11699 /* Register: SPIM_PSEL_MISO */
11700 /* Description: Pin select for MISO signal */
11701 
11702 /* Bit 31 : Connection */
11703 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11704 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11705 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
11706 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
11707 
11708 /* Bits 4..0 : Pin number */
11709 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
11710 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
11711 
11712 /* Register: SPIM_FREQUENCY */
11713 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
11714 
11715 /* Bits 31..0 : SPI master data rate */
11716 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
11717 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
11718 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
11719 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
11720 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
11721 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
11722 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
11723 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
11724 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
11725 
11726 /* Register: SPIM_RXD_PTR */
11727 /* Description: Data pointer */
11728 
11729 /* Bits 31..0 : Data pointer */
11730 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11731 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11732 
11733 /* Register: SPIM_RXD_MAXCNT */
11734 /* Description: Maximum number of bytes in receive buffer */
11735 
11736 /* Bits 7..0 : Maximum number of bytes in receive buffer */
11737 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11738 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11739 
11740 /* Register: SPIM_RXD_AMOUNT */
11741 /* Description: Number of bytes transferred in the last transaction */
11742 
11743 /* Bits 7..0 : Number of bytes transferred in the last transaction */
11744 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11745 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11746 
11747 /* Register: SPIM_RXD_LIST */
11748 /* Description: EasyDMA list type */
11749 
11750 /* Bits 2..0 : List type */
11751 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11752 #define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11753 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11754 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11755 
11756 /* Register: SPIM_TXD_PTR */
11757 /* Description: Data pointer */
11758 
11759 /* Bits 31..0 : Data pointer */
11760 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11761 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11762 
11763 /* Register: SPIM_TXD_MAXCNT */
11764 /* Description: Maximum number of bytes in transmit buffer */
11765 
11766 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
11767 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11768 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11769 
11770 /* Register: SPIM_TXD_AMOUNT */
11771 /* Description: Number of bytes transferred in the last transaction */
11772 
11773 /* Bits 7..0 : Number of bytes transferred in the last transaction */
11774 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11775 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11776 
11777 /* Register: SPIM_TXD_LIST */
11778 /* Description: EasyDMA list type */
11779 
11780 /* Bits 2..0 : List type */
11781 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11782 #define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11783 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11784 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11785 
11786 /* Register: SPIM_CONFIG */
11787 /* Description: Configuration register */
11788 
11789 /* Bit 2 : Serial clock (SCK) polarity */
11790 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
11791 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
11792 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
11793 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
11794 
11795 /* Bit 1 : Serial clock (SCK) phase */
11796 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
11797 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
11798 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
11799 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
11800 
11801 /* Bit 0 : Bit order */
11802 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
11803 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
11804 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
11805 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
11806 
11807 /* Register: SPIM_ORC */
11808 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
11809 
11810 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
11811 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
11812 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
11813 
11814 
11815 /* Peripheral: SPIS */
11816 /* Description: SPI Slave 0 */
11817 
11818 /* Register: SPIS_TASKS_ACQUIRE */
11819 /* Description: Acquire SPI semaphore */
11820 
11821 /* Bit 0 : Acquire SPI semaphore */
11822 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
11823 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
11824 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
11825 
11826 /* Register: SPIS_TASKS_RELEASE */
11827 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
11828 
11829 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
11830 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
11831 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
11832 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
11833 
11834 /* Register: SPIS_EVENTS_END */
11835 /* Description: Granted transaction completed */
11836 
11837 /* Bit 0 : Granted transaction completed */
11838 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
11839 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
11840 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
11841 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
11842 
11843 /* Register: SPIS_EVENTS_ENDRX */
11844 /* Description: End of RXD buffer reached */
11845 
11846 /* Bit 0 : End of RXD buffer reached */
11847 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
11848 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
11849 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
11850 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
11851 
11852 /* Register: SPIS_EVENTS_ACQUIRED */
11853 /* Description: Semaphore acquired */
11854 
11855 /* Bit 0 : Semaphore acquired */
11856 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
11857 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
11858 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
11859 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
11860 
11861 /* Register: SPIS_SHORTS */
11862 /* Description: Shortcuts between local events and tasks */
11863 
11864 /* Bit 2 : Shortcut between event END and task ACQUIRE */
11865 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
11866 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
11867 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
11868 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
11869 
11870 /* Register: SPIS_INTENSET */
11871 /* Description: Enable interrupt */
11872 
11873 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
11874 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
11875 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
11876 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
11877 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
11878 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
11879 
11880 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
11881 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11882 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11883 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
11884 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
11885 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
11886 
11887 /* Bit 1 : Write '1' to enable interrupt for event END */
11888 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
11889 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
11890 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
11891 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
11892 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
11893 
11894 /* Register: SPIS_INTENCLR */
11895 /* Description: Disable interrupt */
11896 
11897 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
11898 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
11899 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
11900 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
11901 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
11902 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
11903 
11904 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
11905 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
11906 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
11907 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
11908 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
11909 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
11910 
11911 /* Bit 1 : Write '1' to disable interrupt for event END */
11912 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
11913 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
11914 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
11915 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
11916 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
11917 
11918 /* Register: SPIS_SEMSTAT */
11919 /* Description: Semaphore status register */
11920 
11921 /* Bits 1..0 : Semaphore status */
11922 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
11923 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
11924 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
11925 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
11926 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
11927 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
11928 
11929 /* Register: SPIS_STATUS */
11930 /* Description: Status from last transaction */
11931 
11932 /* Bit 1 : RX buffer overflow detected, and prevented */
11933 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
11934 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
11935 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
11936 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
11937 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
11938 
11939 /* Bit 0 : TX buffer over-read detected, and prevented */
11940 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
11941 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
11942 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
11943 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
11944 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
11945 
11946 /* Register: SPIS_ENABLE */
11947 /* Description: Enable SPI slave */
11948 
11949 /* Bits 3..0 : Enable or disable SPI slave */
11950 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11951 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11952 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
11953 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
11954 
11955 /* Register: SPIS_PSEL_SCK */
11956 /* Description: Pin select for SCK */
11957 
11958 /* Bit 31 : Connection */
11959 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11960 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11961 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
11962 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
11963 
11964 /* Bits 4..0 : Pin number */
11965 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
11966 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
11967 
11968 /* Register: SPIS_PSEL_MISO */
11969 /* Description: Pin select for MISO signal */
11970 
11971 /* Bit 31 : Connection */
11972 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11973 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11974 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
11975 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
11976 
11977 /* Bits 4..0 : Pin number */
11978 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
11979 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
11980 
11981 /* Register: SPIS_PSEL_MOSI */
11982 /* Description: Pin select for MOSI signal */
11983 
11984 /* Bit 31 : Connection */
11985 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11986 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11987 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
11988 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
11989 
11990 /* Bits 4..0 : Pin number */
11991 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
11992 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
11993 
11994 /* Register: SPIS_PSEL_CSN */
11995 /* Description: Pin select for CSN signal */
11996 
11997 /* Bit 31 : Connection */
11998 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11999 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12000 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
12001 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
12002 
12003 /* Bits 4..0 : Pin number */
12004 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
12005 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
12006 
12007 /* Register: SPIS_RXD_PTR */
12008 /* Description: RXD data pointer */
12009 
12010 /* Bits 31..0 : RXD data pointer */
12011 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12012 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12013 
12014 /* Register: SPIS_RXD_MAXCNT */
12015 /* Description: Maximum number of bytes in receive buffer */
12016 
12017 /* Bits 7..0 : Maximum number of bytes in receive buffer */
12018 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12019 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12020 
12021 /* Register: SPIS_RXD_AMOUNT */
12022 /* Description: Number of bytes received in last granted transaction */
12023 
12024 /* Bits 7..0 : Number of bytes received in the last granted transaction */
12025 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12026 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12027 
12028 /* Register: SPIS_TXD_PTR */
12029 /* Description: TXD data pointer */
12030 
12031 /* Bits 31..0 : TXD data pointer */
12032 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12033 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12034 
12035 /* Register: SPIS_TXD_MAXCNT */
12036 /* Description: Maximum number of bytes in transmit buffer */
12037 
12038 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
12039 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12040 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12041 
12042 /* Register: SPIS_TXD_AMOUNT */
12043 /* Description: Number of bytes transmitted in last granted transaction */
12044 
12045 /* Bits 7..0 : Number of bytes transmitted in last granted transaction */
12046 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12047 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12048 
12049 /* Register: SPIS_CONFIG */
12050 /* Description: Configuration register */
12051 
12052 /* Bit 2 : Serial clock (SCK) polarity */
12053 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
12054 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
12055 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12056 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
12057 
12058 /* Bit 1 : Serial clock (SCK) phase */
12059 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
12060 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
12061 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
12062 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
12063 
12064 /* Bit 0 : Bit order */
12065 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
12066 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
12067 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
12068 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
12069 
12070 /* Register: SPIS_DEF */
12071 /* Description: Default character. Character clocked out in case of an ignored transaction. */
12072 
12073 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
12074 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
12075 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
12076 
12077 /* Register: SPIS_ORC */
12078 /* Description: Over-read character */
12079 
12080 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
12081 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
12082 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
12083 
12084 
12085 /* Peripheral: TEMP */
12086 /* Description: Temperature Sensor */
12087 
12088 /* Register: TEMP_TASKS_START */
12089 /* Description: Start temperature measurement */
12090 
12091 /* Bit 0 : Start temperature measurement */
12092 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
12093 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
12094 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
12095 
12096 /* Register: TEMP_TASKS_STOP */
12097 /* Description: Stop temperature measurement */
12098 
12099 /* Bit 0 : Stop temperature measurement */
12100 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12101 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12102 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
12103 
12104 /* Register: TEMP_EVENTS_DATARDY */
12105 /* Description: Temperature measurement complete, data ready */
12106 
12107 /* Bit 0 : Temperature measurement complete, data ready */
12108 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
12109 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
12110 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
12111 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
12112 
12113 /* Register: TEMP_INTENSET */
12114 /* Description: Enable interrupt */
12115 
12116 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */
12117 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
12118 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
12119 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
12120 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
12121 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
12122 
12123 /* Register: TEMP_INTENCLR */
12124 /* Description: Disable interrupt */
12125 
12126 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */
12127 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
12128 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
12129 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
12130 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
12131 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
12132 
12133 /* Register: TEMP_TEMP */
12134 /* Description: Temperature in degC (0.25deg steps) */
12135 
12136 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
12137 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
12138 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
12139 
12140 /* Register: TEMP_A0 */
12141 /* Description: Slope of 1st piece wise linear function */
12142 
12143 /* Bits 11..0 : Slope of 1st piece wise linear function */
12144 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
12145 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
12146 
12147 /* Register: TEMP_A1 */
12148 /* Description: Slope of 2nd piece wise linear function */
12149 
12150 /* Bits 11..0 : Slope of 2nd piece wise linear function */
12151 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
12152 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
12153 
12154 /* Register: TEMP_A2 */
12155 /* Description: Slope of 3rd piece wise linear function */
12156 
12157 /* Bits 11..0 : Slope of 3rd piece wise linear function */
12158 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
12159 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
12160 
12161 /* Register: TEMP_A3 */
12162 /* Description: Slope of 4th piece wise linear function */
12163 
12164 /* Bits 11..0 : Slope of 4th piece wise linear function */
12165 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
12166 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
12167 
12168 /* Register: TEMP_A4 */
12169 /* Description: Slope of 5th piece wise linear function */
12170 
12171 /* Bits 11..0 : Slope of 5th piece wise linear function */
12172 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
12173 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
12174 
12175 /* Register: TEMP_A5 */
12176 /* Description: Slope of 6th piece wise linear function */
12177 
12178 /* Bits 11..0 : Slope of 6th piece wise linear function */
12179 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
12180 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
12181 
12182 /* Register: TEMP_B0 */
12183 /* Description: y-intercept of 1st piece wise linear function */
12184 
12185 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
12186 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
12187 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
12188 
12189 /* Register: TEMP_B1 */
12190 /* Description: y-intercept of 2nd piece wise linear function */
12191 
12192 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
12193 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
12194 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
12195 
12196 /* Register: TEMP_B2 */
12197 /* Description: y-intercept of 3rd piece wise linear function */
12198 
12199 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
12200 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
12201 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
12202 
12203 /* Register: TEMP_B3 */
12204 /* Description: y-intercept of 4th piece wise linear function */
12205 
12206 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
12207 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
12208 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
12209 
12210 /* Register: TEMP_B4 */
12211 /* Description: y-intercept of 5th piece wise linear function */
12212 
12213 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
12214 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
12215 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
12216 
12217 /* Register: TEMP_B5 */
12218 /* Description: y-intercept of 6th piece wise linear function */
12219 
12220 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
12221 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
12222 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
12223 
12224 /* Register: TEMP_T0 */
12225 /* Description: End point of 1st piece wise linear function */
12226 
12227 /* Bits 7..0 : End point of 1st piece wise linear function */
12228 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
12229 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
12230 
12231 /* Register: TEMP_T1 */
12232 /* Description: End point of 2nd piece wise linear function */
12233 
12234 /* Bits 7..0 : End point of 2nd piece wise linear function */
12235 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
12236 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
12237 
12238 /* Register: TEMP_T2 */
12239 /* Description: End point of 3rd piece wise linear function */
12240 
12241 /* Bits 7..0 : End point of 3rd piece wise linear function */
12242 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
12243 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
12244 
12245 /* Register: TEMP_T3 */
12246 /* Description: End point of 4th piece wise linear function */
12247 
12248 /* Bits 7..0 : End point of 4th piece wise linear function */
12249 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
12250 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
12251 
12252 /* Register: TEMP_T4 */
12253 /* Description: End point of 5th piece wise linear function */
12254 
12255 /* Bits 7..0 : End point of 5th piece wise linear function */
12256 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
12257 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
12258 
12259 
12260 /* Peripheral: TIMER */
12261 /* Description: Timer/Counter 0 */
12262 
12263 /* Register: TIMER_TASKS_START */
12264 /* Description: Start Timer */
12265 
12266 /* Bit 0 : Start Timer */
12267 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
12268 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
12269 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
12270 
12271 /* Register: TIMER_TASKS_STOP */
12272 /* Description: Stop Timer */
12273 
12274 /* Bit 0 : Stop Timer */
12275 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12276 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12277 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
12278 
12279 /* Register: TIMER_TASKS_COUNT */
12280 /* Description: Increment Timer (Counter mode only) */
12281 
12282 /* Bit 0 : Increment Timer (Counter mode only) */
12283 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
12284 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
12285 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
12286 
12287 /* Register: TIMER_TASKS_CLEAR */
12288 /* Description: Clear time */
12289 
12290 /* Bit 0 : Clear time */
12291 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
12292 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
12293 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
12294 
12295 /* Register: TIMER_TASKS_SHUTDOWN */
12296 /* Description: Deprecated register - Shut down timer */
12297 
12298 /* Bit 0 : Deprecated field -  Shut down timer */
12299 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
12300 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
12301 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
12302 
12303 /* Register: TIMER_TASKS_CAPTURE */
12304 /* Description: Description collection: Capture Timer value to CC[n] register */
12305 
12306 /* Bit 0 : Capture Timer value to CC[n] register */
12307 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
12308 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
12309 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
12310 
12311 /* Register: TIMER_EVENTS_COMPARE */
12312 /* Description: Description collection: Compare event on CC[n] match */
12313 
12314 /* Bit 0 : Compare event on CC[n] match */
12315 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
12316 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
12317 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
12318 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
12319 
12320 /* Register: TIMER_SHORTS */
12321 /* Description: Shortcuts between local events and tasks */
12322 
12323 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
12324 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
12325 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
12326 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
12327 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
12328 
12329 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
12330 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
12331 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
12332 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
12333 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
12334 
12335 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
12336 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
12337 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
12338 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
12339 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
12340 
12341 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
12342 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
12343 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
12344 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
12345 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
12346 
12347 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
12348 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
12349 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
12350 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
12351 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
12352 
12353 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
12354 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
12355 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
12356 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
12357 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
12358 
12359 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
12360 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
12361 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
12362 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
12363 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
12364 
12365 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
12366 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
12367 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
12368 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
12369 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
12370 
12371 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
12372 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
12373 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
12374 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
12375 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
12376 
12377 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
12378 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
12379 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
12380 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
12381 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
12382 
12383 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
12384 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
12385 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
12386 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
12387 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
12388 
12389 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
12390 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
12391 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
12392 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
12393 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
12394 
12395 /* Register: TIMER_INTENSET */
12396 /* Description: Enable interrupt */
12397 
12398 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
12399 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
12400 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
12401 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
12402 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
12403 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
12404 
12405 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
12406 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
12407 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
12408 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
12409 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
12410 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
12411 
12412 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
12413 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
12414 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
12415 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
12416 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
12417 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
12418 
12419 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
12420 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
12421 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
12422 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
12423 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
12424 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
12425 
12426 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
12427 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
12428 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
12429 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
12430 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
12431 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
12432 
12433 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
12434 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
12435 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
12436 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
12437 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
12438 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
12439 
12440 /* Register: TIMER_INTENCLR */
12441 /* Description: Disable interrupt */
12442 
12443 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
12444 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
12445 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
12446 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
12447 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
12448 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
12449 
12450 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
12451 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
12452 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
12453 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
12454 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
12455 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
12456 
12457 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
12458 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
12459 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
12460 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
12461 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
12462 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
12463 
12464 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
12465 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
12466 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
12467 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
12468 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
12469 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
12470 
12471 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
12472 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
12473 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
12474 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
12475 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
12476 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
12477 
12478 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
12479 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
12480 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
12481 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
12482 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
12483 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
12484 
12485 /* Register: TIMER_MODE */
12486 /* Description: Timer mode selection */
12487 
12488 /* Bits 1..0 : Timer mode */
12489 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
12490 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
12491 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
12492 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
12493 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
12494 
12495 /* Register: TIMER_BITMODE */
12496 /* Description: Configure the number of bits used by the TIMER */
12497 
12498 /* Bits 1..0 : Timer bit width */
12499 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
12500 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
12501 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
12502 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
12503 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
12504 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
12505 
12506 /* Register: TIMER_PRESCALER */
12507 /* Description: Timer prescaler register */
12508 
12509 /* Bits 3..0 : Prescaler value */
12510 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
12511 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
12512 
12513 /* Register: TIMER_CC */
12514 /* Description: Description collection: Capture/Compare register n */
12515 
12516 /* Bits 31..0 : Capture/Compare value */
12517 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
12518 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
12519 
12520 
12521 /* Peripheral: TWI */
12522 /* Description: I2C compatible Two-Wire Interface 0 */
12523 
12524 /* Register: TWI_TASKS_STARTRX */
12525 /* Description: Start TWI receive sequence */
12526 
12527 /* Bit 0 : Start TWI receive sequence */
12528 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
12529 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
12530 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
12531 
12532 /* Register: TWI_TASKS_STARTTX */
12533 /* Description: Start TWI transmit sequence */
12534 
12535 /* Bit 0 : Start TWI transmit sequence */
12536 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
12537 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
12538 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
12539 
12540 /* Register: TWI_TASKS_STOP */
12541 /* Description: Stop TWI transaction */
12542 
12543 /* Bit 0 : Stop TWI transaction */
12544 #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12545 #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12546 #define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
12547 
12548 /* Register: TWI_TASKS_SUSPEND */
12549 /* Description: Suspend TWI transaction */
12550 
12551 /* Bit 0 : Suspend TWI transaction */
12552 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
12553 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
12554 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
12555 
12556 /* Register: TWI_TASKS_RESUME */
12557 /* Description: Resume TWI transaction */
12558 
12559 /* Bit 0 : Resume TWI transaction */
12560 #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
12561 #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
12562 #define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
12563 
12564 /* Register: TWI_EVENTS_STOPPED */
12565 /* Description: TWI stopped */
12566 
12567 /* Bit 0 : TWI stopped */
12568 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
12569 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
12570 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
12571 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
12572 
12573 /* Register: TWI_EVENTS_RXDREADY */
12574 /* Description: TWI RXD byte received */
12575 
12576 /* Bit 0 : TWI RXD byte received */
12577 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */
12578 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */
12579 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */
12580 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */
12581 
12582 /* Register: TWI_EVENTS_TXDSENT */
12583 /* Description: TWI TXD byte sent */
12584 
12585 /* Bit 0 : TWI TXD byte sent */
12586 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */
12587 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */
12588 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */
12589 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */
12590 
12591 /* Register: TWI_EVENTS_ERROR */
12592 /* Description: TWI error */
12593 
12594 /* Bit 0 : TWI error */
12595 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
12596 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
12597 #define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
12598 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
12599 
12600 /* Register: TWI_EVENTS_BB */
12601 /* Description: TWI byte boundary, generated before each byte that is sent or received */
12602 
12603 /* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */
12604 #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */
12605 #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */
12606 #define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */
12607 #define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */
12608 
12609 /* Register: TWI_EVENTS_SUSPENDED */
12610 /* Description: TWI entered the suspended state */
12611 
12612 /* Bit 0 : TWI entered the suspended state */
12613 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
12614 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
12615 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
12616 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
12617 
12618 /* Register: TWI_SHORTS */
12619 /* Description: Shortcuts between local events and tasks */
12620 
12621 /* Bit 1 : Shortcut between event BB and task STOP */
12622 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
12623 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
12624 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
12625 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
12626 
12627 /* Bit 0 : Shortcut between event BB and task SUSPEND */
12628 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
12629 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
12630 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
12631 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
12632 
12633 /* Register: TWI_INTENSET */
12634 /* Description: Enable interrupt */
12635 
12636 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
12637 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
12638 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
12639 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
12640 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
12641 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
12642 
12643 /* Bit 14 : Write '1' to enable interrupt for event BB */
12644 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
12645 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
12646 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
12647 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
12648 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
12649 
12650 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
12651 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12652 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
12653 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
12654 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
12655 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
12656 
12657 /* Bit 7 : Write '1' to enable interrupt for event TXDSENT */
12658 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
12659 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
12660 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
12661 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
12662 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
12663 
12664 /* Bit 2 : Write '1' to enable interrupt for event RXDREADY */
12665 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
12666 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
12667 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
12668 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
12669 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
12670 
12671 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
12672 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12673 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12674 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12675 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12676 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
12677 
12678 /* Register: TWI_INTENCLR */
12679 /* Description: Disable interrupt */
12680 
12681 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
12682 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
12683 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
12684 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
12685 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
12686 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
12687 
12688 /* Bit 14 : Write '1' to disable interrupt for event BB */
12689 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
12690 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
12691 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
12692 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
12693 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
12694 
12695 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
12696 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12697 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
12698 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
12699 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
12700 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
12701 
12702 /* Bit 7 : Write '1' to disable interrupt for event TXDSENT */
12703 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
12704 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
12705 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
12706 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
12707 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
12708 
12709 /* Bit 2 : Write '1' to disable interrupt for event RXDREADY */
12710 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
12711 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
12712 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
12713 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
12714 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
12715 
12716 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
12717 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12718 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12719 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12720 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12721 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
12722 
12723 /* Register: TWI_ERRORSRC */
12724 /* Description: Error source */
12725 
12726 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
12727 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
12728 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
12729 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
12730 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
12731 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */
12732 
12733 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
12734 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
12735 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
12736 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
12737 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
12738 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */
12739 
12740 /* Bit 0 : Overrun error */
12741 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
12742 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
12743 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
12744 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
12745 #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */
12746 
12747 /* Register: TWI_ENABLE */
12748 /* Description: Enable TWI */
12749 
12750 /* Bits 3..0 : Enable or disable TWI */
12751 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12752 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12753 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
12754 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
12755 
12756 /* Register: TWI_PSELSCL */
12757 /* Description: Pin select for SCL */
12758 
12759 /* Bits 31..0 : Pin number configuration for TWI SCL signal */
12760 #define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
12761 #define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
12762 #define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
12763 
12764 /* Register: TWI_PSELSDA */
12765 /* Description: Pin select for SDA */
12766 
12767 /* Bits 31..0 : Pin number configuration for TWI SDA signal */
12768 #define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
12769 #define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
12770 #define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
12771 
12772 /* Register: TWI_RXD */
12773 /* Description: RXD register */
12774 
12775 /* Bits 7..0 : RXD register */
12776 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
12777 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
12778 
12779 /* Register: TWI_TXD */
12780 /* Description: TXD register */
12781 
12782 /* Bits 7..0 : TXD register */
12783 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
12784 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
12785 
12786 /* Register: TWI_FREQUENCY */
12787 /* Description: TWI frequency */
12788 
12789 /* Bits 31..0 : TWI master clock frequency */
12790 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
12791 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
12792 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
12793 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
12794 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
12795 
12796 /* Register: TWI_ADDRESS */
12797 /* Description: Address used in the TWI transfer */
12798 
12799 /* Bits 6..0 : Address used in the TWI transfer */
12800 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
12801 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
12802 
12803 
12804 /* Peripheral: TWIM */
12805 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
12806 
12807 /* Register: TWIM_TASKS_STARTRX */
12808 /* Description: Start TWI receive sequence */
12809 
12810 /* Bit 0 : Start TWI receive sequence */
12811 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
12812 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
12813 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
12814 
12815 /* Register: TWIM_TASKS_STARTTX */
12816 /* Description: Start TWI transmit sequence */
12817 
12818 /* Bit 0 : Start TWI transmit sequence */
12819 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
12820 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
12821 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
12822 
12823 /* Register: TWIM_TASKS_STOP */
12824 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
12825 
12826 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
12827 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
12828 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
12829 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
12830 
12831 /* Register: TWIM_TASKS_SUSPEND */
12832 /* Description: Suspend TWI transaction */
12833 
12834 /* Bit 0 : Suspend TWI transaction */
12835 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
12836 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
12837 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
12838 
12839 /* Register: TWIM_TASKS_RESUME */
12840 /* Description: Resume TWI transaction */
12841 
12842 /* Bit 0 : Resume TWI transaction */
12843 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
12844 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
12845 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
12846 
12847 /* Register: TWIM_EVENTS_STOPPED */
12848 /* Description: TWI stopped */
12849 
12850 /* Bit 0 : TWI stopped */
12851 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
12852 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
12853 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
12854 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
12855 
12856 /* Register: TWIM_EVENTS_ERROR */
12857 /* Description: TWI error */
12858 
12859 /* Bit 0 : TWI error */
12860 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
12861 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
12862 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
12863 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
12864 
12865 /* Register: TWIM_EVENTS_SUSPENDED */
12866 /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
12867 
12868 /* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
12869 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
12870 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
12871 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
12872 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
12873 
12874 /* Register: TWIM_EVENTS_RXSTARTED */
12875 /* Description: Receive sequence started */
12876 
12877 /* Bit 0 : Receive sequence started */
12878 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
12879 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
12880 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
12881 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
12882 
12883 /* Register: TWIM_EVENTS_TXSTARTED */
12884 /* Description: Transmit sequence started */
12885 
12886 /* Bit 0 : Transmit sequence started */
12887 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
12888 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
12889 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
12890 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
12891 
12892 /* Register: TWIM_EVENTS_LASTRX */
12893 /* Description: Byte boundary, starting to receive the last byte */
12894 
12895 /* Bit 0 : Byte boundary, starting to receive the last byte */
12896 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
12897 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
12898 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
12899 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
12900 
12901 /* Register: TWIM_EVENTS_LASTTX */
12902 /* Description: Byte boundary, starting to transmit the last byte */
12903 
12904 /* Bit 0 : Byte boundary, starting to transmit the last byte */
12905 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
12906 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
12907 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
12908 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
12909 
12910 /* Register: TWIM_SHORTS */
12911 /* Description: Shortcuts between local events and tasks */
12912 
12913 /* Bit 12 : Shortcut between event LASTRX and task STOP */
12914 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
12915 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
12916 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
12917 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
12918 
12919 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
12920 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
12921 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
12922 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
12923 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
12924 
12925 /* Bit 9 : Shortcut between event LASTTX and task STOP */
12926 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
12927 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
12928 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
12929 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
12930 
12931 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
12932 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
12933 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
12934 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
12935 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
12936 
12937 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
12938 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
12939 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
12940 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
12941 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
12942 
12943 /* Register: TWIM_INTEN */
12944 /* Description: Enable or disable interrupt */
12945 
12946 /* Bit 24 : Enable or disable interrupt for event LASTTX */
12947 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
12948 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
12949 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
12950 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
12951 
12952 /* Bit 23 : Enable or disable interrupt for event LASTRX */
12953 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
12954 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
12955 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
12956 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
12957 
12958 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
12959 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
12960 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
12961 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
12962 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
12963 
12964 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
12965 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
12966 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
12967 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
12968 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
12969 
12970 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
12971 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
12972 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
12973 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
12974 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
12975 
12976 /* Bit 9 : Enable or disable interrupt for event ERROR */
12977 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12978 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
12979 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
12980 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
12981 
12982 /* Bit 1 : Enable or disable interrupt for event STOPPED */
12983 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
12984 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
12985 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
12986 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
12987 
12988 /* Register: TWIM_INTENSET */
12989 /* Description: Enable interrupt */
12990 
12991 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
12992 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
12993 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
12994 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
12995 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
12996 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
12997 
12998 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
12999 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
13000 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
13001 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
13002 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
13003 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
13004 
13005 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
13006 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
13007 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
13008 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13009 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13010 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
13011 
13012 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
13013 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
13014 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
13015 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13016 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13017 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
13018 
13019 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
13020 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
13021 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
13022 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13023 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13024 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
13025 
13026 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
13027 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13028 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
13029 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13030 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13031 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
13032 
13033 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
13034 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13035 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13036 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13037 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13038 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
13039 
13040 /* Register: TWIM_INTENCLR */
13041 /* Description: Disable interrupt */
13042 
13043 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
13044 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
13045 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
13046 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
13047 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
13048 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
13049 
13050 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
13051 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
13052 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
13053 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
13054 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
13055 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
13056 
13057 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
13058 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
13059 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
13060 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13061 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13062 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
13063 
13064 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
13065 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
13066 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
13067 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13068 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13069 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
13070 
13071 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
13072 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
13073 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
13074 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13075 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13076 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
13077 
13078 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
13079 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13080 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
13081 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13082 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13083 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
13084 
13085 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
13086 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13087 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13088 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13089 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13090 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
13091 
13092 /* Register: TWIM_ERRORSRC */
13093 /* Description: Error source */
13094 
13095 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
13096 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
13097 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
13098 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
13099 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
13100 
13101 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
13102 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
13103 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
13104 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
13105 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
13106 
13107 /* Bit 0 : Overrun error */
13108 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
13109 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
13110 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
13111 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
13112 
13113 /* Register: TWIM_ENABLE */
13114 /* Description: Enable TWIM */
13115 
13116 /* Bits 3..0 : Enable or disable TWIM */
13117 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13118 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13119 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
13120 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
13121 
13122 /* Register: TWIM_PSEL_SCL */
13123 /* Description: Pin select for SCL signal */
13124 
13125 /* Bit 31 : Connection */
13126 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13127 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13128 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
13129 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
13130 
13131 /* Bits 4..0 : Pin number */
13132 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
13133 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
13134 
13135 /* Register: TWIM_PSEL_SDA */
13136 /* Description: Pin select for SDA signal */
13137 
13138 /* Bit 31 : Connection */
13139 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13140 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13141 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
13142 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
13143 
13144 /* Bits 4..0 : Pin number */
13145 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
13146 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
13147 
13148 /* Register: TWIM_FREQUENCY */
13149 /* Description: TWI frequency */
13150 
13151 /* Bits 31..0 : TWI master clock frequency */
13152 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
13153 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
13154 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
13155 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
13156 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
13157 
13158 /* Register: TWIM_RXD_PTR */
13159 /* Description: Data pointer */
13160 
13161 /* Bits 31..0 : Data pointer */
13162 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
13163 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
13164 
13165 /* Register: TWIM_RXD_MAXCNT */
13166 /* Description: Maximum number of bytes in receive buffer */
13167 
13168 /* Bits 7..0 : Maximum number of bytes in receive buffer */
13169 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
13170 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
13171 
13172 /* Register: TWIM_RXD_AMOUNT */
13173 /* Description: Number of bytes transferred in the last transaction */
13174 
13175 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
13176 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
13177 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
13178 
13179 /* Register: TWIM_RXD_LIST */
13180 /* Description: EasyDMA list type */
13181 
13182 /* Bits 2..0 : List type */
13183 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
13184 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
13185 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
13186 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
13187 
13188 /* Register: TWIM_TXD_PTR */
13189 /* Description: Data pointer */
13190 
13191 /* Bits 31..0 : Data pointer */
13192 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
13193 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
13194 
13195 /* Register: TWIM_TXD_MAXCNT */
13196 /* Description: Maximum number of bytes in transmit buffer */
13197 
13198 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
13199 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
13200 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
13201 
13202 /* Register: TWIM_TXD_AMOUNT */
13203 /* Description: Number of bytes transferred in the last transaction */
13204 
13205 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
13206 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
13207 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
13208 
13209 /* Register: TWIM_TXD_LIST */
13210 /* Description: EasyDMA list type */
13211 
13212 /* Bits 2..0 : List type */
13213 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
13214 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
13215 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
13216 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
13217 
13218 /* Register: TWIM_ADDRESS */
13219 /* Description: Address used in the TWI transfer */
13220 
13221 /* Bits 6..0 : Address used in the TWI transfer */
13222 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
13223 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
13224 
13225 
13226 /* Peripheral: TWIS */
13227 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
13228 
13229 /* Register: TWIS_TASKS_STOP */
13230 /* Description: Stop TWI transaction */
13231 
13232 /* Bit 0 : Stop TWI transaction */
13233 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
13234 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
13235 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
13236 
13237 /* Register: TWIS_TASKS_SUSPEND */
13238 /* Description: Suspend TWI transaction */
13239 
13240 /* Bit 0 : Suspend TWI transaction */
13241 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
13242 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
13243 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
13244 
13245 /* Register: TWIS_TASKS_RESUME */
13246 /* Description: Resume TWI transaction */
13247 
13248 /* Bit 0 : Resume TWI transaction */
13249 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
13250 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
13251 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
13252 
13253 /* Register: TWIS_TASKS_PREPARERX */
13254 /* Description: Prepare the TWI slave to respond to a write command */
13255 
13256 /* Bit 0 : Prepare the TWI slave to respond to a write command */
13257 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
13258 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
13259 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
13260 
13261 /* Register: TWIS_TASKS_PREPARETX */
13262 /* Description: Prepare the TWI slave to respond to a read command */
13263 
13264 /* Bit 0 : Prepare the TWI slave to respond to a read command */
13265 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
13266 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
13267 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
13268 
13269 /* Register: TWIS_EVENTS_STOPPED */
13270 /* Description: TWI stopped */
13271 
13272 /* Bit 0 : TWI stopped */
13273 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
13274 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
13275 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
13276 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
13277 
13278 /* Register: TWIS_EVENTS_ERROR */
13279 /* Description: TWI error */
13280 
13281 /* Bit 0 : TWI error */
13282 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
13283 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
13284 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
13285 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
13286 
13287 /* Register: TWIS_EVENTS_RXSTARTED */
13288 /* Description: Receive sequence started */
13289 
13290 /* Bit 0 : Receive sequence started */
13291 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
13292 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
13293 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
13294 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
13295 
13296 /* Register: TWIS_EVENTS_TXSTARTED */
13297 /* Description: Transmit sequence started */
13298 
13299 /* Bit 0 : Transmit sequence started */
13300 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
13301 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
13302 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
13303 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
13304 
13305 /* Register: TWIS_EVENTS_WRITE */
13306 /* Description: Write command received */
13307 
13308 /* Bit 0 : Write command received */
13309 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
13310 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
13311 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
13312 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
13313 
13314 /* Register: TWIS_EVENTS_READ */
13315 /* Description: Read command received */
13316 
13317 /* Bit 0 : Read command received */
13318 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
13319 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
13320 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
13321 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
13322 
13323 /* Register: TWIS_SHORTS */
13324 /* Description: Shortcuts between local events and tasks */
13325 
13326 /* Bit 14 : Shortcut between event READ and task SUSPEND */
13327 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
13328 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
13329 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
13330 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
13331 
13332 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
13333 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
13334 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
13335 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
13336 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
13337 
13338 /* Register: TWIS_INTEN */
13339 /* Description: Enable or disable interrupt */
13340 
13341 /* Bit 26 : Enable or disable interrupt for event READ */
13342 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
13343 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
13344 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
13345 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
13346 
13347 /* Bit 25 : Enable or disable interrupt for event WRITE */
13348 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
13349 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
13350 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
13351 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
13352 
13353 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
13354 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
13355 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
13356 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
13357 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
13358 
13359 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
13360 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
13361 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
13362 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
13363 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
13364 
13365 /* Bit 9 : Enable or disable interrupt for event ERROR */
13366 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13367 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
13368 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
13369 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
13370 
13371 /* Bit 1 : Enable or disable interrupt for event STOPPED */
13372 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13373 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13374 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
13375 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
13376 
13377 /* Register: TWIS_INTENSET */
13378 /* Description: Enable interrupt */
13379 
13380 /* Bit 26 : Write '1' to enable interrupt for event READ */
13381 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
13382 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
13383 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
13384 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
13385 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
13386 
13387 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
13388 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
13389 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
13390 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
13391 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
13392 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
13393 
13394 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
13395 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
13396 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
13397 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13398 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13399 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
13400 
13401 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
13402 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
13403 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
13404 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13405 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13406 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
13407 
13408 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
13409 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13410 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
13411 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13412 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13413 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
13414 
13415 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
13416 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13417 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13418 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13419 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13420 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
13421 
13422 /* Register: TWIS_INTENCLR */
13423 /* Description: Disable interrupt */
13424 
13425 /* Bit 26 : Write '1' to disable interrupt for event READ */
13426 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
13427 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
13428 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
13429 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
13430 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
13431 
13432 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
13433 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
13434 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
13435 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
13436 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
13437 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
13438 
13439 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
13440 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
13441 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
13442 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13443 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13444 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
13445 
13446 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
13447 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
13448 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
13449 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13450 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13451 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
13452 
13453 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
13454 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13455 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
13456 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13457 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13458 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
13459 
13460 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
13461 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
13462 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
13463 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13464 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13465 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
13466 
13467 /* Register: TWIS_ERRORSRC */
13468 /* Description: Error source */
13469 
13470 /* Bit 3 : TX buffer over-read detected, and prevented */
13471 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
13472 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
13473 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
13474 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
13475 
13476 /* Bit 2 : NACK sent after receiving a data byte */
13477 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
13478 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
13479 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
13480 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
13481 
13482 /* Bit 0 : RX buffer overflow detected, and prevented */
13483 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
13484 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
13485 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
13486 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
13487 
13488 /* Register: TWIS_MATCH */
13489 /* Description: Status register indicating which address had a match */
13490 
13491 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
13492 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
13493 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
13494 
13495 /* Register: TWIS_ENABLE */
13496 /* Description: Enable TWIS */
13497 
13498 /* Bits 3..0 : Enable or disable TWIS */
13499 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13500 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13501 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
13502 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
13503 
13504 /* Register: TWIS_PSEL_SCL */
13505 /* Description: Pin select for SCL signal */
13506 
13507 /* Bit 31 : Connection */
13508 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13509 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13510 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
13511 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
13512 
13513 /* Bits 4..0 : Pin number */
13514 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
13515 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
13516 
13517 /* Register: TWIS_PSEL_SDA */
13518 /* Description: Pin select for SDA signal */
13519 
13520 /* Bit 31 : Connection */
13521 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
13522 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
13523 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
13524 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
13525 
13526 /* Bits 4..0 : Pin number */
13527 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
13528 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
13529 
13530 /* Register: TWIS_RXD_PTR */
13531 /* Description: RXD Data pointer */
13532 
13533 /* Bits 31..0 : RXD Data pointer */
13534 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
13535 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
13536 
13537 /* Register: TWIS_RXD_MAXCNT */
13538 /* Description: Maximum number of bytes in RXD buffer */
13539 
13540 /* Bits 7..0 : Maximum number of bytes in RXD buffer */
13541 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
13542 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
13543 
13544 /* Register: TWIS_RXD_AMOUNT */
13545 /* Description: Number of bytes transferred in the last RXD transaction */
13546 
13547 /* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
13548 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
13549 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
13550 
13551 /* Register: TWIS_TXD_PTR */
13552 /* Description: TXD Data pointer */
13553 
13554 /* Bits 31..0 : TXD Data pointer */
13555 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
13556 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
13557 
13558 /* Register: TWIS_TXD_MAXCNT */
13559 /* Description: Maximum number of bytes in TXD buffer */
13560 
13561 /* Bits 7..0 : Maximum number of bytes in TXD buffer */
13562 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
13563 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
13564 
13565 /* Register: TWIS_TXD_AMOUNT */
13566 /* Description: Number of bytes transferred in the last TXD transaction */
13567 
13568 /* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
13569 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
13570 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
13571 
13572 /* Register: TWIS_ADDRESS */
13573 /* Description: Description collection: TWI slave address n */
13574 
13575 /* Bits 6..0 : TWI slave address */
13576 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
13577 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
13578 
13579 /* Register: TWIS_CONFIG */
13580 /* Description: Configuration register for the address match mechanism */
13581 
13582 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
13583 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
13584 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
13585 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
13586 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
13587 
13588 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
13589 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
13590 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
13591 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
13592 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
13593 
13594 /* Register: TWIS_ORC */
13595 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
13596 
13597 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
13598 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
13599 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
13600 
13601 
13602 /* Peripheral: UART */
13603 /* Description: Universal Asynchronous Receiver/Transmitter */
13604 
13605 /* Register: UART_TASKS_STARTRX */
13606 /* Description: Start UART receiver */
13607 
13608 /* Bit 0 : Start UART receiver */
13609 #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
13610 #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
13611 #define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
13612 
13613 /* Register: UART_TASKS_STOPRX */
13614 /* Description: Stop UART receiver */
13615 
13616 /* Bit 0 : Stop UART receiver */
13617 #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
13618 #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
13619 #define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
13620 
13621 /* Register: UART_TASKS_STARTTX */
13622 /* Description: Start UART transmitter */
13623 
13624 /* Bit 0 : Start UART transmitter */
13625 #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
13626 #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
13627 #define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
13628 
13629 /* Register: UART_TASKS_STOPTX */
13630 /* Description: Stop UART transmitter */
13631 
13632 /* Bit 0 : Stop UART transmitter */
13633 #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
13634 #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
13635 #define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
13636 
13637 /* Register: UART_TASKS_SUSPEND */
13638 /* Description: Suspend UART */
13639 
13640 /* Bit 0 : Suspend UART */
13641 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
13642 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
13643 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
13644 
13645 /* Register: UART_EVENTS_CTS */
13646 /* Description: CTS is activated (set low). Clear To Send. */
13647 
13648 /* Bit 0 : CTS is activated (set low). Clear To Send. */
13649 #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
13650 #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
13651 #define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
13652 #define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
13653 
13654 /* Register: UART_EVENTS_NCTS */
13655 /* Description: CTS is deactivated (set high). Not Clear To Send. */
13656 
13657 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
13658 #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
13659 #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
13660 #define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
13661 #define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
13662 
13663 /* Register: UART_EVENTS_RXDRDY */
13664 /* Description: Data received in RXD */
13665 
13666 /* Bit 0 : Data received in RXD */
13667 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
13668 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
13669 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
13670 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
13671 
13672 /* Register: UART_EVENTS_TXDRDY */
13673 /* Description: Data sent from TXD */
13674 
13675 /* Bit 0 : Data sent from TXD */
13676 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
13677 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
13678 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
13679 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
13680 
13681 /* Register: UART_EVENTS_ERROR */
13682 /* Description: Error detected */
13683 
13684 /* Bit 0 : Error detected */
13685 #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
13686 #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
13687 #define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
13688 #define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
13689 
13690 /* Register: UART_EVENTS_RXTO */
13691 /* Description: Receiver timeout */
13692 
13693 /* Bit 0 : Receiver timeout */
13694 #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
13695 #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
13696 #define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
13697 #define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
13698 
13699 /* Register: UART_SHORTS */
13700 /* Description: Shortcuts between local events and tasks */
13701 
13702 /* Bit 4 : Shortcut between event NCTS and task STOPRX */
13703 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
13704 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
13705 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
13706 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
13707 
13708 /* Bit 3 : Shortcut between event CTS and task STARTRX */
13709 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
13710 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
13711 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
13712 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
13713 
13714 /* Register: UART_INTENSET */
13715 /* Description: Enable interrupt */
13716 
13717 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
13718 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
13719 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
13720 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
13721 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
13722 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
13723 
13724 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
13725 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13726 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
13727 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13728 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13729 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
13730 
13731 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
13732 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
13733 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
13734 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
13735 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
13736 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
13737 
13738 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
13739 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
13740 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
13741 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
13742 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
13743 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
13744 
13745 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
13746 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
13747 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
13748 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
13749 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
13750 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
13751 
13752 /* Bit 0 : Write '1' to enable interrupt for event CTS */
13753 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
13754 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
13755 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
13756 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
13757 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
13758 
13759 /* Register: UART_INTENCLR */
13760 /* Description: Disable interrupt */
13761 
13762 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
13763 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
13764 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
13765 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
13766 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
13767 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
13768 
13769 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
13770 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
13771 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
13772 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13773 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13774 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
13775 
13776 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
13777 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
13778 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
13779 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
13780 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
13781 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
13782 
13783 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
13784 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
13785 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
13786 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
13787 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
13788 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
13789 
13790 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
13791 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
13792 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
13793 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
13794 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
13795 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
13796 
13797 /* Bit 0 : Write '1' to disable interrupt for event CTS */
13798 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
13799 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
13800 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
13801 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
13802 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
13803 
13804 /* Register: UART_ERRORSRC */
13805 /* Description: Error source */
13806 
13807 /* Bit 3 : Break condition */
13808 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
13809 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
13810 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
13811 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
13812 
13813 /* Bit 2 : Framing error occurred */
13814 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
13815 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
13816 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
13817 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
13818 
13819 /* Bit 1 : Parity error */
13820 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
13821 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
13822 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
13823 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
13824 
13825 /* Bit 0 : Overrun error */
13826 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
13827 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
13828 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
13829 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
13830 
13831 /* Register: UART_ENABLE */
13832 /* Description: Enable UART */
13833 
13834 /* Bits 3..0 : Enable or disable UART */
13835 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
13836 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
13837 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
13838 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
13839 
13840 /* Register: UART_PSELRTS */
13841 /* Description: Pin select for RTS */
13842 
13843 /* Bits 31..0 : Pin number configuration for UART RTS signal */
13844 #define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
13845 #define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
13846 #define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
13847 
13848 /* Register: UART_PSELTXD */
13849 /* Description: Pin select for TXD */
13850 
13851 /* Bits 31..0 : Pin number configuration for UART TXD signal */
13852 #define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
13853 #define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
13854 #define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
13855 
13856 /* Register: UART_PSELCTS */
13857 /* Description: Pin select for CTS */
13858 
13859 /* Bits 31..0 : Pin number configuration for UART CTS signal */
13860 #define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
13861 #define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
13862 #define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
13863 
13864 /* Register: UART_PSELRXD */
13865 /* Description: Pin select for RXD */
13866 
13867 /* Bits 31..0 : Pin number configuration for UART RXD signal */
13868 #define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
13869 #define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
13870 #define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
13871 
13872 /* Register: UART_RXD */
13873 /* Description: RXD register */
13874 
13875 /* Bits 7..0 : RX data received in previous transfers, double buffered */
13876 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
13877 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
13878 
13879 /* Register: UART_TXD */
13880 /* Description: TXD register */
13881 
13882 /* Bits 7..0 : TX data to be transferred */
13883 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
13884 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
13885 
13886 /* Register: UART_BAUDRATE */
13887 /* Description: Baud rate */
13888 
13889 /* Bits 31..0 : Baud rate */
13890 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
13891 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
13892 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
13893 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
13894 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
13895 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
13896 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
13897 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
13898 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
13899 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
13900 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
13901 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
13902 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
13903 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
13904 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
13905 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
13906 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
13907 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
13908 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
13909 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
13910 
13911 /* Register: UART_CONFIG */
13912 /* Description: Configuration of parity and hardware flow control */
13913 
13914 /* Bits 3..1 : Parity */
13915 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
13916 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
13917 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
13918 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
13919 
13920 /* Bit 0 : Hardware flow control */
13921 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
13922 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
13923 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
13924 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
13925 
13926 
13927 /* Peripheral: UARTE */
13928 /* Description: UART with EasyDMA */
13929 
13930 /* Register: UARTE_TASKS_STARTRX */
13931 /* Description: Start UART receiver */
13932 
13933 /* Bit 0 : Start UART receiver */
13934 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
13935 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
13936 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
13937 
13938 /* Register: UARTE_TASKS_STOPRX */
13939 /* Description: Stop UART receiver */
13940 
13941 /* Bit 0 : Stop UART receiver */
13942 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
13943 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
13944 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
13945 
13946 /* Register: UARTE_TASKS_STARTTX */
13947 /* Description: Start UART transmitter */
13948 
13949 /* Bit 0 : Start UART transmitter */
13950 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
13951 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
13952 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
13953 
13954 /* Register: UARTE_TASKS_STOPTX */
13955 /* Description: Stop UART transmitter */
13956 
13957 /* Bit 0 : Stop UART transmitter */
13958 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
13959 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
13960 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
13961 
13962 /* Register: UARTE_TASKS_FLUSHRX */
13963 /* Description: Flush RX FIFO into RX buffer */
13964 
13965 /* Bit 0 : Flush RX FIFO into RX buffer */
13966 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
13967 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
13968 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
13969 
13970 /* Register: UARTE_EVENTS_CTS */
13971 /* Description: CTS is activated (set low). Clear To Send. */
13972 
13973 /* Bit 0 : CTS is activated (set low). Clear To Send. */
13974 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
13975 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
13976 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
13977 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
13978 
13979 /* Register: UARTE_EVENTS_NCTS */
13980 /* Description: CTS is deactivated (set high). Not Clear To Send. */
13981 
13982 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
13983 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
13984 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
13985 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
13986 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
13987 
13988 /* Register: UARTE_EVENTS_RXDRDY */
13989 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
13990 
13991 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
13992 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
13993 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
13994 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
13995 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
13996 
13997 /* Register: UARTE_EVENTS_ENDRX */
13998 /* Description: Receive buffer is filled up */
13999 
14000 /* Bit 0 : Receive buffer is filled up */
14001 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
14002 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
14003 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
14004 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
14005 
14006 /* Register: UARTE_EVENTS_TXDRDY */
14007 /* Description: Data sent from TXD */
14008 
14009 /* Bit 0 : Data sent from TXD */
14010 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
14011 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
14012 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
14013 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
14014 
14015 /* Register: UARTE_EVENTS_ENDTX */
14016 /* Description: Last TX byte transmitted */
14017 
14018 /* Bit 0 : Last TX byte transmitted */
14019 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
14020 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
14021 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
14022 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
14023 
14024 /* Register: UARTE_EVENTS_ERROR */
14025 /* Description: Error detected */
14026 
14027 /* Bit 0 : Error detected */
14028 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
14029 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
14030 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
14031 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
14032 
14033 /* Register: UARTE_EVENTS_RXTO */
14034 /* Description: Receiver timeout */
14035 
14036 /* Bit 0 : Receiver timeout */
14037 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
14038 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
14039 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
14040 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
14041 
14042 /* Register: UARTE_EVENTS_RXSTARTED */
14043 /* Description: UART receiver has started */
14044 
14045 /* Bit 0 : UART receiver has started */
14046 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
14047 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
14048 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14049 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
14050 
14051 /* Register: UARTE_EVENTS_TXSTARTED */
14052 /* Description: UART transmitter has started */
14053 
14054 /* Bit 0 : UART transmitter has started */
14055 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
14056 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
14057 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
14058 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
14059 
14060 /* Register: UARTE_EVENTS_TXSTOPPED */
14061 /* Description: Transmitter stopped */
14062 
14063 /* Bit 0 : Transmitter stopped */
14064 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
14065 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
14066 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
14067 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
14068 
14069 /* Register: UARTE_SHORTS */
14070 /* Description: Shortcuts between local events and tasks */
14071 
14072 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
14073 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
14074 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
14075 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
14076 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
14077 
14078 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
14079 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
14080 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
14081 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
14082 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
14083 
14084 /* Register: UARTE_INTEN */
14085 /* Description: Enable or disable interrupt */
14086 
14087 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
14088 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
14089 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
14090 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
14091 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
14092 
14093 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
14094 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14095 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14096 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
14097 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
14098 
14099 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
14100 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14101 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14102 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
14103 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
14104 
14105 /* Bit 17 : Enable or disable interrupt for event RXTO */
14106 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
14107 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
14108 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
14109 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
14110 
14111 /* Bit 9 : Enable or disable interrupt for event ERROR */
14112 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14113 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
14114 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
14115 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
14116 
14117 /* Bit 8 : Enable or disable interrupt for event ENDTX */
14118 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
14119 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
14120 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
14121 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
14122 
14123 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
14124 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
14125 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
14126 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
14127 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
14128 
14129 /* Bit 4 : Enable or disable interrupt for event ENDRX */
14130 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
14131 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
14132 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
14133 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
14134 
14135 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
14136 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
14137 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
14138 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
14139 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
14140 
14141 /* Bit 1 : Enable or disable interrupt for event NCTS */
14142 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
14143 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
14144 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
14145 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
14146 
14147 /* Bit 0 : Enable or disable interrupt for event CTS */
14148 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
14149 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
14150 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
14151 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
14152 
14153 /* Register: UARTE_INTENSET */
14154 /* Description: Enable interrupt */
14155 
14156 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
14157 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
14158 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
14159 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
14160 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
14161 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
14162 
14163 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
14164 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14165 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14166 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14167 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14168 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
14169 
14170 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
14171 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14172 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14173 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14174 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14175 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
14176 
14177 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
14178 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
14179 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
14180 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
14181 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
14182 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
14183 
14184 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
14185 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14186 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
14187 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14188 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14189 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
14190 
14191 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
14192 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
14193 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
14194 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
14195 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
14196 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
14197 
14198 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
14199 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
14200 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
14201 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14202 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14203 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
14204 
14205 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
14206 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
14207 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
14208 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
14209 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
14210 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
14211 
14212 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
14213 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
14214 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
14215 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
14216 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
14217 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
14218 
14219 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
14220 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
14221 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
14222 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
14223 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
14224 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
14225 
14226 /* Bit 0 : Write '1' to enable interrupt for event CTS */
14227 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
14228 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
14229 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
14230 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
14231 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
14232 
14233 /* Register: UARTE_INTENCLR */
14234 /* Description: Disable interrupt */
14235 
14236 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
14237 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
14238 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
14239 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
14240 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
14241 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
14242 
14243 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
14244 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
14245 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
14246 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14247 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14248 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
14249 
14250 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
14251 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
14252 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
14253 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14254 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14255 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
14256 
14257 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
14258 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
14259 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
14260 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
14261 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
14262 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
14263 
14264 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
14265 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
14266 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
14267 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14268 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14269 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
14270 
14271 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
14272 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
14273 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
14274 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
14275 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
14276 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
14277 
14278 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
14279 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
14280 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
14281 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14282 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14283 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
14284 
14285 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
14286 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
14287 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
14288 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
14289 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
14290 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
14291 
14292 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
14293 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
14294 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
14295 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
14296 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
14297 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
14298 
14299 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
14300 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
14301 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
14302 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
14303 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
14304 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
14305 
14306 /* Bit 0 : Write '1' to disable interrupt for event CTS */
14307 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
14308 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
14309 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
14310 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
14311 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
14312 
14313 /* Register: UARTE_ERRORSRC */
14314 /* Description: Error source */
14315 
14316 /* Bit 3 : Break condition */
14317 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
14318 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
14319 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
14320 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
14321 
14322 /* Bit 2 : Framing error occurred */
14323 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
14324 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
14325 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
14326 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
14327 
14328 /* Bit 1 : Parity error */
14329 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
14330 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
14331 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
14332 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
14333 
14334 /* Bit 0 : Overrun error */
14335 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
14336 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
14337 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
14338 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
14339 
14340 /* Register: UARTE_ENABLE */
14341 /* Description: Enable UART */
14342 
14343 /* Bits 3..0 : Enable or disable UARTE */
14344 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
14345 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
14346 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
14347 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
14348 
14349 /* Register: UARTE_PSEL_RTS */
14350 /* Description: Pin select for RTS signal */
14351 
14352 /* Bit 31 : Connection */
14353 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14354 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14355 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
14356 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
14357 
14358 /* Bits 4..0 : Pin number */
14359 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
14360 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
14361 
14362 /* Register: UARTE_PSEL_TXD */
14363 /* Description: Pin select for TXD signal */
14364 
14365 /* Bit 31 : Connection */
14366 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14367 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14368 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
14369 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
14370 
14371 /* Bits 4..0 : Pin number */
14372 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
14373 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
14374 
14375 /* Register: UARTE_PSEL_CTS */
14376 /* Description: Pin select for CTS signal */
14377 
14378 /* Bit 31 : Connection */
14379 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14380 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14381 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
14382 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
14383 
14384 /* Bits 4..0 : Pin number */
14385 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
14386 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
14387 
14388 /* Register: UARTE_PSEL_RXD */
14389 /* Description: Pin select for RXD signal */
14390 
14391 /* Bit 31 : Connection */
14392 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14393 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14394 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
14395 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
14396 
14397 /* Bits 4..0 : Pin number */
14398 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
14399 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
14400 
14401 /* Register: UARTE_BAUDRATE */
14402 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
14403 
14404 /* Bits 31..0 : Baud rate */
14405 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
14406 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
14407 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
14408 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
14409 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
14410 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
14411 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
14412 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
14413 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
14414 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
14415 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
14416 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
14417 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
14418 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
14419 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
14420 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
14421 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
14422 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
14423 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
14424 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
14425 
14426 /* Register: UARTE_RXD_PTR */
14427 /* Description: Data pointer */
14428 
14429 /* Bits 31..0 : Data pointer */
14430 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14431 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14432 
14433 /* Register: UARTE_RXD_MAXCNT */
14434 /* Description: Maximum number of bytes in receive buffer */
14435 
14436 /* Bits 7..0 : Maximum number of bytes in receive buffer */
14437 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14438 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14439 
14440 /* Register: UARTE_RXD_AMOUNT */
14441 /* Description: Number of bytes transferred in the last transaction */
14442 
14443 /* Bits 7..0 : Number of bytes transferred in the last transaction */
14444 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14445 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14446 
14447 /* Register: UARTE_TXD_PTR */
14448 /* Description: Data pointer */
14449 
14450 /* Bits 31..0 : Data pointer */
14451 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
14452 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
14453 
14454 /* Register: UARTE_TXD_MAXCNT */
14455 /* Description: Maximum number of bytes in transmit buffer */
14456 
14457 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
14458 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
14459 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
14460 
14461 /* Register: UARTE_TXD_AMOUNT */
14462 /* Description: Number of bytes transferred in the last transaction */
14463 
14464 /* Bits 7..0 : Number of bytes transferred in the last transaction */
14465 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
14466 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
14467 
14468 /* Register: UARTE_CONFIG */
14469 /* Description: Configuration of parity and hardware flow control */
14470 
14471 /* Bits 3..1 : Parity */
14472 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
14473 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
14474 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
14475 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
14476 
14477 /* Bit 0 : Hardware flow control */
14478 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
14479 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
14480 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
14481 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
14482 
14483 
14484 /* Peripheral: UICR */
14485 /* Description: User Information Configuration Registers */
14486 
14487 /* Register: UICR_NRFFW */
14488 /* Description: Description collection: Reserved for Nordic firmware design */
14489 
14490 /* Bits 31..0 : Reserved for Nordic firmware design */
14491 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
14492 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
14493 
14494 /* Register: UICR_NRFHW */
14495 /* Description: Description collection: Reserved for Nordic hardware design */
14496 
14497 /* Bits 31..0 : Reserved for Nordic hardware design */
14498 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
14499 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
14500 
14501 /* Register: UICR_CUSTOMER */
14502 /* Description: Description collection: Reserved for customer */
14503 
14504 /* Bits 31..0 : Reserved for customer */
14505 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
14506 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
14507 
14508 /* Register: UICR_PSELRESET */
14509 /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */
14510 
14511 /* Bit 31 : Connection */
14512 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
14513 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
14514 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
14515 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
14516 
14517 /* Bits 5..0 : GPIO number P0.n onto which Reset is exposed */
14518 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
14519 #define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
14520 
14521 /* Register: UICR_APPROTECT */
14522 /* Description: Access port protection */
14523 
14524 /* Bits 7..0 : Enable or disable access port protection. */
14525 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
14526 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
14527 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
14528 #define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */
14529 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */
14530 
14531 /* Register: UICR_NFCPINS */
14532 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
14533 
14534 /* Bit 0 : Setting of pins dedicated to NFC functionality */
14535 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
14536 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
14537 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */
14538 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */
14539 
14540 
14541 /* Peripheral: WDT */
14542 /* Description: Watchdog Timer */
14543 
14544 /* Register: WDT_TASKS_START */
14545 /* Description: Start the watchdog */
14546 
14547 /* Bit 0 : Start the watchdog */
14548 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
14549 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
14550 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
14551 
14552 /* Register: WDT_EVENTS_TIMEOUT */
14553 /* Description: Watchdog timeout */
14554 
14555 /* Bit 0 : Watchdog timeout */
14556 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
14557 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
14558 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
14559 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
14560 
14561 /* Register: WDT_INTENSET */
14562 /* Description: Enable interrupt */
14563 
14564 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
14565 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
14566 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
14567 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
14568 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
14569 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
14570 
14571 /* Register: WDT_INTENCLR */
14572 /* Description: Disable interrupt */
14573 
14574 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
14575 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
14576 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
14577 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
14578 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
14579 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
14580 
14581 /* Register: WDT_RUNSTATUS */
14582 /* Description: Run status */
14583 
14584 /* Bit 0 : Indicates whether or not the watchdog is running */
14585 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
14586 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
14587 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
14588 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
14589 
14590 /* Register: WDT_REQSTATUS */
14591 /* Description: Request status */
14592 
14593 /* Bit 7 : Request status for RR[7] register */
14594 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
14595 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
14596 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
14597 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
14598 
14599 /* Bit 6 : Request status for RR[6] register */
14600 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
14601 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
14602 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
14603 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
14604 
14605 /* Bit 5 : Request status for RR[5] register */
14606 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
14607 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
14608 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
14609 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
14610 
14611 /* Bit 4 : Request status for RR[4] register */
14612 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
14613 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
14614 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
14615 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
14616 
14617 /* Bit 3 : Request status for RR[3] register */
14618 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
14619 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
14620 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
14621 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
14622 
14623 /* Bit 2 : Request status for RR[2] register */
14624 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
14625 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
14626 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
14627 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
14628 
14629 /* Bit 1 : Request status for RR[1] register */
14630 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
14631 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
14632 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
14633 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
14634 
14635 /* Bit 0 : Request status for RR[0] register */
14636 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
14637 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
14638 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
14639 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
14640 
14641 /* Register: WDT_CRV */
14642 /* Description: Counter reload value */
14643 
14644 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
14645 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
14646 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
14647 
14648 /* Register: WDT_RREN */
14649 /* Description: Enable register for reload request registers */
14650 
14651 /* Bit 7 : Enable or disable RR[7] register */
14652 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
14653 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
14654 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
14655 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
14656 
14657 /* Bit 6 : Enable or disable RR[6] register */
14658 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
14659 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
14660 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
14661 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
14662 
14663 /* Bit 5 : Enable or disable RR[5] register */
14664 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
14665 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
14666 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
14667 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
14668 
14669 /* Bit 4 : Enable or disable RR[4] register */
14670 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
14671 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
14672 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
14673 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
14674 
14675 /* Bit 3 : Enable or disable RR[3] register */
14676 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
14677 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
14678 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
14679 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
14680 
14681 /* Bit 2 : Enable or disable RR[2] register */
14682 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
14683 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
14684 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
14685 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
14686 
14687 /* Bit 1 : Enable or disable RR[1] register */
14688 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
14689 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
14690 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
14691 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
14692 
14693 /* Bit 0 : Enable or disable RR[0] register */
14694 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
14695 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
14696 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
14697 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
14698 
14699 /* Register: WDT_CONFIG */
14700 /* Description: Configuration register */
14701 
14702 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
14703 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
14704 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
14705 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
14706 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
14707 
14708 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
14709 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
14710 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
14711 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
14712 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
14713 
14714 /* Register: WDT_RR */
14715 /* Description: Description collection: Reload request n */
14716 
14717 /* Bits 31..0 : Reload request register */
14718 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
14719 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
14720 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
14721 
14722 
14723 /*lint --flb "Leave library region" */
14724 #endif
14725