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Searched refs:temp_reg (Results 1 – 5 of 5) sorted by relevance

/hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/
Dvsc8662_phy.c55 uint16_t temp_reg; in vsc8662_enable_bcast_writes() local
59 temp_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)(phy_base_address), 22); in vsc8662_enable_bcast_writes()
60 temp_reg |= 0x0001U; in vsc8662_enable_bcast_writes()
61 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address), 22, temp_reg); in vsc8662_enable_bcast_writes()
71 uint16_t temp_reg; in vsc8662_disable_bcast_writes() local
75 temp_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)(phy_base_address), 22); in vsc8662_disable_bcast_writes()
76 temp_reg &= 0xFFFEU; in vsc8662_disable_bcast_writes()
77 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address), 22, temp_reg); in vsc8662_disable_bcast_writes()
87 uint16_t temp_reg; in vsc8662_enable_LED_blink() local
96 temp_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)(phy_base_address + count), 19); in vsc8662_enable_LED_blink()
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Dvsc8541_phy.c101 volatile uint16_t temp_reg; in MSS_MAC_VSC8541_phy_init()
161 temp_reg = MSS_MAC_read_phy_reg(this_mac, phy_addr, 0); in MSS_MAC_VSC8541_phy_init()
162 temp_reg |= 0x8000U; in MSS_MAC_VSC8541_phy_init()
163 MSS_MAC_write_phy_reg(this_mac, phy_addr, 0, temp_reg); in MSS_MAC_VSC8541_phy_init()
168 temp_reg = MSS_MAC_read_phy_reg(this_mac, phy_addr, 0); in MSS_MAC_VSC8541_phy_init()
169 } while(0 != (temp_reg & 0x8000U)); in MSS_MAC_VSC8541_phy_init()
185 temp_reg = MSS_MAC_read_phy_reg(this_mac, phy_addr, 27); in MSS_MAC_VSC8541_phy_init()
186 temp_reg &= 0xFF1FU; in MSS_MAC_VSC8541_phy_init()
187 temp_reg |= 0x0080U; in MSS_MAC_VSC8541_phy_init()
188 MSS_MAC_write_phy_reg(this_mac, phy_addr, 27, temp_reg); in MSS_MAC_VSC8541_phy_init()
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Dvsc8575_phy.c330 uint16_t temp_reg; in MSS_MAC_VSC8575_phy_init() local
334 temp_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, 0x17U); in MSS_MAC_VSC8575_phy_init()
335 temp_reg &= (uint16_t)(~0x0010U); /* Clear media inhibit odd start delay bit */ in MSS_MAC_VSC8575_phy_init()
336 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, 0x17U, temp_reg); in MSS_MAC_VSC8575_phy_init()
338 temp_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, 0x10U); in MSS_MAC_VSC8575_phy_init()
339 temp_reg &= (uint16_t)(~0x0004U); /* Clear mac inhibit odd start delay bit */ in MSS_MAC_VSC8575_phy_init()
340 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, 0x10U, temp_reg); in MSS_MAC_VSC8575_phy_init()
342 temp_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, 0x10U); in MSS_MAC_VSC8575_phy_init()
343 temp_reg &= (uint16_t)(~0x0100U); /* Turn off 2 byte preamble */ in MSS_MAC_VSC8575_phy_init()
344 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, 0x10U, temp_reg); in MSS_MAC_VSC8575_phy_init()
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Dmss_ethernet_mac.c4151 uint32_t temp_reg; in MSS_MAC_get_sa_filter() local
4176 temp_reg = p_reg[0]; in MSS_MAC_get_sa_filter()
4177 mac_addr[0] = (uint8_t)temp_reg & BITS_08; in MSS_MAC_get_sa_filter()
4178 temp_reg >>= 8; in MSS_MAC_get_sa_filter()
4179 mac_addr[1] = (uint8_t)temp_reg & BITS_08; in MSS_MAC_get_sa_filter()
4180 temp_reg >>= 8; in MSS_MAC_get_sa_filter()
4181 mac_addr[2] = (uint8_t)temp_reg & BITS_08; in MSS_MAC_get_sa_filter()
4182 temp_reg >>= 8; in MSS_MAC_get_sa_filter()
4183 mac_addr[3] = (uint8_t)temp_reg & BITS_08; in MSS_MAC_get_sa_filter()
4185 temp_reg = p_reg[1]; in MSS_MAC_get_sa_filter()
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Dti_dp83867_phy.c148 uint16_t temp_reg = 0x0000U; /* Default with 10M, half duplex */ in MSS_MAC_DP83867_phy_set_link_speed() local
152 temp_reg |= BMCR_FULLDPLX; in MSS_MAC_DP83867_phy_set_link_speed()
157 temp_reg |= BMCR_SPEED100; in MSS_MAC_DP83867_phy_set_link_speed()
162 temp_reg |= BMCR_SPEED1000; in MSS_MAC_DP83867_phy_set_link_speed()
170 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_BMCR, temp_reg); in MSS_MAC_DP83867_phy_set_link_speed()