Searched refs:regval (Results 1 – 6 of 6) sorted by relevance
104 uint32_t regval = 0; in mec_hal_espi_pc_status_clr() local106 regval = xlat_intr_to_hw(bitmap); in mec_hal_espi_pc_status_clr()107 iobase->PCSTS = regval; in mec_hal_espi_pc_status_clr()112 uint32_t regval = 0; in mec_hal_espi_pc_intr_en() local114 regval = xlat_intr_to_hw(bitmap); in mec_hal_espi_pc_intr_en()115 iobase->PCIEN |= regval; in mec_hal_espi_pc_intr_en()120 uint32_t regval = 0; in mec_hal_espi_pc_intr_dis() local122 regval = xlat_intr_to_hw(bitmap); in mec_hal_espi_pc_intr_dis()123 iobase->PCIEN &= ~regval; in mec_hal_espi_pc_intr_dis()
547 uint32_t regval = 0; in pll_clk_src_val() local551 regval = MEC_PCR_SS32K_PLL_REF_SRC_NONE; in pll_clk_src_val()554 regval = MEC_PCR_SS32K_PLL_REF_SRC_INTERNAL_OSC; in pll_clk_src_val()557 regval = MEC_PCR_SS32K_PLL_REF_SRC_CRYSTAL; in pll_clk_src_val()560 regval = MEC_PCR_SS32K_PLL_REF_SRC_PIN_32K_IN; in pll_clk_src_val()563 regval = MEC_PCR_SS32K_PLL_REF_SRC_INTERNAL_OSC; in pll_clk_src_val()566 return (regval << MEC_PCR_SS32K_PLL_REF_SRC_Pos) & MEC_PCR_SS32K_PLL_REF_SRC_Msk; in pll_clk_src_val()571 uint32_t regval = 0; in periph_clk_src_val() local575 regval = MEC_VBATR_CLK32K_SRC_PSSEL_SILOSC; in periph_clk_src_val()578 regval = MEC_VBATR_CLK32K_SRC_PSSEL_XTAL; in periph_clk_src_val()[all …]
363 uint32_t bitpos, regval; in mec_hal_espi_vw_ct_group_girq_ctrl() local369 regval = (uint32_t)(src_msk & 0xfu); in mec_hal_espi_vw_ct_group_girq_ctrl()373 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_SET = regval << bitpos; in mec_hal_espi_vw_ct_group_girq_ctrl()375 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_CLR = regval << bitpos; in mec_hal_espi_vw_ct_group_girq_ctrl()380 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_SET = regval << bitpos; in mec_hal_espi_vw_ct_group_girq_ctrl()382 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_CLR = regval << bitpos; in mec_hal_espi_vw_ct_group_girq_ctrl()606 uint32_t regval = ctvw->HIRSS; in mec_hal_espi_vw_ct_config() local609 regval &= (uint32_t)~MEC_ESPI_VW_CTVW_HIRSS_HOST_IDX_Msk; in mec_hal_espi_vw_ct_config()610 regval |= (((uint32_t)host_index << MEC_ESPI_VW_CTVW_HIRSS_HOST_IDX_Pos) in mec_hal_espi_vw_ct_config()615 regval &= (uint32_t)~MEC_ESPI_VW_CTVW_HIRSS_RST_SRC_Msk; in mec_hal_espi_vw_ct_config()[all …]
161 uint8_t regval = (uint8_t)((temp << MEC_ESPI_IO_CAPFC_MAX_PLD_SIZE_Pos) in set_fc_max_pld() local164 iobase->CAPFC = (iobase->CAPFC & ~msk) | regval; in set_fc_max_pld()212 uint8_t regval = fc_sharing_hw(capabilities); in set_fc_shared_mode() local214 iobase->CAPFC = (iobase->CAPFC & ~msk) | regval; in set_fc_shared_mode()230 uint8_t regval = (uint8_t)((temp << MEC_ESPI_IO_CAPFC_MAX_PLD_SIZE_Pos) in set_fc_capabilities() local235 regval |= in set_fc_capabilities()238 regval |= (MEC_ESPI_IO_CAPFC_SHARING_SUPP_TAF << MEC_ESPI_IO_CAPFC_SHARING_SUPP_Pos); in set_fc_capabilities()241 regval |= (MEC_ESPI_IO_CAPFC_SHARING_SUPP_CAF << MEC_ESPI_IO_CAPFC_SHARING_SUPP_Pos); in set_fc_capabilities()244 iobase->CAPFC = (iobase->CAPFC & ~msk) | regval; in set_fc_capabilities()
1416 uint16_t regval
1255 uint16_t regval in MSS_MAC_write_phy_reg() argument1285 …P_CL22_WRITE << GEM_OPERATION_SHIFT) | (((uint32_t)(2UL)) << GEM_WRITE10_SHIFT) | (uint32_t)regval; in MSS_MAC_write_phy_reg()
