| /hal_microchip-latest/mec5/drivers/ |
| D | mec_gpio.c | 87 uint8_t pin; member
101 static bool pin_is_vci(uint16_t pin) in pin_is_vci() argument
104 if (pin == gpio_vci_table[i].pin) { in pin_is_vci()
111 static struct mec_gpio_vci_pin const *find_gpio_vci_info(uint16_t pin) in find_gpio_vci_info() argument
114 if (pin == gpio_vci_table[i].pin) { in find_gpio_vci_info()
123 static inline uint8_t pin_get_port(uint16_t pin) in pin_get_port() argument
125 return (uint8_t)(((pin & 0x1FFu) >> 5) & 0xffu); in pin_get_port()
128 static inline uint8_t pin_get_bitpos(uint16_t pin) in pin_get_bitpos() argument
130 return (uint8_t)(pin & 0x1Fu); in pin_get_bitpos()
169 static inline bool pin_is_valid(uint32_t pin) in pin_is_valid() argument
[all …]
|
| D | mec_gpio_api.h | 300 int mec_hal_gpio_pin_valid(uint32_t pin);
304 int mec_hal_gpio_pin_config(uint32_t pin, uint32_t config);
316 int mec_hal_gpio_get_property(uint32_t pin, uint8_t prop_id, uint8_t *prop);
318 int mec_hal_gpio_set_property(uint32_t pin, uint8_t prop_id, uint8_t new_val);
319 int mec_hal_gpio_set_props(uint32_t pin, const struct mec_gpio_props *gprops, size_t nprops);
322 int mec_hal_gpio_is_output(uint32_t pin);
325 int mec_hal_gpio_disable_input_pad(uint32_t pin);
327 int mec_hal_gpio_enable_input_pad(uint32_t pin);
330 int mec_hal_gpio_is_locked(uint32_t pin);
333 uintptr_t mec_hal_gpio_ctrl_addr(uint32_t pin);
[all …]
|
| /hal_microchip-latest/scripts/ |
| D | pic32cxsgpinctrl.py | 148 def build_microchip_pic32_gpio_sets(pin_cfgs, pin): argument
158 port, pin_num = get_port_pin(pin)
165 def build_microchip_pic32_sets(pin_cfgs, pin, pin_lst, serie, variant, function): argument
185 port, pin_num = get_port_pin(pin)
206 for pin, pin_cfg in pins.items():
210 build_microchip_pic32_gpio_sets(pin_cfgs, pin)
213 build_microchip_pic32_sets(pin_cfgs, pin, pin_cfg["periph"],
216 build_microchip_pic32_sets(pin_cfgs, pin, pin_cfg["extra"],
219 build_microchip_pic32_sets(pin_cfgs, pin, pin_cfg["system"],
222 build_microchip_pic32_sets(pin_cfgs, pin, pin_cfg["lpm"],
[all …]
|
| D | pic32pinctrl.py | 144 def build_microchip_pic32_gpio_sets(pin_cfgs, pin): argument
154 port, pin_num = get_port_pin(pin)
161 def build_microchip_pic32_sets(pin_cfgs, pin, pin_lst, serie, variant, function): argument
181 port, pin_num = get_port_pin(pin)
202 for pin, pin_cfg in pins.items():
206 build_microchip_pic32_gpio_sets(pin_cfgs, pin)
209 build_microchip_pic32_sets(pin_cfgs, pin, pin_cfg["periph"],
212 build_microchip_pic32_sets(pin_cfgs, pin, pin_cfg["extra"],
215 build_microchip_pic32_sets(pin_cfgs, pin, pin_cfg["system"],
218 build_microchip_pic32_sets(pin_cfgs, pin, pin_cfg["lpm"],
[all …]
|
| /hal_microchip-latest/pinconfigs/ |
| D | README.md | 1 # Microchip PIC32C/PIC32M pin configurations
3 This directory contains a set of files describing valid pin configurations for
5 pin to a peripheral signal which multiplex, at end, I/O lines pins. For example,
7 for `PIC32CX` SoC. These configurations can be used to generate valid pin
12 use similar definitions where each pin has one or more associated alternate
22 All fields are common, independently of the pin controller, and all fields are
32 - `variants`: Each variant has a different set of valid pin combinations because
34 - `pins` (required): The pin map itself
136 of `cx1025sg41` and `cx1025sg61` pin mux. Note, some devices my present some
137 challenges like define a part number which uses same pin code with different
[all …]
|
| /hal_microchip-latest/dts/microchip/mec5/ |
| D | mec1743qsz-a0-pinctrl.dtsi | 1119 /* FW functions using the pin as a GPIO */
|
| D | mec1753qsz-a0-pinctrl.dtsi | 1135 /* FW functions using the pin as a GPIO */
|
| D | mec1743qlj-a0-pinctrl.dtsi | 1279 /* FW functions using the pin as a GPIO */
|
| D | mec1753qlj-a0-pinctrl.dtsi | 1295 /* FW functions using the pin as a GPIO */
|
