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Searched refs:phyclk (Results 1 – 2 of 2) sorted by relevance

/hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/
Dmss_ethernet_mac_types.h643 uint32_t phyclk; /*!< 3-bit MGMT clock divider value */ member
Dmss_ethernet_mac.c768 cfg->phyclk = MSS_MAC_DEF_PHY_CLK; in MSS_MAC_cfg_struct_def_init()
1077 …temp_net_config = (((uint32_t)(1UL)) << GEM_DATA_BUS_WIDTH_SHIFT) | ((cfg->phyclk & GEM_MDC_CLOCK_… in config_mac_hw()
1082 …temp_net_config = (((uint32_t)(1UL)) << GEM_DATA_BUS_WIDTH_SHIFT) | ((cfg->phyclk & GEM_MDC_CLOCK_… in config_mac_hw()
1087 temp_net_config = (cfg->phyclk & GEM_MDC_CLOCK_DIVISOR_MASK) << GEM_MDC_CLOCK_DIVISOR_SHIFT; in config_mac_hw()