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Searched refs:phy_reg (Results 1 – 7 of 7) sorted by relevance

/hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/
Dvsc8575_phy.c349 uint16_t phy_reg; in MSS_MAC_VSC8575_phy_init() local
355 phy_reg = (uint16_t)this_mac->mac_base->PCS_CONTROL; in MSS_MAC_VSC8575_phy_init()
356 phy_reg |= 0x1000U; in MSS_MAC_VSC8575_phy_init()
357 this_mac->mac_base->PCS_CONTROL = phy_reg; in MSS_MAC_VSC8575_phy_init()
358 phy_reg |= 0x0200U; in MSS_MAC_VSC8575_phy_init()
359 this_mac->mac_base->PCS_CONTROL = phy_reg; in MSS_MAC_VSC8575_phy_init()
363 phy_reg = (uint16_t)this_mac->mac_base->PCS_STATUS; in MSS_MAC_VSC8575_phy_init()
364 autoneg_complete = phy_reg & BMSR_AUTO_NEGOTIATION_COMPLETE; in MSS_MAC_VSC8575_phy_init()
366 … } while(((0U == autoneg_complete) && (0U != sgmii_aneg_timeout)) || (0xFFFF == phy_reg)); in MSS_MAC_VSC8575_phy_init()
377 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR); in MSS_MAC_VSC8575_phy_init()
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Dti_dp83867_phy.c56 uint16_t phy_reg; in MSS_MAC_DP83867_phy_init() local
63 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_PHYCR); in MSS_MAC_DP83867_phy_init()
64 phy_reg |= PHYCR_SGMII_EN; in MSS_MAC_DP83867_phy_init()
65 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_TI_PHYCR, phy_reg); in MSS_MAC_DP83867_phy_init()
75 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR); in MSS_MAC_DP83867_phy_init()
76 phy_reg |= 0x9000U; /* Reset and start autonegotiation */ in MSS_MAC_DP83867_phy_init()
77 phy_reg &= 0xFBFFU; /* Clear Isolate bit */ in MSS_MAC_DP83867_phy_init()
78 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR, phy_reg); in MSS_MAC_DP83867_phy_init()
80 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR); in MSS_MAC_DP83867_phy_init()
81 phy_reg &= 0xFBFFU; /* Clear Isolate bit */ in MSS_MAC_DP83867_phy_init()
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Dvsc8541_phy.c242 uint16_t phy_reg; in MSS_MAC_VSC8541_phy_set_link_speed() local
253 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_ADVERTISE); in MSS_MAC_VSC8541_phy_set_link_speed()
254 phy_reg &= (uint16_t)(~(ADVERTISE_10HALF | ADVERTISE_10FULL | in MSS_MAC_VSC8541_phy_set_link_speed()
264 phy_reg |= mii_advertise_bits[inc]; in MSS_MAC_VSC8541_phy_set_link_speed()
269 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_ADVERTISE, phy_reg); in MSS_MAC_VSC8541_phy_set_link_speed()
272 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000); in MSS_MAC_VSC8541_phy_set_link_speed()
273 phy_reg &= (uint16_t)(~(ADVERTISE_1000FULL | ADVERTISE_1000HALF)); in MSS_MAC_VSC8541_phy_set_link_speed()
277 phy_reg |= ADVERTISE_1000FULL; in MSS_MAC_VSC8541_phy_set_link_speed()
282 phy_reg |= ADVERTISE_1000HALF; in MSS_MAC_VSC8541_phy_set_link_speed()
285 MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000, phy_reg); in MSS_MAC_VSC8541_phy_set_link_speed()
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Dvsc8662_phy.c250 volatile uint16_t phy_reg; in MSS_MAC_VSC8662_phy_init() local
426 phy_reg = (uint16_t)this_mac->mac_base->PCS_CONTROL; in MSS_MAC_VSC8662_phy_init()
427 phy_reg |= 0x1000U; in MSS_MAC_VSC8662_phy_init()
428 this_mac->mac_base->PCS_CONTROL = phy_reg; in MSS_MAC_VSC8662_phy_init()
429 phy_reg |= 0x0200U; in MSS_MAC_VSC8662_phy_init()
430 this_mac->mac_base->PCS_CONTROL = phy_reg; in MSS_MAC_VSC8662_phy_init()
434 phy_reg = (uint16_t)this_mac->mac_base->PCS_STATUS; in MSS_MAC_VSC8662_phy_init()
435 autoneg_complete = phy_reg & BMSR_AUTO_NEGOTIATION_COMPLETE; in MSS_MAC_VSC8662_phy_init()
437 } while(((0U == autoneg_complete) && (0U != sgmii_aneg_timeout)) || (0xFFFFU == phy_reg)); in MSS_MAC_VSC8662_phy_init()
447 uint16_t phy_reg; in MSS_MAC_VSC8662_phy_set_link_speed() local
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Dvsc8575_support.c170 const u8 phy_reg,
175 const u8 phy_reg,
309 const u8 phy_reg, in miim_read() argument
314 uint8_t addr = (uint8_t)phy_reg & 0xff; in miim_read()
319 …ead_phy_reg(g_my_mac, (uint8_t)(phy_port + g_my_mac->phy_addr), (uint8_t)phy_reg); /* TBD: PMCS Wa… in miim_read()
354 const u8 phy_reg, in miim_write() argument
359 uint8_t addr = phy_reg & 0xff; in miim_write()
364 if(0x1f == phy_reg) in miim_write()
376 mii_data[mii_data_index].reg = phy_reg; in miim_write()
388 …MSS_MAC_write_phy_reg(g_my_mac, (uint8_t)(phy_port + g_my_mac->phy_addr), (uint8_t)phy_reg, value)… in miim_write()
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Dmss_ethernet_mac.c660 uint16_t phy_reg; in MSS_MAC_get_link_status() local
671 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMSR); in MSS_MAC_get_link_status()
672 phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMSR); in MSS_MAC_get_link_status()
673 sgmii_link_up = phy_reg & BMSR_LSTATUS; in MSS_MAC_get_link_status()
678 … phy_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR); in MSS_MAC_get_link_status()
679 phy_reg |= BMCR_ANENABLE; in MSS_MAC_get_link_status()
680 … MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR, phy_reg); in MSS_MAC_get_link_status()
681 phy_reg |= BMCR_ANRESTART; in MSS_MAC_get_link_status()
682 … MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->pcs_phy_addr, MII_BMCR, phy_reg); in MSS_MAC_get_link_status()
704 uint16_t phy_reg; in MSS_MAC_get_link_status()
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/hal_microchip-latest/mpfs/drivers/mss/pf_pcie/
Dpf_pcie.c853 uint32_t phy_reg; in PF_PCIE_master_atr_table_init() local
901 phy_reg = ~((1u << (cfg->bar_size + 1u)) -1u); in PF_PCIE_master_atr_table_init()
902 *p_pcie_bar = (phy_reg | cfg->bar_type); in PF_PCIE_master_atr_table_init()
920 phy_reg = ~((1u << (cfg->bar_size + 1u)) -1u); in PF_PCIE_master_atr_table_init()
921 *p_pcie_bar = (phy_reg | cfg->bar_type); in PF_PCIE_master_atr_table_init()
937 phy_reg = (uint32_t)(cfg->src_addr & ATR_ADDR_MASK); in PF_PCIE_master_atr_table_init()
938 phy_reg |= (uint32_t)((cfg->table_size) << PCIE_SET); in PF_PCIE_master_atr_table_init()
939 phy_reg |= (uint32_t)(cfg->state); in PF_PCIE_master_atr_table_init()
942 *(p_pcie_master_table + WIN0_SRCADDR_PARAM) = phy_reg; in PF_PCIE_master_atr_table_init()
976 uint32_t phy_reg = PCIE_CLEAR; in PF_PCIE_slave_atr_table_init() local
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