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Searched refs:p_ddr_cached (Results 1 – 1 of 1) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr_debug.c847 uint32_t * p_ddr_cached = (uint32_t *)0x80000000; in test_ddr() local
863 load_test_buffers(p_ddr_cached, p_ddr_noncached, pattern_length); in test_ddr()
874 uprint64(g_debug_uart, " Mismatch, 0x", (uint64_t)p_ddr_cached); in test_ddr()
876 uprint32(g_debug_uart, " address: 0x", (uint64_t)(p_ddr_cached + word_offset)); in test_ddr()
879 … uprint32(g_debug_uart, " direct cached read: 0x", (uint32_t)*(p_ddr_cached + word_offset)); in test_ddr()
889 … if (((uint64_t)p_ddr_cached + ( 2 * pattern_length)) < (LIBERO_SETTING_DDR_32_CACHE + size)) in test_ddr()
891 p_ddr_cached += (pattern_length / sizeof(uint32_t)); in test_ddr()
896 p_ddr_cached = (uint32_t *)0x80000000; in test_ddr()