1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_I3C_API_H_ 7 #define _MEC_I3C_API_H_ 8 9 #include "mec_defs.h" 10 #include "mec_i3c_pvt.h" 11 12 /* MEC I3C Control structure required by API */ 13 struct mec_i3c_ctx { 14 uintptr_t base; 15 uint32_t devi; 16 }; 17 18 #define MAX_I3C_MSGS 32U 19 #define I3C_HOT_JOIN_ADDR 0x2U 20 #define IBI_QUEUE_STATUS_IBI_ID(x) (((x) & GENMASK(15, 8)) >> 8U) 21 #define IBI_QUEUE_STATUS_DATA_LEN(x) ((x) & GENMASK(7, 0)) 22 #define IBI_QUEUE_IBI_ADDR(x) (IBI_QUEUE_STATUS_IBI_ID(x) >> 1U) 23 #define IBI_QUEUE_IBI_RNW(x) (IBI_QUEUE_STATUS_IBI_ID(x) & MEC_BIT(0)) 24 #define IBI_TYPE_MR(x) \ 25 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x)) 26 #define IBI_TYPE_HJ(x) \ 27 ((IBI_QUEUE_IBI_ADDR(x) == I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x)) 28 #define IBI_TYPE_SIRQ(x) \ 29 ((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && IBI_QUEUE_IBI_RNW(x)) 30 31 #define RESPONSE_NO_ERROR 0U 32 #define RESPONSE_ERROR_CRC 1U 33 #define RESPONSE_ERROR_PARITY 2U 34 #define RESPONSE_ERROR_FRAME 3U 35 #define RESPONSE_ERROR_IBA_NACK 4U 36 #define RESPONSE_ERROR_ADDRESS_NACK 5U 37 #define RESPONSE_ERROR_OVER_UNDER_FLOW 6U 38 #define RESPONSE_ERROR_TRANSF_ABORT 8U 39 #define RESPONSE_ERROR_I2C_W_NACK_ERR 9U 40 41 #define TGT_MIPI_MFG_ID(x) ((x & MEC_GENMASK64(47, 33)) >> 33U) 42 #define TGT_PROV_ID_SEL(x) ((x & MEC_GENMASK64(32, 32)) >> 32U) 43 44 #define TGT_PART_ID(x) ((x & MEC_GENMASK64(31, 16)) >> 16U) 45 #define TGT_INST_ID(x) ((x & MEC_GENMASK64(15, 12)) >> 12U) 46 #define TGT_PID_DCR(x) ((x & MEC_GENMASK64(11, 0)) >> 0U) 47 48 #define MEC_I3C_GIRQ_EN 0x1 49 #define MEC_I3C_GIRQ_DIS 0x2 50 #define MEC_I3C_GIRQ_CLR_STS 0x4 51 52 enum mec_i3c_channels 53 { 54 MEC_I3C_PRIM_CTRLR, 55 MEC_I3C_SEC_CTRLR, 56 MEC_I3C_CHAN_0 = MEC_I3C_PRIM_CTRLR, 57 MEC_I3C_CHAN_1 = MEC_I3C_SEC_CTRLR, 58 MEC_I3C_MAX_CHAN 59 }; 60 61 enum mec_i3c_role_cfg 62 { 63 MEC_I3C_ROLE_CFG_PRIM_CTRLR = 1U, 64 MEC_I3C_ROLE_CFG_SEC_CTRLR = 3U, 65 MEC_I3C_ROLE_CFG_TGT = 4U, 66 MEC_I3C_MAX_ROLES 67 }; 68 69 /* configuration bit definitions */ 70 enum mec_config_bits 71 { 72 sbit_CONFG_ENABLE = (1U << 0) // BIT_0_MASK 73 ,sbit_MODE_TARGET = (1U << 1) // BIT_1_MASK 74 ,sbit_HOTJOIN_DISABLE = (1U << 2) // BIT_2_MASK 75 ,sbit_DMA_MODE = (1U << 3) // BIT_3_MASK 76 }; 77 78 enum mec_i3c_xfer_speeds { 79 MEC_XFER_SPEED_SDR0 = 0 /* 12.5 MHz (~12.5Mbps)*/ 80 ,MEC_XFER_SPEED_SDR1 /* 8MHz */ 81 ,MEC_XFER_SPEED_SDR2 /* 6MHz */ 82 ,MEC_XFER_SPEED_SDR3 /* 4MHz */ 83 ,MEC_XFER_SPEED_SDR4 /* 2MHz */ 84 ,MEC_XFER_SPEED_HDR_TS /* Not supported on KF */ 85 ,MEC_XFER_SPEED_HDR_DDR /* 12.5MHz (~25Mbps) */ 86 }; 87 88 enum mec_i2c_xfer_speeds { 89 MEC_XFER_SPEED_FM = 0 90 ,MEC_XFER_SPEED_FMP 91 }; 92 93 enum mec_mxds_max_wr_speed { 94 MEC_MXDS_MAX_WR_SPEED_12P5MHZ = 0 95 ,MEC_MXDS_MAX_WR_SPEED_8MHZ 96 ,MEC_MXDS_MAX_WR_SPEED_6MHZ 97 ,MEC_MXDS_MAX_WR_SPEED_4MHZ 98 ,MEC_MXDS_MAX_WR_SPEED_2MHZ 99 }; 100 101 enum mec_mxds_max_rd_speed { 102 MEC_MXDS_MAX_RD_SPEED_12P5MHZ = 0 103 ,MEC_MXDS_MAX_RD_SPEED_8MHZ 104 ,MEC_MXDS_MAX_RD_SPEED_6MHZ 105 ,MEC_MXDS_MAX_RD_SPEED_4MHZ 106 ,MEC_MXDS_MAX_RD_SPEED_2MHZ 107 }; 108 109 enum mec_mxds_tsco { 110 MEC_MXDS_TSCO_8NS = 0 111 ,MEC_MXDS_TSCO_9NS 112 ,MEC_MXDS_TSCO_10NS 113 ,MEC_MXDS_TSCO_11NS 114 ,MEC_MXDS_TSCO_12NS 115 }; 116 117 /** 118 * @brief Structure to use by target to raise Target Interrupt Request (SIR) 119 */ 120 struct mec_i3c_raise_IBI_SIR { 121 122 /** Pointer to buffer for SIR Data */ 123 uint8_t *data_buf; 124 125 /** SIR data length */ 126 uint8_t data_len; 127 128 /** Mandatory Byte */ 129 uint8_t mdb; 130 131 }; 132 133 /** 134 * @brief Structure to use for DO CCC procedure 135 */ 136 struct mec_i3c_DO_CCC { 137 138 /** Pointer to buffer for TX/RX Data */ 139 uint8_t *data_buf; 140 141 /** Number of bytes to read/write */ 142 uint16_t data_len; 143 144 /** CCC Id */ 145 uint8_t ccc_id; 146 147 /** Target index */ 148 uint8_t tgt_idx; 149 150 /** Defining Byte (optional) */ 151 uint8_t defining_byte; 152 153 /** Set True for Read */ 154 bool read; 155 156 /** Set True if defining byte is valid */ 157 bool defining_byte_valid; 158 }; 159 160 /** 161 * @brief Structure to use for Enable IBI procedure 162 */ 163 struct mec_i3c_IBI_SIR { 164 165 /** DAT start address */ 166 uint16_t DAT_start; 167 168 /** Target index in DAT */ 169 uint8_t tgt_dat_idx; 170 171 /** True if target's IBI has payload */ 172 bool ibi_has_payload; 173 }; 174 175 /* Single command/transfer */ 176 struct mec_i3c_dw_cmd { 177 178 uint32_t cmd; 179 180 uint32_t arg; 181 182 /** Pointer to buffer for TX/RX Data */ 183 uint8_t *data_buf; 184 185 /** Number of bytes to read/write */ 186 uint16_t data_len; 187 188 #if CONFIG_I3C_ENABLE_THRESHOLDS_INTR 189 /** Remaining data length - used with thresholds */ 190 uint16_t rem_data_len; 191 #endif 192 193 /** Target index */ 194 uint8_t tgt_idx; 195 196 /** Set True for Read */ 197 bool read; 198 199 /** Set True to enable PEC */ 200 bool pec_en; 201 202 /** Set True for STOP */ 203 bool stop; 204 205 /** Xfer speed */ 206 uint8_t xfer_speed; 207 }; 208 209 /** 210 * @brief Structure to use for DO XFER procedure 211 */ 212 struct mec_i3c_XFER { 213 214 struct mec_i3c_dw_cmd cmds[MAX_I3C_MSGS]; 215 }; 216 217 typedef void (*MEC_I3C_CALLBACK) (uintptr_t context); 218 219 typedef struct 220 { 221 MEC_I3C_CALLBACK callback; 222 uintptr_t context; 223 } MEC_I3C_OBJECT; 224 225 void MEC_HAL_I3C_Soft_Reset(struct mec_i3c_ctx *ctx); 226 227 void MEC_HAL_I3C_Controller_Clk_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz, 228 uint32_t i3c_freq); 229 230 void MEC_HAL_I3C_Controller_Clk_Cfg(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz, 231 uint32_t i3c_freq); 232 233 void MEC_HAL_I3C_Controller_Clk_I2C_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz); 234 235 void MEC_HAL_I3C_Target_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz, 236 uint16_t *max_rd_len, uint16_t *max_wr_len); 237 238 void MEC_HAL_I3C_Controller_Interrupts_Init(struct mec_i3c_ctx *ctx); 239 240 void MEC_HAL_I3C_Thresholds_Init(struct mec_i3c_ctx *ctx); 241 242 void MEC_HAL_I3C_Thresholds_Response_buf_set(struct mec_i3c_ctx *ctx, uint8_t threshold); 243 244 void MEC_HAL_I3C_Host_Config(struct mec_i3c_ctx *ctx); 245 246 void MEC_HAL_I3C_Sec_Host_Config(struct mec_i3c_ctx *ctx); 247 248 void MEC_HAL_I3C_Enable(struct mec_i3c_ctx *ctx, uint8_t address, uint8_t config); 249 250 void MEC_HAL_I3C_DO_DAA(struct mec_i3c_ctx *ctx, uint8_t tgt_idx, uint8_t tgts_count, 251 uint8_t *tid_xfer); 252 253 void MEC_HAL_I3C_DO_CCC(struct mec_i3c_ctx *ctx, struct mec_i3c_DO_CCC *tgt, uint8_t *tid_xfer); 254 255 void MEC_HAL_I3C_CallbackRegister(uint32_t channel, MEC_I3C_CALLBACK callback, uintptr_t context); 256 257 void MEC_HAL_I3C_Xfer_Error_Resume(struct mec_i3c_ctx *ctx); 258 259 void MEC_HAL_I3C_Xfer_Reset(struct mec_i3c_ctx *ctx); 260 261 void MEC_HAL_I3C_DAT_info_get(struct mec_i3c_ctx *ctx, uint16_t *start_addr, uint16_t *depth); 262 263 void MEC_HAL_I3C_DCT_info_get(struct mec_i3c_ctx *ctx, uint16_t *start_addr, uint16_t *depth); 264 265 void MEC_HAL_I3C_DCT_read(struct mec_i3c_ctx *ctx, uint16_t DCT_start, uint16_t DCT_idx, 266 struct mec_i3c_DCT_info *info); 267 268 bool MEC_HAL_I3C_Is_Current_Role_Primary(struct mec_i3c_ctx *ctx); 269 270 bool MEC_HAL_I3C_Is_Current_Role_Master(struct mec_i3c_ctx *ctx); 271 272 bool MEC_HAL_I3C_Is_Current_Role_BusMaster(struct mec_i3c_ctx *ctx); 273 274 void MEC_HAL_I3C_DAT_DynamicAddrAssign_write(struct mec_i3c_ctx *ctx, uint16_t DAT_start, 275 uint16_t DAT_idx, uint8_t address); 276 277 void MEC_HAL_I3C_DAT_DynamicAddr_write(struct mec_i3c_ctx *ctx, uint16_t DAT_start, 278 uint16_t DAT_idx, uint8_t address); 279 280 void MEC_HAL_I3C_queue_depths_get(struct mec_i3c_ctx *ctx, uint8_t *tx_depth, uint8_t *rx_depth, 281 uint8_t *cmd_depth, uint8_t *resp_depth, uint8_t *ibi_depth); 282 283 void MEC_HAL_I3C_DO_Xfer_Prep(struct mec_i3c_ctx *ctx, struct mec_i3c_dw_cmd *cmd, 284 uint8_t *tid_xfer); 285 286 void MEC_HAL_I3C_DO_Xfer(struct mec_i3c_ctx *ctx, struct mec_i3c_dw_cmd *tgt); 287 288 void MEC_HAL_I3C_IBI_SIR_Enable(struct mec_i3c_ctx *ctx, struct mec_i3c_IBI_SIR *ibi_sir_info, 289 bool enable_ibi_interrupt); 290 291 void MEC_HAL_I3C_IBI_SIR_Disable(struct mec_i3c_ctx *ctx, struct mec_i3c_IBI_SIR *ibi_sir_info, 292 bool disable_ibi_interrupt); 293 294 void MEC_HAL_I3C_TGT_PID_set(struct mec_i3c_ctx *ctx, uint64_t pid, bool pid_random); 295 296 bool MEC_HAL_I3C_TGT_is_dyn_addr_valid(struct mec_i3c_ctx *ctx); 297 298 uint8_t MEC_HAL_I3C_TGT_dyn_addr_get(struct mec_i3c_ctx *ctx); 299 300 void MEC_HAL_I3C_TGT_MRL_set(struct mec_i3c_ctx *ctx, uint16_t mrl); 301 302 void MEC_HAL_I3C_TGT_MWL_set(struct mec_i3c_ctx *ctx, uint16_t mwl); 303 304 void MEC_HAL_I3C_TGT_MXDS_set(struct mec_i3c_ctx *ctx, 305 uint8_t wr_speed, 306 uint8_t rd_speed, 307 uint8_t tsco, 308 uint32_t rd_trnd_us); 309 310 int MEC_HAL_I3C_TGT_IBI_SIR_Raise(struct mec_i3c_ctx *ctx, 311 struct mec_i3c_raise_IBI_SIR *ibi_sir_request); 312 313 int MEC_HAL_I3C_TGT_IBI_MR_Raise(struct mec_i3c_ctx *ctx); 314 315 void MEC_HAL_I3C_Target_Interrupts_Init(struct mec_i3c_ctx *ctx); 316 317 void MEC_HAL_I3C_TGT_IBI_SIR_Residual_handle(struct mec_i3c_ctx *ctx); 318 319 void MEC_HAL_I3C_TGT_Error_Recovery(struct mec_i3c_ctx *ctx, uint8_t err_sts); 320 321 #if CONFIG_I3C_ENABLE_THRESHOLDS_INTR 322 void MEC_HAL_I3C_DO_TGT_Xfer(struct mec_i3c_ctx *ctx, uint8_t *data_buf, uint16_t data_len, 323 uint16_t rem_data_len); 324 #else 325 void MEC_HAL_I3C_DO_TGT_Xfer(struct mec_i3c_ctx *ctx, uint8_t *data_buf, uint16_t data_len); 326 #endif 327 328 void MEC_HAL_I3C_Target_MRL_MWL_update(struct mec_i3c_ctx *ctx, uint16_t *max_rd_len, 329 uint16_t *max_wr_len); 330 331 void MEC_HAL_I3C_Target_MRL_MWL_set(struct mec_i3c_ctx *ctx, uint16_t max_rd_len, 332 uint16_t max_wr_len); 333 334 void MEC_HAL_I3C_SDCT_read(struct mec_i3c_ctx *ctx, uint16_t DCT_start, uint16_t idx, 335 struct mec_i3c_SDCT_info *info); 336 337 void MEC_HAL_I3C_TGT_DEFTGTS_DAT_write(struct mec_i3c_ctx *ctx, uint16_t DCT_start, 338 uint16_t DAT_start, uint8_t targets_count); 339 340 void MEC_HAL_I3C_TGT_RoleSwitch_Resume(struct mec_i3c_ctx *ctx); 341 342 void MEC_HAL_I3C_GIRQ_Status_Clr(struct mec_i3c_ctx *ctx); 343 344 void MEC_HAL_I3C_GIRQ_CTRL(struct mec_i3c_ctx *ctx, int flags); 345 346 int MEC_HAL_I3C_GIRQ_Status(struct mec_i3c_ctx *ctx); 347 348 int MEC_HAL_I3C_GIRQ_Result(struct mec_i3c_ctx *ctx); 349 350 #endif /* _MEC_I3C_API_H_ */ 351
