1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_TACH_API_H 7 #define _MEC_TACH_API_H 8 9 #include <stdbool.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 13 #include "mec_defs.h" 14 #include "mec_retval.h" 15 16 /* Interfaces to any C modules */ 17 #ifdef __cplusplus 18 extern "C" 19 { 20 #endif 21 22 #define MEC5_TACH_CFG_RESET 0x01u 23 #define MEC5_TACH_CFG_ENABLE 0x02u 24 #define MEC5_TACH_CFG_FILTER_EN 0x04u 25 #define MEC5_TACH_CFG_CNT_INCR_CLK 0x08u 26 #define MEC5_TACH_CFG_OOL_INTR_EN 0x10u 27 #define MEC5_TACH_CFG_CNT_RDY_INTR_EN 0x20u 28 #define MEC5_TACH_CFG_INPUT_CHG_INTR_EN 0x40u 29 #define MEC5_TACH_CFG_INTERVAL_EDGES_POS 8 30 #define MEC5_TACH_CFG_INTERVAL_EDGES_MSK 0x300u 31 #define MEC5_TACH_CFG_INTERVAL_EDGES_2 0 32 #define MEC5_TACH_CFG_INTERVAL_EDGES_3 0x100u 33 #define MEC5_TACH_CFG_INTERVAL_EDGES_5 0x200u 34 #define MEC5_TACH_CFG_INTERVAL_EDGES_9 0x300u 35 36 #define MEC5_TACH_LIMITS(limlo, limhi) \ 37 (((uint32_t)(limhi) << 16) | ((uint32_t)(limlo) & 0xffffu)) 38 39 enum mec5_tach_read_mode { 40 MEC_TACH_READ_MODE_INPUT_REDGE = 0, 41 MEC_TACH_READ_MODE_100K_CLK_REDGE, 42 }; 43 44 enum mec5_tach_edge_count { 45 MEC_TACH_CNT2_EDGES_HPER = 0, 46 MEC_TACH_CNT3_EDGES_1PER, 47 MEC_TACH_CNT5_EDGES_2PER, 48 MEC_TACH_CNT9_EDGES_4PER, 49 }; 50 51 enum mec5_tach_status { 52 MEC5_TACH_STS_OOL = MEC_BIT(0), /* counter out of limit */ 53 MEC5_TACH_STS_PIN_STATE = MEC_BIT(1), 54 MEC5_TACH_STS_PIN_TOGGLE = MEC_BIT(2), 55 MEC5_TACH_STS_CNT_RDY = MEC_BIT(3), 56 }; 57 58 /* All clearable status bits */ 59 #define MEC5_TACH_STATUS_ALL \ 60 (MEC5_TACH_STS_CNT_RDY | MEC5_TACH_STS_PIN_TOGGLE | MEC5_TACH_STS_OOL) 61 62 enum mec5_tach_ien { 63 MEC5_TACH_IEN_OOL_POS = 0, 64 MEC5_TACH_IEN_CNT_RDY_POS, 65 MEC5_TACH_IEN_INPUT_TOGGLE_POS, 66 }; 67 68 /* forward declaration */ 69 struct mec_tach_regs; 70 71 int mec_hal_tach_init(struct mec_tach_regs *regs, uint32_t limits, uint32_t flags); 72 void mec_hal_tach_enable(struct mec_tach_regs *regs, uint8_t enable); 73 bool mec_hal_tach_is_enabled(struct mec_tach_regs *regs); 74 75 uint32_t mec_hal_tach_clock_freq(void); 76 uint32_t mec_hal_tach_counter(struct mec_tach_regs *regs); 77 uint32_t mec_hal_tach_status(struct mec_tach_regs *regs); 78 void mec_hal_tach_status_clr(struct mec_tach_regs *regs, uint32_t status); 79 int mec_hal_tach_intr_enable(struct mec_tach_regs *regs, uint32_t intr_events, uint8_t enable); 80 81 void mec_hal_tach_girq_status_clr(struct mec_tach_regs *regs); 82 void mec_hal_tach_girq_enable(struct mec_tach_regs *regs, uint8_t enable); 83 84 #ifdef __cplusplus 85 } 86 #endif 87 88 #endif /* #ifndef _MEC_TACH_API_H */ 89
