1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * MPFS HAL Embedded Software 7 * 8 */ 9 10 /******************************************************************************* 11 * @file mss_ddr_sgmii_phy_defs.h 12 * @author Microchip-FPGA Embedded Systems Solutions 13 * @brief Register bit offsets and masks definitions for MPFS MSS DDR 14 * This was generated directly from the RTL 15 * 16 */ 17 18 #ifndef MSS_DDR_SGMII_PHY_DEFS_H_ 19 #define MSS_DDR_SGMII_PHY_DEFS_H_ 20 21 22 #include "mpfs_hal/mss_hal.h" 23 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #ifndef __I 30 #define __I const volatile 31 #endif 32 #ifndef __IO 33 #define __IO volatile 34 #endif 35 #ifndef __O 36 #define __O volatile 37 #endif 38 39 /*----------------------------------------------------------------------------*/ 40 /*----------------------------------- DDR -----------------------------------*/ 41 /*----------------------------------------------------------------------------*/ 42 43 44 /*============================== CFG_DDR_SGMII_PHY definitions ===========================*/ 45 46 typedef enum { /*!< SOFT_RESET_DDR_PHY.PERIPH_DDR_PHY bitfield definition*/ 47 scb_periph_not_in_soft_reset_ddr_phy = 0, 48 scb_periph_reset_ddr_phy = 1 49 } CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_PERIPH_DDR_PHY_TypeDef; 50 51 typedef enum { /*!< SOFT_RESET_DDR_PHY.V_MAP_DDR_PHY bitfield definition*/ 52 scb_v_regs_not_in_soft_reset_ddr_phy = 0, 53 scb_v_regs_reset_ddr_phy = 1 54 } CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_V_MAP_DDR_PHY_TypeDef; 55 56 typedef enum { /*!< SOFT_RESET_DDR_PHY.NV_MAP_DDR_PHY bitfield definition*/ 57 scb_nv_regs_not_in_soft_reset_ddr_phy = 0, 58 scb_nv_regs_reset_ddr_phy = 1 59 } CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_NV_MAP_DDR_PHY_TypeDef; 60 61 typedef enum { /*!< SOFT_RESET_MAIN_PLL.BLOCKID_MAIN_PLL bitfield definition*/ 62 block_address_main_pll = 0 63 } CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_BLOCKID_MAIN_PLL_TypeDef; 64 65 typedef enum { /*!< SOFT_RESET_MAIN_PLL.PERIPH_MAIN_PLL bitfield definition*/ 66 scb_periph_not_in_soft_reset_main_pll = 0, 67 scb_periph_reset_main_pll = 1 68 } CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_PERIPH_MAIN_PLL_TypeDef; 69 70 typedef enum { /*!< SOFT_RESET_MAIN_PLL.V_MAP_MAIN_PLL bitfield definition*/ 71 scb_v_regs_not_in_soft_reset_main_pll = 0, 72 scb_v_regs_reset_main_pll = 1 73 } CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_V_MAP_MAIN_PLL_TypeDef; 74 75 typedef enum { /*!< SOFT_RESET_MAIN_PLL.NV_MAP_MAIN_PLL bitfield definition*/ 76 scb_nv_regs_not_in_soft_reset_main_pll = 0, 77 scb_nv_regs_reset_main_pll = 1 78 } CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_NV_MAP_MAIN_PLL_TypeDef; 79 80 typedef enum { /*!< SOFT_RESET_IOSCB_PLL.BLOCKID_IOSCB_PLL bitfield definition*/ 81 block_address_ioscb_pll = 0 82 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_BLOCKID_IOSCB_PLL_TypeDef; 83 84 typedef enum { /*!< SOFT_RESET_IOSCB_PLL.PERIPH_IOSCB_PLL bitfield definition*/ 85 scb_periph_not_in_soft_reset_ioscb_pll = 0, 86 scb_periph_reset_ioscb_pll = 1 87 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_PERIPH_IOSCB_PLL_TypeDef; 88 89 typedef enum { /*!< SOFT_RESET_IOSCB_PLL.V_MAP_IOSCB_PLL bitfield definition*/ 90 scb_v_regs_not_in_soft_reset_ioscb_pll = 0, 91 scb_v_regs_reset_ioscb_pll = 1 92 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_V_MAP_IOSCB_PLL_TypeDef; 93 94 typedef enum { /*!< SOFT_RESET_IOSCB_PLL.NV_MAP_IOSCB_PLL bitfield definition*/ 95 scb_nv_regs_not_in_soft_reset_ioscb_pll = 0, 96 scb_nv_regs_reset_ioscb_pll = 1 97 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_NV_MAP_IOSCB_PLL_TypeDef; 98 99 typedef enum { /*!< SOFT_RESET_BANK_CTRL.BLOCKID_BANK_CTRL bitfield definition*/ 100 block_address_bank_ctrl = 0 101 } CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_BLOCKID_BANK_CTRL_TypeDef; 102 103 typedef enum { /*!< SOFT_RESET_BANK_CTRL.PERIPH_BANK_CTRL bitfield definition*/ 104 scb_periph_not_in_soft_reset_bank_ctrl = 0, 105 scb_periph_reset_bank_ctrl = 1 106 } CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_PERIPH_BANK_CTRL_TypeDef; 107 108 typedef enum { /*!< SOFT_RESET_BANK_CTRL.V_MAP_BANK_CTRL bitfield definition*/ 109 scb_v_regs_not_in_soft_reset_bank_ctrl = 0, 110 scb_v_regs_reset_bank_ctrl = 1 111 } CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_V_MAP_BANK_CTRL_TypeDef; 112 113 typedef enum { /*!< SOFT_RESET_BANK_CTRL.NV_MAP_BANK_CTRL bitfield definition*/ 114 scb_nv_regs_not_in_soft_reset_bank_ctrl = 0, 115 scb_nv_regs_reset_bank_ctrl = 1 116 } CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_NV_MAP_BANK_CTRL_TypeDef; 117 118 typedef enum { /*!< SOFT_RESET_IOCALIB.BLOCKID_IOCALIB bitfield definition*/ 119 block_address_iocalib = 0 120 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_BLOCKID_IOCALIB_TypeDef; 121 122 typedef enum { /*!< SOFT_RESET_IOCALIB.PERIPH_IOCALIB bitfield definition*/ 123 scb_periph_not_in_soft_reset_iocalib = 0, 124 scb_periph_reset_iocalib = 1 125 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_PERIPH_IOCALIB_TypeDef; 126 127 typedef enum { /*!< SOFT_RESET_IOCALIB.V_MAP_IOCALIB bitfield definition*/ 128 scb_v_regs_not_in_soft_reset_iocalib = 0, 129 scb_v_regs_reset_iocalib = 1 130 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_V_MAP_IOCALIB_TypeDef; 131 132 typedef enum { /*!< SOFT_RESET_IOCALIB.NV_MAP_IOCALIB bitfield definition*/ 133 scb_nv_regs_not_in_soft_reset_iocalib = 0, 134 scb_nv_regs_reset_iocalib = 1 135 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_NV_MAP_IOCALIB_TypeDef; 136 137 typedef enum { /*!< SOFT_RESET_CFM.BLOCKID_CFM bitfield definition*/ 138 block_address_cfm = 0 139 } CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_BLOCKID_CFM_TypeDef; 140 141 typedef enum { /*!< SOFT_RESET_CFM.PERIPH_CFM bitfield definition*/ 142 scb_periph_not_in_soft_reset_cfm = 0, 143 scb_periph_reset_cfm = 1 144 } CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_PERIPH_CFM_TypeDef; 145 146 typedef enum { /*!< SOFT_RESET_CFM.V_MAP_CFM bitfield definition*/ 147 scb_v_regs_not_in_soft_reset_cfm = 0, 148 scb_v_regs_reset_cfm = 1 149 } CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_V_MAP_CFM_TypeDef; 150 151 typedef enum { /*!< SOFT_RESET_CFM.NV_MAP_CFM bitfield definition*/ 152 scb_nv_regs_not_in_soft_reset_cfm = 0, 153 scb_nv_regs_reset_cfm = 1 154 } CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_NV_MAP_CFM_TypeDef; 155 156 typedef enum { /*!< SOFT_RESET_DECODER_DRIVER.BLOCKID_DECODER_DRIVER bitfield definition*/ 157 block_address_decoder_driver = 0 158 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_BLOCKID_DECODER_DRIVER_TypeDef; 159 160 typedef enum { /*!< SOFT_RESET_DECODER_DRIVER.PERIPH_DECODER_DRIVER bitfield definition*/ 161 scb_periph_not_in_soft_reset_decoder_driver = 0, 162 scb_periph_reset_decoder_driver = 1 163 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_PERIPH_DECODER_DRIVER_TypeDef; 164 165 typedef enum { /*!< SOFT_RESET_DECODER_DRIVER.V_MAP_DECODER_DRIVER bitfield definition*/ 166 scb_v_regs_not_in_soft_reset_decoder_driver = 0, 167 scb_v_regs_reset_decoder_driver = 1 168 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_V_MAP_DECODER_DRIVER_TypeDef; 169 170 typedef enum { /*!< SOFT_RESET_DECODER_DRIVER.NV_MAP_DECODER_DRIVER bitfield definition*/ 171 scb_nv_regs_not_in_soft_reset_decoder_driver = 0, 172 scb_nv_regs_reset_decoder_driver = 1 173 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_NV_MAP_DECODER_DRIVER_TypeDef; 174 175 typedef enum { /*!< SOFT_RESET_DECODER_ODT.BLOCKID_DECODER_ODT bitfield definition*/ 176 block_address_decoder_odt = 0 177 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_BLOCKID_DECODER_ODT_TypeDef; 178 179 typedef enum { /*!< SOFT_RESET_DECODER_ODT.PERIPH_DECODER_ODT bitfield definition*/ 180 scb_periph_not_in_soft_reset_decoder_odt = 0, 181 scb_periph_reset_decoder_odt = 1 182 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_PERIPH_DECODER_ODT_TypeDef; 183 184 typedef enum { /*!< SOFT_RESET_DECODER_ODT.V_MAP_DECODER_ODT bitfield definition*/ 185 scb_v_regs_not_in_soft_reset_decoder_odt = 0, 186 scb_v_regs_reset_decoder_odt = 1 187 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_V_MAP_DECODER_ODT_TypeDef; 188 189 typedef enum { /*!< SOFT_RESET_DECODER_ODT.NV_MAP_DECODER_ODT bitfield definition*/ 190 scb_nv_regs_not_in_soft_reset_decoder_odt = 0, 191 scb_nv_regs_reset_decoder_odt = 1 192 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_NV_MAP_DECODER_ODT_TypeDef; 193 194 typedef enum { /*!< SOFT_RESET_DECODER_IO.BLOCKID_DECODER_IO bitfield definition*/ 195 block_address_decoder_io = 0 196 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_BLOCKID_DECODER_IO_TypeDef; 197 198 typedef enum { /*!< SOFT_RESET_DECODER_IO.PERIPH_DECODER_IO bitfield definition*/ 199 scb_periph_not_in_soft_reset_decoder_io = 0, 200 scb_periph_reset_decoder_io = 1 201 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_PERIPH_DECODER_IO_TypeDef; 202 203 typedef enum { /*!< SOFT_RESET_DECODER_IO.V_MAP_DECODER_IO bitfield definition*/ 204 scb_v_regs_not_in_soft_reset_decoder_io = 0, 205 scb_v_regs_reset_decoder_io = 1 206 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_V_MAP_DECODER_IO_TypeDef; 207 208 typedef enum { /*!< SOFT_RESET_DECODER_IO.NV_MAP_DECODER_IO bitfield definition*/ 209 scb_nv_regs_not_in_soft_reset_decoder_io = 0, 210 scb_nv_regs_reset_decoder_io = 1 211 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_NV_MAP_DECODER_IO_TypeDef; 212 213 typedef enum { /*!< SOFT_RESET_TIP.PERIPH_TIP bitfield definition*/ 214 scb_periph_not_in_soft_reset_ddr_tip = 0, 215 scb_periph_reset_ddr_tip = 1 216 } CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_PERIPH_TIP_TypeDef; 217 218 typedef enum { /*!< SOFT_RESET_TIP.V_MAP_TIP bitfield definition*/ 219 scb_v_regs_not_in_soft_reset_ddr_tip = 0, 220 scb_v_regs_reset_ddr_tip = 1 221 } CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_V_MAP_TIP_TypeDef; 222 223 typedef enum { /*!< SOFT_RESET_TIP.NV_MAP_TIP bitfield definition*/ 224 scb_nv_regs_not_in_soft_reset_ddr_tip = 0, 225 scb_nv_regs_reset_ddr_tip = 1 226 } CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_NV_MAP_TIP_TypeDef; 227 228 typedef union{ /*!< SOFT_RESET_DDR_PHY register definition*/ 229 __IO uint32_t SOFT_RESET_DDR_PHY; 230 struct 231 { 232 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_NV_MAP_DDR_PHY_TypeDef NV_MAP_DDR_PHY :1; 233 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_V_MAP_DDR_PHY_TypeDef V_MAP_DDR_PHY :1; 234 __I uint32_t reserved_01 :6; 235 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_PERIPH_DDR_PHY_TypeDef PERIPH_DDR_PHY :1; 236 __I uint32_t reserved_02 :7; 237 __I uint32_t BLOCKID_DDR_PHY :16; 238 } bitfield; 239 } CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_TypeDef; 240 241 typedef union{ /*!< DDRPHY_MODE register definition*/ 242 __IO uint32_t DDRPHY_MODE; 243 struct 244 { 245 __IO uint32_t DDRMODE :3; 246 __IO uint32_t ECC :1; 247 __IO uint32_t CRC :1; 248 __IO uint32_t Bus_width :3; 249 __IO uint32_t DMI_DBI :1; 250 __IO uint32_t DQ_drive :2; 251 __IO uint32_t DQS_drive :2; 252 __IO uint32_t ADD_CMD_drive :2; 253 __IO uint32_t Clock_out_drive :2; 254 __IO uint32_t DQ_termination :2; 255 __IO uint32_t DQS_termination :2; 256 __IO uint32_t ADD_CMD_input_pin_termination :2; 257 __IO uint32_t preset_odt_clk :2; 258 __IO uint32_t Power_down :1; 259 __IO uint32_t rank :1; 260 __IO uint32_t Command_Address_Pipe :2; 261 __I uint32_t Reserved :3; 262 } bitfield; 263 } CFG_DDR_SGMII_PHY_DDRPHY_MODE_TypeDef; 264 265 typedef union{ /*!< DDRPHY_STARTUP register definition*/ 266 __IO uint32_t DDRPHY_STARTUP; 267 struct 268 { 269 __IO uint32_t ADD_CMD_Lockdn :1; 270 __IO uint32_t DATA_Lockdn :1; 271 __IO uint32_t PERSIST_ADD_CMD :1; 272 __IO uint32_t Persist_CLKOUT :1; 273 __IO uint32_t Persist_DATA :1; 274 __I uint32_t reserved :3; 275 __IO uint32_t DYNEN_SCB_PLL0 :1; 276 __IO uint32_t DYNEN_SCB_PLL1 :1; 277 __IO uint32_t DYNEN_SCB_CFM :1; 278 __IO uint32_t DYNEN_SCB_IO_CALIB :1; 279 __IO uint32_t DYNEN_SCB_BANKCNTL :1; 280 __I uint32_t reserved2 :3; 281 __IO uint32_t DYNEN_APB_PLL0 :1; 282 __IO uint32_t DYNEN_APB_PLL1 :1; 283 __IO uint32_t DYNEN_APB_CFM :1; 284 __IO uint32_t DYNEN_APB_IO_CALIB :1; 285 __IO uint32_t DYNEN_APB_BANKCNTL :1; 286 __IO uint32_t DYNEN_APB_DECODER_PRESETS :1; 287 __IO uint32_t reserved3 :10; 288 } bitfield; 289 } CFG_DDR_SGMII_PHY_DDRPHY_STARTUP_TypeDef; 290 291 typedef union{ /*!< SOFT_RESET_MAIN_PLL register definition*/ 292 __IO uint32_t SOFT_RESET_MAIN_PLL; 293 struct 294 { 295 __O CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_NV_MAP_MAIN_PLL_TypeDef NV_MAP_MAIN_PLL :1; 296 __O CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_V_MAP_MAIN_PLL_TypeDef V_MAP_MAIN_PLL :1; 297 __I uint32_t reserved_01 :6; 298 __O CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_PERIPH_MAIN_PLL_TypeDef PERIPH_MAIN_PLL :1; 299 __I uint32_t reserved_02 :7; 300 __I CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_BLOCKID_MAIN_PLL_TypeDef BLOCKID_MAIN_PLL :16; 301 } bitfield; 302 } CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_TypeDef; 303 304 typedef union{ /*!< PLL_CTRL_MAIN register definition*/ 305 __IO uint32_t PLL_CTRL_MAIN; 306 struct 307 { 308 __IO uint32_t REG_POWERDOWN_B :1; 309 __IO uint32_t REG_RFDIV_EN :1; 310 __IO uint32_t REG_DIVQ0_EN :1; 311 __IO uint32_t REG_DIVQ1_EN :1; 312 __IO uint32_t REG_DIVQ2_EN :1; 313 __IO uint32_t REG_DIVQ3_EN :1; 314 __IO uint32_t REG_RFCLK_SEL :1; 315 __I uint32_t RESETONLOCK :1; 316 __I uint32_t BYPCK_SEL :4; 317 __I uint32_t REG_BYPASS_GO_B :1; 318 __I uint32_t reserve10 :3; 319 __I uint32_t REG_BYPASSPRE :4; 320 __I uint32_t REG_BYPASSPOST :4; 321 __IO uint32_t LP_REQUIRES_LOCK :1; 322 __I uint32_t LOCK :1; 323 __I uint32_t LOCK_INT_EN :1; 324 __I uint32_t UNLOCK_INT_EN :1; 325 __I uint32_t LOCK_INT :1; 326 __I uint32_t UNLOCK_INT :1; 327 __I uint32_t reserve11 :1; 328 __I uint32_t LOCK_B :1; 329 } bitfield; 330 } CFG_DDR_SGMII_PHY_PLL_CTRL_MAIN_TypeDef; 331 332 typedef union{ /*!< PLL_REF_FB_MAIN register definition*/ 333 __IO uint32_t PLL_REF_FB_MAIN; 334 struct 335 { 336 __I uint32_t FSE_B :1; 337 __I uint32_t FBCK_SEL :2; 338 __I uint32_t FOUTFB_SELMUX_EN :1; 339 __I uint32_t reserve12 :4; 340 __IO uint32_t RFDIV :6; 341 __I uint32_t reserve13 :2; 342 __I uint32_t reserve14 :12; 343 __I uint32_t reserve15 :4; 344 } bitfield; 345 } CFG_DDR_SGMII_PHY_PLL_REF_FB_MAIN_TypeDef; 346 347 typedef union{ /*!< PLL_FRACN_MAIN register definition*/ 348 __IO uint32_t PLL_FRACN_MAIN; 349 struct 350 { 351 __I uint32_t FRACN_EN :1; 352 __I uint32_t FRACN_DAC_EN :1; 353 __I uint32_t reserve16 :6; 354 __I uint32_t reserve17 :24; 355 } bitfield; 356 } CFG_DDR_SGMII_PHY_PLL_FRACN_MAIN_TypeDef; 357 358 typedef union{ /*!< PLL_DIV_0_1_MAIN register definition*/ 359 __IO uint32_t PLL_DIV_0_1_MAIN; 360 struct 361 { 362 __I uint32_t VCO0PH_SEL :3; 363 __I uint32_t DIV0_START :3; 364 __I uint32_t reserve18 :2; 365 __IO uint32_t POST0DIV :7; 366 __I uint32_t reserve19 :1; 367 __I uint32_t VCO1PH_SEL :3; 368 __I uint32_t DIV1_START :3; 369 __I uint32_t reserve20 :2; 370 __IO uint32_t POST1DIV :7; 371 __I uint32_t reserve21 :1; 372 } bitfield; 373 } CFG_DDR_SGMII_PHY_PLL_DIV_0_1_MAIN_TypeDef; 374 375 typedef union{ /*!< PLL_DIV_2_3_MAIN register definition*/ 376 __IO uint32_t PLL_DIV_2_3_MAIN; 377 struct 378 { 379 __I uint32_t VCO2PH_SEL :3; 380 __I uint32_t DIV2_START :3; 381 __I uint32_t reserve22 :2; 382 __IO uint32_t POST2DIV :7; 383 __I uint32_t reserve23 :1; 384 __I uint32_t VCO3PH_SEL :3; 385 __I uint32_t DIV3_START :3; 386 __I uint32_t reserve24 :2; 387 __IO uint32_t POST3DIV :7; 388 __I uint32_t CKPOST3_SEL :1; 389 } bitfield; 390 } CFG_DDR_SGMII_PHY_PLL_DIV_2_3_MAIN_TypeDef; 391 392 typedef union{ /*!< PLL_CTRL2_MAIN register definition*/ 393 __IO uint32_t PLL_CTRL2_MAIN; 394 struct 395 { 396 __IO uint32_t BWI :2; 397 __IO uint32_t BWP :2; 398 __I uint32_t IREF_EN :1; 399 __I uint32_t IREF_TOGGLE :1; 400 __I uint32_t reserve25 :3; 401 __I uint32_t LOCKCNT :4; 402 __I uint32_t reserve26 :4; 403 __I uint32_t ATEST_EN :1; 404 __I uint32_t ATEST_SEL :3; 405 __I uint32_t reserve27 :11; 406 } bitfield; 407 } CFG_DDR_SGMII_PHY_PLL_CTRL2_MAIN_TypeDef; 408 409 typedef union{ /*!< PLL_CAL_MAIN register definition*/ 410 __I uint32_t PLL_CAL_MAIN; 411 struct 412 { 413 __I uint32_t DSKEWCALCNT :3; 414 __I uint32_t DSKEWCAL_EN :1; 415 __I uint32_t DSKEWCALBYP :1; 416 __I uint32_t reserve28 :3; 417 __I uint32_t DSKEWCALIN :7; 418 __I uint32_t reserve29 :1; 419 __I uint32_t DSKEWCALOUT :7; 420 __I uint32_t reserve30 :9; 421 } bitfield; 422 } CFG_DDR_SGMII_PHY_PLL_CAL_MAIN_TypeDef; 423 424 typedef union{ /*!< PLL_PHADJ_MAIN register definition*/ 425 __IO uint32_t PLL_PHADJ_MAIN; 426 struct 427 { 428 __I uint32_t PLL_REG_SYNCREFDIV_EN :1; 429 __I uint32_t PLL_REG_ENABLE_SYNCREFDIV :1; 430 __IO uint32_t REG_OUT0_PHSINIT :3; 431 __IO uint32_t REG_OUT1_PHSINIT :3; 432 __IO uint32_t REG_OUT2_PHSINIT :3; 433 __IO uint32_t REG_OUT3_PHSINIT :3; 434 __IO uint32_t REG_LOADPHS_B :1; 435 __I uint32_t reserve31 :17; 436 } bitfield; 437 } CFG_DDR_SGMII_PHY_PLL_PHADJ_MAIN_TypeDef; 438 439 typedef union{ /*!< SSCG_REG_0_MAIN register definition*/ 440 __IO uint32_t SSCG_REG_0_MAIN; /* todo: verify should be r/w, it is not in source file from Duolog */ 441 struct 442 { 443 __I uint32_t DIVVAL :6; 444 __I uint32_t FRACIN :24; 445 __I uint32_t reserve00 :2; 446 } bitfield; 447 } CFG_DDR_SGMII_PHY_SSCG_REG_0_MAIN_TypeDef; 448 449 typedef union{ /*!< SSCG_REG_1_MAIN register definition*/ 450 __I uint32_t SSCG_REG_1_MAIN; 451 struct 452 { 453 __I uint32_t DOWNSPREAD :1; 454 __I uint32_t SSMD :5; 455 __I uint32_t FRACMOD :24; 456 __I uint32_t reserve01 :2; 457 } bitfield; 458 } CFG_DDR_SGMII_PHY_SSCG_REG_1_MAIN_TypeDef; 459 460 typedef union{ /*!< SSCG_REG_2_MAIN register definition*/ 461 __IO uint32_t SSCG_REG_2_MAIN; 462 struct 463 { 464 __IO uint32_t INTIN :12; 465 __I uint32_t INTMOD :12; 466 __I uint32_t reserve02 :8; 467 } bitfield; 468 } CFG_DDR_SGMII_PHY_SSCG_REG_2_MAIN_TypeDef; 469 470 typedef union{ /*!< SSCG_REG_3_MAIN register definition*/ 471 __IO uint32_t SSCG_REG_3_MAIN; /* todo: verify if should be __IO */ 472 struct 473 { 474 __I uint32_t SSE_B :1; 475 __I uint32_t SEL_EXTWAVE :2; 476 __I uint32_t EXT_MAXADDR :8; 477 __I uint32_t TBLADDR :8; 478 __I uint32_t RANDOM_FILTER :1; 479 __I uint32_t RANDOM_SEL :2; 480 __I uint32_t reserve03 :1; 481 __I uint32_t reserve04 :9; 482 } bitfield; 483 } CFG_DDR_SGMII_PHY_SSCG_REG_3_MAIN_TypeDef; 484 485 typedef union{ /*!< RPC_RESET_MAIN_PLL register definition*/ 486 __IO uint32_t RPC_RESET_MAIN_PLL; 487 struct 488 { 489 __IO uint32_t soft_reset_periph_MAIN_PLL :1; 490 __I uint32_t Reserved :31; 491 } bitfield; 492 } CFG_DDR_SGMII_PHY_RPC_RESET_MAIN_PLL_TypeDef; 493 494 typedef union{ /*!< SOFT_RESET_IOSCB_PLL register definition*/ 495 __IO uint32_t SOFT_RESET_IOSCB_PLL; 496 struct 497 { 498 __O CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_NV_MAP_IOSCB_PLL_TypeDef NV_MAP_IOSCB_PLL :1; 499 __O CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_V_MAP_IOSCB_PLL_TypeDef V_MAP_IOSCB_PLL :1; 500 __I uint32_t reserved_01 :6; 501 __O CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_PERIPH_IOSCB_PLL_TypeDef PERIPH_IOSCB_PLL :1; 502 __I uint32_t reserved_02 :7; 503 __I CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_BLOCKID_IOSCB_PLL_TypeDef BLOCKID_IOSCB_PLL :16; 504 } bitfield; 505 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_TypeDef; 506 507 typedef union{ /*!< PLL_CTRL_IOSCB register definition*/ 508 __IO uint32_t PLL_CTRL_IOSCB; 509 struct 510 { 511 __IO uint32_t REG_POWERDOWN_B :1; 512 __IO uint32_t REG_RFDIV_EN :1; 513 __IO uint32_t REG_DIVQ0_EN :1; 514 __IO uint32_t REG_DIVQ1_EN :1; 515 __IO uint32_t REG_DIVQ2_EN :1; 516 __IO uint32_t REG_DIVQ3_EN :1; 517 __IO uint32_t REG_RFCLK_SEL :1; 518 __I uint32_t RESETONLOCK :1; 519 __I uint32_t BYPCK_SEL :4; 520 __I uint32_t REG_BYPASS_GO_B :1; 521 __I uint32_t reserve10 :3; 522 __I uint32_t REG_BYPASSPRE :4; 523 __I uint32_t REG_BYPASSPOST :4; 524 __IO uint32_t LP_REQUIRES_LOCK :1; 525 __I uint32_t LOCK :1; 526 __I uint32_t LOCK_INT_EN :1; 527 __I uint32_t UNLOCK_INT_EN :1; 528 __I uint32_t LOCK_INT :1; 529 __I uint32_t UNLOCK_INT :1; 530 __I uint32_t reserve11 :1; 531 __I uint32_t LOCK_B :1; 532 } bitfield; 533 } CFG_DDR_SGMII_PHY_PLL_CTRL_IOSCB_TypeDef; 534 535 typedef union{ /*!< PLL_REF_FB_IOSCB register definition*/ 536 __IO uint32_t PLL_REF_FB_IOSCB; 537 struct 538 { 539 __I uint32_t FSE_B :1; 540 __I uint32_t FBCK_SEL :2; 541 __I uint32_t FOUTFB_SELMUX_EN :1; 542 __I uint32_t reserve12 :4; 543 __IO uint32_t RFDIV :6; 544 __I uint32_t reserve13 :2; 545 __I uint32_t reserve14 :12; 546 __I uint32_t reserve15 :4; 547 } bitfield; 548 } CFG_DDR_SGMII_PHY_PLL_REF_FB_IOSCB_TypeDef; 549 550 typedef union{ /*!< PLL_FRACN_IOSCB register definition*/ 551 __I uint32_t PLL_FRACN_IOSCB; 552 struct 553 { 554 __I uint32_t FRACN_EN :1; 555 __I uint32_t FRACN_DAC_EN :1; 556 __I uint32_t reserve16 :6; 557 __I uint32_t reserve17 :24; 558 } bitfield; 559 } CFG_DDR_SGMII_PHY_PLL_FRACN_IOSCB_TypeDef; 560 561 typedef union{ /*!< PLL_DIV_0_1_IOSCB register definition*/ 562 __IO uint32_t PLL_DIV_0_1_IOSCB; 563 struct 564 { 565 __I uint32_t VCO0PH_SEL :3; 566 __I uint32_t DIV0_START :3; 567 __I uint32_t reserve18 :2; 568 __IO uint32_t POST0DIV :7; 569 __I uint32_t reserve19 :1; 570 __I uint32_t VCO1PH_SEL :3; 571 __I uint32_t DIV1_START :3; 572 __I uint32_t reserve20 :2; 573 __IO uint32_t POST1DIV :7; 574 __I uint32_t reserve21 :1; 575 } bitfield; 576 } CFG_DDR_SGMII_PHY_PLL_DIV_0_1_IOSCB_TypeDef; 577 578 typedef union{ /*!< PLL_DIV_2_3_IOSCB register definition*/ 579 __IO uint32_t PLL_DIV_2_3_IOSCB; 580 struct 581 { 582 __I uint32_t VCO2PH_SEL :3; 583 __I uint32_t DIV2_START :3; 584 __I uint32_t reserve22 :2; 585 __IO uint32_t POST2DIV :7; 586 __I uint32_t reserve23 :1; 587 __I uint32_t VCO3PH_SEL :3; 588 __I uint32_t DIV3_START :3; 589 __I uint32_t reserve24 :2; 590 __IO uint32_t POST3DIV :7; 591 __I uint32_t CKPOST3_SEL :1; 592 } bitfield; 593 } CFG_DDR_SGMII_PHY_PLL_DIV_2_3_IOSCB_TypeDef; 594 595 typedef union{ /*!< PLL_CTRL2_IOSCB register definition*/ 596 __IO uint32_t PLL_CTRL2_IOSCB; 597 struct 598 { 599 __IO uint32_t BWI :2; 600 __IO uint32_t BWP :2; 601 __I uint32_t IREF_EN :1; 602 __I uint32_t IREF_TOGGLE :1; 603 __I uint32_t reserve25 :3; 604 __I uint32_t LOCKCNT :4; 605 __I uint32_t reserve26 :4; 606 __I uint32_t ATEST_EN :1; 607 __I uint32_t ATEST_SEL :3; 608 __I uint32_t reserve27 :11; 609 } bitfield; 610 } CFG_DDR_SGMII_PHY_PLL_CTRL2_IOSCB_TypeDef; 611 612 typedef union{ /*!< PLL_CAL_IOSCB register definition*/ 613 __I uint32_t PLL_CAL_IOSCB; 614 struct 615 { 616 __I uint32_t DSKEWCALCNT :3; 617 __I uint32_t DSKEWCAL_EN :1; 618 __I uint32_t DSKEWCALBYP :1; 619 __I uint32_t reserve28 :3; 620 __I uint32_t DSKEWCALIN :7; 621 __I uint32_t reserve29 :1; 622 __I uint32_t DSKEWCALOUT :7; 623 __I uint32_t reserve30 :9; 624 } bitfield; 625 } CFG_DDR_SGMII_PHY_PLL_CAL_IOSCB_TypeDef; 626 627 typedef union{ /*!< PLL_PHADJ_IOSCB register definition*/ 628 __IO uint32_t PLL_PHADJ_IOSCB; 629 struct 630 { 631 __I uint32_t PLL_REG_SYNCREFDIV_EN :1; 632 __I uint32_t PLL_REG_ENABLE_SYNCREFDIV :1; 633 __IO uint32_t REG_OUT0_PHSINIT :3; 634 __IO uint32_t REG_OUT1_PHSINIT :3; 635 __IO uint32_t REG_OUT2_PHSINIT :3; 636 __IO uint32_t REG_OUT3_PHSINIT :3; 637 __IO uint32_t REG_LOADPHS_B :1; 638 __I uint32_t reserve31 :17; 639 } bitfield; 640 } CFG_DDR_SGMII_PHY_PLL_PHADJ_IOSCB_TypeDef; 641 642 typedef union{ /*!< SSCG_REG_0_IOSCB register definition*/ 643 __I uint32_t SSCG_REG_0_IOSCB; 644 struct 645 { 646 __I uint32_t DIVVAL :6; 647 __I uint32_t FRACIN :24; 648 __I uint32_t reserve00 :2; 649 } bitfield; 650 } CFG_DDR_SGMII_PHY_SSCG_REG_0_IOSCB_TypeDef; 651 652 typedef union{ /*!< SSCG_REG_1_IOSCB register definition*/ 653 __I uint32_t SSCG_REG_1_IOSCB; 654 struct 655 { 656 __I uint32_t DOWNSPREAD :1; 657 __I uint32_t SSMD :5; 658 __I uint32_t FRACMOD :24; 659 __I uint32_t reserve01 :2; 660 } bitfield; 661 } CFG_DDR_SGMII_PHY_SSCG_REG_1_IOSCB_TypeDef; 662 663 typedef union{ /*!< SSCG_REG_2_IOSCB register definition*/ 664 __IO uint32_t SSCG_REG_2_IOSCB; 665 struct 666 { 667 __IO uint32_t INTIN :12; 668 __I uint32_t INTMOD :12; 669 __I uint32_t reserve02 :8; 670 } bitfield; 671 } CFG_DDR_SGMII_PHY_SSCG_REG_2_IOSCB_TypeDef; 672 673 typedef union{ /*!< SSCG_REG_3_IOSCB register definition*/ 674 __I uint32_t SSCG_REG_3_IOSCB; 675 struct 676 { 677 __I uint32_t SSE_B :1; 678 __I uint32_t SEL_EXTWAVE :2; 679 __I uint32_t EXT_MAXADDR :8; 680 __I uint32_t TBLADDR :8; 681 __I uint32_t RANDOM_FILTER :1; 682 __I uint32_t RANDOM_SEL :2; 683 __I uint32_t reserve03 :1; 684 __I uint32_t reserve04 :9; 685 } bitfield; 686 } CFG_DDR_SGMII_PHY_SSCG_REG_3_IOSCB_TypeDef; 687 688 typedef union{ /*!< RPC_RESET_IOSCB register definition*/ 689 __IO uint32_t RPC_RESET_IOSCB; 690 struct 691 { 692 __IO uint32_t soft_reset_periph_IOSCB :1; 693 __I uint32_t Reserved :31; 694 } bitfield; 695 } CFG_DDR_SGMII_PHY_RPC_RESET_IOSCB_TypeDef; 696 697 typedef union{ /*!< SOFT_RESET_BANK_CTRL register definition*/ 698 __IO uint32_t SOFT_RESET_BANK_CTRL; 699 struct 700 { 701 __O CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_NV_MAP_BANK_CTRL_TypeDef NV_MAP_BANK_CTRL :1; 702 __O CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_V_MAP_BANK_CTRL_TypeDef V_MAP_BANK_CTRL :1; 703 __I uint32_t reserved_01 :6; 704 __O CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_PERIPH_BANK_CTRL_TypeDef PERIPH_BANK_CTRL :1; 705 __I uint32_t reserved_02 :7; 706 __I CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_BLOCKID_BANK_CTRL_TypeDef BLOCKID_BANK_CTRL :16; 707 } bitfield; 708 } CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_TypeDef; 709 710 typedef union{ /*!< DPC_BITS register definition*/ 711 __IO uint32_t DPC_BITS; 712 struct 713 { 714 __IO uint32_t dpc_vs :4; 715 __IO uint32_t dpc_vrgen_h :6; 716 __IO uint32_t dpc_vrgen_en_h :1; 717 __IO uint32_t dpc_move_en_h :1; 718 __IO uint32_t dpc_vrgen_v :6; 719 __IO uint32_t dpc_vrgen_en_v :1; 720 __IO uint32_t dpc_move_en_v :1; 721 __I uint32_t reserve01 :12; 722 } bitfield; 723 } CFG_DDR_SGMII_PHY_DPC_BITS_TypeDef; 724 725 typedef union{ /*!< BANK_STATUS register definition*/ 726 __I uint32_t BANK_STATUS; 727 struct 728 { 729 __I uint32_t sro_calib_status_b :1; 730 __I uint32_t sro_ioen_bnk_b :1; 731 __I uint32_t reserved_01 :30; 732 } bitfield; 733 } CFG_DDR_SGMII_PHY_BANK_STATUS_TypeDef; 734 735 typedef union{ /*!< RPC_RESET_BANK_CTRL register definition*/ 736 __IO uint32_t RPC_RESET_BANK_CTRL; 737 struct 738 { 739 __IO uint32_t soft_reset_periph_BANK_CTRL :1; 740 __I uint32_t Reserved :31; 741 } bitfield; 742 } CFG_DDR_SGMII_PHY_RPC_RESET_BANK_CTRL_TypeDef; 743 744 typedef union{ /*!< SOFT_RESET_IOCALIB register definition*/ 745 __IO uint32_t SOFT_RESET_IOCALIB; 746 struct 747 { 748 __O CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_NV_MAP_IOCALIB_TypeDef NV_MAP_IOCALIB :1; 749 __O CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_V_MAP_IOCALIB_TypeDef V_MAP_IOCALIB :1; 750 __I uint32_t reserved_01 :6; 751 __O CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_PERIPH_IOCALIB_TypeDef PERIPH_IOCALIB :1; 752 __I uint32_t reserved_02 :7; 753 __I CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_BLOCKID_IOCALIB_TypeDef BLOCKID_IOCALIB :16; 754 } bitfield; 755 } CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_TypeDef; 756 757 typedef union{ /*!< IOC_REG0 register definition*/ 758 __IO uint32_t IOC_REG0; 759 struct 760 { 761 __IO uint32_t reg_pcode :6; 762 __IO uint32_t reg_ncode :6; 763 __I uint32_t reg_calib_trim :1; 764 __IO uint32_t reg_calib_start :1; 765 __IO uint32_t reg_calib_lock :1; 766 __I uint32_t reg_calib_load :1; 767 __I uint32_t reg_calib_direction :1; 768 __I uint32_t reg_calib_move_pcode :1; 769 __I uint32_t reg_calib_move_ncode :1; 770 __I uint32_t reserve01 :13; 771 } bitfield; 772 } CFG_DDR_SGMII_PHY_IOC_REG0_TypeDef; 773 774 typedef union{ /*!< IOC_REG1 register definition*/ 775 __I uint32_t IOC_REG1; 776 struct 777 { 778 __I uint32_t sro_code_done_p :1; 779 __I uint32_t sro_code_done_n :1; 780 __I uint32_t sro_calib_status :1; 781 __I uint32_t sro_calib_intrpt :1; 782 __I uint32_t sro_ioen_out :1; 783 __I uint32_t sro_power_on :1; 784 __I uint32_t sro_comp_sel :1; 785 __I uint32_t sro_comp_en :1; 786 __I uint32_t reserve02 :24; 787 } bitfield; 788 } CFG_DDR_SGMII_PHY_IOC_REG1_TypeDef; 789 790 typedef union{ /*!< IOC_REG2 register definition*/ 791 __I uint32_t IOC_REG2; 792 struct 793 { 794 __I uint32_t sro_pcode :7; 795 __I uint32_t sro_ncode :7; 796 __I uint32_t sro_ref_pcode :7; 797 __I uint32_t sro_ref_ncode :7; 798 __I uint32_t sro_comp_out :1; 799 __I uint32_t reserve03 :3; 800 } bitfield; 801 } CFG_DDR_SGMII_PHY_IOC_REG2_TypeDef; 802 803 typedef union{ /*!< IOC_REG3 register definition*/ 804 __I uint32_t IOC_REG3; 805 struct 806 { 807 __I uint32_t reserve04 :5; 808 __I uint32_t reg_calib_poffset :6; 809 __I uint32_t reg_calib_poffset_dir :1; 810 __I uint32_t reg_calib_noffset :6; 811 __I uint32_t reg_calib_noffset_dir :1; 812 __I uint32_t reg_calib_move_slewr :1; 813 __I uint32_t reg_calib_move_slewf :1; 814 __I uint32_t reg_calib_roffset_dir :1; 815 __I uint32_t reg_calib_foffset_dir :1; 816 __I uint32_t reserve05 :9; 817 } bitfield; 818 } CFG_DDR_SGMII_PHY_IOC_REG3_TypeDef; 819 820 typedef union{ /*!< IOC_REG4 register definition*/ 821 __I uint32_t IOC_REG4; 822 struct 823 { 824 __I uint32_t reg_roffset :6; 825 __I uint32_t reg_foffset :6; 826 __I uint32_t reg_slewr :6; 827 __I uint32_t reg_slewf :6; 828 __I uint32_t sro_slew_intrpt :1; 829 __I uint32_t sro_slew_status :1; 830 __I uint32_t sro_slew_comp_out :1; 831 __I uint32_t sro_slew_comp_en :1; 832 __I uint32_t sro_slew_comp_sel :1; 833 __I uint32_t sro_slew_ioen_out :1; 834 __I uint32_t sro_slew_power_on :1; 835 __I uint32_t reserve06 :1; 836 } bitfield; 837 } CFG_DDR_SGMII_PHY_IOC_REG4_TypeDef; 838 839 typedef union{ /*!< IOC_REG5 register definition*/ 840 __I uint32_t IOC_REG5; 841 struct 842 { 843 __I uint32_t sro_ref_slewr :6; 844 __I uint32_t sro_ref_slewf :12; 845 __I uint32_t sro_slewr :6; 846 __I uint32_t sro_slewf :6; 847 __I uint32_t reserve07 :2; 848 } bitfield; 849 } CFG_DDR_SGMII_PHY_IOC_REG5_TypeDef; 850 851 typedef union{ /*!< IOC_REG6 register definition*/ 852 __IO uint32_t IOC_REG6; 853 struct 854 { 855 __IO uint32_t reg_calib_reset :1; 856 __IO uint32_t reg_calib_clkdiv :2; 857 __I uint32_t reserve08 :29; 858 } bitfield; 859 } CFG_DDR_SGMII_PHY_IOC_REG6_TypeDef; 860 861 typedef union{ /*!< RPC_RESET_IOCALIB register definition*/ 862 __IO uint32_t RPC_RESET_IOCALIB; 863 struct 864 { 865 __IO uint32_t soft_reset_periph_IOCALIB :1; 866 __I uint32_t Reserved :31; 867 } bitfield; 868 } CFG_DDR_SGMII_PHY_RPC_RESET_IOCALIB_TypeDef; 869 870 typedef union{ /*!< rpc_calib register definition*/ 871 __IO uint32_t rpc_calib; 872 struct 873 { 874 __IO uint32_t start_pvt :1; 875 __IO uint32_t lock_pvt :1; 876 __I uint32_t Reserved :30; 877 } bitfield; 878 } CFG_DDR_SGMII_PHY_rpc_calib_TypeDef; 879 880 typedef union{ /*!< SOFT_RESET_CFM register definition*/ 881 __IO uint32_t SOFT_RESET_CFM; 882 struct 883 { 884 __O CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_NV_MAP_CFM_TypeDef NV_MAP_CFM :1; 885 __O CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_V_MAP_CFM_TypeDef V_MAP_CFM :1; 886 __I uint32_t reserved_01 :6; 887 __O CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_PERIPH_CFM_TypeDef PERIPH_CFM :1; 888 __I uint32_t reserved_02 :7; 889 __I CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_BLOCKID_CFM_TypeDef BLOCKID_CFM :16; 890 } bitfield; 891 } CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_TypeDef; 892 893 typedef union{ /*!< BCLKMUX register definition*/ 894 __IO uint32_t BCLKMUX; 895 struct 896 { 897 __IO uint32_t bclk0_sel :5; 898 __IO uint32_t bclk1_sel :5; 899 __IO uint32_t bclk2_sel :5; 900 __IO uint32_t bclk3_sel :5; 901 __IO uint32_t bclk4_sel :5; 902 __IO uint32_t bclk5_sel :5; 903 __I uint32_t reserve0 :2; 904 } bitfield; 905 } CFG_DDR_SGMII_PHY_BCLKMUX_TypeDef; 906 907 typedef union{ /*!< PLL_CKMUX register definition*/ 908 __IO uint32_t PLL_CKMUX; 909 struct 910 { 911 __IO uint32_t clk_in_mac_tsu :2; 912 __IO uint32_t pll0_rfclk0_sel :2; 913 __IO uint32_t pll0_rfclk1_sel :2; 914 __IO uint32_t pll1_rfclk0_sel :2; 915 __IO uint32_t pll1_rfclk1_sel :2; 916 __IO uint32_t pll1_fdr_sel :5; 917 __I uint32_t reserve1 :17; 918 } bitfield; 919 } CFG_DDR_SGMII_PHY_PLL_CKMUX_TypeDef; 920 921 typedef union{ /*!< MSSCLKMUX register definition*/ 922 __IO uint32_t MSSCLKMUX; 923 struct 924 { 925 __IO uint32_t mssclk_mux_sel :2; 926 __IO uint32_t mssclk_mux_md :2; 927 __IO uint32_t clk_standby_sel :1; 928 __I uint32_t reserve2 :27; 929 } bitfield; 930 } CFG_DDR_SGMII_PHY_MSSCLKMUX_TypeDef; 931 932 typedef union{ /*!< SPARE0 register definition*/ 933 __IO uint32_t SPARE0; 934 struct 935 { 936 __IO uint32_t spare0 :32; 937 } bitfield; 938 } CFG_DDR_SGMII_PHY_SPARE0_TypeDef; 939 940 typedef union{ /*!< FMETER_ADDR register definition*/ 941 __I uint32_t FMETER_ADDR; 942 struct 943 { 944 __I uint32_t addr10 :2; 945 __I uint32_t addr :4; 946 __I uint32_t reserve3 :26; 947 } bitfield; 948 } CFG_DDR_SGMII_PHY_FMETER_ADDR_TypeDef; 949 950 typedef union{ /*!< FMETER_DATAW register definition*/ 951 __I uint32_t FMETER_DATAW; 952 struct 953 { 954 __I uint32_t data :24; 955 __I uint32_t strobe :1; 956 __I uint32_t reserve4 :7; 957 } bitfield; 958 } CFG_DDR_SGMII_PHY_FMETER_DATAW_TypeDef; 959 960 typedef union{ /*!< FMETER_DATAR register definition*/ 961 __I uint32_t FMETER_DATAR; 962 struct 963 { 964 __I uint32_t data :24; 965 __I uint32_t reserve5 :8; 966 } bitfield; 967 } CFG_DDR_SGMII_PHY_FMETER_DATAR_TypeDef; 968 969 typedef union{ /*!< TEST_CTRL register definition*/ 970 __I uint32_t TEST_CTRL; 971 struct 972 { 973 __I uint32_t atest_en :1; 974 __I uint32_t atest_sel :5; 975 __I uint32_t dtest_en :1; 976 __I uint32_t dtest_sel :5; 977 __I uint32_t reserve6 :20; 978 } bitfield; 979 } CFG_DDR_SGMII_PHY_TEST_CTRL_TypeDef; 980 981 typedef union{ /*!< RPC_RESET_CFM register definition*/ 982 __IO uint32_t RPC_RESET_CFM; 983 struct 984 { 985 __IO uint32_t soft_reset_periph_CFM :1; 986 __I uint32_t Reserved :31; 987 } bitfield; 988 } CFG_DDR_SGMII_PHY_RPC_RESET_CFM_TypeDef; 989 990 typedef union{ /*!< SOFT_RESET_DECODER_DRIVER register definition*/ 991 __IO uint32_t SOFT_RESET_DECODER_DRIVER; 992 struct 993 { 994 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_NV_MAP_DECODER_DRIVER_TypeDef NV_MAP_DECODER_DRIVER :1; 995 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_V_MAP_DECODER_DRIVER_TypeDef V_MAP_DECODER_DRIVER :1; 996 __I uint32_t reserved_01 :6; 997 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_PERIPH_DECODER_DRIVER_TypeDef PERIPH_DECODER_DRIVER :1; 998 __I uint32_t reserved_02 :7; 999 __I CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_BLOCKID_DECODER_DRIVER_TypeDef BLOCKID_DECODER_DRIVER :16; 1000 } bitfield; 1001 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_TypeDef; 1002 1003 typedef union{ /*!< rpc1_DRV register definition*/ 1004 __IO uint32_t rpc1_DRV; 1005 struct 1006 { 1007 __IO uint32_t drv_addcmd :4; 1008 __I uint32_t reserved_01 :28; 1009 } bitfield; 1010 } CFG_DDR_SGMII_PHY_rpc1_DRV_TypeDef; 1011 1012 typedef union{ /*!< rpc2_DRV register definition*/ 1013 __IO uint32_t rpc2_DRV; 1014 struct 1015 { 1016 __IO uint32_t drv_clk :4; 1017 __I uint32_t reserved_01 :28; 1018 } bitfield; 1019 } CFG_DDR_SGMII_PHY_rpc2_DRV_TypeDef; 1020 1021 typedef union{ /*!< rpc3_DRV register definition*/ 1022 __IO uint32_t rpc3_DRV; 1023 struct 1024 { 1025 __IO uint32_t drv_dq :4; 1026 __I uint32_t reserved_01 :28; 1027 } bitfield; 1028 } CFG_DDR_SGMII_PHY_rpc3_DRV_TypeDef; 1029 1030 typedef union{ /*!< rpc4_DRV register definition*/ 1031 __IO uint32_t rpc4_DRV; 1032 struct 1033 { 1034 __IO uint32_t drv_dqs :4; 1035 __I uint32_t reserved_01 :28; 1036 } bitfield; 1037 } CFG_DDR_SGMII_PHY_rpc4_DRV_TypeDef; 1038 1039 typedef union{ /*!< SOFT_RESET_DECODER_ODT register definition*/ 1040 __IO uint32_t SOFT_RESET_DECODER_ODT; 1041 struct 1042 { 1043 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_NV_MAP_DECODER_ODT_TypeDef NV_MAP_DECODER_ODT :1; 1044 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_V_MAP_DECODER_ODT_TypeDef V_MAP_DECODER_ODT :1; 1045 __I uint32_t reserved_01 :6; 1046 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_PERIPH_DECODER_ODT_TypeDef PERIPH_DECODER_ODT :1; 1047 __I uint32_t reserved_02 :7; 1048 __I CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_BLOCKID_DECODER_ODT_TypeDef BLOCKID_DECODER_ODT :16; 1049 } bitfield; 1050 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_TypeDef; 1051 1052 typedef union{ /*!< rpc1_ODT register definition*/ 1053 __IO uint32_t rpc1_ODT; 1054 struct 1055 { 1056 __IO uint32_t odt_addcmd :4; 1057 __I uint32_t reserved_01 :28; 1058 } bitfield; 1059 } CFG_DDR_SGMII_PHY_rpc1_ODT_TypeDef; 1060 1061 typedef union{ /*!< rpc2_ODT register definition*/ 1062 __IO uint32_t rpc2_ODT; 1063 struct 1064 { 1065 __IO uint32_t odt_clk :4; 1066 __I uint32_t reserved_01 :28; 1067 } bitfield; 1068 } CFG_DDR_SGMII_PHY_rpc2_ODT_TypeDef; 1069 1070 typedef union{ /*!< rpc3_ODT register definition*/ 1071 __IO uint32_t rpc3_ODT; 1072 struct 1073 { 1074 __IO uint32_t odt_dq :4; 1075 __I uint32_t reserved_01 :28; 1076 } bitfield; 1077 } CFG_DDR_SGMII_PHY_rpc3_ODT_TypeDef; 1078 1079 typedef union{ /*!< rpc4_ODT register definition*/ 1080 __IO uint32_t rpc4_ODT; 1081 struct 1082 { 1083 __IO uint32_t odt_dqs :4; 1084 __I uint32_t reserved_01 :28; 1085 } bitfield; 1086 } CFG_DDR_SGMII_PHY_rpc4_ODT_TypeDef; 1087 1088 typedef union{ /*!< rpc5_ODT register definition*/ 1089 __IO uint32_t rpc5_ODT; 1090 struct 1091 { 1092 __IO uint32_t odt_dyn_sel_addcmd :1; 1093 __I uint32_t reserved_01 :31; 1094 } bitfield; 1095 } CFG_DDR_SGMII_PHY_rpc5_ODT_TypeDef; 1096 1097 typedef union{ /*!< rpc6_ODT register definition*/ 1098 __IO uint32_t rpc6_ODT; 1099 struct 1100 { 1101 __IO uint32_t odt_dyn_sel_data :1; 1102 __I uint32_t reserved_01 :31; 1103 } bitfield; 1104 } CFG_DDR_SGMII_PHY_rpc6_ODT_TypeDef; 1105 1106 typedef union{ /*!< rpc7_ODT register definition*/ 1107 __IO uint32_t rpc7_ODT; 1108 struct 1109 { 1110 __IO uint32_t odt_static_addcmd :3; 1111 __I uint32_t reserved_01 :29; 1112 } bitfield; 1113 } CFG_DDR_SGMII_PHY_rpc7_ODT_TypeDef; 1114 1115 typedef union{ /*!< rpc8_ODT register definition*/ 1116 __IO uint32_t rpc8_ODT; 1117 struct 1118 { 1119 __IO uint32_t odt_static_clkn :3; 1120 __I uint32_t reserved_01 :29; 1121 } bitfield; 1122 } CFG_DDR_SGMII_PHY_rpc8_ODT_TypeDef; 1123 1124 typedef union{ /*!< rpc9_ODT register definition*/ 1125 __IO uint32_t rpc9_ODT; 1126 struct 1127 { 1128 __IO uint32_t odt_static_clkp :3; 1129 __I uint32_t reserved_01 :29; 1130 } bitfield; 1131 } CFG_DDR_SGMII_PHY_rpc9_ODT_TypeDef; 1132 1133 typedef union{ /*!< rpc10_ODT register definition*/ 1134 __IO uint32_t rpc10_ODT; 1135 struct 1136 { 1137 __IO uint32_t odt_static_dq :3; 1138 __I uint32_t reserved_01 :29; 1139 } bitfield; 1140 } CFG_DDR_SGMII_PHY_rpc10_ODT_TypeDef; 1141 1142 typedef union{ /*!< rpc11_ODT register definition*/ 1143 __IO uint32_t rpc11_ODT; 1144 struct 1145 { 1146 __IO uint32_t odt_static_dqs :3; 1147 __I uint32_t reserved_01 :29; 1148 } bitfield; 1149 } CFG_DDR_SGMII_PHY_rpc11_ODT_TypeDef; 1150 1151 typedef union{ /*!< SOFT_RESET_DECODER_IO register definition*/ 1152 __IO uint32_t SOFT_RESET_DECODER_IO; 1153 struct 1154 { 1155 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_NV_MAP_DECODER_IO_TypeDef NV_MAP_DECODER_IO :1; 1156 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_V_MAP_DECODER_IO_TypeDef V_MAP_DECODER_IO :1; 1157 __I uint32_t reserved_01 :6; 1158 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_PERIPH_DECODER_IO_TypeDef PERIPH_DECODER_IO :1; 1159 __I uint32_t reserved_02 :7; 1160 __I CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_BLOCKID_DECODER_IO_TypeDef BLOCKID_DECODER_IO :16; 1161 } bitfield; 1162 } CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_TypeDef; 1163 1164 typedef union{ /*!< ovrt1 register definition*/ 1165 __IO uint32_t ovrt1; 1166 struct 1167 { 1168 __IO uint32_t drv_addcmd0 :12; 1169 __I uint32_t reserved_01 :20; 1170 } bitfield; 1171 } CFG_DDR_SGMII_PHY_ovrt1_TypeDef; 1172 1173 typedef union{ /*!< ovrt2 register definition*/ 1174 __IO uint32_t ovrt2; 1175 struct 1176 { 1177 __IO uint32_t drv_addcmd1 :12; 1178 __I uint32_t reserved_01 :20; 1179 } bitfield; 1180 } CFG_DDR_SGMII_PHY_ovrt2_TypeDef; 1181 1182 typedef union{ /*!< ovrt3 register definition*/ 1183 __IO uint32_t ovrt3; 1184 struct 1185 { 1186 __IO uint32_t drv_addcmd2 :12; 1187 __I uint32_t reserved_01 :20; 1188 } bitfield; 1189 } CFG_DDR_SGMII_PHY_ovrt3_TypeDef; 1190 1191 typedef union{ /*!< ovrt4 register definition*/ 1192 __IO uint32_t ovrt4; 1193 struct 1194 { 1195 __IO uint32_t drv_data0 :12; 1196 __I uint32_t reserved_01 :20; 1197 } bitfield; 1198 } CFG_DDR_SGMII_PHY_ovrt4_TypeDef; 1199 1200 typedef union{ /*!< ovrt5 register definition*/ 1201 __IO uint32_t ovrt5; 1202 struct 1203 { 1204 __IO uint32_t drv_data1 :12; 1205 __I uint32_t reserved_01 :20; 1206 } bitfield; 1207 } CFG_DDR_SGMII_PHY_ovrt5_TypeDef; 1208 1209 typedef union{ /*!< ovrt6 register definition*/ 1210 __IO uint32_t ovrt6; 1211 struct 1212 { 1213 __IO uint32_t drv_data2 :12; 1214 __I uint32_t reserved_01 :20; 1215 } bitfield; 1216 } CFG_DDR_SGMII_PHY_ovrt6_TypeDef; 1217 1218 typedef union{ /*!< ovrt7 register definition*/ 1219 __IO uint32_t ovrt7; 1220 struct 1221 { 1222 __IO uint32_t drv_data3 :12; 1223 __I uint32_t reserved_01 :20; 1224 } bitfield; 1225 } CFG_DDR_SGMII_PHY_ovrt7_TypeDef; 1226 1227 typedef union{ /*!< ovrt8 register definition*/ 1228 __IO uint32_t ovrt8; 1229 struct 1230 { 1231 __IO uint32_t drv_ecc :12; 1232 __I uint32_t reserved_01 :20; 1233 } bitfield; 1234 } CFG_DDR_SGMII_PHY_ovrt8_TypeDef; 1235 1236 typedef union{ /*!< ovrt9 register definition*/ 1237 __IO uint32_t ovrt9; 1238 struct 1239 { 1240 __IO uint32_t en_addcmd0 :12; 1241 __I uint32_t reserved_01 :20; 1242 } bitfield; 1243 } CFG_DDR_SGMII_PHY_ovrt9_TypeDef; 1244 1245 typedef union{ /*!< ovrt10 register definition*/ 1246 __IO uint32_t ovrt10; 1247 struct 1248 { 1249 __IO uint32_t en_addcmd1 :12; 1250 __I uint32_t reserved_01 :20; 1251 } bitfield; 1252 } CFG_DDR_SGMII_PHY_ovrt10_TypeDef; 1253 1254 typedef union{ /*!< ovrt11 register definition*/ 1255 __IO uint32_t ovrt11; 1256 struct 1257 { 1258 __IO uint32_t en_addcmd2 :12; 1259 __I uint32_t reserved_01 :20; 1260 } bitfield; 1261 } CFG_DDR_SGMII_PHY_ovrt11_TypeDef; 1262 1263 typedef union{ /*!< ovrt12 register definition*/ 1264 __IO uint32_t ovrt12; 1265 struct 1266 { 1267 __IO uint32_t en_data0 :12; 1268 __I uint32_t reserved_01 :20; 1269 } bitfield; 1270 } CFG_DDR_SGMII_PHY_ovrt12_TypeDef; 1271 1272 typedef union{ /*!< ovrt13 register definition*/ 1273 __IO uint32_t ovrt13; 1274 struct 1275 { 1276 __IO uint32_t en_data1 :12; 1277 __I uint32_t reserved_01 :20; 1278 } bitfield; 1279 } CFG_DDR_SGMII_PHY_ovrt13_TypeDef; 1280 1281 typedef union{ /*!< ovrt14 register definition*/ 1282 __IO uint32_t ovrt14; 1283 struct 1284 { 1285 __IO uint32_t en_data2 :12; 1286 __I uint32_t reserved_01 :20; 1287 } bitfield; 1288 } CFG_DDR_SGMII_PHY_ovrt14_TypeDef; 1289 1290 typedef union{ /*!< ovrt15 register definition*/ 1291 __IO uint32_t ovrt15; 1292 struct 1293 { 1294 __IO uint32_t en_data3 :12; 1295 __I uint32_t reserved_01 :20; 1296 } bitfield; 1297 } CFG_DDR_SGMII_PHY_ovrt15_TypeDef; 1298 1299 typedef union{ /*!< ovrt16 register definition*/ 1300 __IO uint32_t ovrt16; 1301 struct 1302 { 1303 __IO uint32_t en_ecc :12; 1304 __I uint32_t reserved_01 :20; 1305 } bitfield; 1306 } CFG_DDR_SGMII_PHY_ovrt16_TypeDef; 1307 1308 typedef union{ /*!< rpc17 register definition*/ 1309 __IO uint32_t rpc17; 1310 struct 1311 { 1312 __IO uint32_t bclk_sel_ac :3; 1313 __I uint32_t reserved_01 :29; 1314 } bitfield; 1315 } CFG_DDR_SGMII_PHY_rpc17_TypeDef; 1316 1317 typedef union{ /*!< rpc18 register definition*/ 1318 __IO uint32_t rpc18; 1319 struct 1320 { 1321 __IO uint32_t bclk_sel_addcmd :9; 1322 __I uint32_t reserved_01 :23; 1323 } bitfield; 1324 } CFG_DDR_SGMII_PHY_rpc18_TypeDef; 1325 1326 typedef union{ /*!< rpc19 register definition*/ 1327 __IO uint32_t rpc19; 1328 struct 1329 { 1330 __IO uint32_t bclk_sel_clkn :3; 1331 __I uint32_t reserved_01 :29; 1332 } bitfield; 1333 } CFG_DDR_SGMII_PHY_rpc19_TypeDef; 1334 1335 typedef union{ /*!< rpc20 register definition*/ 1336 __IO uint32_t rpc20; 1337 struct 1338 { 1339 __IO uint32_t bclk_sel_clkp :3; 1340 __I uint32_t reserved_01 :29; 1341 } bitfield; 1342 } CFG_DDR_SGMII_PHY_rpc20_TypeDef; 1343 1344 typedef union{ /*!< rpc21 register definition*/ 1345 __IO uint32_t rpc21; 1346 struct 1347 { 1348 __IO uint32_t bclk_sel_data :9; 1349 __I uint32_t reserved_01 :23; 1350 } bitfield; 1351 } CFG_DDR_SGMII_PHY_rpc21_TypeDef; 1352 1353 typedef union{ /*!< rpc22 register definition*/ 1354 __IO uint32_t rpc22; 1355 struct 1356 { 1357 __IO uint32_t bclk_sel_dq :3; 1358 __I uint32_t reserved_01 :29; 1359 } bitfield; 1360 } CFG_DDR_SGMII_PHY_rpc22_TypeDef; 1361 1362 typedef union{ /*!< rpc23 register definition*/ 1363 __IO uint32_t rpc23; 1364 struct 1365 { 1366 __IO uint32_t bclk_sel_dqsn :3; 1367 __I uint32_t reserved_01 :29; 1368 } bitfield; 1369 } CFG_DDR_SGMII_PHY_rpc23_TypeDef; 1370 1371 typedef union{ /*!< rpc24 register definition*/ 1372 __IO uint32_t rpc24; 1373 struct 1374 { 1375 __IO uint32_t bclk_sel_dqsp :3; 1376 __I uint32_t reserved_01 :29; 1377 } bitfield; 1378 } CFG_DDR_SGMII_PHY_rpc24_TypeDef; 1379 1380 typedef union{ /*!< rpc25 register definition*/ 1381 __IO uint32_t rpc25; 1382 struct 1383 { 1384 __IO uint32_t cdr_md_addcmd :2; 1385 __I uint32_t reserved_01 :30; 1386 } bitfield; 1387 } CFG_DDR_SGMII_PHY_rpc25_TypeDef; 1388 1389 typedef union{ /*!< rpc26 register definition*/ 1390 __IO uint32_t rpc26; 1391 struct 1392 { 1393 __IO uint32_t cdr_md_data :2; 1394 __I uint32_t reserved_01 :30; 1395 } bitfield; 1396 } CFG_DDR_SGMII_PHY_rpc26_TypeDef; 1397 1398 typedef union{ /*!< rpc27 register definition*/ 1399 __IO uint32_t rpc27; 1400 struct 1401 { 1402 __IO uint32_t clk_md_addcmd :3; 1403 __I uint32_t reserved_01 :29; 1404 } bitfield; 1405 } CFG_DDR_SGMII_PHY_rpc27_TypeDef; 1406 1407 typedef union{ /*!< rpc28 register definition*/ 1408 __IO uint32_t rpc28; 1409 struct 1410 { 1411 __IO uint32_t clk_sel_addcmd :12; 1412 __I uint32_t reserved_01 :20; 1413 } bitfield; 1414 } CFG_DDR_SGMII_PHY_rpc28_TypeDef; 1415 1416 typedef union{ /*!< rpc29 register definition*/ 1417 __IO uint32_t rpc29; 1418 struct 1419 { 1420 __IO uint32_t clk_sel_data :12; 1421 __I uint32_t reserved_01 :20; 1422 } bitfield; 1423 } CFG_DDR_SGMII_PHY_rpc29_TypeDef; 1424 1425 typedef union{ /*!< rpc30 register definition*/ 1426 __IO uint32_t rpc30; 1427 struct 1428 { 1429 __IO uint32_t code_sel_addcmd :2; 1430 __I uint32_t reserved_01 :30; 1431 } bitfield; 1432 } CFG_DDR_SGMII_PHY_rpc30_TypeDef; 1433 1434 typedef union{ /*!< rpc31 register definition*/ 1435 __IO uint32_t rpc31; 1436 struct 1437 { 1438 __IO uint32_t code_sel_data :2; 1439 __I uint32_t reserved_01 :30; 1440 } bitfield; 1441 } CFG_DDR_SGMII_PHY_rpc31_TypeDef; 1442 1443 typedef union{ /*!< rpc32 register definition*/ 1444 __IO uint32_t rpc32; 1445 struct 1446 { 1447 __IO uint32_t comp_addcmd :1; 1448 __I uint32_t reserved_01 :31; 1449 } bitfield; 1450 } CFG_DDR_SGMII_PHY_rpc32_TypeDef; 1451 1452 typedef union{ /*!< rpc33 register definition*/ 1453 __IO uint32_t rpc33; 1454 struct 1455 { 1456 __IO uint32_t comp_clkn :1; 1457 __I uint32_t reserved_01 :31; 1458 } bitfield; 1459 } CFG_DDR_SGMII_PHY_rpc33_TypeDef; 1460 1461 typedef union{ /*!< rpc34 register definition*/ 1462 __IO uint32_t rpc34; 1463 struct 1464 { 1465 __IO uint32_t comp_clkp :1; 1466 __I uint32_t reserved_01 :31; 1467 } bitfield; 1468 } CFG_DDR_SGMII_PHY_rpc34_TypeDef; 1469 1470 typedef union{ /*!< rpc35 register definition*/ 1471 __IO uint32_t rpc35; 1472 struct 1473 { 1474 __IO uint32_t comp_dq :1; 1475 __I uint32_t reserved_01 :31; 1476 } bitfield; 1477 } CFG_DDR_SGMII_PHY_rpc35_TypeDef; 1478 1479 typedef union{ /*!< rpc36 register definition*/ 1480 __IO uint32_t rpc36; 1481 struct 1482 { 1483 __IO uint32_t comp_dqsn :1; 1484 __I uint32_t reserved_01 :31; 1485 } bitfield; 1486 } CFG_DDR_SGMII_PHY_rpc36_TypeDef; 1487 1488 typedef union{ /*!< rpc37 register definition*/ 1489 __IO uint32_t rpc37; 1490 struct 1491 { 1492 __IO uint32_t comp_dqsp :1; 1493 __I uint32_t reserved_01 :31; 1494 } bitfield; 1495 } CFG_DDR_SGMII_PHY_rpc37_TypeDef; 1496 1497 typedef union{ /*!< rpc38 register definition*/ 1498 __IO uint32_t rpc38; 1499 struct 1500 { 1501 __IO uint32_t divclk_sel_addcmd :2; 1502 __I uint32_t reserved_01 :30; 1503 } bitfield; 1504 } CFG_DDR_SGMII_PHY_rpc38_TypeDef; 1505 1506 typedef union{ /*!< rpc39 register definition*/ 1507 __IO uint32_t rpc39; 1508 struct 1509 { 1510 __IO uint32_t divclk_sel_data :2; 1511 __I uint32_t reserved_01 :30; 1512 } bitfield; 1513 } CFG_DDR_SGMII_PHY_rpc39_TypeDef; 1514 1515 typedef union{ /*!< rpc40 register definition*/ 1516 __IO uint32_t rpc40; 1517 struct 1518 { 1519 __IO uint32_t div_addcmd :3; 1520 __I uint32_t reserved_01 :29; 1521 } bitfield; 1522 } CFG_DDR_SGMII_PHY_rpc40_TypeDef; 1523 1524 typedef union{ /*!< rpc41 register definition*/ 1525 __IO uint32_t rpc41; 1526 struct 1527 { 1528 __IO uint32_t div_data :3; 1529 __I uint32_t reserved_01 :29; 1530 } bitfield; 1531 } CFG_DDR_SGMII_PHY_rpc41_TypeDef; 1532 1533 typedef union{ /*!< rpc42 register definition*/ 1534 __IO uint32_t rpc42; 1535 struct 1536 { 1537 __IO uint32_t dly_md_addcmd :2; 1538 __I uint32_t reserved_01 :30; 1539 } bitfield; 1540 } CFG_DDR_SGMII_PHY_rpc42_TypeDef; 1541 1542 typedef union{ /*!< rpc43 register definition*/ 1543 __IO uint32_t rpc43; 1544 struct 1545 { 1546 __IO uint32_t dly_md_clkn :2; 1547 __I uint32_t reserved_01 :30; 1548 } bitfield; 1549 } CFG_DDR_SGMII_PHY_rpc43_TypeDef; 1550 1551 typedef union{ /*!< rpc44 register definition*/ 1552 __IO uint32_t rpc44; 1553 struct 1554 { 1555 __IO uint32_t dly_md_clkp :2; 1556 __I uint32_t reserved_01 :30; 1557 } bitfield; 1558 } CFG_DDR_SGMII_PHY_rpc44_TypeDef; 1559 1560 typedef union{ /*!< rpc45 register definition*/ 1561 __IO uint32_t rpc45; 1562 struct 1563 { 1564 __IO uint32_t dly_md_dq :2; 1565 __I uint32_t reserved_01 :30; 1566 } bitfield; 1567 } CFG_DDR_SGMII_PHY_rpc45_TypeDef; 1568 1569 typedef union{ /*!< rpc46 register definition*/ 1570 __IO uint32_t rpc46; 1571 struct 1572 { 1573 __IO uint32_t dly_md_dqsn :2; 1574 __I uint32_t reserved_01 :30; 1575 } bitfield; 1576 } CFG_DDR_SGMII_PHY_rpc46_TypeDef; 1577 1578 typedef union{ /*!< rpc47 register definition*/ 1579 __IO uint32_t rpc47; 1580 struct 1581 { 1582 __IO uint32_t dly_md_dqsp :2; 1583 __I uint32_t reserved_01 :30; 1584 } bitfield; 1585 } CFG_DDR_SGMII_PHY_rpc47_TypeDef; 1586 1587 typedef union{ /*!< rpc48 register definition*/ 1588 __IO uint32_t rpc48; 1589 struct 1590 { 1591 __IO uint32_t dqs_md_data :3; 1592 __I uint32_t reserved_01 :29; 1593 } bitfield; 1594 } CFG_DDR_SGMII_PHY_rpc48_TypeDef; 1595 1596 typedef union{ /*!< rpc49 register definition*/ 1597 __IO uint32_t rpc49; 1598 struct 1599 { 1600 __IO uint32_t dynen_addcmd :1; 1601 __I uint32_t reserved_01 :31; 1602 } bitfield; 1603 } CFG_DDR_SGMII_PHY_rpc49_TypeDef; 1604 1605 typedef union{ /*!< rpc50 register definition*/ 1606 __IO uint32_t rpc50; 1607 struct 1608 { 1609 __IO uint32_t dynen_data :1; 1610 __I uint32_t reserved_01 :31; 1611 } bitfield; 1612 } CFG_DDR_SGMII_PHY_rpc50_TypeDef; 1613 1614 typedef union{ /*!< rpc51 register definition*/ 1615 __IO uint32_t rpc51; 1616 struct 1617 { 1618 __IO uint32_t dynen_soft_reset_addcmd :1; 1619 __I uint32_t reserved_01 :31; 1620 } bitfield; 1621 } CFG_DDR_SGMII_PHY_rpc51_TypeDef; 1622 1623 typedef union{ /*!< rpc52 register definition*/ 1624 __IO uint32_t rpc52; 1625 struct 1626 { 1627 __IO uint32_t dynen_soft_reset_data :1; 1628 __I uint32_t reserved_01 :31; 1629 } bitfield; 1630 } CFG_DDR_SGMII_PHY_rpc52_TypeDef; 1631 1632 typedef union{ /*!< rpc53 register definition*/ 1633 __IO uint32_t rpc53; 1634 struct 1635 { 1636 __IO uint32_t edgedet_addcmd :1; 1637 __I uint32_t reserved_01 :31; 1638 } bitfield; 1639 } CFG_DDR_SGMII_PHY_rpc53_TypeDef; 1640 1641 typedef union{ /*!< rpc54 register definition*/ 1642 __IO uint32_t rpc54; 1643 struct 1644 { 1645 __IO uint32_t edgedet_clkn :1; 1646 __I uint32_t reserved_01 :31; 1647 } bitfield; 1648 } CFG_DDR_SGMII_PHY_rpc54_TypeDef; 1649 1650 typedef union{ /*!< rpc55 register definition*/ 1651 __IO uint32_t rpc55; 1652 struct 1653 { 1654 __IO uint32_t edgedet_clkp :1; 1655 __I uint32_t reserved_01 :31; 1656 } bitfield; 1657 } CFG_DDR_SGMII_PHY_rpc55_TypeDef; 1658 1659 typedef union{ /*!< rpc56 register definition*/ 1660 __IO uint32_t rpc56; 1661 struct 1662 { 1663 __IO uint32_t edgedet_dq :1; 1664 __I uint32_t reserved_01 :31; 1665 } bitfield; 1666 } CFG_DDR_SGMII_PHY_rpc56_TypeDef; 1667 1668 typedef union{ /*!< rpc57 register definition*/ 1669 __IO uint32_t rpc57; 1670 struct 1671 { 1672 __IO uint32_t edgedet_dqsn :1; 1673 __I uint32_t reserved_01 :31; 1674 } bitfield; 1675 } CFG_DDR_SGMII_PHY_rpc57_TypeDef; 1676 1677 typedef union{ /*!< rpc58 register definition*/ 1678 __IO uint32_t rpc58; 1679 struct 1680 { 1681 __IO uint32_t edgedet_dqsp :1; 1682 __I uint32_t reserved_01 :31; 1683 } bitfield; 1684 } CFG_DDR_SGMII_PHY_rpc58_TypeDef; 1685 1686 typedef union{ /*!< rpc59 register definition*/ 1687 __IO uint32_t rpc59; 1688 struct 1689 { 1690 __IO uint32_t eyewidth_addcmd :3; 1691 __I uint32_t reserved_01 :29; 1692 } bitfield; 1693 } CFG_DDR_SGMII_PHY_rpc59_TypeDef; 1694 1695 typedef union{ /*!< rpc60 register definition*/ 1696 __IO uint32_t rpc60; 1697 struct 1698 { 1699 __IO uint32_t eyewidth_clkn :3; 1700 __I uint32_t reserved_01 :29; 1701 } bitfield; 1702 } CFG_DDR_SGMII_PHY_rpc60_TypeDef; 1703 1704 typedef union{ /*!< rpc61 register definition*/ 1705 __IO uint32_t rpc61; 1706 struct 1707 { 1708 __IO uint32_t eyewidth_clkp :3; 1709 __I uint32_t reserved_01 :29; 1710 } bitfield; 1711 } CFG_DDR_SGMII_PHY_rpc61_TypeDef; 1712 1713 typedef union{ /*!< rpc62 register definition*/ 1714 __IO uint32_t rpc62; 1715 struct 1716 { 1717 __IO uint32_t eyewidth_dq :3; 1718 __I uint32_t reserved_01 :29; 1719 } bitfield; 1720 } CFG_DDR_SGMII_PHY_rpc62_TypeDef; 1721 1722 typedef union{ /*!< rpc63 register definition*/ 1723 __IO uint32_t rpc63; 1724 struct 1725 { 1726 __IO uint32_t eyewidth_dqsn :3; 1727 __I uint32_t reserved_01 :29; 1728 } bitfield; 1729 } CFG_DDR_SGMII_PHY_rpc63_TypeDef; 1730 1731 typedef union{ /*!< rpc64 register definition*/ 1732 __IO uint32_t rpc64; 1733 struct 1734 { 1735 __IO uint32_t eyewidth_dqsp :3; 1736 __I uint32_t reserved_01 :29; 1737 } bitfield; 1738 } CFG_DDR_SGMII_PHY_rpc64_TypeDef; 1739 1740 typedef union{ /*!< rpc65 register definition*/ 1741 __IO uint32_t rpc65; 1742 struct 1743 { 1744 __IO uint32_t eyewidth_sel_addcmd :1; 1745 __I uint32_t reserved_01 :31; 1746 } bitfield; 1747 } CFG_DDR_SGMII_PHY_rpc65_TypeDef; 1748 1749 typedef union{ /*!< rpc66 register definition*/ 1750 __IO uint32_t rpc66; 1751 struct 1752 { 1753 __IO uint32_t eyewidth_sel_clkn :1; 1754 __I uint32_t reserved_01 :31; 1755 } bitfield; 1756 } CFG_DDR_SGMII_PHY_rpc66_TypeDef; 1757 1758 typedef union{ /*!< rpc67 register definition*/ 1759 __IO uint32_t rpc67; 1760 struct 1761 { 1762 __IO uint32_t eyewidth_sel_clkp :1; 1763 __I uint32_t reserved_01 :31; 1764 } bitfield; 1765 } CFG_DDR_SGMII_PHY_rpc67_TypeDef; 1766 1767 typedef union{ /*!< rpc68 register definition*/ 1768 __IO uint32_t rpc68; 1769 struct 1770 { 1771 __IO uint32_t eyewidth_sel_dq :1; 1772 __I uint32_t reserved_01 :31; 1773 } bitfield; 1774 } CFG_DDR_SGMII_PHY_rpc68_TypeDef; 1775 1776 typedef union{ /*!< rpc69 register definition*/ 1777 __IO uint32_t rpc69; 1778 struct 1779 { 1780 __IO uint32_t eyewidth_sel_dqsn :1; 1781 __I uint32_t reserved_01 :31; 1782 } bitfield; 1783 } CFG_DDR_SGMII_PHY_rpc69_TypeDef; 1784 1785 typedef union{ /*!< rpc70 register definition*/ 1786 __IO uint32_t rpc70; 1787 struct 1788 { 1789 __IO uint32_t eyewidth_sel_dqsp :1; 1790 __I uint32_t reserved_01 :31; 1791 } bitfield; 1792 } CFG_DDR_SGMII_PHY_rpc70_TypeDef; 1793 1794 typedef union{ /*!< rpc71 register definition*/ 1795 __IO uint32_t rpc71; 1796 struct 1797 { 1798 __IO uint32_t eye_en_addcmd :1; 1799 __I uint32_t reserved_01 :31; 1800 } bitfield; 1801 } CFG_DDR_SGMII_PHY_rpc71_TypeDef; 1802 1803 typedef union{ /*!< rpc72 register definition*/ 1804 __IO uint32_t rpc72; 1805 struct 1806 { 1807 __IO uint32_t eye_en_clkn :1; 1808 __I uint32_t reserved_01 :31; 1809 } bitfield; 1810 } CFG_DDR_SGMII_PHY_rpc72_TypeDef; 1811 1812 typedef union{ /*!< rpc73 register definition*/ 1813 __IO uint32_t rpc73; 1814 struct 1815 { 1816 __IO uint32_t eye_en_clkp :1; 1817 __I uint32_t reserved_01 :31; 1818 } bitfield; 1819 } CFG_DDR_SGMII_PHY_rpc73_TypeDef; 1820 1821 typedef union{ /*!< rpc74 register definition*/ 1822 __IO uint32_t rpc74; 1823 struct 1824 { 1825 __IO uint32_t eye_en_dq :1; 1826 __I uint32_t reserved_01 :31; 1827 } bitfield; 1828 } CFG_DDR_SGMII_PHY_rpc74_TypeDef; 1829 1830 typedef union{ /*!< rpc75 register definition*/ 1831 __IO uint32_t rpc75; 1832 struct 1833 { 1834 __IO uint32_t eye_en_dqsn :1; 1835 __I uint32_t reserved_01 :31; 1836 } bitfield; 1837 } CFG_DDR_SGMII_PHY_rpc75_TypeDef; 1838 1839 typedef union{ /*!< rpc76 register definition*/ 1840 __IO uint32_t rpc76; 1841 struct 1842 { 1843 __IO uint32_t eye_en_dqsp :1; 1844 __I uint32_t reserved_01 :31; 1845 } bitfield; 1846 } CFG_DDR_SGMII_PHY_rpc76_TypeDef; 1847 1848 typedef union{ /*!< rpc77 register definition*/ 1849 __IO uint32_t rpc77; 1850 struct 1851 { 1852 __IO uint32_t eye_sdr_addcmd :1; 1853 __I uint32_t reserved_01 :31; 1854 } bitfield; 1855 } CFG_DDR_SGMII_PHY_rpc77_TypeDef; 1856 1857 typedef union{ /*!< rpc78 register definition*/ 1858 __IO uint32_t rpc78; 1859 struct 1860 { 1861 __IO uint32_t eye_sdr_clkn :1; 1862 __I uint32_t reserved_01 :31; 1863 } bitfield; 1864 } CFG_DDR_SGMII_PHY_rpc78_TypeDef; 1865 1866 typedef union{ /*!< rpc79 register definition*/ 1867 __IO uint32_t rpc79; 1868 struct 1869 { 1870 __IO uint32_t eye_sdr_clkp :1; 1871 __I uint32_t reserved_01 :31; 1872 } bitfield; 1873 } CFG_DDR_SGMII_PHY_rpc79_TypeDef; 1874 1875 typedef union{ /*!< rpc80 register definition*/ 1876 __IO uint32_t rpc80; 1877 struct 1878 { 1879 __IO uint32_t eye_sdr_dq :1; 1880 __I uint32_t reserved_01 :31; 1881 } bitfield; 1882 } CFG_DDR_SGMII_PHY_rpc80_TypeDef; 1883 1884 typedef union{ /*!< rpc81 register definition*/ 1885 __IO uint32_t rpc81; 1886 struct 1887 { 1888 __IO uint32_t eye_sdr_dqsn :1; 1889 __I uint32_t reserved_01 :31; 1890 } bitfield; 1891 } CFG_DDR_SGMII_PHY_rpc81_TypeDef; 1892 1893 typedef union{ /*!< rpc82 register definition*/ 1894 __IO uint32_t rpc82; 1895 struct 1896 { 1897 __IO uint32_t eye_sdr_dqsp :1; 1898 __I uint32_t reserved_01 :31; 1899 } bitfield; 1900 } CFG_DDR_SGMII_PHY_rpc82_TypeDef; 1901 1902 typedef union{ /*!< rpc83 register definition*/ 1903 __IO uint32_t rpc83; 1904 struct 1905 { 1906 __IO uint32_t fifowe_addcmd :1; 1907 __I uint32_t reserved_01 :31; 1908 } bitfield; 1909 } CFG_DDR_SGMII_PHY_rpc83_TypeDef; 1910 1911 typedef union{ /*!< rpc84 register definition*/ 1912 __IO uint32_t rpc84; 1913 struct 1914 { 1915 __IO uint32_t fifowe_clkn :1; 1916 __I uint32_t reserved_01 :31; 1917 } bitfield; 1918 } CFG_DDR_SGMII_PHY_rpc84_TypeDef; 1919 1920 typedef union{ /*!< rpc85 register definition*/ 1921 __IO uint32_t rpc85; 1922 struct 1923 { 1924 __IO uint32_t fifowe_clkp :1; 1925 __I uint32_t reserved_01 :31; 1926 } bitfield; 1927 } CFG_DDR_SGMII_PHY_rpc85_TypeDef; 1928 1929 typedef union{ /*!< rpc86 register definition*/ 1930 __IO uint32_t rpc86; 1931 struct 1932 { 1933 __IO uint32_t fifowe_dq :1; 1934 __I uint32_t reserved_01 :31; 1935 } bitfield; 1936 } CFG_DDR_SGMII_PHY_rpc86_TypeDef; 1937 1938 typedef union{ /*!< rpc87 register definition*/ 1939 __IO uint32_t rpc87; 1940 struct 1941 { 1942 __IO uint32_t fifowe_dqsn :1; 1943 __I uint32_t reserved_01 :31; 1944 } bitfield; 1945 } CFG_DDR_SGMII_PHY_rpc87_TypeDef; 1946 1947 typedef union{ /*!< rpc88 register definition*/ 1948 __IO uint32_t rpc88; 1949 struct 1950 { 1951 __IO uint32_t fifowe_dqsp :1; 1952 __I uint32_t reserved_01 :31; 1953 } bitfield; 1954 } CFG_DDR_SGMII_PHY_rpc88_TypeDef; 1955 1956 typedef union{ /*!< rpc89 register definition*/ 1957 __IO uint32_t rpc89; 1958 struct 1959 { 1960 __IO uint32_t fifo_en_addcmd :1; 1961 __I uint32_t reserved_01 :31; 1962 } bitfield; 1963 } CFG_DDR_SGMII_PHY_rpc89_TypeDef; 1964 1965 typedef union{ /*!< rpc90 register definition*/ 1966 __IO uint32_t rpc90; 1967 struct 1968 { 1969 __IO uint32_t fifo_en_data :1; 1970 __I uint32_t reserved_01 :31; 1971 } bitfield; 1972 } CFG_DDR_SGMII_PHY_rpc90_TypeDef; 1973 1974 typedef union{ /*!< rpc91 register definition*/ 1975 __IO uint32_t rpc91; 1976 struct 1977 { 1978 __IO uint32_t fifo_run_addcmd :1; 1979 __I uint32_t reserved_01 :31; 1980 } bitfield; 1981 } CFG_DDR_SGMII_PHY_rpc91_TypeDef; 1982 1983 typedef union{ /*!< rpc92 register definition*/ 1984 __IO uint32_t rpc92; 1985 struct 1986 { 1987 __IO uint32_t fifo_run_data :1; 1988 __I uint32_t reserved_01 :31; 1989 } bitfield; 1990 } CFG_DDR_SGMII_PHY_rpc92_TypeDef; 1991 1992 typedef union{ /*!< rpc93 register definition*/ 1993 __IO uint32_t rpc93; 1994 struct 1995 { 1996 __IO uint32_t gsr_disable_addcmd :1; 1997 __I uint32_t reserved_01 :31; 1998 } bitfield; 1999 } CFG_DDR_SGMII_PHY_rpc93_TypeDef; 2000 2001 typedef union{ /*!< rpc94 register definition*/ 2002 __IO uint32_t rpc94; 2003 struct 2004 { 2005 __IO uint32_t gsr_disable_data :1; 2006 __I uint32_t reserved_01 :31; 2007 } bitfield; 2008 } CFG_DDR_SGMII_PHY_rpc94_TypeDef; 2009 2010 typedef union{ /*!< rpc95 register definition*/ 2011 __IO uint32_t rpc95; 2012 struct 2013 { 2014 __IO uint32_t ibufmd_addcmd :3; 2015 __I uint32_t reserved_01 :29; 2016 } bitfield; 2017 } CFG_DDR_SGMII_PHY_rpc95_TypeDef; 2018 2019 typedef union{ /*!< rpc96 register definition*/ 2020 __IO uint32_t rpc96; 2021 struct 2022 { 2023 __IO uint32_t ibufmd_clk :3; 2024 __I uint32_t reserved_01 :29; 2025 } bitfield; 2026 } CFG_DDR_SGMII_PHY_rpc96_TypeDef; 2027 2028 typedef union{ /*!< rpc97 register definition*/ 2029 __IO uint32_t rpc97; 2030 struct 2031 { 2032 __IO uint32_t ibufmd_dq :3; 2033 __I uint32_t reserved_01 :29; 2034 } bitfield; 2035 } CFG_DDR_SGMII_PHY_rpc97_TypeDef; 2036 2037 typedef union{ /*!< rpc98 register definition*/ 2038 __IO uint32_t rpc98; 2039 struct 2040 { 2041 __IO uint32_t ibufmd_dqs :3; 2042 __I uint32_t reserved_01 :29; 2043 } bitfield; 2044 } CFG_DDR_SGMII_PHY_rpc98_TypeDef; 2045 2046 typedef union{ /*!< rpc99 register definition*/ 2047 __IO uint32_t rpc99; 2048 struct 2049 { 2050 __IO uint32_t indly_sel_addcmd :2; 2051 __I uint32_t reserved_01 :30; 2052 } bitfield; 2053 } CFG_DDR_SGMII_PHY_rpc99_TypeDef; 2054 2055 typedef union{ /*!< rpc100 register definition*/ 2056 __IO uint32_t rpc100; 2057 struct 2058 { 2059 __IO uint32_t indly_sel_clkn :2; 2060 __I uint32_t reserved_01 :30; 2061 } bitfield; 2062 } CFG_DDR_SGMII_PHY_rpc100_TypeDef; 2063 2064 typedef union{ /*!< rpc101 register definition*/ 2065 __IO uint32_t rpc101; 2066 struct 2067 { 2068 __IO uint32_t indly_sel_clkp :2; 2069 __I uint32_t reserved_01 :30; 2070 } bitfield; 2071 } CFG_DDR_SGMII_PHY_rpc101_TypeDef; 2072 2073 typedef union{ /*!< rpc102 register definition*/ 2074 __IO uint32_t rpc102; 2075 struct 2076 { 2077 __IO uint32_t indly_sel_dq :2; 2078 __I uint32_t reserved_01 :30; 2079 } bitfield; 2080 } CFG_DDR_SGMII_PHY_rpc102_TypeDef; 2081 2082 typedef union{ /*!< rpc103 register definition*/ 2083 __IO uint32_t rpc103; 2084 struct 2085 { 2086 __IO uint32_t indly_sel_dqsn :2; 2087 __I uint32_t reserved_01 :30; 2088 } bitfield; 2089 } CFG_DDR_SGMII_PHY_rpc103_TypeDef; 2090 2091 typedef union{ /*!< rpc104 register definition*/ 2092 __IO uint32_t rpc104; 2093 struct 2094 { 2095 __IO uint32_t indly_sel_dqsp :2; 2096 __I uint32_t reserved_01 :30; 2097 } bitfield; 2098 } CFG_DDR_SGMII_PHY_rpc104_TypeDef; 2099 2100 typedef union{ /*!< rpc105 register definition*/ 2101 __IO uint32_t rpc105; 2102 struct 2103 { 2104 __IO uint32_t lane_pvt_addcmd :1; 2105 __I uint32_t reserved_01 :31; 2106 } bitfield; 2107 } CFG_DDR_SGMII_PHY_rpc105_TypeDef; 2108 2109 typedef union{ /*!< rpc106 register definition*/ 2110 __IO uint32_t rpc106; 2111 struct 2112 { 2113 __IO uint32_t lane_pvt_data :1; 2114 __I uint32_t reserved_01 :31; 2115 } bitfield; 2116 } CFG_DDR_SGMII_PHY_rpc106_TypeDef; 2117 2118 typedef union{ /*!< rpc107 register definition*/ 2119 __IO uint32_t rpc107; 2120 struct 2121 { 2122 __IO uint32_t lsr_disable_addcmd :1; 2123 __I uint32_t reserved_01 :31; 2124 } bitfield; 2125 } CFG_DDR_SGMII_PHY_rpc107_TypeDef; 2126 2127 typedef union{ /*!< rpc108 register definition*/ 2128 __IO uint32_t rpc108; 2129 struct 2130 { 2131 __IO uint32_t lsr_disable_clkn :1; 2132 __I uint32_t reserved_01 :31; 2133 } bitfield; 2134 } CFG_DDR_SGMII_PHY_rpc108_TypeDef; 2135 2136 typedef union{ /*!< rpc109 register definition*/ 2137 __IO uint32_t rpc109; 2138 struct 2139 { 2140 __IO uint32_t lsr_disable_clkp :1; 2141 __I uint32_t reserved_01 :31; 2142 } bitfield; 2143 } CFG_DDR_SGMII_PHY_rpc109_TypeDef; 2144 2145 typedef union{ /*!< rpc110 register definition*/ 2146 __IO uint32_t rpc110; 2147 struct 2148 { 2149 __IO uint32_t lsr_disable_dq :1; 2150 __I uint32_t reserved_01 :31; 2151 } bitfield; 2152 } CFG_DDR_SGMII_PHY_rpc110_TypeDef; 2153 2154 typedef union{ /*!< rpc111 register definition*/ 2155 __IO uint32_t rpc111; 2156 struct 2157 { 2158 __IO uint32_t lsr_disable_dqsn :1; 2159 __I uint32_t reserved_01 :31; 2160 } bitfield; 2161 } CFG_DDR_SGMII_PHY_rpc111_TypeDef; 2162 2163 typedef union{ /*!< rpc112 register definition*/ 2164 __IO uint32_t rpc112; 2165 struct 2166 { 2167 __IO uint32_t lsr_disable_dqsp :1; 2168 __I uint32_t reserved_01 :31; 2169 } bitfield; 2170 } CFG_DDR_SGMII_PHY_rpc112_TypeDef; 2171 2172 typedef union{ /*!< rpc113 register definition*/ 2173 __IO uint32_t rpc113; 2174 struct 2175 { 2176 __IO uint32_t mvdly_en_addcmd :1; 2177 __I uint32_t reserved_01 :31; 2178 } bitfield; 2179 } CFG_DDR_SGMII_PHY_rpc113_TypeDef; 2180 2181 typedef union{ /*!< rpc114 register definition*/ 2182 __IO uint32_t rpc114; 2183 struct 2184 { 2185 __IO uint32_t mvdly_en_clkn :1; 2186 __I uint32_t reserved_01 :31; 2187 } bitfield; 2188 } CFG_DDR_SGMII_PHY_rpc114_TypeDef; 2189 2190 typedef union{ /*!< rpc115 register definition*/ 2191 __IO uint32_t rpc115; 2192 struct 2193 { 2194 __IO uint32_t mvdly_en_clkp :1; 2195 __I uint32_t reserved_01 :31; 2196 } bitfield; 2197 } CFG_DDR_SGMII_PHY_rpc115_TypeDef; 2198 2199 typedef union{ /*!< rpc116 register definition*/ 2200 __IO uint32_t rpc116; 2201 struct 2202 { 2203 __IO uint32_t mvdly_en_dq :1; 2204 __I uint32_t reserved_01 :31; 2205 } bitfield; 2206 } CFG_DDR_SGMII_PHY_rpc116_TypeDef; 2207 2208 typedef union{ /*!< rpc117 register definition*/ 2209 __IO uint32_t rpc117; 2210 struct 2211 { 2212 __IO uint32_t mvdly_en_dqsn :1; 2213 __I uint32_t reserved_01 :31; 2214 } bitfield; 2215 } CFG_DDR_SGMII_PHY_rpc117_TypeDef; 2216 2217 typedef union{ /*!< rpc118 register definition*/ 2218 __IO uint32_t rpc118; 2219 struct 2220 { 2221 __IO uint32_t mvdly_en_dqsp :1; 2222 __I uint32_t reserved_01 :31; 2223 } bitfield; 2224 } CFG_DDR_SGMII_PHY_rpc118_TypeDef; 2225 2226 typedef union{ /*!< rpc119 register definition*/ 2227 __IO uint32_t rpc119; 2228 struct 2229 { 2230 __IO uint32_t oeclk_inv_addcmd :1; 2231 __I uint32_t reserved_01 :31; 2232 } bitfield; 2233 } CFG_DDR_SGMII_PHY_rpc119_TypeDef; 2234 2235 typedef union{ /*!< rpc120 register definition*/ 2236 __IO uint32_t rpc120; 2237 struct 2238 { 2239 __IO uint32_t oeclk_inv_clkn :1; 2240 __I uint32_t reserved_01 :31; 2241 } bitfield; 2242 } CFG_DDR_SGMII_PHY_rpc120_TypeDef; 2243 2244 typedef union{ /*!< rpc121 register definition*/ 2245 __IO uint32_t rpc121; 2246 struct 2247 { 2248 __IO uint32_t oeclk_inv_clkp :1; 2249 __I uint32_t reserved_01 :31; 2250 } bitfield; 2251 } CFG_DDR_SGMII_PHY_rpc121_TypeDef; 2252 2253 typedef union{ /*!< rpc122 register definition*/ 2254 __IO uint32_t rpc122; 2255 struct 2256 { 2257 __IO uint32_t oeclk_inv_dq :1; 2258 __I uint32_t reserved_01 :31; 2259 } bitfield; 2260 } CFG_DDR_SGMII_PHY_rpc122_TypeDef; 2261 2262 typedef union{ /*!< rpc123 register definition*/ 2263 __IO uint32_t rpc123; 2264 struct 2265 { 2266 __IO uint32_t oeclk_inv_dqsn :1; 2267 __I uint32_t reserved_01 :31; 2268 } bitfield; 2269 } CFG_DDR_SGMII_PHY_rpc123_TypeDef; 2270 2271 typedef union{ /*!< rpc124 register definition*/ 2272 __IO uint32_t rpc124; 2273 struct 2274 { 2275 __IO uint32_t oeclk_inv_dqsp :1; 2276 __I uint32_t reserved_01 :31; 2277 } bitfield; 2278 } CFG_DDR_SGMII_PHY_rpc124_TypeDef; 2279 2280 typedef union{ /*!< rpc125 register definition*/ 2281 __IO uint32_t rpc125; 2282 struct 2283 { 2284 __IO uint32_t oe_md_addcmd :3; 2285 __I uint32_t reserved_01 :29; 2286 } bitfield; 2287 } CFG_DDR_SGMII_PHY_rpc125_TypeDef; 2288 2289 typedef union{ /*!< rpc126 register definition*/ 2290 __IO uint32_t rpc126; 2291 struct 2292 { 2293 __IO uint32_t oe_md_clkn :3; 2294 __I uint32_t reserved_01 :29; 2295 } bitfield; 2296 } CFG_DDR_SGMII_PHY_rpc126_TypeDef; 2297 2298 typedef union{ /*!< rpc127 register definition*/ 2299 __IO uint32_t rpc127; 2300 struct 2301 { 2302 __IO uint32_t oe_md_clkp :3; 2303 __I uint32_t reserved_01 :29; 2304 } bitfield; 2305 } CFG_DDR_SGMII_PHY_rpc127_TypeDef; 2306 2307 typedef union{ /*!< rpc128 register definition*/ 2308 __IO uint32_t rpc128; 2309 struct 2310 { 2311 __IO uint32_t oe_md_dq :3; 2312 __I uint32_t reserved_01 :29; 2313 } bitfield; 2314 } CFG_DDR_SGMII_PHY_rpc128_TypeDef; 2315 2316 typedef union{ /*!< rpc129 register definition*/ 2317 __IO uint32_t rpc129; 2318 struct 2319 { 2320 __IO uint32_t oe_md_dqsn :3; 2321 __I uint32_t reserved_01 :29; 2322 } bitfield; 2323 } CFG_DDR_SGMII_PHY_rpc129_TypeDef; 2324 2325 typedef union{ /*!< rpc130 register definition*/ 2326 __IO uint32_t rpc130; 2327 struct 2328 { 2329 __IO uint32_t oe_md_dqsp :3; 2330 __I uint32_t reserved_01 :29; 2331 } bitfield; 2332 } CFG_DDR_SGMII_PHY_rpc130_TypeDef; 2333 2334 typedef union{ /*!< rpc131 register definition*/ 2335 __IO uint32_t rpc131; 2336 struct 2337 { 2338 __IO uint32_t pause_en_addcmd :1; 2339 __I uint32_t reserved_01 :31; 2340 } bitfield; 2341 } CFG_DDR_SGMII_PHY_rpc131_TypeDef; 2342 2343 typedef union{ /*!< rpc132 register definition*/ 2344 __IO uint32_t rpc132; 2345 struct 2346 { 2347 __IO uint32_t pause_en_data :1; 2348 __I uint32_t reserved_01 :31; 2349 } bitfield; 2350 } CFG_DDR_SGMII_PHY_rpc132_TypeDef; 2351 2352 typedef union{ /*!< rpc133 register definition*/ 2353 __IO uint32_t rpc133; 2354 struct 2355 { 2356 __IO uint32_t qdr_addcmd :1; 2357 __I uint32_t reserved_01 :31; 2358 } bitfield; 2359 } CFG_DDR_SGMII_PHY_rpc133_TypeDef; 2360 2361 typedef union{ /*!< rpc134 register definition*/ 2362 __IO uint32_t rpc134; 2363 struct 2364 { 2365 __IO uint32_t qdr_data :1; 2366 __I uint32_t reserved_01 :31; 2367 } bitfield; 2368 } CFG_DDR_SGMII_PHY_rpc134_TypeDef; 2369 2370 typedef union{ /*!< rpc135 register definition*/ 2371 __IO uint32_t rpc135; 2372 struct 2373 { 2374 __IO uint32_t qdr_md_addcmd :1; 2375 __I uint32_t reserved_01 :31; 2376 } bitfield; 2377 } CFG_DDR_SGMII_PHY_rpc135_TypeDef; 2378 2379 typedef union{ /*!< rpc136 register definition*/ 2380 __IO uint32_t rpc136; 2381 struct 2382 { 2383 __IO uint32_t qdr_md_clkn :1; 2384 __I uint32_t reserved_01 :31; 2385 } bitfield; 2386 } CFG_DDR_SGMII_PHY_rpc136_TypeDef; 2387 2388 typedef union{ /*!< rpc137 register definition*/ 2389 __IO uint32_t rpc137; 2390 struct 2391 { 2392 __IO uint32_t qdr_md_clkp :1; 2393 __I uint32_t reserved_01 :31; 2394 } bitfield; 2395 } CFG_DDR_SGMII_PHY_rpc137_TypeDef; 2396 2397 typedef union{ /*!< rpc138 register definition*/ 2398 __IO uint32_t rpc138; 2399 struct 2400 { 2401 __IO uint32_t qdr_md_dq :1; 2402 __I uint32_t reserved_01 :31; 2403 } bitfield; 2404 } CFG_DDR_SGMII_PHY_rpc138_TypeDef; 2405 2406 typedef union{ /*!< rpc139 register definition*/ 2407 __IO uint32_t rpc139; 2408 struct 2409 { 2410 __IO uint32_t qdr_md_dqsn :1; 2411 __I uint32_t reserved_01 :31; 2412 } bitfield; 2413 } CFG_DDR_SGMII_PHY_rpc139_TypeDef; 2414 2415 typedef union{ /*!< rpc140 register definition*/ 2416 __IO uint32_t rpc140; 2417 struct 2418 { 2419 __IO uint32_t qdr_md_dqsp :1; 2420 __I uint32_t reserved_01 :31; 2421 } bitfield; 2422 } CFG_DDR_SGMII_PHY_rpc140_TypeDef; 2423 2424 typedef union{ /*!< rpc141 register definition*/ 2425 __IO uint32_t rpc141; 2426 struct 2427 { 2428 __IO uint32_t rank2_addcmd :1; 2429 __I uint32_t reserved_01 :31; 2430 } bitfield; 2431 } CFG_DDR_SGMII_PHY_rpc141_TypeDef; 2432 2433 typedef union{ /*!< rpc142 register definition*/ 2434 __IO uint32_t rpc142; 2435 struct 2436 { 2437 __IO uint32_t rank2_data :1; 2438 __I uint32_t reserved_01 :31; 2439 } bitfield; 2440 } CFG_DDR_SGMII_PHY_rpc142_TypeDef; 2441 2442 typedef union{ /*!< rpc143 register definition*/ 2443 __IO uint32_t rpc143; 2444 struct 2445 { 2446 __IO uint32_t rst_inv_addcmd :1; 2447 __I uint32_t reserved_01 :31; 2448 } bitfield; 2449 } CFG_DDR_SGMII_PHY_rpc143_TypeDef; 2450 2451 typedef union{ /*!< rpc144 register definition*/ 2452 __IO uint32_t rpc144; 2453 struct 2454 { 2455 __IO uint32_t rst_inv_data :1; 2456 __I uint32_t reserved_01 :31; 2457 } bitfield; 2458 } CFG_DDR_SGMII_PHY_rpc144_TypeDef; 2459 2460 typedef union{ /*!< rpc145 register definition*/ 2461 __IO uint32_t rpc145; 2462 struct 2463 { 2464 __IO uint32_t rxdly_addcmd :7; 2465 __I uint32_t reserved_01 :25; 2466 } bitfield; 2467 } CFG_DDR_SGMII_PHY_rpc145_TypeDef; 2468 2469 typedef union{ /*!< rpc146 register definition*/ 2470 __IO uint32_t rpc146; 2471 struct 2472 { 2473 __IO uint32_t rxdly_clkn :7; 2474 __I uint32_t reserved_01 :25; 2475 } bitfield; 2476 } CFG_DDR_SGMII_PHY_rpc146_TypeDef; 2477 2478 typedef union{ /*!< rpc147 register definition*/ 2479 __IO uint32_t rpc147; 2480 struct 2481 { 2482 __IO uint32_t rxdly_clkp :7; 2483 __I uint32_t reserved_01 :25; 2484 } bitfield; 2485 } CFG_DDR_SGMII_PHY_rpc147_TypeDef; 2486 2487 typedef union{ /*!< rpc148 register definition*/ 2488 __IO uint32_t rpc148; 2489 struct 2490 { 2491 __IO uint32_t rxdly_dir_addcmd :1; 2492 __I uint32_t reserved_01 :31; 2493 } bitfield; 2494 } CFG_DDR_SGMII_PHY_rpc148_TypeDef; 2495 2496 typedef union{ /*!< rpc149 register definition*/ 2497 __IO uint32_t rpc149; 2498 struct 2499 { 2500 __IO uint32_t rxdly_dir_data :1; 2501 __I uint32_t reserved_01 :31; 2502 } bitfield; 2503 } CFG_DDR_SGMII_PHY_rpc149_TypeDef; 2504 2505 typedef union{ /*!< rpc150 register definition*/ 2506 __IO uint32_t rpc150; 2507 struct 2508 { 2509 __IO uint32_t rxdly_dq :7; 2510 __I uint32_t reserved_01 :25; 2511 } bitfield; 2512 } CFG_DDR_SGMII_PHY_rpc150_TypeDef; 2513 2514 typedef union{ /*!< rpc151 register definition*/ 2515 __IO uint32_t rpc151; 2516 struct 2517 { 2518 __IO uint32_t rxdly_dqsn :7; 2519 __I uint32_t reserved_01 :25; 2520 } bitfield; 2521 } CFG_DDR_SGMII_PHY_rpc151_TypeDef; 2522 2523 typedef union{ /*!< rpc152 register definition*/ 2524 __IO uint32_t rpc152; 2525 struct 2526 { 2527 __IO uint32_t rxdly_dqsp :7; 2528 __I uint32_t reserved_01 :25; 2529 } bitfield; 2530 } CFG_DDR_SGMII_PHY_rpc152_TypeDef; 2531 2532 typedef union{ /*!< rpc153 register definition*/ 2533 __IO uint32_t rpc153; 2534 struct 2535 { 2536 __IO uint32_t rxdly_en_addcmd :1; 2537 __I uint32_t reserved_01 :31; 2538 } bitfield; 2539 } CFG_DDR_SGMII_PHY_rpc153_TypeDef; 2540 2541 typedef union{ /*!< rpc154 register definition*/ 2542 __IO uint32_t rpc154; 2543 struct 2544 { 2545 __IO uint32_t rxdly_en_data :1; 2546 __I uint32_t reserved_01 :31; 2547 } bitfield; 2548 } CFG_DDR_SGMII_PHY_rpc154_TypeDef; 2549 2550 typedef union{ /*!< rpc155 register definition*/ 2551 __IO uint32_t rpc155; 2552 struct 2553 { 2554 __IO uint32_t rxdly_offset_addcmd :8; 2555 __I uint32_t reserved_01 :24; 2556 } bitfield; 2557 } CFG_DDR_SGMII_PHY_rpc155_TypeDef; 2558 2559 typedef union{ /*!< rpc156 register definition*/ 2560 __IO uint32_t rpc156; 2561 struct 2562 { 2563 __IO uint32_t rxdly_offset_data :8; 2564 __I uint32_t reserved_01 :24; 2565 } bitfield; 2566 } CFG_DDR_SGMII_PHY_rpc156_TypeDef; 2567 2568 typedef union{ /*!< rpc157 register definition*/ 2569 __IO uint32_t rpc157; 2570 struct 2571 { 2572 __IO uint32_t rxdly_wide_addcmd :1; 2573 __I uint32_t reserved_01 :31; 2574 } bitfield; 2575 } CFG_DDR_SGMII_PHY_rpc157_TypeDef; 2576 2577 typedef union{ /*!< rpc158 register definition*/ 2578 __IO uint32_t rpc158; 2579 struct 2580 { 2581 __IO uint32_t rxdly_wide_clkn :1; 2582 __I uint32_t reserved_01 :31; 2583 } bitfield; 2584 } CFG_DDR_SGMII_PHY_rpc158_TypeDef; 2585 2586 typedef union{ /*!< rpc159 register definition*/ 2587 __IO uint32_t rpc159; 2588 struct 2589 { 2590 __IO uint32_t rxdly_wide_clkp :1; 2591 __I uint32_t reserved_01 :31; 2592 } bitfield; 2593 } CFG_DDR_SGMII_PHY_rpc159_TypeDef; 2594 2595 typedef union{ /*!< rpc160 register definition*/ 2596 __IO uint32_t rpc160; 2597 struct 2598 { 2599 __IO uint32_t rxdly_wide_dq :1; 2600 __I uint32_t reserved_01 :31; 2601 } bitfield; 2602 } CFG_DDR_SGMII_PHY_rpc160_TypeDef; 2603 2604 typedef union{ /*!< rpc161 register definition*/ 2605 __IO uint32_t rpc161; 2606 struct 2607 { 2608 __IO uint32_t rxdly_wide_dqsn :1; 2609 __I uint32_t reserved_01 :31; 2610 } bitfield; 2611 } CFG_DDR_SGMII_PHY_rpc161_TypeDef; 2612 2613 typedef union{ /*!< rpc162 register definition*/ 2614 __IO uint32_t rpc162; 2615 struct 2616 { 2617 __IO uint32_t rxdly_wide_dqsp :1; 2618 __I uint32_t reserved_01 :31; 2619 } bitfield; 2620 } CFG_DDR_SGMII_PHY_rpc162_TypeDef; 2621 2622 typedef union{ /*!< rpc163 register definition*/ 2623 __IO uint32_t rpc163; 2624 struct 2625 { 2626 __IO uint32_t rxmvdly_en_addcmd :1; 2627 __I uint32_t reserved_01 :31; 2628 } bitfield; 2629 } CFG_DDR_SGMII_PHY_rpc163_TypeDef; 2630 2631 typedef union{ /*!< rpc164 register definition*/ 2632 __IO uint32_t rpc164; 2633 struct 2634 { 2635 __IO uint32_t rxmvdly_en_data :1; 2636 __I uint32_t reserved_01 :31; 2637 } bitfield; 2638 } CFG_DDR_SGMII_PHY_rpc164_TypeDef; 2639 2640 typedef union{ /*!< rpc165 register definition*/ 2641 __IO uint32_t rpc165; 2642 struct 2643 { 2644 __IO uint32_t rxptr_addcmd :3; 2645 __I uint32_t reserved_01 :29; 2646 } bitfield; 2647 } CFG_DDR_SGMII_PHY_rpc165_TypeDef; 2648 2649 typedef union{ /*!< rpc166 register definition*/ 2650 __IO uint32_t rpc166; 2651 struct 2652 { 2653 __IO uint32_t rxptr_data :3; 2654 __I uint32_t reserved_01 :29; 2655 } bitfield; 2656 } CFG_DDR_SGMII_PHY_rpc166_TypeDef; 2657 2658 typedef union{ /*!< rpc167 register definition*/ 2659 __IO uint32_t rpc167; 2660 struct 2661 { 2662 __IO uint32_t rx_md_addcmd :4; 2663 __I uint32_t reserved_01 :28; 2664 } bitfield; 2665 } CFG_DDR_SGMII_PHY_rpc167_TypeDef; 2666 2667 typedef union{ /*!< rpc168 register definition*/ 2668 __IO uint32_t rpc168; 2669 struct 2670 { 2671 __IO uint32_t rx_md_clkn :4; 2672 __I uint32_t reserved_01 :28; 2673 } bitfield; 2674 } CFG_DDR_SGMII_PHY_rpc168_TypeDef; 2675 2676 typedef union{ /*!< rpc169 register definition*/ 2677 __IO uint32_t rpc169; 2678 struct 2679 { 2680 __IO uint32_t rx_md_clkp :4; 2681 __I uint32_t reserved_01 :28; 2682 } bitfield; 2683 } CFG_DDR_SGMII_PHY_rpc169_TypeDef; 2684 2685 typedef union{ /*!< rpc170 register definition*/ 2686 __IO uint32_t rpc170; 2687 struct 2688 { 2689 __IO uint32_t rx_md_dq :4; 2690 __I uint32_t reserved_01 :28; 2691 } bitfield; 2692 } CFG_DDR_SGMII_PHY_rpc170_TypeDef; 2693 2694 typedef union{ /*!< rpc171 register definition*/ 2695 __IO uint32_t rpc171; 2696 struct 2697 { 2698 __IO uint32_t rx_md_dqsn :4; 2699 __I uint32_t reserved_01 :28; 2700 } bitfield; 2701 } CFG_DDR_SGMII_PHY_rpc171_TypeDef; 2702 2703 typedef union{ /*!< rpc172 register definition*/ 2704 __IO uint32_t rpc172; 2705 struct 2706 { 2707 __IO uint32_t rx_md_dqsp :4; 2708 __I uint32_t reserved_01 :28; 2709 } bitfield; 2710 } CFG_DDR_SGMII_PHY_rpc172_TypeDef; 2711 2712 typedef union{ /*!< rpc173 register definition*/ 2713 __IO uint32_t rpc173; 2714 struct 2715 { 2716 __IO uint32_t sclk0_en_addcmd :1; 2717 __I uint32_t reserved_01 :31; 2718 } bitfield; 2719 } CFG_DDR_SGMII_PHY_rpc173_TypeDef; 2720 2721 typedef union{ /*!< rpc174 register definition*/ 2722 __IO uint32_t rpc174; 2723 struct 2724 { 2725 __IO uint32_t sclk0_en_clkn :1; 2726 __I uint32_t reserved_01 :31; 2727 } bitfield; 2728 } CFG_DDR_SGMII_PHY_rpc174_TypeDef; 2729 2730 typedef union{ /*!< rpc175 register definition*/ 2731 __IO uint32_t rpc175; 2732 struct 2733 { 2734 __IO uint32_t sclk0_en_clkp :1; 2735 __I uint32_t reserved_01 :31; 2736 } bitfield; 2737 } CFG_DDR_SGMII_PHY_rpc175_TypeDef; 2738 2739 typedef union{ /*!< rpc176 register definition*/ 2740 __IO uint32_t rpc176; 2741 struct 2742 { 2743 __IO uint32_t sclk0_en_dq :1; 2744 __I uint32_t reserved_01 :31; 2745 } bitfield; 2746 } CFG_DDR_SGMII_PHY_rpc176_TypeDef; 2747 2748 typedef union{ /*!< rpc177 register definition*/ 2749 __IO uint32_t rpc177; 2750 struct 2751 { 2752 __IO uint32_t sclk0_en_dqsn :1; 2753 __I uint32_t reserved_01 :31; 2754 } bitfield; 2755 } CFG_DDR_SGMII_PHY_rpc177_TypeDef; 2756 2757 typedef union{ /*!< rpc178 register definition*/ 2758 __IO uint32_t rpc178; 2759 struct 2760 { 2761 __IO uint32_t sclk0_en_dqsp :1; 2762 __I uint32_t reserved_01 :31; 2763 } bitfield; 2764 } CFG_DDR_SGMII_PHY_rpc178_TypeDef; 2765 2766 typedef union{ /*!< rpc179 register definition*/ 2767 __IO uint32_t rpc179; 2768 struct 2769 { 2770 __IO uint32_t sclk0_inv_addcmd :1; 2771 __I uint32_t reserved_01 :31; 2772 } bitfield; 2773 } CFG_DDR_SGMII_PHY_rpc179_TypeDef; 2774 2775 typedef union{ /*!< rpc180 register definition*/ 2776 __IO uint32_t rpc180; 2777 struct 2778 { 2779 __IO uint32_t sclk0_inv_clkn :1; 2780 __I uint32_t reserved_01 :31; 2781 } bitfield; 2782 } CFG_DDR_SGMII_PHY_rpc180_TypeDef; 2783 2784 typedef union{ /*!< rpc181 register definition*/ 2785 __IO uint32_t rpc181; 2786 struct 2787 { 2788 __IO uint32_t sclk0_inv_clkp :1; 2789 __I uint32_t reserved_01 :31; 2790 } bitfield; 2791 } CFG_DDR_SGMII_PHY_rpc181_TypeDef; 2792 2793 typedef union{ /*!< rpc182 register definition*/ 2794 __IO uint32_t rpc182; 2795 struct 2796 { 2797 __IO uint32_t sclk0_inv_dq :1; 2798 __I uint32_t reserved_01 :31; 2799 } bitfield; 2800 } CFG_DDR_SGMII_PHY_rpc182_TypeDef; 2801 2802 typedef union{ /*!< rpc183 register definition*/ 2803 __IO uint32_t rpc183; 2804 struct 2805 { 2806 __IO uint32_t sclk0_inv_dqsn :1; 2807 __I uint32_t reserved_01 :31; 2808 } bitfield; 2809 } CFG_DDR_SGMII_PHY_rpc183_TypeDef; 2810 2811 typedef union{ /*!< rpc184 register definition*/ 2812 __IO uint32_t rpc184; 2813 struct 2814 { 2815 __IO uint32_t sclk0_inv_dqsp :1; 2816 __I uint32_t reserved_01 :31; 2817 } bitfield; 2818 } CFG_DDR_SGMII_PHY_rpc184_TypeDef; 2819 2820 typedef union{ /*!< rpc185 register definition*/ 2821 __IO uint32_t rpc185; 2822 struct 2823 { 2824 __IO uint32_t sclk1_en_addcmd :1; 2825 __I uint32_t reserved_01 :31; 2826 } bitfield; 2827 } CFG_DDR_SGMII_PHY_rpc185_TypeDef; 2828 2829 typedef union{ /*!< rpc186 register definition*/ 2830 __IO uint32_t rpc186; 2831 struct 2832 { 2833 __IO uint32_t sclk1_en_clkn :1; 2834 __I uint32_t reserved_01 :31; 2835 } bitfield; 2836 } CFG_DDR_SGMII_PHY_rpc186_TypeDef; 2837 2838 typedef union{ /*!< rpc187 register definition*/ 2839 __IO uint32_t rpc187; 2840 struct 2841 { 2842 __IO uint32_t sclk1_en_clkp :1; 2843 __I uint32_t reserved_01 :31; 2844 } bitfield; 2845 } CFG_DDR_SGMII_PHY_rpc187_TypeDef; 2846 2847 typedef union{ /*!< rpc188 register definition*/ 2848 __IO uint32_t rpc188; 2849 struct 2850 { 2851 __IO uint32_t sclk1_en_dq :1; 2852 __I uint32_t reserved_01 :31; 2853 } bitfield; 2854 } CFG_DDR_SGMII_PHY_rpc188_TypeDef; 2855 2856 typedef union{ /*!< rpc189 register definition*/ 2857 __IO uint32_t rpc189; 2858 struct 2859 { 2860 __IO uint32_t sclk1_en_dqsn :1; 2861 __I uint32_t reserved_01 :31; 2862 } bitfield; 2863 } CFG_DDR_SGMII_PHY_rpc189_TypeDef; 2864 2865 typedef union{ /*!< rpc190 register definition*/ 2866 __IO uint32_t rpc190; 2867 struct 2868 { 2869 __IO uint32_t sclk1_en_dqsp :1; 2870 __I uint32_t reserved_01 :31; 2871 } bitfield; 2872 } CFG_DDR_SGMII_PHY_rpc190_TypeDef; 2873 2874 typedef union{ /*!< rpc191 register definition*/ 2875 __IO uint32_t rpc191; 2876 struct 2877 { 2878 __IO uint32_t sclk1_inv_addcmd :1; 2879 __I uint32_t reserved_01 :31; 2880 } bitfield; 2881 } CFG_DDR_SGMII_PHY_rpc191_TypeDef; 2882 2883 typedef union{ /*!< rpc192 register definition*/ 2884 __IO uint32_t rpc192; 2885 struct 2886 { 2887 __IO uint32_t sclk1_inv_clkn :1; 2888 __I uint32_t reserved_01 :31; 2889 } bitfield; 2890 } CFG_DDR_SGMII_PHY_rpc192_TypeDef; 2891 2892 typedef union{ /*!< rpc193 register definition*/ 2893 __IO uint32_t rpc193; 2894 struct 2895 { 2896 __IO uint32_t sclk1_inv_clkp :1; 2897 __I uint32_t reserved_01 :31; 2898 } bitfield; 2899 } CFG_DDR_SGMII_PHY_rpc193_TypeDef; 2900 2901 typedef union{ /*!< rpc194 register definition*/ 2902 __IO uint32_t rpc194; 2903 struct 2904 { 2905 __IO uint32_t sclk1_inv_dq :1; 2906 __I uint32_t reserved_01 :31; 2907 } bitfield; 2908 } CFG_DDR_SGMII_PHY_rpc194_TypeDef; 2909 2910 typedef union{ /*!< rpc195 register definition*/ 2911 __IO uint32_t rpc195; 2912 struct 2913 { 2914 __IO uint32_t sclk1_inv_dqsn :1; 2915 __I uint32_t reserved_01 :31; 2916 } bitfield; 2917 } CFG_DDR_SGMII_PHY_rpc195_TypeDef; 2918 2919 typedef union{ /*!< rpc196 register definition*/ 2920 __IO uint32_t rpc196; 2921 struct 2922 { 2923 __IO uint32_t sclk1_inv_dqsp :1; 2924 __I uint32_t reserved_01 :31; 2925 } bitfield; 2926 } CFG_DDR_SGMII_PHY_rpc196_TypeDef; 2927 2928 typedef union{ /*!< rpc197 register definition*/ 2929 __IO uint32_t rpc197; 2930 struct 2931 { 2932 __IO uint32_t soft_reset_addcmd :1; 2933 __I uint32_t reserved_01 :31; 2934 } bitfield; 2935 } CFG_DDR_SGMII_PHY_rpc197_TypeDef; 2936 2937 typedef union{ /*!< rpc198 register definition*/ 2938 __IO uint32_t rpc198; 2939 struct 2940 { 2941 __IO uint32_t soft_reset_data :1; 2942 __I uint32_t reserved_01 :31; 2943 } bitfield; 2944 } CFG_DDR_SGMII_PHY_rpc198_TypeDef; 2945 2946 typedef union{ /*!< rpc199 register definition*/ 2947 __IO uint32_t rpc199; 2948 struct 2949 { 2950 __IO uint32_t spare_iog_addcmd :1; 2951 __I uint32_t reserved_01 :31; 2952 } bitfield; 2953 } CFG_DDR_SGMII_PHY_rpc199_TypeDef; 2954 2955 typedef union{ /*!< rpc200 register definition*/ 2956 __IO uint32_t rpc200; 2957 struct 2958 { 2959 __IO uint32_t spare_iog_clkn :1; 2960 __I uint32_t reserved_01 :31; 2961 } bitfield; 2962 } CFG_DDR_SGMII_PHY_rpc200_TypeDef; 2963 2964 typedef union{ /*!< rpc201 register definition*/ 2965 __IO uint32_t rpc201; 2966 struct 2967 { 2968 __IO uint32_t spare_iog_clkp :1; 2969 __I uint32_t reserved_01 :31; 2970 } bitfield; 2971 } CFG_DDR_SGMII_PHY_rpc201_TypeDef; 2972 2973 typedef union{ /*!< rpc202 register definition*/ 2974 __IO uint32_t rpc202; 2975 struct 2976 { 2977 __IO uint32_t spare_iog_dq :1; 2978 __I uint32_t reserved_01 :31; 2979 } bitfield; 2980 } CFG_DDR_SGMII_PHY_rpc202_TypeDef; 2981 2982 typedef union{ /*!< rpc203 register definition*/ 2983 __IO uint32_t rpc203; 2984 struct 2985 { 2986 __IO uint32_t spare_iog_dqsn :1; 2987 __I uint32_t reserved_01 :31; 2988 } bitfield; 2989 } CFG_DDR_SGMII_PHY_rpc203_TypeDef; 2990 2991 typedef union{ /*!< rpc204 register definition*/ 2992 __IO uint32_t rpc204; 2993 struct 2994 { 2995 __IO uint32_t spare_iog_dqsp :1; 2996 __I uint32_t reserved_01 :31; 2997 } bitfield; 2998 } CFG_DDR_SGMII_PHY_rpc204_TypeDef; 2999 3000 typedef union{ /*!< rpc205 register definition*/ 3001 __IO uint32_t rpc205; 3002 struct 3003 { 3004 __IO uint32_t spio_sel_di_dqsn :2; 3005 __I uint32_t reserved_01 :30; 3006 } bitfield; 3007 } CFG_DDR_SGMII_PHY_rpc205_TypeDef; 3008 3009 typedef union{ /*!< rpc206 register definition*/ 3010 __IO uint32_t rpc206; 3011 struct 3012 { 3013 __IO uint32_t spio_sel_di_dqsp :2; 3014 __I uint32_t reserved_01 :30; 3015 } bitfield; 3016 } CFG_DDR_SGMII_PHY_rpc206_TypeDef; 3017 3018 typedef union{ /*!< rpc207 register definition*/ 3019 __IO uint32_t rpc207; 3020 struct 3021 { 3022 __IO uint32_t stop_sel_addcmd :2; 3023 __I uint32_t reserved_01 :30; 3024 } bitfield; 3025 } CFG_DDR_SGMII_PHY_rpc207_TypeDef; 3026 3027 typedef union{ /*!< rpc208 register definition*/ 3028 __IO uint32_t rpc208; 3029 struct 3030 { 3031 __IO uint32_t stop_sel_data :2; 3032 __I uint32_t reserved_01 :30; 3033 } bitfield; 3034 } CFG_DDR_SGMII_PHY_rpc208_TypeDef; 3035 3036 typedef union{ /*!< rpc209 register definition*/ 3037 __IO uint32_t rpc209; 3038 struct 3039 { 3040 __IO uint32_t txclk_sel_addcmd :2; 3041 __I uint32_t reserved_01 :30; 3042 } bitfield; 3043 } CFG_DDR_SGMII_PHY_rpc209_TypeDef; 3044 3045 typedef union{ /*!< rpc210 register definition*/ 3046 __IO uint32_t rpc210; 3047 struct 3048 { 3049 __IO uint32_t txclk_sel_clkn :2; 3050 __I uint32_t reserved_01 :30; 3051 } bitfield; 3052 } CFG_DDR_SGMII_PHY_rpc210_TypeDef; 3053 3054 typedef union{ /*!< rpc211 register definition*/ 3055 __IO uint32_t rpc211; 3056 struct 3057 { 3058 __IO uint32_t txclk_sel_clkp :2; 3059 __I uint32_t reserved_01 :30; 3060 } bitfield; 3061 } CFG_DDR_SGMII_PHY_rpc211_TypeDef; 3062 3063 typedef union{ /*!< rpc212 register definition*/ 3064 __IO uint32_t rpc212; 3065 struct 3066 { 3067 __IO uint32_t txclk_sel_dq :2; 3068 __I uint32_t reserved_01 :30; 3069 } bitfield; 3070 } CFG_DDR_SGMII_PHY_rpc212_TypeDef; 3071 3072 typedef union{ /*!< rpc213 register definition*/ 3073 __IO uint32_t rpc213; 3074 struct 3075 { 3076 __IO uint32_t txclk_sel_dqsn :2; 3077 __I uint32_t reserved_01 :30; 3078 } bitfield; 3079 } CFG_DDR_SGMII_PHY_rpc213_TypeDef; 3080 3081 typedef union{ /*!< rpc214 register definition*/ 3082 __IO uint32_t rpc214; 3083 struct 3084 { 3085 __IO uint32_t txclk_sel_dqsp :2; 3086 __I uint32_t reserved_01 :30; 3087 } bitfield; 3088 } CFG_DDR_SGMII_PHY_rpc214_TypeDef; 3089 3090 typedef union{ /*!< rpc215 register definition*/ 3091 __IO uint32_t rpc215; 3092 struct 3093 { 3094 __IO uint32_t txdly_addcmd :7; 3095 __I uint32_t reserved_01 :25; 3096 } bitfield; 3097 } CFG_DDR_SGMII_PHY_rpc215_TypeDef; 3098 3099 typedef union{ /*!< rpc216 register definition*/ 3100 __IO uint32_t rpc216; 3101 struct 3102 { 3103 __IO uint32_t txdly_clkn :7; 3104 __I uint32_t reserved_01 :25; 3105 } bitfield; 3106 } CFG_DDR_SGMII_PHY_rpc216_TypeDef; 3107 3108 typedef union{ /*!< rpc217 register definition*/ 3109 __IO uint32_t rpc217; 3110 struct 3111 { 3112 __IO uint32_t txdly_clkp :7; 3113 __I uint32_t reserved_01 :25; 3114 } bitfield; 3115 } CFG_DDR_SGMII_PHY_rpc217_TypeDef; 3116 3117 typedef union{ /*!< rpc218 register definition*/ 3118 __IO uint32_t rpc218; 3119 struct 3120 { 3121 __IO uint32_t txdly_dir_addcmd :1; 3122 __I uint32_t reserved_01 :31; 3123 } bitfield; 3124 } CFG_DDR_SGMII_PHY_rpc218_TypeDef; 3125 3126 typedef union{ /*!< rpc219 register definition*/ 3127 __IO uint32_t rpc219; 3128 struct 3129 { 3130 __IO uint32_t txdly_dir_data :1; 3131 __I uint32_t reserved_01 :31; 3132 } bitfield; 3133 } CFG_DDR_SGMII_PHY_rpc219_TypeDef; 3134 3135 typedef union{ /*!< rpc220 register definition*/ 3136 __IO uint32_t rpc220; 3137 struct 3138 { 3139 __IO uint32_t txdly_dq :7; 3140 __I uint32_t reserved_01 :25; 3141 } bitfield; 3142 } CFG_DDR_SGMII_PHY_rpc220_TypeDef; 3143 3144 typedef union{ /*!< rpc221 register definition*/ 3145 __IO uint32_t rpc221; 3146 struct 3147 { 3148 __IO uint32_t txdly_dqsn :7; 3149 __I uint32_t reserved_01 :25; 3150 } bitfield; 3151 } CFG_DDR_SGMII_PHY_rpc221_TypeDef; 3152 3153 typedef union{ /*!< rpc222 register definition*/ 3154 __IO uint32_t rpc222; 3155 struct 3156 { 3157 __IO uint32_t txdly_dqsp :7; 3158 __I uint32_t reserved_01 :25; 3159 } bitfield; 3160 } CFG_DDR_SGMII_PHY_rpc222_TypeDef; 3161 3162 typedef union{ /*!< rpc223 register definition*/ 3163 __IO uint32_t rpc223; 3164 struct 3165 { 3166 __IO uint32_t txdly_en_addcmd :1; 3167 __I uint32_t reserved_01 :31; 3168 } bitfield; 3169 } CFG_DDR_SGMII_PHY_rpc223_TypeDef; 3170 3171 typedef union{ /*!< rpc224 register definition*/ 3172 __IO uint32_t rpc224; 3173 struct 3174 { 3175 __IO uint32_t txdly_en_data :1; 3176 __I uint32_t reserved_01 :31; 3177 } bitfield; 3178 } CFG_DDR_SGMII_PHY_rpc224_TypeDef; 3179 3180 typedef union{ /*!< rpc225 register definition*/ 3181 __IO uint32_t rpc225; 3182 struct 3183 { 3184 __IO uint32_t txdly_offset_addcmd :8; 3185 __I uint32_t reserved_01 :24; 3186 } bitfield; 3187 } CFG_DDR_SGMII_PHY_rpc225_TypeDef; 3188 3189 typedef union{ /*!< rpc226 register definition*/ 3190 __IO uint32_t rpc226; 3191 struct 3192 { 3193 __IO uint32_t txdly_offset_data :8; 3194 __I uint32_t reserved_01 :24; 3195 } bitfield; 3196 } CFG_DDR_SGMII_PHY_rpc226_TypeDef; 3197 3198 typedef union{ /*!< rpc227 register definition*/ 3199 __IO uint32_t rpc227; 3200 struct 3201 { 3202 __IO uint32_t txmvdly_en_addcmd :1; 3203 __I uint32_t reserved_01 :31; 3204 } bitfield; 3205 } CFG_DDR_SGMII_PHY_rpc227_TypeDef; 3206 3207 typedef union{ /*!< rpc228 register definition*/ 3208 __IO uint32_t rpc228; 3209 struct 3210 { 3211 __IO uint32_t txmvdly_en_data :1; 3212 __I uint32_t reserved_01 :31; 3213 } bitfield; 3214 } CFG_DDR_SGMII_PHY_rpc228_TypeDef; 3215 3216 typedef union{ /*!< rpc229 register definition*/ 3217 __IO uint32_t rpc229; 3218 struct 3219 { 3220 __IO uint32_t tx_md_addcmd :7; 3221 __I uint32_t reserved_01 :25; 3222 } bitfield; 3223 } CFG_DDR_SGMII_PHY_rpc229_TypeDef; 3224 3225 typedef union{ /*!< rpc230 register definition*/ 3226 __IO uint32_t rpc230; 3227 struct 3228 { 3229 __IO uint32_t tx_md_clkn :7; 3230 __I uint32_t reserved_01 :25; 3231 } bitfield; 3232 } CFG_DDR_SGMII_PHY_rpc230_TypeDef; 3233 3234 typedef union{ /*!< rpc231 register definition*/ 3235 __IO uint32_t rpc231; 3236 struct 3237 { 3238 __IO uint32_t tx_md_clkp :7; 3239 __I uint32_t reserved_01 :25; 3240 } bitfield; 3241 } CFG_DDR_SGMII_PHY_rpc231_TypeDef; 3242 3243 typedef union{ /*!< rpc232 register definition*/ 3244 __IO uint32_t rpc232; 3245 struct 3246 { 3247 __IO uint32_t tx_md_dq :7; 3248 __I uint32_t reserved_01 :25; 3249 } bitfield; 3250 } CFG_DDR_SGMII_PHY_rpc232_TypeDef; 3251 3252 typedef union{ /*!< rpc233 register definition*/ 3253 __IO uint32_t rpc233; 3254 struct 3255 { 3256 __IO uint32_t tx_md_dqsn :7; 3257 __I uint32_t reserved_01 :25; 3258 } bitfield; 3259 } CFG_DDR_SGMII_PHY_rpc233_TypeDef; 3260 3261 typedef union{ /*!< rpc234 register definition*/ 3262 __IO uint32_t rpc234; 3263 struct 3264 { 3265 __IO uint32_t tx_md_dqsp :7; 3266 __I uint32_t reserved_01 :25; 3267 } bitfield; 3268 } CFG_DDR_SGMII_PHY_rpc234_TypeDef; 3269 3270 typedef union{ /*!< rpc235 register definition*/ 3271 __IO uint32_t rpc235; 3272 struct 3273 { 3274 __IO uint32_t wpd_addcmd0 :12; 3275 __I uint32_t reserved_01 :20; 3276 } bitfield; 3277 } CFG_DDR_SGMII_PHY_rpc235_TypeDef; 3278 3279 typedef union{ /*!< rpc236 register definition*/ 3280 __IO uint32_t rpc236; 3281 struct 3282 { 3283 __IO uint32_t wpd_addcmd1 :12; 3284 __I uint32_t reserved_01 :20; 3285 } bitfield; 3286 } CFG_DDR_SGMII_PHY_rpc236_TypeDef; 3287 3288 typedef union{ /*!< rpc237 register definition*/ 3289 __IO uint32_t rpc237; 3290 struct 3291 { 3292 __IO uint32_t wpd_addcmd2 :12; 3293 __I uint32_t reserved_01 :20; 3294 } bitfield; 3295 } CFG_DDR_SGMII_PHY_rpc237_TypeDef; 3296 3297 typedef union{ /*!< rpc238 register definition*/ 3298 __IO uint32_t rpc238; 3299 struct 3300 { 3301 __IO uint32_t wpd_data0 :12; 3302 __I uint32_t reserved_01 :20; 3303 } bitfield; 3304 } CFG_DDR_SGMII_PHY_rpc238_TypeDef; 3305 3306 typedef union{ /*!< rpc239 register definition*/ 3307 __IO uint32_t rpc239; 3308 struct 3309 { 3310 __IO uint32_t wpd_data1 :12; 3311 __I uint32_t reserved_01 :20; 3312 } bitfield; 3313 } CFG_DDR_SGMII_PHY_rpc239_TypeDef; 3314 3315 typedef union{ /*!< rpc240 register definition*/ 3316 __IO uint32_t rpc240; 3317 struct 3318 { 3319 __IO uint32_t wpd_data2 :12; 3320 __I uint32_t reserved_01 :20; 3321 } bitfield; 3322 } CFG_DDR_SGMII_PHY_rpc240_TypeDef; 3323 3324 typedef union{ /*!< rpc241 register definition*/ 3325 __IO uint32_t rpc241; 3326 struct 3327 { 3328 __IO uint32_t wpd_data3 :12; 3329 __I uint32_t reserved_01 :20; 3330 } bitfield; 3331 } CFG_DDR_SGMII_PHY_rpc241_TypeDef; 3332 3333 typedef union{ /*!< rpc242 register definition*/ 3334 __IO uint32_t rpc242; 3335 struct 3336 { 3337 __IO uint32_t wpd_ecc :12; 3338 __I uint32_t reserved_01 :20; 3339 } bitfield; 3340 } CFG_DDR_SGMII_PHY_rpc242_TypeDef; 3341 3342 typedef union{ /*!< rpc243 register definition*/ 3343 __IO uint32_t rpc243; 3344 struct 3345 { 3346 __IO uint32_t wpu_addcmd0 :12; 3347 __I uint32_t reserved_01 :20; 3348 } bitfield; 3349 } CFG_DDR_SGMII_PHY_rpc243_TypeDef; 3350 3351 typedef union{ /*!< rpc244 register definition*/ 3352 __IO uint32_t rpc244; 3353 struct 3354 { 3355 __IO uint32_t wpu_addcmd1 :12; 3356 __I uint32_t reserved_01 :20; 3357 } bitfield; 3358 } CFG_DDR_SGMII_PHY_rpc244_TypeDef; 3359 3360 typedef union{ /*!< rpc245 register definition*/ 3361 __IO uint32_t rpc245; 3362 struct 3363 { 3364 __IO uint32_t wpu_addcmd2 :12; 3365 __I uint32_t reserved_01 :20; 3366 } bitfield; 3367 } CFG_DDR_SGMII_PHY_rpc245_TypeDef; 3368 3369 typedef union{ /*!< rpc246 register definition*/ 3370 __IO uint32_t rpc246; 3371 struct 3372 { 3373 __IO uint32_t wpu_data0 :12; 3374 __I uint32_t reserved_01 :20; 3375 } bitfield; 3376 } CFG_DDR_SGMII_PHY_rpc246_TypeDef; 3377 3378 typedef union{ /*!< rpc247 register definition*/ 3379 __IO uint32_t rpc247; 3380 struct 3381 { 3382 __IO uint32_t wpu_data1 :12; 3383 __I uint32_t reserved_01 :20; 3384 } bitfield; 3385 } CFG_DDR_SGMII_PHY_rpc247_TypeDef; 3386 3387 typedef union{ /*!< rpc248 register definition*/ 3388 __IO uint32_t rpc248; 3389 struct 3390 { 3391 __IO uint32_t wpu_data2 :12; 3392 __I uint32_t reserved_01 :20; 3393 } bitfield; 3394 } CFG_DDR_SGMII_PHY_rpc248_TypeDef; 3395 3396 typedef union{ /*!< rpc249 register definition*/ 3397 __IO uint32_t rpc249; 3398 struct 3399 { 3400 __IO uint32_t wpu_data3 :12; 3401 __I uint32_t reserved_01 :20; 3402 } bitfield; 3403 } CFG_DDR_SGMII_PHY_rpc249_TypeDef; 3404 3405 typedef union{ /*!< rpc250 register definition*/ 3406 __IO uint32_t rpc250; 3407 struct 3408 { 3409 __IO uint32_t wpu_ecc :12; 3410 __I uint32_t reserved_01 :20; 3411 } bitfield; 3412 } CFG_DDR_SGMII_PHY_rpc250_TypeDef; 3413 3414 typedef union{ /*!< spio251 register definition*/ 3415 __IO uint32_t spio251; 3416 struct 3417 { 3418 __IO uint32_t sel_refclk0 :1; 3419 __I uint32_t reserved_01 :31; 3420 } bitfield; 3421 } CFG_DDR_SGMII_PHY_spio251_TypeDef; 3422 3423 typedef union{ /*!< spio252 register definition*/ 3424 __IO uint32_t spio252; 3425 struct 3426 { 3427 __IO uint32_t sel_refclk1 :1; 3428 __I uint32_t reserved_01 :31; 3429 } bitfield; 3430 } CFG_DDR_SGMII_PHY_spio252_TypeDef; 3431 3432 typedef union{ /*!< spio253 register definition*/ 3433 __IO uint32_t spio253; 3434 struct 3435 { 3436 __IO uint32_t sel_refclk2 :1; 3437 __I uint32_t reserved_01 :31; 3438 } bitfield; 3439 } CFG_DDR_SGMII_PHY_spio253_TypeDef; 3440 3441 typedef union{ /*!< SOFT_RESET_TIP register definition*/ 3442 __IO uint32_t SOFT_RESET_TIP; 3443 struct 3444 { 3445 __O CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_NV_MAP_TIP_TypeDef NV_MAP_TIP :1; 3446 __O CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_V_MAP_TIP_TypeDef V_MAP_TIP :1; 3447 __I uint32_t reserved_01 :6; 3448 __O CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_PERIPH_TIP_TypeDef PERIPH_TIP :1; 3449 __I uint32_t reserved_02 :7; 3450 __I uint32_t BLOCKID_TIP :16; 3451 } bitfield; 3452 } CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_TypeDef; 3453 3454 typedef union{ /*!< rank_select register definition*/ 3455 __IO uint32_t rank_select; 3456 struct 3457 { 3458 __IO uint32_t rank :1; 3459 __I uint32_t reserved_01 :31; 3460 } bitfield; 3461 } CFG_DDR_SGMII_PHY_rank_select_TypeDef; 3462 3463 typedef union{ /*!< lane_select register definition*/ 3464 __IO uint32_t lane_select; 3465 struct 3466 { 3467 __IO uint32_t lane :3; 3468 __I uint32_t reserved_01 :29; 3469 } bitfield; 3470 } CFG_DDR_SGMII_PHY_lane_select_TypeDef; 3471 3472 typedef union{ /*!< training_skip register definition*/ 3473 __IO uint32_t training_skip; 3474 struct 3475 { 3476 __IO uint32_t skip_bclksclk :1; 3477 __IO uint32_t skip_addcmd :1; 3478 __IO uint32_t skip_wrlvl :1; 3479 __IO uint32_t skip_rdgate :1; 3480 __IO uint32_t skip_dq_dqs_opt :1; 3481 __IO uint32_t skip_write_calibration :1; 3482 __IO uint32_t skip_vref_mr6 :1; 3483 __IO uint32_t step7 :1; 3484 __I uint32_t reserved_01 :24; 3485 } bitfield; 3486 } CFG_DDR_SGMII_PHY_training_skip_TypeDef; 3487 3488 typedef union{ /*!< training_start register definition*/ 3489 __IO uint32_t training_start; 3490 struct 3491 { 3492 __IO uint32_t start :1; 3493 __I uint32_t reserved_01 :31; 3494 } bitfield; 3495 } CFG_DDR_SGMII_PHY_training_start_TypeDef; 3496 3497 typedef union{ /*!< training_status register definition*/ 3498 __I uint32_t training_status; 3499 struct 3500 { 3501 __I uint32_t status :8; 3502 __I uint32_t reserved_01 :24; 3503 } bitfield; 3504 } CFG_DDR_SGMII_PHY_training_status_TypeDef; 3505 3506 typedef union{ /*!< training_reset register definition*/ 3507 __IO uint32_t training_reset; 3508 struct 3509 { 3510 __IO uint32_t reset :1; 3511 __I uint32_t reserved_01 :31; 3512 } bitfield; 3513 } CFG_DDR_SGMII_PHY_training_reset_TypeDef; 3514 3515 typedef union{ /*!< gt_err_comb register definition*/ 3516 __I uint32_t gt_err_comb; 3517 struct 3518 { 3519 __I uint32_t error_comb_lanex :6; 3520 __I uint32_t reserved_01 :26; 3521 } bitfield; 3522 } CFG_DDR_SGMII_PHY_gt_err_comb_TypeDef; 3523 3524 typedef union{ /*!< gt_clk_sel register definition*/ 3525 __I uint32_t gt_clk_sel; 3526 struct 3527 { 3528 __I uint32_t clk_sel_lanex_rankx :3; 3529 __I uint32_t reserved_01 :29; 3530 } bitfield; 3531 } CFG_DDR_SGMII_PHY_gt_clk_sel_TypeDef; 3532 3533 typedef union{ /*!< gt_txdly register definition*/ 3534 __I uint32_t gt_txdly; 3535 struct 3536 { 3537 __I uint32_t txdly0_lanex :8; 3538 __I uint32_t txdly1_lanex :8; 3539 __I uint32_t txdly2_lanex :8; 3540 __I uint32_t txdly3_lanex :8; 3541 } bitfield; 3542 } CFG_DDR_SGMII_PHY_gt_txdly_TypeDef; 3543 3544 typedef union{ /*!< gt_steps_180 register definition*/ 3545 __I uint32_t gt_steps_180; 3546 struct 3547 { 3548 __I uint32_t steps_180_lanex_rankx :4; 3549 __I uint32_t reserved_01 :28; 3550 } bitfield; 3551 } CFG_DDR_SGMII_PHY_gt_steps_180_TypeDef; 3552 3553 typedef union{ /*!< gt_state register definition*/ 3554 __I uint32_t gt_state; 3555 struct 3556 { 3557 __I uint32_t gt_state_lanex :4; 3558 __I uint32_t reserved_01 :28; 3559 } bitfield; 3560 } CFG_DDR_SGMII_PHY_gt_state_TypeDef; 3561 3562 typedef union{ /*!< wl_delay_0 register definition*/ 3563 __I uint32_t wl_delay_0; 3564 struct 3565 { 3566 __I uint32_t wldelay_lanex_rankx :8; 3567 __I uint32_t reserved_01 :24; 3568 } bitfield; 3569 } CFG_DDR_SGMII_PHY_wl_delay_0_TypeDef; 3570 3571 typedef union{ /*!< dq_dqs_err_done register definition*/ 3572 __I uint32_t dq_dqs_err_done; 3573 struct 3574 { 3575 __I uint32_t dq_dqs_error_done_lanex_rankx :4; 3576 __I uint32_t reserved_01 :28; 3577 } bitfield; 3578 } CFG_DDR_SGMII_PHY_dq_dqs_err_done_TypeDef; 3579 3580 typedef union{ /*!< dqdqs_window register definition*/ 3581 __I uint32_t dqdqs_window; 3582 struct 3583 { 3584 __I uint32_t ils_lanex_rankx :8; 3585 __I uint32_t irs_lanex_rankx :8; 3586 __I uint32_t reserved_01 :16; 3587 } bitfield; 3588 } CFG_DDR_SGMII_PHY_dqdqs_window_TypeDef; 3589 3590 typedef union{ /*!< dqdqs_state register definition*/ 3591 __I uint32_t dqdqs_state; 3592 struct 3593 { 3594 __I uint32_t state_lanex_rankx :8; 3595 __I uint32_t reserved_01 :24; 3596 } bitfield; 3597 } CFG_DDR_SGMII_PHY_dqdqs_state_TypeDef; 3598 3599 typedef union{ /*!< delta0 register definition*/ 3600 __I uint32_t delta0; 3601 struct 3602 { 3603 __I uint32_t delay0_lanex :8; 3604 __I uint32_t delay1_lanex :8; 3605 __I uint32_t delay2_lanex :8; 3606 __I uint32_t delay3_lanex :8; 3607 } bitfield; 3608 } CFG_DDR_SGMII_PHY_delta0_TypeDef; 3609 3610 typedef union{ /*!< delta1 register definition*/ 3611 __I uint32_t delta1; 3612 struct 3613 { 3614 __I uint32_t delay4_lanex :8; 3615 __I uint32_t delay5_lanex :8; 3616 __I uint32_t delay6_lanex :8; 3617 __I uint32_t delay7_lanex :8; 3618 } bitfield; 3619 } CFG_DDR_SGMII_PHY_delta1_TypeDef; 3620 3621 typedef union{ /*!< dqdqs_status0 register definition*/ 3622 __I uint32_t dqdqs_status0; 3623 struct 3624 { 3625 __I uint32_t init_dly_lanex :8; 3626 __I uint32_t reserved_01 :24; 3627 } bitfield; 3628 } CFG_DDR_SGMII_PHY_dqdqs_status0_TypeDef; 3629 3630 typedef union{ /*!< dqdqs_status1 register definition*/ 3631 __I uint32_t dqdqs_status1; 3632 struct 3633 { 3634 __I uint32_t dqs_dly_lanex_rankx :8; 3635 __I uint32_t reserved_01 :24; 3636 } bitfield; 3637 } CFG_DDR_SGMII_PHY_dqdqs_status1_TypeDef; 3638 3639 typedef union{ /*!< dqdqs_status2 register definition*/ 3640 __I uint32_t dqdqs_status2; 3641 struct 3642 { 3643 __I uint32_t bit_width_lanex :8; 3644 __I uint32_t reserved_01 :24; 3645 } bitfield; 3646 } CFG_DDR_SGMII_PHY_dqdqs_status2_TypeDef; 3647 3648 typedef union{ /*!< dqdqs_status3 register definition*/ 3649 __I uint32_t dqdqs_status3; 3650 struct 3651 { 3652 __I uint32_t initldqs_2_mid_lanex_rankx :8; 3653 __I uint32_t reserved_01 :24; 3654 } bitfield; 3655 } CFG_DDR_SGMII_PHY_dqdqs_status3_TypeDef; 3656 3657 typedef union{ /*!< dqdqs_status4 register definition*/ 3658 __I uint32_t dqdqs_status4; 3659 struct 3660 { 3661 __I uint32_t mid_2_initldqs_lanex_rankx :8; 3662 __I uint32_t reserved_01 :24; 3663 } bitfield; 3664 } CFG_DDR_SGMII_PHY_dqdqs_status4_TypeDef; 3665 3666 typedef union{ /*!< dqdqs_status5 register definition*/ 3667 __I uint32_t dqdqs_status5; 3668 struct 3669 { 3670 __I uint32_t stw_2_initldqs_lanex_rankx :8; 3671 __I uint32_t reserved_01 :24; 3672 } bitfield; 3673 } CFG_DDR_SGMII_PHY_dqdqs_status5_TypeDef; 3674 3675 typedef union{ /*!< dqdqs_status6 register definition*/ 3676 __I uint32_t dqdqs_status6; 3677 struct 3678 { 3679 __I uint32_t initldqs_2_stw_lanex_rankx :8; 3680 __I uint32_t reserved_01 :24; 3681 } bitfield; 3682 } CFG_DDR_SGMII_PHY_dqdqs_status6_TypeDef; 3683 3684 typedef union{ /*!< addcmd_status0 register definition*/ 3685 __I uint32_t addcmd_status0; 3686 struct 3687 { 3688 __I uint32_t delay_vcophs_sel0 :8; 3689 __I uint32_t delay_vcophs_sel1 :8; 3690 __I uint32_t delay_vcophs_sel2 :8; 3691 __I uint32_t delay_vcophs_sel3 :8; 3692 } bitfield; 3693 } CFG_DDR_SGMII_PHY_addcmd_status0_TypeDef; 3694 3695 typedef union{ /*!< addcmd_status1 register definition*/ 3696 __I uint32_t addcmd_status1; 3697 struct 3698 { 3699 __I uint32_t delay_vcophs_sel4 :8; 3700 __I uint32_t delay_vcophs_sel5 :8; 3701 __I uint32_t delay_vcophs_sel6 :8; 3702 __I uint32_t delay_vcophs_sel7 :8; 3703 } bitfield; 3704 } CFG_DDR_SGMII_PHY_addcmd_status1_TypeDef; 3705 3706 typedef union{ /*!< addcmd_answer register definition*/ 3707 __I uint32_t addcmd_answer; 3708 struct 3709 { 3710 __I uint32_t vcophs_sel_after_training :4; 3711 __I uint32_t reserved_01 :28; 3712 } bitfield; 3713 } CFG_DDR_SGMII_PHY_addcmd_answer_TypeDef; 3714 3715 typedef union{ /*!< bclksclk_answer register definition*/ 3716 __I uint32_t bclksclk_answer; 3717 struct 3718 { 3719 __I uint32_t bclk0_vcophs_sel :4; 3720 __I uint32_t reserved_01 :28; 3721 } bitfield; 3722 } CFG_DDR_SGMII_PHY_bclksclk_answer_TypeDef; 3723 3724 typedef union{ /*!< dqdqs_wrcalib_offset register definition*/ 3725 __I uint32_t dqdqs_wrcalib_offset; 3726 struct 3727 { 3728 __I uint32_t wrcalib_offset_lanex :8; 3729 __I uint32_t reserved_01 :24; 3730 } bitfield; 3731 } CFG_DDR_SGMII_PHY_dqdqs_wrcalib_offset_TypeDef; 3732 3733 typedef union{ /*!< expert_mode_en register definition*/ 3734 __IO uint32_t expert_mode_en; 3735 struct 3736 { 3737 __IO uint32_t dyn_ovr_dlycnt_en :1; 3738 __IO uint32_t dyn_ovr_pllcnt_en :1; 3739 __IO uint32_t dyn_ovr_rdgate_en :1; 3740 __IO uint32_t dyn_ovr_wrcalib_en :1; 3741 __IO uint32_t dyn_ovr_calif_en :1; 3742 __IO uint32_t dyn_ovr_dfi_shim_en :1; 3743 __I uint32_t reserved_01 :26; 3744 } bitfield; 3745 } CFG_DDR_SGMII_PHY_expert_mode_en_TypeDef; 3746 3747 typedef union{ /*!< expert_dlycnt_move_reg0 register definition*/ 3748 __IO uint32_t expert_dlycnt_move_reg0; 3749 struct 3750 { 3751 __IO uint32_t dyn_ovr_dlycnt_dq_move0 :8; 3752 __IO uint32_t dyn_ovr_dlycnt_dq_move1 :8; 3753 __IO uint32_t dyn_ovr_dlycnt_dq_move2 :8; 3754 __IO uint32_t dyn_ovr_dlycnt_dq_move3 :8; 3755 } bitfield; 3756 } CFG_DDR_SGMII_PHY_expert_dlycnt_move_reg0_TypeDef; 3757 3758 typedef union{ /*!< expert_dlycnt_move_reg1 register definition*/ 3759 __IO uint32_t expert_dlycnt_move_reg1; 3760 struct 3761 { 3762 __IO uint32_t dyn_ovr_dlycnt_dq_move4 :4; 3763 __IO uint32_t dyn_ovr_dlycnt_lanectrl_move0 :1; 3764 __IO uint32_t dyn_ovr_dlycnt_lanectrl_move1 :1; 3765 __IO uint32_t dyn_ovr_dlycnt_lanectrl_move2 :1; 3766 __IO uint32_t dyn_ovr_dlycnt_lanectrl_move3 :1; 3767 __IO uint32_t dyn_ovr_dlycnt_lanectrl_move4 :1; 3768 __IO uint32_t dyn_ovr_dlycnt_dqsw270_move0 :1; 3769 __IO uint32_t dyn_ovr_dlycnt_dqsw270_move1 :1; 3770 __IO uint32_t dyn_ovr_dlycnt_dqsw270_move2 :1; 3771 __IO uint32_t dyn_ovr_dlycnt_dqsw270_move3 :1; 3772 __IO uint32_t dyn_ovr_dlycnt_dqsw270_move4 :1; 3773 __IO uint32_t dyn_ovr_dlycnt_dqsw_move0 :1; 3774 __IO uint32_t dyn_ovr_dlycnt_dqsw_move1 :1; 3775 __IO uint32_t dyn_ovr_dlycnt_dqsw_move2 :1; 3776 __IO uint32_t dyn_ovr_dlycnt_dqsw_move3 :1; 3777 __IO uint32_t dyn_ovr_dlycnt_dqsw_move4 :1; 3778 __IO uint32_t dyn_ovr_dlycnt_catrn_move :1; 3779 __IO uint32_t dyn_ovr_dlycnt_ca_move :1; 3780 __I uint32_t reserved_01 :11; 3781 } bitfield; 3782 } CFG_DDR_SGMII_PHY_expert_dlycnt_move_reg1_TypeDef; 3783 3784 typedef union{ /*!< expert_dlycnt_direction_reg0 register definition*/ 3785 __IO uint32_t expert_dlycnt_direction_reg0; 3786 struct 3787 { 3788 __IO uint32_t dyn_ovr_dlycnt_dq_direction0 :8; 3789 __IO uint32_t dyn_ovr_dlycnt_dq_direction1 :8; 3790 __IO uint32_t dyn_ovr_dlycnt_dq_direction2 :8; 3791 __IO uint32_t dyn_ovr_dlycnt_dq_direction3 :8; 3792 } bitfield; 3793 } CFG_DDR_SGMII_PHY_expert_dlycnt_direction_reg0_TypeDef; 3794 3795 typedef union{ /*!< expert_dlycnt_direction_reg1 register definition*/ 3796 __IO uint32_t expert_dlycnt_direction_reg1; 3797 struct 3798 { 3799 __IO uint32_t dyn_ovr_dlycnt_dq_direction4 :4; 3800 __IO uint32_t dyn_ovr_dlycnt_lanectrl_direction0 :1; 3801 __IO uint32_t dyn_ovr_dlycnt_lanectrl_direction1 :1; 3802 __IO uint32_t dyn_ovr_dlycnt_lanectrl_direction2 :1; 3803 __IO uint32_t dyn_ovr_dlycnt_lanectrl_direction3 :1; 3804 __IO uint32_t dyn_ovr_dlycnt_lanectrl_direction4 :1; 3805 __IO uint32_t dyn_ovr_dlycnt_dqsw270_direction0 :1; 3806 __IO uint32_t dyn_ovr_dlycnt_dqsw270_direction1 :1; 3807 __IO uint32_t dyn_ovr_dlycnt_dqsw270_direction2 :1; 3808 __IO uint32_t dyn_ovr_dlycnt_dqsw270_direction3 :1; 3809 __IO uint32_t dyn_ovr_dlycnt_dqsw270_direction4 :1; 3810 __IO uint32_t dyn_ovr_dlycnt_dqsw_direction0 :1; 3811 __IO uint32_t dyn_ovr_dlycnt_dqsw_direction1 :1; 3812 __IO uint32_t dyn_ovr_dlycnt_dqsw_direction2 :1; 3813 __IO uint32_t dyn_ovr_dlycnt_dqsw_direction3 :1; 3814 __IO uint32_t dyn_ovr_dlycnt_dqsw_direction4 :1; 3815 __IO uint32_t dyn_ovr_dlycnt_catrn_direction :1; 3816 __IO uint32_t dyn_ovr_dlycnt_ca_direction :1; 3817 __I uint32_t reserved_01 :11; 3818 } bitfield; 3819 } CFG_DDR_SGMII_PHY_expert_dlycnt_direction_reg1_TypeDef; 3820 3821 typedef union{ /*!< expert_dlycnt_load_reg0 register definition*/ 3822 __IO uint32_t expert_dlycnt_load_reg0; 3823 struct 3824 { 3825 __IO uint32_t dyn_ovr_dlycnt_dq_load0 :8; 3826 __IO uint32_t dyn_ovr_dlycnt_dq_load1 :8; 3827 __IO uint32_t dyn_ovr_dlycnt_dq_load2 :8; 3828 __IO uint32_t dyn_ovr_dlycnt_dq_load3 :8; 3829 } bitfield; 3830 } CFG_DDR_SGMII_PHY_expert_dlycnt_load_reg0_TypeDef; 3831 3832 typedef union{ /*!< expert_dlycnt_load_reg1 register definition*/ 3833 __IO uint32_t expert_dlycnt_load_reg1; 3834 struct 3835 { 3836 __IO uint32_t dyn_ovr_dlycnt_dq_load4 :4; 3837 __IO uint32_t dyn_ovr_dlycnt_lanectrl_load0 :1; 3838 __IO uint32_t dyn_ovr_dlycnt_lanectrl_load1 :1; 3839 __IO uint32_t dyn_ovr_dlycnt_lanectrl_load2 :1; 3840 __IO uint32_t dyn_ovr_dlycnt_lanectrl_load3 :1; 3841 __IO uint32_t dyn_ovr_dlycnt_lanectrl_load4 :1; 3842 __IO uint32_t dyn_ovr_dlycnt_dqsw270_load0 :1; 3843 __IO uint32_t dyn_ovr_dlycnt_dqsw270_load1 :1; 3844 __IO uint32_t dyn_ovr_dlycnt_dqsw270_load2 :1; 3845 __IO uint32_t dyn_ovr_dlycnt_dqsw270_load3 :1; 3846 __IO uint32_t dyn_ovr_dlycnt_dqsw270_load4 :1; 3847 __IO uint32_t dyn_ovr_dlycnt_dqsw_load0 :1; 3848 __IO uint32_t dyn_ovr_dlycnt_dqsw_load1 :1; 3849 __IO uint32_t dyn_ovr_dlycnt_dqsw_load2 :1; 3850 __IO uint32_t dyn_ovr_dlycnt_dqsw_load3 :1; 3851 __IO uint32_t dyn_ovr_dlycnt_dqsw_load4 :1; 3852 __IO uint32_t dyn_ovr_dlycnt_catrn_load :1; 3853 __IO uint32_t dyn_ovr_dlycnt_ca_load :1; 3854 __I uint32_t reserved_01 :11; 3855 } bitfield; 3856 } CFG_DDR_SGMII_PHY_expert_dlycnt_load_reg1_TypeDef; 3857 3858 typedef union{ /*!< expert_dlycnt_oor_reg0 register definition*/ 3859 __I uint32_t expert_dlycnt_oor_reg0; 3860 struct 3861 { 3862 __I uint32_t dyn_ovr_dlycnt_dq_oor0 :8; 3863 __I uint32_t dyn_ovr_dlycnt_dq_oor1 :8; 3864 __I uint32_t dyn_ovr_dlycnt_dq_oor2 :8; 3865 __I uint32_t dyn_ovr_dlycnt_dq_oor3 :8; 3866 } bitfield; 3867 } CFG_DDR_SGMII_PHY_expert_dlycnt_oor_reg0_TypeDef; 3868 3869 typedef union{ /*!< expert_dlycnt_oor_reg1 register definition*/ 3870 __I uint32_t expert_dlycnt_oor_reg1; 3871 struct 3872 { 3873 __I uint32_t dyn_ovr_dlycnt_dq_oor4 :4; 3874 __I uint32_t dyn_ovr_dlycnt_lanectrl_oor0 :1; 3875 __I uint32_t dyn_ovr_dlycnt_lanectrl_oor1 :1; 3876 __I uint32_t dyn_ovr_dlycnt_lanectrl_oor2 :1; 3877 __I uint32_t dyn_ovr_dlycnt_lanectrl_oor3 :1; 3878 __I uint32_t dyn_ovr_dlycnt_lanectrl_oor4 :1; 3879 __I uint32_t dyn_ovr_dlycnt_dqsw270_oor0 :1; 3880 __I uint32_t dyn_ovr_dlycnt_dqsw270_oor1 :1; 3881 __I uint32_t dyn_ovr_dlycnt_dqsw270_oor2 :1; 3882 __I uint32_t dyn_ovr_dlycnt_dqsw270_oor3 :1; 3883 __I uint32_t dyn_ovr_dlycnt_dqsw270_oor4 :1; 3884 __I uint32_t dyn_ovr_dlycnt_dqsw_oor0 :1; 3885 __I uint32_t dyn_ovr_dlycnt_dqsw_oor1 :1; 3886 __I uint32_t dyn_ovr_dlycnt_dqsw_oor2 :1; 3887 __I uint32_t dyn_ovr_dlycnt_dqsw_oor3 :1; 3888 __I uint32_t dyn_ovr_dlycnt_dqsw_oor4 :1; 3889 __I uint32_t dyn_ovr_dlycnt_catrn_oor :1; 3890 __I uint32_t dyn_ovr_dlycnt_ca_oor :1; 3891 __I uint32_t reserved_01 :11; 3892 } bitfield; 3893 } CFG_DDR_SGMII_PHY_expert_dlycnt_oor_reg1_TypeDef; 3894 3895 typedef union{ /*!< expert_dlycnt_mv_rd_dly_reg register definition*/ 3896 __IO uint32_t expert_dlycnt_mv_rd_dly_reg; 3897 struct 3898 { 3899 __IO uint32_t dyn_ovr_dlycnt_lanectrl_mv_rd_dly0 :1; 3900 __IO uint32_t dyn_ovr_dlycnt_lanectrl_mv_rd_dly1 :1; 3901 __IO uint32_t dyn_ovr_dlycnt_lanectrl_mv_rd_dly2 :1; 3902 __IO uint32_t dyn_ovr_dlycnt_lanectrl_mv_rd_dly3 :1; 3903 __IO uint32_t dyn_ovr_dlycnt_lanectrl_mv_rd_dly4 :1; 3904 __I uint32_t reserved_01 :27; 3905 } bitfield; 3906 } CFG_DDR_SGMII_PHY_expert_dlycnt_mv_rd_dly_reg_TypeDef; 3907 3908 typedef union{ /*!< expert_dlycnt_pause register definition*/ 3909 __IO uint32_t expert_dlycnt_pause; 3910 struct 3911 { 3912 __IO uint32_t dyn_ovr_dlycnt_lanectrl_pause_addcmd :1; 3913 __IO uint32_t dyn_ovr_dlycnt_lanectrl_pause_data0 :1; 3914 __IO uint32_t dyn_ovr_dlycnt_lanectrl_pause_data1 :1; 3915 __IO uint32_t dyn_ovr_dlycnt_lanectrl_pause_data2 :1; 3916 __IO uint32_t dyn_ovr_dlycnt_lanectrl_pause_data3 :1; 3917 __IO uint32_t dyn_ovr_dlycnt_lanectrl_pause_data4 :1; 3918 __I uint32_t reserved_01 :26; 3919 } bitfield; 3920 } CFG_DDR_SGMII_PHY_expert_dlycnt_pause_TypeDef; 3921 3922 typedef union{ /*!< expert_pllcnt register definition*/ 3923 __IO uint32_t expert_pllcnt; 3924 struct 3925 { 3926 __IO uint32_t dyn_ovr_dlycnt_rotate :1; 3927 __IO uint32_t dyn_ovr_dlycnt_direction :1; 3928 __IO uint32_t dyn_ovr_dlycnt_loadphs_b :1; 3929 __IO uint32_t dyn_ovr_dlycnt_phsel :4; 3930 __I uint32_t reserved_01 :25; 3931 } bitfield; 3932 } CFG_DDR_SGMII_PHY_expert_pllcnt_TypeDef; 3933 3934 typedef union{ /*!< expert_dqlane_readback register definition*/ 3935 __I uint32_t expert_dqlane_readback; 3936 struct 3937 { 3938 __I uint32_t dq_or :5; 3939 __I uint32_t dq_and :5; 3940 __I uint32_t burst_valid :5; 3941 __I uint32_t reserved_01 :17; 3942 } bitfield; 3943 } CFG_DDR_SGMII_PHY_expert_dqlane_readback_TypeDef; 3944 3945 typedef union{ /*!< expert_addcmd_ln_readback register definition*/ 3946 __I uint32_t expert_addcmd_ln_readback; 3947 struct 3948 { 3949 __I uint32_t rx_refclk :8; 3950 __I uint32_t rx_addcmd :4; 3951 __I uint32_t rx_bclksclk :2; 3952 __I uint32_t reserved_01 :18; 3953 } bitfield; 3954 } CFG_DDR_SGMII_PHY_expert_addcmd_ln_readback_TypeDef; 3955 3956 typedef union{ /*!< expert_read_gate_controls register definition*/ 3957 __IO uint32_t expert_read_gate_controls; 3958 struct 3959 { 3960 __IO uint32_t dyn_ovr_rdgate_clksel :10; 3961 __IO uint32_t dyn_ovr_rdgate_steps180 :20; 3962 __I uint32_t reserved_01 :2; 3963 } bitfield; 3964 } CFG_DDR_SGMII_PHY_expert_read_gate_controls_TypeDef; 3965 3966 typedef union{ /*!< expert_dq_dqs_optimization0 register definition*/ 3967 __I uint32_t expert_dq_dqs_optimization0; 3968 struct 3969 { 3970 __I uint32_t dyn_ovr_dqdqs_data_match_lane0 :8; 3971 __I uint32_t dyn_ovr_dqdqs_data_match_lane1 :8; 3972 __I uint32_t dyn_ovr_dqdqs_data_match_lane2 :8; 3973 __I uint32_t dyn_ovr_dqdqs_data_match_lane3 :8; 3974 } bitfield; 3975 } CFG_DDR_SGMII_PHY_expert_dq_dqs_optimization0_TypeDef; 3976 3977 typedef union{ /*!< expert_dq_dqs_optimization1 register definition*/ 3978 __I uint32_t expert_dq_dqs_optimization1; 3979 struct 3980 { 3981 __I uint32_t dyn_ovr_dqdqs_data_match_lane4 :8; 3982 __I uint32_t reserved_01 :24; 3983 } bitfield; 3984 } CFG_DDR_SGMII_PHY_expert_dq_dqs_optimization1_TypeDef; 3985 3986 typedef union{ /*!< expert_wrcalib register definition*/ 3987 __IO uint32_t expert_wrcalib; 3988 struct 3989 { 3990 __IO uint32_t dyn_ovr_wrcalib_offset_lane0 :4; 3991 __IO uint32_t dyn_ovr_wrcalib_offset_lane1 :4; 3992 __IO uint32_t dyn_ovr_wrcalib_offset_lane2 :4; 3993 __IO uint32_t dyn_ovr_wrcalib_offset_lane3 :4; 3994 __IO uint32_t dyn_ovr_wrcalib_offset_lane4 :4; 3995 __I uint32_t reserved_01 :12; 3996 } bitfield; 3997 } CFG_DDR_SGMII_PHY_expert_wrcalib_TypeDef; 3998 3999 typedef union{ /*!< expert_calif register definition*/ 4000 __IO uint32_t expert_calif; 4001 struct 4002 { 4003 __IO uint32_t dyn_ovr_calif_read :1; 4004 __IO uint32_t dyn_ovr_calif_write :1; 4005 __IO uint32_t dyn_ovr_pattern_sel :4; 4006 __I uint32_t reserved_01 :26; 4007 } bitfield; 4008 } CFG_DDR_SGMII_PHY_expert_calif_TypeDef; 4009 4010 typedef union{ /*!< expert_calif_readback register definition*/ 4011 __I uint32_t expert_calif_readback; 4012 struct 4013 { 4014 __I uint32_t wrcalib_pattern_match_lane0 :8; 4015 __I uint32_t wrcalib_pattern_match_lane1 :8; 4016 __I uint32_t wrcalib_pattern_match_lane2 :8; 4017 __I uint32_t wrcalib_pattern_match_lane3 :8; 4018 } bitfield; 4019 } CFG_DDR_SGMII_PHY_expert_calif_readback_TypeDef; 4020 4021 typedef union{ /*!< expert_calif_readback1 register definition*/ 4022 __I uint32_t expert_calif_readback1; 4023 struct 4024 { 4025 __I uint32_t wrcalib_pattern_match_lane4 :8; 4026 __I uint32_t reserved_01 :24; 4027 } bitfield; 4028 } CFG_DDR_SGMII_PHY_expert_calif_readback1_TypeDef; 4029 4030 typedef union{ /*!< expert_dfi_status_override_to_shim register definition*/ 4031 __IO uint32_t expert_dfi_status_override_to_shim; 4032 struct 4033 { 4034 __IO uint32_t dfi_init_complete_shim :1; 4035 __IO uint32_t dfi_training_complete_shim :1; 4036 __IO uint32_t dfi_wrlvl_en_shim :1; 4037 __IO uint32_t dfi_rdlvl_en_shim :1; 4038 __IO uint32_t dfi_rdlvl_gate_en_shim :1; 4039 __I uint32_t reserved_01 :27; 4040 } bitfield; 4041 } CFG_DDR_SGMII_PHY_expert_dfi_status_override_to_shim_TypeDef; 4042 4043 typedef union{ /*!< tip_cfg_params register definition*/ 4044 __IO uint32_t tip_cfg_params; 4045 struct 4046 { 4047 __IO uint32_t addcmd_offset :3; 4048 __IO uint32_t bcklsclk_offset :3; 4049 __IO uint32_t wrcalib_write_count :7; 4050 __IO uint32_t read_gate_min_reads :9; 4051 __IO uint32_t addrcmd_wait_count :9; 4052 __I uint32_t reserved_01 :1; 4053 } bitfield; 4054 } CFG_DDR_SGMII_PHY_tip_cfg_params_TypeDef; 4055 4056 typedef union{ /*!< tip_vref_param register definition*/ 4057 __IO uint32_t tip_vref_param; 4058 struct 4059 { 4060 __IO uint32_t vref_override :1; 4061 __IO uint32_t data_vref :8; 4062 __IO uint32_t ca_vref :8; 4063 __I uint32_t reserved_01 :15; 4064 } bitfield; 4065 } CFG_DDR_SGMII_PHY_tip_vref_param_TypeDef; 4066 4067 typedef union{ /*!< lane_alignment_fifo_control register definition*/ 4068 __IO uint32_t lane_alignment_fifo_control; 4069 struct 4070 { 4071 __IO uint32_t block_fifo :1; 4072 __IO uint32_t fifo_reset_n :1; 4073 __I uint32_t reserved_01 :30; 4074 } bitfield; 4075 } CFG_DDR_SGMII_PHY_lane_alignment_fifo_control_TypeDef; 4076 4077 typedef union{ /*!< SOFT_RESET_SGMII register definition*/ 4078 __IO uint32_t SOFT_RESET_SGMII; 4079 struct 4080 { 4081 __O uint32_t nv_map_SGMII :1; 4082 __O uint32_t v_map_SGMII :1; 4083 __I uint32_t reserved_01 :6; 4084 __O uint32_t periph_SGMII :1; 4085 __I uint32_t reserved_02 :7; 4086 __I uint32_t blockid_SGMII :16; 4087 } bitfield; 4088 } CFG_DDR_SGMII_PHY_SOFT_RESET_SGMII_TypeDef; 4089 4090 typedef union{ /*!< SGMII_MODE register definition*/ 4091 __IO uint32_t SGMII_MODE; 4092 struct 4093 { 4094 __IO uint32_t reg_pll_en :1; 4095 __IO uint32_t reg_dll_en :1; 4096 __IO uint32_t reg_pvt_en :1; 4097 __IO uint32_t reg_bc_vrgen_en :1; 4098 __IO uint32_t reg_tx0_en :1; 4099 __IO uint32_t reg_rx0_en :1; 4100 __IO uint32_t reg_tx1_en :1; 4101 __IO uint32_t reg_rx1_en :1; 4102 __IO uint32_t reg_dll_lock_flt :2; 4103 __IO uint32_t reg_dll_adj_code :4; 4104 __IO uint32_t reg_rx0_cdr_reset_b :1; 4105 __IO uint32_t reg_rx1_cdr_reset_b :1; 4106 __IO uint32_t reg_bc_vrgen :6; 4107 __IO uint32_t reg_cdr_move_step :1; 4108 __IO uint32_t reg_refclk_en_rdiff :1; 4109 __IO uint32_t reg_bc_vs :4; 4110 __IO uint32_t reg_refclk_en_udrive_p :1; 4111 __IO uint32_t reg_refclk_en_ins_hyst_p :1; 4112 __IO uint32_t reg_refclk_en_udrive_n :1; 4113 __IO uint32_t reg_refclk_en_ins_hyst_n :1; 4114 } bitfield; 4115 } CFG_DDR_SGMII_PHY_SGMII_MODE_TypeDef; 4116 4117 typedef union{ /*!< PLL_CNTL register definition*/ 4118 __IO uint32_t PLL_CNTL; 4119 struct 4120 { 4121 __IO uint32_t reg_pll_postdiv :7; 4122 __I uint32_t aro_pll0_lock :1; 4123 __IO uint32_t reg_pll_rfdiv :6; 4124 __IO uint32_t reg_pll_reg_rfclk_sel :1; 4125 __IO uint32_t reg_pll_lp_requires_lock :1; 4126 __IO uint32_t reg_pll_intin :12; 4127 __IO uint32_t reg_pll_bwi :2; 4128 __IO uint32_t reg_pll_bwp :2; 4129 } bitfield; 4130 } CFG_DDR_SGMII_PHY_PLL_CNTL_TypeDef; 4131 4132 typedef union{ /*!< CH0_CNTL register definition*/ 4133 __IO uint32_t CH0_CNTL; 4134 struct 4135 { 4136 __IO uint32_t reg_tx0_wpu_p :1; 4137 __IO uint32_t reg_tx0_wpd_p :1; 4138 __IO uint32_t reg_tx0_slew_p :2; 4139 __IO uint32_t reg_tx0_drv_p :4; 4140 __IO uint32_t reg_tx0_odt_p :4; 4141 __IO uint32_t reg_tx0_odt_static_p :3; 4142 __IO uint32_t reg_rx0_tim_long :1; 4143 __IO uint32_t reg_rx0_wpu_p :1; 4144 __IO uint32_t reg_rx0_wpd_p :1; 4145 __IO uint32_t reg_rx0_ibufmd_p :3; 4146 __IO uint32_t reg_rx0_eyewidth_p :3; 4147 __IO uint32_t reg_rx0_odt_p :4; 4148 __IO uint32_t reg_rx0_odt_static_p :3; 4149 __I uint32_t reserved_01 :1; 4150 } bitfield; 4151 } CFG_DDR_SGMII_PHY_CH0_CNTL_TypeDef; 4152 4153 typedef union{ /*!< CH1_CNTL register definition*/ 4154 __IO uint32_t CH1_CNTL; 4155 struct 4156 { 4157 __IO uint32_t reg_tx1_wpu_p :1; 4158 __IO uint32_t reg_tx1_wpd_p :1; 4159 __IO uint32_t reg_tx1_slew_p :2; 4160 __IO uint32_t reg_tx1_drv_p :4; 4161 __IO uint32_t reg_tx1_odt_p :4; 4162 __IO uint32_t reg_tx1_odt_static_p :3; 4163 __IO uint32_t reg_rx1_tim_long :1; 4164 __IO uint32_t reg_rx1_wpu_p :1; 4165 __IO uint32_t reg_rx1_wpd_p :1; 4166 __IO uint32_t reg_rx1_ibufmd_p :3; 4167 __IO uint32_t reg_rx1_eyewidth_p :3; 4168 __IO uint32_t reg_rx1_odt_p :4; 4169 __IO uint32_t reg_rx1_odt_static_p :3; 4170 __I uint32_t reserved_01 :1; 4171 } bitfield; 4172 } CFG_DDR_SGMII_PHY_CH1_CNTL_TypeDef; 4173 4174 typedef union{ /*!< RECAL_CNTL register definition*/ 4175 __IO uint32_t RECAL_CNTL; 4176 struct 4177 { 4178 __IO uint32_t reg_recal_diff_range :5; 4179 __IO uint32_t reg_recal_start_en :1; 4180 __IO uint32_t reg_pvt_calib_start :1; 4181 __IO uint32_t reg_pvt_calib_lock :1; 4182 __IO uint32_t reg_recal_upd :1; 4183 __IO uint32_t bc_vrgen_direction :1; 4184 __IO uint32_t bc_vrgen_load :1; 4185 __IO uint32_t bc_vrgen_move :1; 4186 __IO uint32_t reg_pvt_reg_calib_clkdiv :2; 4187 __IO uint32_t reg_pvt_reg_calib_diffr_vsel :2; 4188 __I uint32_t sro_dll_90_code :7; 4189 __I uint32_t sro_dll_lock :1; 4190 __I uint32_t sro_dll_st_code :7; 4191 __I uint32_t sro_recal_start :1; 4192 } bitfield; 4193 } CFG_DDR_SGMII_PHY_RECAL_CNTL_TypeDef; 4194 4195 typedef union{ /*!< CLK_CNTL register definition*/ 4196 __IO uint32_t CLK_CNTL; 4197 struct 4198 { 4199 __IO uint32_t reg_refclk_en_term_p :2; 4200 __IO uint32_t reg_refclk_en_rxmode_p :2; 4201 __IO uint32_t reg_refclk_en_term_n :2; 4202 __IO uint32_t reg_refclk_en_rxmode_n :2; 4203 __IO uint32_t reg_refclk_clkbuf_en_pullup :1; 4204 __IO uint32_t reg_clkmux_fclk_sel :3; 4205 __IO uint32_t reg_clkmux_pll0_rfclk0_sel :2; 4206 __IO uint32_t reg_clkmux_pll0_rfclk1_sel :2; 4207 __IO uint32_t reg_clkmux_spare0 :16; 4208 } bitfield; 4209 } CFG_DDR_SGMII_PHY_CLK_CNTL_TypeDef; 4210 4211 typedef union{ /*!< DYN_CNTL register definition*/ 4212 __IO uint32_t DYN_CNTL; 4213 struct 4214 { 4215 __IO uint32_t reg_pll_dynen :1; 4216 __IO uint32_t reg_dll_dynen :1; 4217 __IO uint32_t reg_pvt_dynen :1; 4218 __IO uint32_t reg_bc_dynen :1; 4219 __IO uint32_t reg_clkmux_dynen :1; 4220 __IO uint32_t reg_lane0_dynen :1; 4221 __IO uint32_t reg_lane1_dynen :1; 4222 __I uint32_t bc_vrgen_oor :1; 4223 __IO uint32_t reg_pll_soft_reset_periph :1; 4224 __IO uint32_t reg_dll_soft_reset_periph :1; 4225 __IO uint32_t reg_pvt_soft_reset_periph :1; 4226 __IO uint32_t reg_bc_soft_reset_periph :1; 4227 __IO uint32_t reg_clkmux_soft_reset_periph :1; 4228 __IO uint32_t reg_lane0_soft_reset_periph :1; 4229 __IO uint32_t reg_lane1_soft_reset_periph :1; 4230 __I uint32_t pvt_calib_status :1; 4231 __I uint32_t aro_pll0_vco0ph_sel :3; 4232 __I uint32_t aro_pll0_vco1ph_sel :3; 4233 __I uint32_t aro_pll0_vco2ph_sel :3; 4234 __I uint32_t aro_pll0_vco3ph_sel :3; 4235 __I uint32_t aro_ref_diffr :4; 4236 } bitfield; 4237 } CFG_DDR_SGMII_PHY_DYN_CNTL_TypeDef; 4238 4239 typedef union{ /*!< PVT_STAT register definition*/ 4240 __IO uint32_t PVT_STAT; 4241 struct 4242 { 4243 __I uint32_t aro_ref_pcode :6; 4244 __I uint32_t aro_ioen_bnk :1; 4245 __I uint32_t aro_ioen_bnk_b :1; 4246 __I uint32_t aro_ref_ncode :6; 4247 __I uint32_t aro_calib_status :1; 4248 __I uint32_t aro_calib_status_b :1; 4249 __I uint32_t aro_pcode :6; 4250 __I uint32_t aro_calib_intrpt :1; 4251 __I uint32_t pvt_calib_intrpt :1; 4252 __I uint32_t aro_ncode :6; 4253 __IO uint32_t pvt_calib_lock :1; 4254 __IO uint32_t pvt_calib_start :1; 4255 } bitfield; 4256 } CFG_DDR_SGMII_PHY_PVT_STAT_TypeDef; 4257 4258 typedef union{ /*!< SPARE_CNTL register definition*/ 4259 __IO uint32_t SPARE_CNTL; 4260 struct 4261 { 4262 __IO uint32_t reg_spare :32; 4263 } bitfield; 4264 } CFG_DDR_SGMII_PHY_SPARE_CNTL_TypeDef; 4265 4266 typedef union{ /*!< SPARE_STAT register definition*/ 4267 __I uint32_t SPARE_STAT; 4268 struct 4269 { 4270 __I uint32_t sro_spare :32; 4271 } bitfield; 4272 } CFG_DDR_SGMII_PHY_SPARE_STAT_TypeDef; 4273 4274 /*------------ CFG_DDR_SGMII_PHY definition -----------*/ 4275 typedef struct 4276 { 4277 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_TypeDef SOFT_RESET_DDR_PHY; /*!< Offset: 0x0 */ 4278 __IO CFG_DDR_SGMII_PHY_DDRPHY_MODE_TypeDef DDRPHY_MODE; /*!< Offset: 0x4 */ 4279 __IO CFG_DDR_SGMII_PHY_DDRPHY_STARTUP_TypeDef DDRPHY_STARTUP; /*!< Offset: 0x8 */ 4280 __IO uint32_t UNUSED_SPACE0[29]; /*!< Offset: 0xc */ 4281 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_TypeDef SOFT_RESET_MAIN_PLL; /*!< Offset: 0x80 */ 4282 __IO CFG_DDR_SGMII_PHY_PLL_CTRL_MAIN_TypeDef PLL_CTRL_MAIN; /*!< Offset: 0x84 */ 4283 __IO CFG_DDR_SGMII_PHY_PLL_REF_FB_MAIN_TypeDef PLL_REF_FB_MAIN; /*!< Offset: 0x88 */ 4284 __I CFG_DDR_SGMII_PHY_PLL_FRACN_MAIN_TypeDef PLL_FRACN_MAIN; /*!< Offset: 0x8c */ 4285 __IO CFG_DDR_SGMII_PHY_PLL_DIV_0_1_MAIN_TypeDef PLL_DIV_0_1_MAIN; /*!< Offset: 0x90 */ 4286 __IO CFG_DDR_SGMII_PHY_PLL_DIV_2_3_MAIN_TypeDef PLL_DIV_2_3_MAIN; /*!< Offset: 0x94 */ 4287 __IO CFG_DDR_SGMII_PHY_PLL_CTRL2_MAIN_TypeDef PLL_CTRL2_MAIN; /*!< Offset: 0x98 */ 4288 __I CFG_DDR_SGMII_PHY_PLL_CAL_MAIN_TypeDef PLL_CAL_MAIN; /*!< Offset: 0x9c */ 4289 __IO CFG_DDR_SGMII_PHY_PLL_PHADJ_MAIN_TypeDef PLL_PHADJ_MAIN; /*!< Offset: 0xa0 */ 4290 __I CFG_DDR_SGMII_PHY_SSCG_REG_0_MAIN_TypeDef SSCG_REG_0_MAIN; /*!< Offset: 0xa4 */ 4291 __I CFG_DDR_SGMII_PHY_SSCG_REG_1_MAIN_TypeDef SSCG_REG_1_MAIN; /*!< Offset: 0xa8 */ 4292 __IO CFG_DDR_SGMII_PHY_SSCG_REG_2_MAIN_TypeDef SSCG_REG_2_MAIN; /*!< Offset: 0xac */ 4293 __I CFG_DDR_SGMII_PHY_SSCG_REG_3_MAIN_TypeDef SSCG_REG_3_MAIN; /*!< Offset: 0xb0 */ 4294 __IO CFG_DDR_SGMII_PHY_RPC_RESET_MAIN_PLL_TypeDef RPC_RESET_MAIN_PLL; /*!< Offset: 0xb4 */ 4295 __I uint32_t UNUSED_SPACE1[18]; /*!< Offset: 0xb8 */ 4296 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_TypeDef SOFT_RESET_IOSCB_PLL; /*!< Offset: 0x100 */ 4297 __IO CFG_DDR_SGMII_PHY_PLL_CTRL_IOSCB_TypeDef PLL_CTRL_IOSCB; /*!< Offset: 0x104 */ 4298 __IO CFG_DDR_SGMII_PHY_PLL_REF_FB_IOSCB_TypeDef PLL_REF_FB_IOSCB; /*!< Offset: 0x108 */ 4299 __I CFG_DDR_SGMII_PHY_PLL_FRACN_IOSCB_TypeDef PLL_FRACN_IOSCB; /*!< Offset: 0x10c */ 4300 __IO CFG_DDR_SGMII_PHY_PLL_DIV_0_1_IOSCB_TypeDef PLL_DIV_0_1_IOSCB; /*!< Offset: 0x110 */ 4301 __IO CFG_DDR_SGMII_PHY_PLL_DIV_2_3_IOSCB_TypeDef PLL_DIV_2_3_IOSCB; /*!< Offset: 0x114 */ 4302 __IO CFG_DDR_SGMII_PHY_PLL_CTRL2_IOSCB_TypeDef PLL_CTRL2_IOSCB; /*!< Offset: 0x118 */ 4303 __I CFG_DDR_SGMII_PHY_PLL_CAL_IOSCB_TypeDef PLL_CAL_IOSCB; /*!< Offset: 0x11c */ 4304 __IO CFG_DDR_SGMII_PHY_PLL_PHADJ_IOSCB_TypeDef PLL_PHADJ_IOSCB; /*!< Offset: 0x120 */ 4305 __I CFG_DDR_SGMII_PHY_SSCG_REG_0_IOSCB_TypeDef SSCG_REG_0_IOSCB; /*!< Offset: 0x124 */ 4306 __I CFG_DDR_SGMII_PHY_SSCG_REG_1_IOSCB_TypeDef SSCG_REG_1_IOSCB; /*!< Offset: 0x128 */ 4307 __IO CFG_DDR_SGMII_PHY_SSCG_REG_2_IOSCB_TypeDef SSCG_REG_2_IOSCB; /*!< Offset: 0x12c */ 4308 __I CFG_DDR_SGMII_PHY_SSCG_REG_3_IOSCB_TypeDef SSCG_REG_3_IOSCB; /*!< Offset: 0x130 */ 4309 __IO CFG_DDR_SGMII_PHY_RPC_RESET_IOSCB_TypeDef RPC_RESET_IOSCB; /*!< Offset: 0x134 */ 4310 __I uint32_t UNUSED_SPACE2[18]; /*!< Offset: 0x138 */ 4311 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_TypeDef SOFT_RESET_BANK_CTRL; /*!< Offset: 0x180 */ 4312 __IO CFG_DDR_SGMII_PHY_DPC_BITS_TypeDef DPC_BITS; /*!< Offset: 0x184 */ 4313 __I CFG_DDR_SGMII_PHY_BANK_STATUS_TypeDef BANK_STATUS; /*!< Offset: 0x188 */ 4314 __IO CFG_DDR_SGMII_PHY_RPC_RESET_BANK_CTRL_TypeDef RPC_RESET_BANK_CTRL; /*!< Offset: 0x18c */ 4315 __I uint32_t UNUSED_SPACE3[28]; /*!< Offset: 0x190 */ 4316 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_TypeDef SOFT_RESET_IOCALIB; /*!< Offset: 0x200 */ 4317 __IO CFG_DDR_SGMII_PHY_IOC_REG0_TypeDef IOC_REG0; /*!< Offset: 0x204 */ 4318 __I CFG_DDR_SGMII_PHY_IOC_REG1_TypeDef IOC_REG1; /*!< Offset: 0x208 */ 4319 __I CFG_DDR_SGMII_PHY_IOC_REG2_TypeDef IOC_REG2; /*!< Offset: 0x20c */ 4320 __I CFG_DDR_SGMII_PHY_IOC_REG3_TypeDef IOC_REG3; /*!< Offset: 0x210 */ 4321 __I CFG_DDR_SGMII_PHY_IOC_REG4_TypeDef IOC_REG4; /*!< Offset: 0x214 */ 4322 __I CFG_DDR_SGMII_PHY_IOC_REG5_TypeDef IOC_REG5; /*!< Offset: 0x218 */ 4323 __IO CFG_DDR_SGMII_PHY_IOC_REG6_TypeDef IOC_REG6; /*!< Offset: 0x21c */ 4324 __IO CFG_DDR_SGMII_PHY_RPC_RESET_IOCALIB_TypeDef RPC_RESET_IOCALIB; /*!< Offset: 0x220 */ 4325 __IO CFG_DDR_SGMII_PHY_rpc_calib_TypeDef rpc_calib; /*!< Offset: 0x224 */ 4326 __I uint32_t UNUSED_SPACE4[22]; /*!< Offset: 0x228 */ 4327 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_TypeDef SOFT_RESET_CFM; /*!< Offset: 0x280 */ 4328 __IO CFG_DDR_SGMII_PHY_BCLKMUX_TypeDef BCLKMUX; /*!< Offset: 0x284 */ 4329 __IO CFG_DDR_SGMII_PHY_PLL_CKMUX_TypeDef PLL_CKMUX; /*!< Offset: 0x288 */ 4330 __IO CFG_DDR_SGMII_PHY_MSSCLKMUX_TypeDef MSSCLKMUX; /*!< Offset: 0x28c */ 4331 __IO CFG_DDR_SGMII_PHY_SPARE0_TypeDef SPARE0; /*!< Offset: 0x290 */ 4332 __I CFG_DDR_SGMII_PHY_FMETER_ADDR_TypeDef FMETER_ADDR; /*!< Offset: 0x294 */ 4333 __I CFG_DDR_SGMII_PHY_FMETER_DATAW_TypeDef FMETER_DATAW; /*!< Offset: 0x298 */ 4334 __I CFG_DDR_SGMII_PHY_FMETER_DATAR_TypeDef FMETER_DATAR; /*!< Offset: 0x29c */ 4335 __I CFG_DDR_SGMII_PHY_TEST_CTRL_TypeDef TEST_CTRL; /*!< Offset: 0x2a0 */ 4336 __IO CFG_DDR_SGMII_PHY_RPC_RESET_CFM_TypeDef RPC_RESET_CFM; /*!< Offset: 0x2a4 */ 4337 __I uint32_t UNUSED_SPACE5[22]; /*!< Offset: 0x2a8 */ 4338 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_TypeDef SOFT_RESET_DECODER_DRIVER; /*!< Offset: 0x300 */ 4339 __IO CFG_DDR_SGMII_PHY_rpc1_DRV_TypeDef rpc1_DRV; /*!< Offset: 0x304 */ 4340 __IO CFG_DDR_SGMII_PHY_rpc2_DRV_TypeDef rpc2_DRV; /*!< Offset: 0x308 */ 4341 __IO CFG_DDR_SGMII_PHY_rpc3_DRV_TypeDef rpc3_DRV; /*!< Offset: 0x30c */ 4342 __IO CFG_DDR_SGMII_PHY_rpc4_DRV_TypeDef rpc4_DRV; /*!< Offset: 0x310 */ 4343 __I uint32_t UNUSED_SPACE6[27]; /*!< Offset: 0x314 */ 4344 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_TypeDef SOFT_RESET_DECODER_ODT; /*!< Offset: 0x380 */ 4345 __IO CFG_DDR_SGMII_PHY_rpc1_ODT_TypeDef rpc1_ODT; /*!< Offset: 0x384 */ 4346 __IO CFG_DDR_SGMII_PHY_rpc2_ODT_TypeDef rpc2_ODT; /*!< Offset: 0x388 */ 4347 __IO CFG_DDR_SGMII_PHY_rpc3_ODT_TypeDef rpc3_ODT; /*!< Offset: 0x38c */ 4348 __IO CFG_DDR_SGMII_PHY_rpc4_ODT_TypeDef rpc4_ODT; /*!< Offset: 0x390 */ 4349 __IO CFG_DDR_SGMII_PHY_rpc5_ODT_TypeDef rpc5_ODT; /*!< Offset: 0x394 */ 4350 __IO CFG_DDR_SGMII_PHY_rpc6_ODT_TypeDef rpc6_ODT; /*!< Offset: 0x398 */ 4351 __IO CFG_DDR_SGMII_PHY_rpc7_ODT_TypeDef rpc7_ODT; /*!< Offset: 0x39c */ 4352 __IO CFG_DDR_SGMII_PHY_rpc8_ODT_TypeDef rpc8_ODT; /*!< Offset: 0x3a0 */ 4353 __IO CFG_DDR_SGMII_PHY_rpc9_ODT_TypeDef rpc9_ODT; /*!< Offset: 0x3a4 */ 4354 __IO CFG_DDR_SGMII_PHY_rpc10_ODT_TypeDef rpc10_ODT; /*!< Offset: 0x3a8 */ 4355 __IO CFG_DDR_SGMII_PHY_rpc11_ODT_TypeDef rpc11_ODT; /*!< Offset: 0x3ac */ 4356 __I uint32_t UNUSED_SPACE7[20]; /*!< Offset: 0x3b0 */ 4357 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_TypeDef SOFT_RESET_DECODER_IO; /*!< Offset: 0x400 */ 4358 __IO CFG_DDR_SGMII_PHY_ovrt1_TypeDef ovrt1; /*!< Offset: 0x404 */ 4359 __IO CFG_DDR_SGMII_PHY_ovrt2_TypeDef ovrt2; /*!< Offset: 0x408 */ 4360 __IO CFG_DDR_SGMII_PHY_ovrt3_TypeDef ovrt3; /*!< Offset: 0x40c */ 4361 __IO CFG_DDR_SGMII_PHY_ovrt4_TypeDef ovrt4; /*!< Offset: 0x410 */ 4362 __IO CFG_DDR_SGMII_PHY_ovrt5_TypeDef ovrt5; /*!< Offset: 0x414 */ 4363 __IO CFG_DDR_SGMII_PHY_ovrt6_TypeDef ovrt6; /*!< Offset: 0x418 */ 4364 __IO CFG_DDR_SGMII_PHY_ovrt7_TypeDef ovrt7; /*!< Offset: 0x41c */ 4365 __IO CFG_DDR_SGMII_PHY_ovrt8_TypeDef ovrt8; /*!< Offset: 0x420 */ 4366 __IO CFG_DDR_SGMII_PHY_ovrt9_TypeDef ovrt9; /*!< Offset: 0x424 */ 4367 __IO CFG_DDR_SGMII_PHY_ovrt10_TypeDef ovrt10; /*!< Offset: 0x428 */ 4368 __IO CFG_DDR_SGMII_PHY_ovrt11_TypeDef ovrt11; /*!< Offset: 0x42c */ 4369 __IO CFG_DDR_SGMII_PHY_ovrt12_TypeDef ovrt12; /*!< Offset: 0x430 */ 4370 __IO CFG_DDR_SGMII_PHY_ovrt13_TypeDef ovrt13; /*!< Offset: 0x434 */ 4371 __IO CFG_DDR_SGMII_PHY_ovrt14_TypeDef ovrt14; /*!< Offset: 0x438 */ 4372 __IO CFG_DDR_SGMII_PHY_ovrt15_TypeDef ovrt15; /*!< Offset: 0x43c */ 4373 __IO CFG_DDR_SGMII_PHY_ovrt16_TypeDef ovrt16; /*!< Offset: 0x440 */ 4374 __IO CFG_DDR_SGMII_PHY_rpc17_TypeDef rpc17; /*!< Offset: 0x444 */ 4375 __IO CFG_DDR_SGMII_PHY_rpc18_TypeDef rpc18; /*!< Offset: 0x448 */ 4376 __IO CFG_DDR_SGMII_PHY_rpc19_TypeDef rpc19; /*!< Offset: 0x44c */ 4377 __IO CFG_DDR_SGMII_PHY_rpc20_TypeDef rpc20; /*!< Offset: 0x450 */ 4378 __IO CFG_DDR_SGMII_PHY_rpc21_TypeDef rpc21; /*!< Offset: 0x454 */ 4379 __IO CFG_DDR_SGMII_PHY_rpc22_TypeDef rpc22; /*!< Offset: 0x458 */ 4380 __IO CFG_DDR_SGMII_PHY_rpc23_TypeDef rpc23; /*!< Offset: 0x45c */ 4381 __IO CFG_DDR_SGMII_PHY_rpc24_TypeDef rpc24; /*!< Offset: 0x460 */ 4382 __IO CFG_DDR_SGMII_PHY_rpc25_TypeDef rpc25; /*!< Offset: 0x464 */ 4383 __IO CFG_DDR_SGMII_PHY_rpc26_TypeDef rpc26; /*!< Offset: 0x468 */ 4384 __IO CFG_DDR_SGMII_PHY_rpc27_TypeDef rpc27; /*!< Offset: 0x46c */ 4385 __IO CFG_DDR_SGMII_PHY_rpc28_TypeDef rpc28; /*!< Offset: 0x470 */ 4386 __IO CFG_DDR_SGMII_PHY_rpc29_TypeDef rpc29; /*!< Offset: 0x474 */ 4387 __IO CFG_DDR_SGMII_PHY_rpc30_TypeDef rpc30; /*!< Offset: 0x478 */ 4388 __IO CFG_DDR_SGMII_PHY_rpc31_TypeDef rpc31; /*!< Offset: 0x47c */ 4389 __IO CFG_DDR_SGMII_PHY_rpc32_TypeDef rpc32; /*!< Offset: 0x480 */ 4390 __IO CFG_DDR_SGMII_PHY_rpc33_TypeDef rpc33; /*!< Offset: 0x484 */ 4391 __IO CFG_DDR_SGMII_PHY_rpc34_TypeDef rpc34; /*!< Offset: 0x488 */ 4392 __IO CFG_DDR_SGMII_PHY_rpc35_TypeDef rpc35; /*!< Offset: 0x48c */ 4393 __IO CFG_DDR_SGMII_PHY_rpc36_TypeDef rpc36; /*!< Offset: 0x490 */ 4394 __IO CFG_DDR_SGMII_PHY_rpc37_TypeDef rpc37; /*!< Offset: 0x494 */ 4395 __IO CFG_DDR_SGMII_PHY_rpc38_TypeDef rpc38; /*!< Offset: 0x498 */ 4396 __IO CFG_DDR_SGMII_PHY_rpc39_TypeDef rpc39; /*!< Offset: 0x49c */ 4397 __IO CFG_DDR_SGMII_PHY_rpc40_TypeDef rpc40; /*!< Offset: 0x4a0 */ 4398 __IO CFG_DDR_SGMII_PHY_rpc41_TypeDef rpc41; /*!< Offset: 0x4a4 */ 4399 __IO CFG_DDR_SGMII_PHY_rpc42_TypeDef rpc42; /*!< Offset: 0x4a8 */ 4400 __IO CFG_DDR_SGMII_PHY_rpc43_TypeDef rpc43; /*!< Offset: 0x4ac */ 4401 __IO CFG_DDR_SGMII_PHY_rpc44_TypeDef rpc44; /*!< Offset: 0x4b0 */ 4402 __IO CFG_DDR_SGMII_PHY_rpc45_TypeDef rpc45; /*!< Offset: 0x4b4 */ 4403 __IO CFG_DDR_SGMII_PHY_rpc46_TypeDef rpc46; /*!< Offset: 0x4b8 */ 4404 __IO CFG_DDR_SGMII_PHY_rpc47_TypeDef rpc47; /*!< Offset: 0x4bc */ 4405 __IO CFG_DDR_SGMII_PHY_rpc48_TypeDef rpc48; /*!< Offset: 0x4c0 */ 4406 __IO CFG_DDR_SGMII_PHY_rpc49_TypeDef rpc49; /*!< Offset: 0x4c4 */ 4407 __IO CFG_DDR_SGMII_PHY_rpc50_TypeDef rpc50; /*!< Offset: 0x4c8 */ 4408 __IO CFG_DDR_SGMII_PHY_rpc51_TypeDef rpc51; /*!< Offset: 0x4cc */ 4409 __IO CFG_DDR_SGMII_PHY_rpc52_TypeDef rpc52; /*!< Offset: 0x4d0 */ 4410 __IO CFG_DDR_SGMII_PHY_rpc53_TypeDef rpc53; /*!< Offset: 0x4d4 */ 4411 __IO CFG_DDR_SGMII_PHY_rpc54_TypeDef rpc54; /*!< Offset: 0x4d8 */ 4412 __IO CFG_DDR_SGMII_PHY_rpc55_TypeDef rpc55; /*!< Offset: 0x4dc */ 4413 __IO CFG_DDR_SGMII_PHY_rpc56_TypeDef rpc56; /*!< Offset: 0x4e0 */ 4414 __IO CFG_DDR_SGMII_PHY_rpc57_TypeDef rpc57; /*!< Offset: 0x4e4 */ 4415 __IO CFG_DDR_SGMII_PHY_rpc58_TypeDef rpc58; /*!< Offset: 0x4e8 */ 4416 __IO CFG_DDR_SGMII_PHY_rpc59_TypeDef rpc59; /*!< Offset: 0x4ec */ 4417 __IO CFG_DDR_SGMII_PHY_rpc60_TypeDef rpc60; /*!< Offset: 0x4f0 */ 4418 __IO CFG_DDR_SGMII_PHY_rpc61_TypeDef rpc61; /*!< Offset: 0x4f4 */ 4419 __IO CFG_DDR_SGMII_PHY_rpc62_TypeDef rpc62; /*!< Offset: 0x4f8 */ 4420 __IO CFG_DDR_SGMII_PHY_rpc63_TypeDef rpc63; /*!< Offset: 0x4fc */ 4421 __IO CFG_DDR_SGMII_PHY_rpc64_TypeDef rpc64; /*!< Offset: 0x500 */ 4422 __IO CFG_DDR_SGMII_PHY_rpc65_TypeDef rpc65; /*!< Offset: 0x504 */ 4423 __IO CFG_DDR_SGMII_PHY_rpc66_TypeDef rpc66; /*!< Offset: 0x508 */ 4424 __IO CFG_DDR_SGMII_PHY_rpc67_TypeDef rpc67; /*!< Offset: 0x50c */ 4425 __IO CFG_DDR_SGMII_PHY_rpc68_TypeDef rpc68; /*!< Offset: 0x510 */ 4426 __IO CFG_DDR_SGMII_PHY_rpc69_TypeDef rpc69; /*!< Offset: 0x514 */ 4427 __IO CFG_DDR_SGMII_PHY_rpc70_TypeDef rpc70; /*!< Offset: 0x518 */ 4428 __IO CFG_DDR_SGMII_PHY_rpc71_TypeDef rpc71; /*!< Offset: 0x51c */ 4429 __IO CFG_DDR_SGMII_PHY_rpc72_TypeDef rpc72; /*!< Offset: 0x520 */ 4430 __IO CFG_DDR_SGMII_PHY_rpc73_TypeDef rpc73; /*!< Offset: 0x524 */ 4431 __IO CFG_DDR_SGMII_PHY_rpc74_TypeDef rpc74; /*!< Offset: 0x528 */ 4432 __IO CFG_DDR_SGMII_PHY_rpc75_TypeDef rpc75; /*!< Offset: 0x52c */ 4433 __IO CFG_DDR_SGMII_PHY_rpc76_TypeDef rpc76; /*!< Offset: 0x530 */ 4434 __IO CFG_DDR_SGMII_PHY_rpc77_TypeDef rpc77; /*!< Offset: 0x534 */ 4435 __IO CFG_DDR_SGMII_PHY_rpc78_TypeDef rpc78; /*!< Offset: 0x538 */ 4436 __IO CFG_DDR_SGMII_PHY_rpc79_TypeDef rpc79; /*!< Offset: 0x53c */ 4437 __IO CFG_DDR_SGMII_PHY_rpc80_TypeDef rpc80; /*!< Offset: 0x540 */ 4438 __IO CFG_DDR_SGMII_PHY_rpc81_TypeDef rpc81; /*!< Offset: 0x544 */ 4439 __IO CFG_DDR_SGMII_PHY_rpc82_TypeDef rpc82; /*!< Offset: 0x548 */ 4440 __IO CFG_DDR_SGMII_PHY_rpc83_TypeDef rpc83; /*!< Offset: 0x54c */ 4441 __IO CFG_DDR_SGMII_PHY_rpc84_TypeDef rpc84; /*!< Offset: 0x550 */ 4442 __IO CFG_DDR_SGMII_PHY_rpc85_TypeDef rpc85; /*!< Offset: 0x554 */ 4443 __IO CFG_DDR_SGMII_PHY_rpc86_TypeDef rpc86; /*!< Offset: 0x558 */ 4444 __IO CFG_DDR_SGMII_PHY_rpc87_TypeDef rpc87; /*!< Offset: 0x55c */ 4445 __IO CFG_DDR_SGMII_PHY_rpc88_TypeDef rpc88; /*!< Offset: 0x560 */ 4446 __IO CFG_DDR_SGMII_PHY_rpc89_TypeDef rpc89; /*!< Offset: 0x564 */ 4447 __IO CFG_DDR_SGMII_PHY_rpc90_TypeDef rpc90; /*!< Offset: 0x568 */ 4448 __IO CFG_DDR_SGMII_PHY_rpc91_TypeDef rpc91; /*!< Offset: 0x56c */ 4449 __IO CFG_DDR_SGMII_PHY_rpc92_TypeDef rpc92; /*!< Offset: 0x570 */ 4450 __IO CFG_DDR_SGMII_PHY_rpc93_TypeDef rpc93; /*!< Offset: 0x574 */ 4451 __IO CFG_DDR_SGMII_PHY_rpc94_TypeDef rpc94; /*!< Offset: 0x578 */ 4452 __IO CFG_DDR_SGMII_PHY_rpc95_TypeDef rpc95; /*!< Offset: 0x57c */ 4453 __IO CFG_DDR_SGMII_PHY_rpc96_TypeDef rpc96; /*!< Offset: 0x580 */ 4454 __IO CFG_DDR_SGMII_PHY_rpc97_TypeDef rpc97; /*!< Offset: 0x584 */ 4455 __IO CFG_DDR_SGMII_PHY_rpc98_TypeDef rpc98; /*!< Offset: 0x588 */ 4456 __IO CFG_DDR_SGMII_PHY_rpc99_TypeDef rpc99; /*!< Offset: 0x58c */ 4457 __IO CFG_DDR_SGMII_PHY_rpc100_TypeDef rpc100; /*!< Offset: 0x590 */ 4458 __IO CFG_DDR_SGMII_PHY_rpc101_TypeDef rpc101; /*!< Offset: 0x594 */ 4459 __IO CFG_DDR_SGMII_PHY_rpc102_TypeDef rpc102; /*!< Offset: 0x598 */ 4460 __IO CFG_DDR_SGMII_PHY_rpc103_TypeDef rpc103; /*!< Offset: 0x59c */ 4461 __IO CFG_DDR_SGMII_PHY_rpc104_TypeDef rpc104; /*!< Offset: 0x5a0 */ 4462 __IO CFG_DDR_SGMII_PHY_rpc105_TypeDef rpc105; /*!< Offset: 0x5a4 */ 4463 __IO CFG_DDR_SGMII_PHY_rpc106_TypeDef rpc106; /*!< Offset: 0x5a8 */ 4464 __IO CFG_DDR_SGMII_PHY_rpc107_TypeDef rpc107; /*!< Offset: 0x5ac */ 4465 __IO CFG_DDR_SGMII_PHY_rpc108_TypeDef rpc108; /*!< Offset: 0x5b0 */ 4466 __IO CFG_DDR_SGMII_PHY_rpc109_TypeDef rpc109; /*!< Offset: 0x5b4 */ 4467 __IO CFG_DDR_SGMII_PHY_rpc110_TypeDef rpc110; /*!< Offset: 0x5b8 */ 4468 __IO CFG_DDR_SGMII_PHY_rpc111_TypeDef rpc111; /*!< Offset: 0x5bc */ 4469 __IO CFG_DDR_SGMII_PHY_rpc112_TypeDef rpc112; /*!< Offset: 0x5c0 */ 4470 __IO CFG_DDR_SGMII_PHY_rpc113_TypeDef rpc113; /*!< Offset: 0x5c4 */ 4471 __IO CFG_DDR_SGMII_PHY_rpc114_TypeDef rpc114; /*!< Offset: 0x5c8 */ 4472 __IO CFG_DDR_SGMII_PHY_rpc115_TypeDef rpc115; /*!< Offset: 0x5cc */ 4473 __IO CFG_DDR_SGMII_PHY_rpc116_TypeDef rpc116; /*!< Offset: 0x5d0 */ 4474 __IO CFG_DDR_SGMII_PHY_rpc117_TypeDef rpc117; /*!< Offset: 0x5d4 */ 4475 __IO CFG_DDR_SGMII_PHY_rpc118_TypeDef rpc118; /*!< Offset: 0x5d8 */ 4476 __IO CFG_DDR_SGMII_PHY_rpc119_TypeDef rpc119; /*!< Offset: 0x5dc */ 4477 __IO CFG_DDR_SGMII_PHY_rpc120_TypeDef rpc120; /*!< Offset: 0x5e0 */ 4478 __IO CFG_DDR_SGMII_PHY_rpc121_TypeDef rpc121; /*!< Offset: 0x5e4 */ 4479 __IO CFG_DDR_SGMII_PHY_rpc122_TypeDef rpc122; /*!< Offset: 0x5e8 */ 4480 __IO CFG_DDR_SGMII_PHY_rpc123_TypeDef rpc123; /*!< Offset: 0x5ec */ 4481 __IO CFG_DDR_SGMII_PHY_rpc124_TypeDef rpc124; /*!< Offset: 0x5f0 */ 4482 __IO CFG_DDR_SGMII_PHY_rpc125_TypeDef rpc125; /*!< Offset: 0x5f4 */ 4483 __IO CFG_DDR_SGMII_PHY_rpc126_TypeDef rpc126; /*!< Offset: 0x5f8 */ 4484 __IO CFG_DDR_SGMII_PHY_rpc127_TypeDef rpc127; /*!< Offset: 0x5fc */ 4485 __IO CFG_DDR_SGMII_PHY_rpc128_TypeDef rpc128; /*!< Offset: 0x600 */ 4486 __IO CFG_DDR_SGMII_PHY_rpc129_TypeDef rpc129; /*!< Offset: 0x604 */ 4487 __IO CFG_DDR_SGMII_PHY_rpc130_TypeDef rpc130; /*!< Offset: 0x608 */ 4488 __IO CFG_DDR_SGMII_PHY_rpc131_TypeDef rpc131; /*!< Offset: 0x60c */ 4489 __IO CFG_DDR_SGMII_PHY_rpc132_TypeDef rpc132; /*!< Offset: 0x610 */ 4490 __IO CFG_DDR_SGMII_PHY_rpc133_TypeDef rpc133; /*!< Offset: 0x614 */ 4491 __IO CFG_DDR_SGMII_PHY_rpc134_TypeDef rpc134; /*!< Offset: 0x618 */ 4492 __IO CFG_DDR_SGMII_PHY_rpc135_TypeDef rpc135; /*!< Offset: 0x61c */ 4493 __IO CFG_DDR_SGMII_PHY_rpc136_TypeDef rpc136; /*!< Offset: 0x620 */ 4494 __IO CFG_DDR_SGMII_PHY_rpc137_TypeDef rpc137; /*!< Offset: 0x624 */ 4495 __IO CFG_DDR_SGMII_PHY_rpc138_TypeDef rpc138; /*!< Offset: 0x628 */ 4496 __IO CFG_DDR_SGMII_PHY_rpc139_TypeDef rpc139; /*!< Offset: 0x62c */ 4497 __IO CFG_DDR_SGMII_PHY_rpc140_TypeDef rpc140; /*!< Offset: 0x630 */ 4498 __IO CFG_DDR_SGMII_PHY_rpc141_TypeDef rpc141; /*!< Offset: 0x634 */ 4499 __IO CFG_DDR_SGMII_PHY_rpc142_TypeDef rpc142; /*!< Offset: 0x638 */ 4500 __IO CFG_DDR_SGMII_PHY_rpc143_TypeDef rpc143; /*!< Offset: 0x63c */ 4501 __IO CFG_DDR_SGMII_PHY_rpc144_TypeDef rpc144; /*!< Offset: 0x640 */ 4502 __IO CFG_DDR_SGMII_PHY_rpc145_TypeDef rpc145; /*!< Offset: 0x644 */ 4503 __IO CFG_DDR_SGMII_PHY_rpc146_TypeDef rpc146; /*!< Offset: 0x648 */ 4504 __IO CFG_DDR_SGMII_PHY_rpc147_TypeDef rpc147; /*!< Offset: 0x64c */ 4505 __IO CFG_DDR_SGMII_PHY_rpc148_TypeDef rpc148; /*!< Offset: 0x650 */ 4506 __IO CFG_DDR_SGMII_PHY_rpc149_TypeDef rpc149; /*!< Offset: 0x654 */ 4507 __IO CFG_DDR_SGMII_PHY_rpc150_TypeDef rpc150; /*!< Offset: 0x658 */ 4508 __IO CFG_DDR_SGMII_PHY_rpc151_TypeDef rpc151; /*!< Offset: 0x65c */ 4509 __IO CFG_DDR_SGMII_PHY_rpc152_TypeDef rpc152; /*!< Offset: 0x660 */ 4510 __IO CFG_DDR_SGMII_PHY_rpc153_TypeDef rpc153; /*!< Offset: 0x664 */ 4511 __IO CFG_DDR_SGMII_PHY_rpc154_TypeDef rpc154; /*!< Offset: 0x668 */ 4512 __IO CFG_DDR_SGMII_PHY_rpc155_TypeDef rpc155; /*!< Offset: 0x66c */ 4513 __IO CFG_DDR_SGMII_PHY_rpc156_TypeDef rpc156; /*!< Offset: 0x670 */ 4514 __IO CFG_DDR_SGMII_PHY_rpc157_TypeDef rpc157; /*!< Offset: 0x674 */ 4515 __IO CFG_DDR_SGMII_PHY_rpc158_TypeDef rpc158; /*!< Offset: 0x678 */ 4516 __IO CFG_DDR_SGMII_PHY_rpc159_TypeDef rpc159; /*!< Offset: 0x67c */ 4517 __IO CFG_DDR_SGMII_PHY_rpc160_TypeDef rpc160; /*!< Offset: 0x680 */ 4518 __IO CFG_DDR_SGMII_PHY_rpc161_TypeDef rpc161; /*!< Offset: 0x684 */ 4519 __IO CFG_DDR_SGMII_PHY_rpc162_TypeDef rpc162; /*!< Offset: 0x688 */ 4520 __IO CFG_DDR_SGMII_PHY_rpc163_TypeDef rpc163; /*!< Offset: 0x68c */ 4521 __IO CFG_DDR_SGMII_PHY_rpc164_TypeDef rpc164; /*!< Offset: 0x690 */ 4522 __IO CFG_DDR_SGMII_PHY_rpc165_TypeDef rpc165; /*!< Offset: 0x694 */ 4523 __IO CFG_DDR_SGMII_PHY_rpc166_TypeDef rpc166; /*!< Offset: 0x698 */ 4524 __IO CFG_DDR_SGMII_PHY_rpc167_TypeDef rpc167; /*!< Offset: 0x69c */ 4525 __IO CFG_DDR_SGMII_PHY_rpc168_TypeDef rpc168; /*!< Offset: 0x6a0 */ 4526 __IO CFG_DDR_SGMII_PHY_rpc169_TypeDef rpc169; /*!< Offset: 0x6a4 */ 4527 __IO CFG_DDR_SGMII_PHY_rpc170_TypeDef rpc170; /*!< Offset: 0x6a8 */ 4528 __IO CFG_DDR_SGMII_PHY_rpc171_TypeDef rpc171; /*!< Offset: 0x6ac */ 4529 __IO CFG_DDR_SGMII_PHY_rpc172_TypeDef rpc172; /*!< Offset: 0x6b0 */ 4530 __IO CFG_DDR_SGMII_PHY_rpc173_TypeDef rpc173; /*!< Offset: 0x6b4 */ 4531 __IO CFG_DDR_SGMII_PHY_rpc174_TypeDef rpc174; /*!< Offset: 0x6b8 */ 4532 __IO CFG_DDR_SGMII_PHY_rpc175_TypeDef rpc175; /*!< Offset: 0x6bc */ 4533 __IO CFG_DDR_SGMII_PHY_rpc176_TypeDef rpc176; /*!< Offset: 0x6c0 */ 4534 __IO CFG_DDR_SGMII_PHY_rpc177_TypeDef rpc177; /*!< Offset: 0x6c4 */ 4535 __IO CFG_DDR_SGMII_PHY_rpc178_TypeDef rpc178; /*!< Offset: 0x6c8 */ 4536 __IO CFG_DDR_SGMII_PHY_rpc179_TypeDef rpc179; /*!< Offset: 0x6cc */ 4537 __IO CFG_DDR_SGMII_PHY_rpc180_TypeDef rpc180; /*!< Offset: 0x6d0 */ 4538 __IO CFG_DDR_SGMII_PHY_rpc181_TypeDef rpc181; /*!< Offset: 0x6d4 */ 4539 __IO CFG_DDR_SGMII_PHY_rpc182_TypeDef rpc182; /*!< Offset: 0x6d8 */ 4540 __IO CFG_DDR_SGMII_PHY_rpc183_TypeDef rpc183; /*!< Offset: 0x6dc */ 4541 __IO CFG_DDR_SGMII_PHY_rpc184_TypeDef rpc184; /*!< Offset: 0x6e0 */ 4542 __IO CFG_DDR_SGMII_PHY_rpc185_TypeDef rpc185; /*!< Offset: 0x6e4 */ 4543 __IO CFG_DDR_SGMII_PHY_rpc186_TypeDef rpc186; /*!< Offset: 0x6e8 */ 4544 __IO CFG_DDR_SGMII_PHY_rpc187_TypeDef rpc187; /*!< Offset: 0x6ec */ 4545 __IO CFG_DDR_SGMII_PHY_rpc188_TypeDef rpc188; /*!< Offset: 0x6f0 */ 4546 __IO CFG_DDR_SGMII_PHY_rpc189_TypeDef rpc189; /*!< Offset: 0x6f4 */ 4547 __IO CFG_DDR_SGMII_PHY_rpc190_TypeDef rpc190; /*!< Offset: 0x6f8 */ 4548 __IO CFG_DDR_SGMII_PHY_rpc191_TypeDef rpc191; /*!< Offset: 0x6fc */ 4549 __IO CFG_DDR_SGMII_PHY_rpc192_TypeDef rpc192; /*!< Offset: 0x700 */ 4550 __IO CFG_DDR_SGMII_PHY_rpc193_TypeDef rpc193; /*!< Offset: 0x704 */ 4551 __IO CFG_DDR_SGMII_PHY_rpc194_TypeDef rpc194; /*!< Offset: 0x708 */ 4552 __IO CFG_DDR_SGMII_PHY_rpc195_TypeDef rpc195; /*!< Offset: 0x70c */ 4553 __IO CFG_DDR_SGMII_PHY_rpc196_TypeDef rpc196; /*!< Offset: 0x710 */ 4554 __IO CFG_DDR_SGMII_PHY_rpc197_TypeDef rpc197; /*!< Offset: 0x714 */ 4555 __IO CFG_DDR_SGMII_PHY_rpc198_TypeDef rpc198; /*!< Offset: 0x718 */ 4556 __IO CFG_DDR_SGMII_PHY_rpc199_TypeDef rpc199; /*!< Offset: 0x71c */ 4557 __IO CFG_DDR_SGMII_PHY_rpc200_TypeDef rpc200; /*!< Offset: 0x720 */ 4558 __IO CFG_DDR_SGMII_PHY_rpc201_TypeDef rpc201; /*!< Offset: 0x724 */ 4559 __IO CFG_DDR_SGMII_PHY_rpc202_TypeDef rpc202; /*!< Offset: 0x728 */ 4560 __IO CFG_DDR_SGMII_PHY_rpc203_TypeDef rpc203; /*!< Offset: 0x72c */ 4561 __IO CFG_DDR_SGMII_PHY_rpc204_TypeDef rpc204; /*!< Offset: 0x730 */ 4562 __IO CFG_DDR_SGMII_PHY_rpc205_TypeDef rpc205; /*!< Offset: 0x734 */ 4563 __IO CFG_DDR_SGMII_PHY_rpc206_TypeDef rpc206; /*!< Offset: 0x738 */ 4564 __IO CFG_DDR_SGMII_PHY_rpc207_TypeDef rpc207; /*!< Offset: 0x73c */ 4565 __IO CFG_DDR_SGMII_PHY_rpc208_TypeDef rpc208; /*!< Offset: 0x740 */ 4566 __IO CFG_DDR_SGMII_PHY_rpc209_TypeDef rpc209; /*!< Offset: 0x744 */ 4567 __IO CFG_DDR_SGMII_PHY_rpc210_TypeDef rpc210; /*!< Offset: 0x748 */ 4568 __IO CFG_DDR_SGMII_PHY_rpc211_TypeDef rpc211; /*!< Offset: 0x74c */ 4569 __IO CFG_DDR_SGMII_PHY_rpc212_TypeDef rpc212; /*!< Offset: 0x750 */ 4570 __IO CFG_DDR_SGMII_PHY_rpc213_TypeDef rpc213; /*!< Offset: 0x754 */ 4571 __IO CFG_DDR_SGMII_PHY_rpc214_TypeDef rpc214; /*!< Offset: 0x758 */ 4572 __IO CFG_DDR_SGMII_PHY_rpc215_TypeDef rpc215; /*!< Offset: 0x75c */ 4573 __IO CFG_DDR_SGMII_PHY_rpc216_TypeDef rpc216; /*!< Offset: 0x760 */ 4574 __IO CFG_DDR_SGMII_PHY_rpc217_TypeDef rpc217; /*!< Offset: 0x764 */ 4575 __IO CFG_DDR_SGMII_PHY_rpc218_TypeDef rpc218; /*!< Offset: 0x768 */ 4576 __IO CFG_DDR_SGMII_PHY_rpc219_TypeDef rpc219; /*!< Offset: 0x76c */ 4577 __IO CFG_DDR_SGMII_PHY_rpc220_TypeDef rpc220; /*!< Offset: 0x770 */ 4578 __IO CFG_DDR_SGMII_PHY_rpc221_TypeDef rpc221; /*!< Offset: 0x774 */ 4579 __IO CFG_DDR_SGMII_PHY_rpc222_TypeDef rpc222; /*!< Offset: 0x778 */ 4580 __IO CFG_DDR_SGMII_PHY_rpc223_TypeDef rpc223; /*!< Offset: 0x77c */ 4581 __IO CFG_DDR_SGMII_PHY_rpc224_TypeDef rpc224; /*!< Offset: 0x780 */ 4582 __IO CFG_DDR_SGMII_PHY_rpc225_TypeDef rpc225; /*!< Offset: 0x784 */ 4583 __IO CFG_DDR_SGMII_PHY_rpc226_TypeDef rpc226; /*!< Offset: 0x788 */ 4584 __IO CFG_DDR_SGMII_PHY_rpc227_TypeDef rpc227; /*!< Offset: 0x78c */ 4585 __IO CFG_DDR_SGMII_PHY_rpc228_TypeDef rpc228; /*!< Offset: 0x790 */ 4586 __IO CFG_DDR_SGMII_PHY_rpc229_TypeDef rpc229; /*!< Offset: 0x794 */ 4587 __IO CFG_DDR_SGMII_PHY_rpc230_TypeDef rpc230; /*!< Offset: 0x798 */ 4588 __IO CFG_DDR_SGMII_PHY_rpc231_TypeDef rpc231; /*!< Offset: 0x79c */ 4589 __IO CFG_DDR_SGMII_PHY_rpc232_TypeDef rpc232; /*!< Offset: 0x7a0 */ 4590 __IO CFG_DDR_SGMII_PHY_rpc233_TypeDef rpc233; /*!< Offset: 0x7a4 */ 4591 __IO CFG_DDR_SGMII_PHY_rpc234_TypeDef rpc234; /*!< Offset: 0x7a8 */ 4592 __IO CFG_DDR_SGMII_PHY_rpc235_TypeDef rpc235; /*!< Offset: 0x7ac */ 4593 __IO CFG_DDR_SGMII_PHY_rpc236_TypeDef rpc236; /*!< Offset: 0x7b0 */ 4594 __IO CFG_DDR_SGMII_PHY_rpc237_TypeDef rpc237; /*!< Offset: 0x7b4 */ 4595 __IO CFG_DDR_SGMII_PHY_rpc238_TypeDef rpc238; /*!< Offset: 0x7b8 */ 4596 __IO CFG_DDR_SGMII_PHY_rpc239_TypeDef rpc239; /*!< Offset: 0x7bc */ 4597 __IO CFG_DDR_SGMII_PHY_rpc240_TypeDef rpc240; /*!< Offset: 0x7c0 */ 4598 __IO CFG_DDR_SGMII_PHY_rpc241_TypeDef rpc241; /*!< Offset: 0x7c4 */ 4599 __IO CFG_DDR_SGMII_PHY_rpc242_TypeDef rpc242; /*!< Offset: 0x7c8 */ 4600 __IO CFG_DDR_SGMII_PHY_rpc243_TypeDef rpc243; /*!< Offset: 0x7cc */ 4601 __IO CFG_DDR_SGMII_PHY_rpc244_TypeDef rpc244; /*!< Offset: 0x7d0 */ 4602 __IO CFG_DDR_SGMII_PHY_rpc245_TypeDef rpc245; /*!< Offset: 0x7d4 */ 4603 __IO CFG_DDR_SGMII_PHY_rpc246_TypeDef rpc246; /*!< Offset: 0x7d8 */ 4604 __IO CFG_DDR_SGMII_PHY_rpc247_TypeDef rpc247; /*!< Offset: 0x7dc */ 4605 __IO CFG_DDR_SGMII_PHY_rpc248_TypeDef rpc248; /*!< Offset: 0x7e0 */ 4606 __IO CFG_DDR_SGMII_PHY_rpc249_TypeDef rpc249; /*!< Offset: 0x7e4 */ 4607 __IO CFG_DDR_SGMII_PHY_rpc250_TypeDef rpc250; /*!< Offset: 0x7e8 */ 4608 __IO CFG_DDR_SGMII_PHY_spio251_TypeDef spio251; /*!< Offset: 0x7ec */ 4609 __IO CFG_DDR_SGMII_PHY_spio252_TypeDef spio252; /*!< Offset: 0x7f0 */ 4610 __IO CFG_DDR_SGMII_PHY_spio253_TypeDef spio253; /*!< Offset: 0x7f4 */ 4611 __I uint32_t UNUSED_SPACE8[2]; /*!< Offset: 0x7f8 */ 4612 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_TypeDef SOFT_RESET_TIP; /*!< Offset: 0x800 */ 4613 __IO CFG_DDR_SGMII_PHY_rank_select_TypeDef rank_select; /*!< Offset: 0x804 */ 4614 __IO CFG_DDR_SGMII_PHY_lane_select_TypeDef lane_select; /*!< Offset: 0x808 */ 4615 __IO CFG_DDR_SGMII_PHY_training_skip_TypeDef training_skip; /*!< Offset: 0x80c */ 4616 __IO CFG_DDR_SGMII_PHY_training_start_TypeDef training_start; /*!< Offset: 0x810 */ 4617 __I CFG_DDR_SGMII_PHY_training_status_TypeDef training_status; /*!< Offset: 0x814 */ 4618 __IO CFG_DDR_SGMII_PHY_training_reset_TypeDef training_reset; /*!< Offset: 0x818 */ 4619 __I CFG_DDR_SGMII_PHY_gt_err_comb_TypeDef gt_err_comb; /*!< Offset: 0x81c */ 4620 __I CFG_DDR_SGMII_PHY_gt_clk_sel_TypeDef gt_clk_sel; /*!< Offset: 0x820 */ 4621 __I CFG_DDR_SGMII_PHY_gt_txdly_TypeDef gt_txdly; /*!< Offset: 0x824 */ 4622 __I CFG_DDR_SGMII_PHY_gt_steps_180_TypeDef gt_steps_180; /*!< Offset: 0x828 */ 4623 __I CFG_DDR_SGMII_PHY_gt_state_TypeDef gt_state; /*!< Offset: 0x82c */ 4624 __I CFG_DDR_SGMII_PHY_wl_delay_0_TypeDef wl_delay_0; /*!< Offset: 0x830 */ 4625 __I CFG_DDR_SGMII_PHY_dq_dqs_err_done_TypeDef dq_dqs_err_done; /*!< Offset: 0x834 */ 4626 __I CFG_DDR_SGMII_PHY_dqdqs_window_TypeDef dqdqs_window; /*!< Offset: 0x838 */ 4627 __I CFG_DDR_SGMII_PHY_dqdqs_state_TypeDef dqdqs_state; /*!< Offset: 0x83c */ 4628 __I CFG_DDR_SGMII_PHY_delta0_TypeDef delta0; /*!< Offset: 0x840 */ 4629 __I CFG_DDR_SGMII_PHY_delta1_TypeDef delta1; /*!< Offset: 0x844 */ 4630 __I CFG_DDR_SGMII_PHY_dqdqs_status0_TypeDef dqdqs_status0; /*!< Offset: 0x848 */ 4631 __I CFG_DDR_SGMII_PHY_dqdqs_status1_TypeDef dqdqs_status1; /*!< Offset: 0x84c */ 4632 __I CFG_DDR_SGMII_PHY_dqdqs_status2_TypeDef dqdqs_status2; /*!< Offset: 0x850 */ 4633 __I CFG_DDR_SGMII_PHY_dqdqs_status3_TypeDef dqdqs_status3; /*!< Offset: 0x854 */ 4634 __I CFG_DDR_SGMII_PHY_dqdqs_status4_TypeDef dqdqs_status4; /*!< Offset: 0x858 */ 4635 __I CFG_DDR_SGMII_PHY_dqdqs_status5_TypeDef dqdqs_status5; /*!< Offset: 0x85c */ 4636 __I CFG_DDR_SGMII_PHY_dqdqs_status6_TypeDef dqdqs_status6; /*!< Offset: 0x860 */ 4637 __I CFG_DDR_SGMII_PHY_addcmd_status0_TypeDef addcmd_status0; /*!< Offset: 0x864 */ 4638 __I CFG_DDR_SGMII_PHY_addcmd_status1_TypeDef addcmd_status1; /*!< Offset: 0x868 */ 4639 __I CFG_DDR_SGMII_PHY_addcmd_answer_TypeDef addcmd_answer; /*!< Offset: 0x86c */ 4640 __I CFG_DDR_SGMII_PHY_bclksclk_answer_TypeDef bclksclk_answer; /*!< Offset: 0x870 */ 4641 __I CFG_DDR_SGMII_PHY_dqdqs_wrcalib_offset_TypeDef dqdqs_wrcalib_offset; /*!< Offset: 0x874 */ 4642 __IO CFG_DDR_SGMII_PHY_expert_mode_en_TypeDef expert_mode_en; /*!< Offset: 0x878 */ 4643 __IO CFG_DDR_SGMII_PHY_expert_dlycnt_move_reg0_TypeDef expert_dlycnt_move_reg0; /*!< Offset: 0x87c */ 4644 __IO CFG_DDR_SGMII_PHY_expert_dlycnt_move_reg1_TypeDef expert_dlycnt_move_reg1; /*!< Offset: 0x880 */ 4645 __IO CFG_DDR_SGMII_PHY_expert_dlycnt_direction_reg0_TypeDef expert_dlycnt_direction_reg0; /*!< Offset: 0x884 */ 4646 __IO CFG_DDR_SGMII_PHY_expert_dlycnt_direction_reg1_TypeDef expert_dlycnt_direction_reg1; /*!< Offset: 0x888 */ 4647 __IO CFG_DDR_SGMII_PHY_expert_dlycnt_load_reg0_TypeDef expert_dlycnt_load_reg0; /*!< Offset: 0x88c */ 4648 __IO CFG_DDR_SGMII_PHY_expert_dlycnt_load_reg1_TypeDef expert_dlycnt_load_reg1; /*!< Offset: 0x890 */ 4649 __I CFG_DDR_SGMII_PHY_expert_dlycnt_oor_reg0_TypeDef expert_dlycnt_oor_reg0; /*!< Offset: 0x894 */ 4650 __I CFG_DDR_SGMII_PHY_expert_dlycnt_oor_reg1_TypeDef expert_dlycnt_oor_reg1; /*!< Offset: 0x898 */ 4651 __IO CFG_DDR_SGMII_PHY_expert_dlycnt_mv_rd_dly_reg_TypeDef expert_dlycnt_mv_rd_dly_reg; /*!< Offset: 0x89c */ 4652 __IO CFG_DDR_SGMII_PHY_expert_dlycnt_pause_TypeDef expert_dlycnt_pause; /*!< Offset: 0x8a0 */ 4653 __IO CFG_DDR_SGMII_PHY_expert_pllcnt_TypeDef expert_pllcnt; /*!< Offset: 0x8a4 */ 4654 __I CFG_DDR_SGMII_PHY_expert_dqlane_readback_TypeDef expert_dqlane_readback; /*!< Offset: 0x8a8 */ 4655 __I CFG_DDR_SGMII_PHY_expert_addcmd_ln_readback_TypeDef expert_addcmd_ln_readback; /*!< Offset: 0x8ac */ 4656 __IO CFG_DDR_SGMII_PHY_expert_read_gate_controls_TypeDef expert_read_gate_controls; /*!< Offset: 0x8b0 */ 4657 __I CFG_DDR_SGMII_PHY_expert_dq_dqs_optimization0_TypeDef expert_dq_dqs_optimization0; /*!< Offset: 0x8b4 */ 4658 __I CFG_DDR_SGMII_PHY_expert_dq_dqs_optimization1_TypeDef expert_dq_dqs_optimization1; /*!< Offset: 0x8b8 */ 4659 __IO CFG_DDR_SGMII_PHY_expert_wrcalib_TypeDef expert_wrcalib; /*!< Offset: 0x8bc */ 4660 __IO CFG_DDR_SGMII_PHY_expert_calif_TypeDef expert_calif; /*!< Offset: 0x8c0 */ 4661 __I CFG_DDR_SGMII_PHY_expert_calif_readback_TypeDef expert_calif_readback; /*!< Offset: 0x8c4 */ 4662 __I CFG_DDR_SGMII_PHY_expert_calif_readback1_TypeDef expert_calif_readback1; /*!< Offset: 0x8c8 */ 4663 __IO CFG_DDR_SGMII_PHY_expert_dfi_status_override_to_shim_TypeDef expert_dfi_status_override_to_shim; /*!< Offset: 0x8cc */ 4664 __IO CFG_DDR_SGMII_PHY_tip_cfg_params_TypeDef tip_cfg_params; /*!< Offset: 0x8d0 */ 4665 __IO CFG_DDR_SGMII_PHY_tip_vref_param_TypeDef tip_vref_param; /*!< Offset: 0x8d4 */ 4666 __IO CFG_DDR_SGMII_PHY_lane_alignment_fifo_control_TypeDef lane_alignment_fifo_control; /*!< Offset: 0x8d8 */ 4667 __I uint32_t UNUSED_SPACE9[201]; /*!< Offset: 0x8dc */ 4668 __IO CFG_DDR_SGMII_PHY_SOFT_RESET_SGMII_TypeDef SOFT_RESET_SGMII; /*!< Offset: 0xc00 */ 4669 __IO CFG_DDR_SGMII_PHY_SGMII_MODE_TypeDef SGMII_MODE; /*!< Offset: 0xc04 */ 4670 __IO CFG_DDR_SGMII_PHY_PLL_CNTL_TypeDef PLL_CNTL; /*!< Offset: 0xc08 */ 4671 __IO CFG_DDR_SGMII_PHY_CH0_CNTL_TypeDef CH0_CNTL; /*!< Offset: 0xc0c */ 4672 __IO CFG_DDR_SGMII_PHY_CH1_CNTL_TypeDef CH1_CNTL; /*!< Offset: 0xc10 */ 4673 __IO CFG_DDR_SGMII_PHY_RECAL_CNTL_TypeDef RECAL_CNTL; /*!< Offset: 0xc14 */ 4674 __IO CFG_DDR_SGMII_PHY_CLK_CNTL_TypeDef CLK_CNTL; /*!< Offset: 0xc18 */ 4675 __IO CFG_DDR_SGMII_PHY_DYN_CNTL_TypeDef DYN_CNTL; /*!< Offset: 0xc1c */ 4676 __IO CFG_DDR_SGMII_PHY_PVT_STAT_TypeDef PVT_STAT; /*!< Offset: 0xc20 */ 4677 __IO CFG_DDR_SGMII_PHY_SPARE_CNTL_TypeDef SPARE_CNTL; /*!< Offset: 0xc24 */ 4678 __I CFG_DDR_SGMII_PHY_SPARE_STAT_TypeDef SPARE_STAT; /*!< Offset: 0xc28 */ 4679 } CFG_DDR_SGMII_PHY_TypeDef; 4680 4681 4682 /******************************************************************************/ 4683 /* finish of CFG_DDR_SGMII_PHY definitions */ 4684 /******************************************************************************/ 4685 4686 4687 4688 #ifdef __cplusplus 4689 } 4690 #endif 4691 4692 #endif /* MSS_DDR_SGMII_PHY_DEFS_H_ */ 4693
