Searched refs:hw_reg (Results 1 – 8 of 8) sorted by relevance
155 this_spi->hw_reg = MSS_SPI0_LO_BASE; in MSS_SPI_init()161 this_spi->hw_reg = MSS_SPI1_LO_BASE; in MSS_SPI_init()167 this_spi->hw_reg = MSS_SPI0_HI_BASE; in MSS_SPI_init()173 this_spi->hw_reg = MSS_SPI1_HI_BASE; in MSS_SPI_init()183 this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK; in MSS_SPI_init()212 this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_MASTER_MASK; in MSS_SPI_configure_slave_mode()215 this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK; in MSS_SPI_configure_slave_mode()216 this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~PROTOCOL_MODE_MASK) in MSS_SPI_configure_slave_mode()220 this_spi->hw_reg->FRAMESUP = 0u; in MSS_SPI_configure_slave_mode()221 this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) in MSS_SPI_configure_slave_mode()[all …]
419 SPI_TypeDef * hw_reg; /*!< Pointer to SPI registers. */ member
116 this_can->hw_reg->Config.L = pcan_config->L; in MSS_CAN_init()121 this_can->hw_reg->Config.L = bitrate; in MSS_CAN_init()125 this_can->hw_reg->IntEbl.L = DISABLE; in MSS_CAN_init()142 this_can->hw_reg->IntStatus.L = DISABLE; in MSS_CAN_set_config_reg()145 this_can->hw_reg->Command.RUN_STOP = DISABLE; in MSS_CAN_set_config_reg()148 this_can->hw_reg->IntEbl.RX_MSG = DISABLE; in MSS_CAN_set_config_reg()151 this_can->hw_reg->IntEbl.INT_EBL = DISABLE; in MSS_CAN_set_config_reg()154 this_can->hw_reg->Config.L = cfg; in MSS_CAN_set_config_reg()169 this_can->hw_reg->Command.RUN_STOP = DISABLE; in MSS_CAN_set_mode()177 this_can->hw_reg->Command.L = (uint32_t)mode; in MSS_CAN_set_mode()[all …]
912 CAN_DEVICE * hw_reg; /* Pointer to CAN registers. */ member
130 this_uart->hw_reg->MM0 &= ~ELIN_MASK; in MSS_UART_init()133 this_uart->hw_reg->MM1 &= ~EIRD_MASK; in MSS_UART_init()136 this_uart->hw_reg->MM2 &= ~EERR_MASK; in MSS_UART_init()156 this_uart->hw_reg->MM0 |= ELIN_MASK; in MSS_UART_lin_init()159 this_uart->hw_reg->MM1 &= ~EIRD_MASK; in MSS_UART_lin_init()162 this_uart->hw_reg->MM2 &= ~EERR_MASK; in MSS_UART_lin_init()183 this_uart->hw_reg->MM0 &= ~ELIN_MASK; in MSS_UART_irda_init()186 this_uart->hw_reg->MM1 |= EIRD_MASK; in MSS_UART_irda_init()188 ((rxpol == MSS_UART_ACTIVE_LOW) ? (this_uart->hw_reg->MM1 &= ~EIRX_MASK) : in MSS_UART_irda_init()189 (this_uart->hw_reg->MM1 |= EIRX_MASK)); in MSS_UART_irda_init()[all …]
776 MSS_UART_TypeDef * hw_reg; /*!< Pointer to UART registers. */ member
131 this_i2c->hw_reg->CTRL |= (uint8_t)((((clock_speed >> 2u) & 0x01u) << CR2) in MSS_I2C_init()134 this_i2c->hw_reg->CTRL |= (uint8_t)((((clock_speed >> 1u) & 0x01u) << CR1) in MSS_I2C_init()137 this_i2c->hw_reg->CTRL |= (uint8_t)(((clock_speed & (uint8_t)0x01u) << CR0) in MSS_I2C_init()140 this_i2c->hw_reg->ADDR = (uint8_t)this_i2c->ser_address; in MSS_I2C_init()142 this_i2c->hw_reg->CTRL |= ENS1_MASK; /* Set enable bit */ in MSS_I2C_init()201 this_i2c->hw_reg->CTRL |= STA_MASK; in MSS_I2C_write()211 this_i2c->hw_reg->CTRL &= ~SI_MASK; in MSS_I2C_write()213 stat_ctrl = this_i2c->hw_reg->STATUS; in MSS_I2C_write()274 this_i2c->hw_reg->CTRL |= STA_MASK; in MSS_I2C_read()284 this_i2c->hw_reg->CTRL &= ~SI_MASK; in MSS_I2C_read()[all …]
575 I2C_TypeDef * hw_reg; member