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Searched refs:gt_txdly (Results 1 – 3 of 3) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr_debug.c603 MSS_DDR_APB_ADDR = CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly; in tip_register_status()
Dmss_ddr.c1873 … if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly)&0xFFU) == 0U) // Gate training tx_dly check: AL in ddr_setup()
1881 if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly>>8U)&0xFFU) == 0U) in ddr_setup()
1889 if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly>>16U)&0xFFU) == 0U) in ddr_setup()
1897 if(((CFG_DDR_SGMII_PHY->gt_txdly.gt_txdly>>24U)&0xFFU) == 0U) in ddr_setup()
Dmss_ddr_sgmii_phy_defs.h3534 __I uint32_t gt_txdly; member
4621 …__I CFG_DDR_SGMII_PHY_gt_txdly_TypeDef gt_txdly; /*!< … member