Home
last modified time | relevance | path

Searched refs:flags (Results 1 – 25 of 56) sorted by relevance

123

/hal_microchip-latest/mec5/drivers/
Dmec_kbc.c69 int mec_hal_kbc_init(struct mec_kbc_regs *base, uint32_t flags) in mec_hal_kbc_init() argument
78 if (flags & MEC_KBC_RESET) { in mec_hal_kbc_init()
87 val = (flags & MEC_KBC_PORT92_EN) ? 1 : 0; in mec_hal_kbc_init()
90 if (flags & MEC_KBC_GATEA20_FWC_EN) { in mec_hal_kbc_init()
94 if (flags & (MEC_KBC_IBF_IRQ | MEC_KBC_OBE_IRQ)) { in mec_hal_kbc_init()
98 if (flags & MEC_KBC_PCOBF_EN) { in mec_hal_kbc_init()
101 if (flags & MEC_KBC_AUXOBF_EN) { in mec_hal_kbc_init()
105 if (flags & MEC_KBC_UD3_SET) { in mec_hal_kbc_init()
106 if (flags & MEC_KBC_UD3_ONE) { in mec_hal_kbc_init()
111 if (flags & MEC_KBC_UD4_SET) { in mec_hal_kbc_init()
[all …]
Dmec_adc.c22 static inline uint32_t adc_intr_flag_to_bitmap(uint32_t flags) in adc_intr_flag_to_bitmap() argument
26 if (flags & MEC_BIT(MEC_ADC_SINGLE_INTR_POS)) { in adc_intr_flag_to_bitmap()
29 if (flags & MEC_BIT(MEC_ADC_REPEAT_INTR_POS)) { in adc_intr_flag_to_bitmap()
43 uint8_t flags = 0; in mec_hal_adc_init() local
56 flags = cfg->flags; in mec_hal_adc_init()
58 if (flags & MEC_BIT(MEC_ADC_CFG_SOFT_RESET_POS)) { in mec_hal_adc_init()
68 if (flags & MEC_BIT(MEC_ADC_CFG_PWR_SAVE_DIS_POS)) { in mec_hal_adc_init()
74 if (flags & MEC_BIT(MEC_ADC_CFG_SAMPLE_TIME_POS)) { in mec_hal_adc_init()
84 if (flags & MEC_BIT(MEC_ADC_CFG_WARM_UP_POS)) { in mec_hal_adc_init()
90 if (flags & MEC_BIT(MEC_ADC_CFG_RPT_DELAY_POS)) { in mec_hal_adc_init()
[all …]
Dmec_acpi_ec.c99 int mec_hal_acpi_ec_init(struct mec_acpi_ec_regs *regs, uint32_t flags) in mec_hal_acpi_ec_init() argument
111 if (flags & MEC_ACPI_EC_RESET) { in mec_hal_acpi_ec_init()
119 if (flags & MEC_ACPI_EC_4BYTE_MODE) { in mec_hal_acpi_ec_init()
125 if (flags & MEC_ACPI_EC_UD0A_SET) { in mec_hal_acpi_ec_init()
126 if (flags & MEC_ACPI_EC_UD0A_ONE) { in mec_hal_acpi_ec_init()
133 if (flags & MEC_ACPI_EC_UD1A_SET) { in mec_hal_acpi_ec_init()
134 if (flags & MEC_ACPI_EC_UD1A_ONE) { in mec_hal_acpi_ec_init()
141 mec_hal_acpi_ec_girq_dis(regs, flags); in mec_hal_acpi_ec_init()
146 static uint32_t acpi_ec_irq_bitmap(const struct mec_acpi_ec_info *info, uint32_t flags) in acpi_ec_irq_bitmap() argument
150 if (flags & MEC_ACPI_EC_IBF_IRQ) { in acpi_ec_irq_bitmap()
[all …]
Dmec_espi_taf.c70 static inline uint32_t iflags_to_bitmap(uint32_t flags) in iflags_to_bitmap() argument
74 if (flags & MEC_BIT(MEC_ESPI_TAF_INTR_ECP_DONE_POS)) { in iflags_to_bitmap()
77 if (flags & MEC_BIT(MEC_ESPI_TAF_INTR_HWMON_ERR_POS)) { in iflags_to_bitmap()
111 void mec_hal_espi_taf_girq_ctrl(uint8_t enable, uint32_t flags) in mec_hal_espi_taf_girq_ctrl() argument
113 uint32_t bitmap = iflags_to_bitmap(flags); in mec_hal_espi_taf_girq_ctrl()
120 void mec_hal_espi_taf_girq_status_clr(uint32_t flags) in mec_hal_espi_taf_girq_status_clr() argument
122 uint32_t bitmap = iflags_to_bitmap(flags); in mec_hal_espi_taf_girq_status_clr()
242 if (thwcfg->flags & MEC_BIT(MEC_ESPI_TAF_HW_CFG_FLAG_FREQ_POS)) { in taf_qspi_freq_timing()
250 if (thwcfg->flags & MEC_BIT(MEC_ESPI_TAF_HW_CFG_FLAG_CPHA_POS)) { in taf_qspi_freq_timing()
254 if (thwcfg->flags & MEC_BIT(MEC_ESPI_TAF_HW_CFG_FLAG_CSTM_POS)) { in taf_qspi_freq_timing()
[all …]
Dmec_tach.c51 int mec_hal_tach_init(struct mec_tach_regs *regs, uint32_t limits, uint32_t flags) in mec_hal_tach_init() argument
62 if (flags & MEC5_TACH_CFG_RESET) { in mec_hal_tach_init()
77 temp = (flags & MEC5_TACH_CFG_INTERVAL_EDGES_MSK) >> MEC5_TACH_CFG_INTERVAL_EDGES_POS; in mec_hal_tach_init()
80 if (flags & MEC5_TACH_CFG_FILTER_EN) { in mec_hal_tach_init()
87 if (flags & MEC5_TACH_CFG_CNT_INCR_CLK) { in mec_hal_tach_init()
91 if (flags & MEC5_TACH_CFG_OOL_INTR_EN) { /* out of limit interrupt? */ in mec_hal_tach_init()
96 if (flags & MEC5_TACH_CFG_CNT_RDY_INTR_EN) { in mec_hal_tach_init()
101 if (flags & MEC5_TACH_CFG_INPUT_CHG_INTR_EN) { in mec_hal_tach_init()
106 if (flags & MEC5_TACH_CFG_ENABLE) { in mec_hal_tach_init()
Dmec_eeprom.c28 int mec_hal_eeprom_init(struct mec_eeprom_ctrl_regs *regs, uint32_t flags, uint32_t password) in mec_hal_eeprom_init() argument
39 if (flags & MEC_HAL_EEPROM_CFG_SRST) { in mec_hal_eeprom_init()
47 if (flags & MEC_HAL_EEPROM_CFG_LOAD_PSWD) { in mec_hal_eeprom_init()
51 if (flags & MEC_HAL_EEPROM_CFG_LOCK_ON_PSWD) { in mec_hal_eeprom_init()
55 if (flags & MEC_HAL_EEPROM_CFG_LOCK_ON_JTAG) { in mec_hal_eeprom_init()
59 if (flags & MEC_HAL_EEPROM_CFG_DONE_IEN) { in mec_hal_eeprom_init()
62 if (flags & MEC_HAL_EEPROM_CFG_EXE_ERR_IEN) { in mec_hal_eeprom_init()
66 if (flags & MEC_HAL_EEPROM_CFG_ENABLE) { in mec_hal_eeprom_init()
143 int mec_hal_eeprom_intr_en(struct mec_eeprom_ctrl_regs *regs, uint8_t enable, uint32_t flags) in mec_hal_eeprom_intr_en() argument
151 if (flags & MEC_BIT(MEC_HAL_EEPROM_INTR_DONE_POS)) { in mec_hal_eeprom_intr_en()
[all …]
Dmec_btimer.c99 uint32_t count, uint32_t flags) in mec_hal_btimer_init() argument
119 if (flags & MEC_BIT(MEC5_BTIMER_CFG_FLAG_AUTO_RELOAD_POS)) { in mec_hal_btimer_init()
123 if (flags & MEC_BIT(MEC5_BTIMER_CFG_FLAG_COUNT_UP_POS)) { in mec_hal_btimer_init()
127 if (flags & MEC_BIT(MEC5_BTIMER_CFG_FLAG_INTR_EN_POS)) { in mec_hal_btimer_init()
131 if (flags & MEC_BIT(MEC5_BTIMER_CFG_FLAG_START_POS)) { in mec_hal_btimer_init()
151 int mec_hal_btimer_reset(struct mec_btmr_regs *regs, uint32_t flags) in mec_hal_btimer_reset() argument
159 if (flags & MEC_BIT(MEC5_BTMR_RST_PRESERVE_FDIV_POS)) { in mec_hal_btimer_reset()
163 if (flags & MEC_BIT(MEC5_BTMR_RST_PRESERVE_DIR_POS)) { in mec_hal_btimer_reset()
241 uint32_t flags) in mec_hal_btimer_start_load() argument
248 if (flags & MEC_BIT(MEC5_BTIMER_START_FLAG_IEN_POS)) { in mec_hal_btimer_start_load()
[all …]
Dmec_kscan.c53 int mec_hal_kscan_init(struct mec_kscan_regs *regs, uint32_t flags, uint8_t ksi_in_intr_mask) in mec_hal_kscan_init() argument
62 if (flags & MEC_KSCAN_CFG_RESET) { in mec_hal_kscan_init()
70 if (flags & MEC_KSCAN_KSO_PREDRIVE_EN) { in mec_hal_kscan_init()
77 if (flags & MEC_KSCAN_KSO_SELECT_DRV_HI) { in mec_hal_kscan_init()
84 if (flags & MEC_KSCAN_INTR_EN) { in mec_hal_kscan_init()
88 if (flags & MEC_KSCAN_CFG_ENABLE) { in mec_hal_kscan_init()
Dmec_wdt.c38 int mec_hal_wdt_init(struct mec_wdt_regs *regs, uint16_t n32k_ticks, uint32_t flags) in mec_hal_wdt_init() argument
55 if (flags & MEC5_WDT_INIT_ENABLE) { in mec_hal_wdt_init()
58 if (flags & MEC5_WDT_INIT_STALL_HTMR) { in mec_hal_wdt_init()
61 if (flags & MEC5_WDT_INIT_STALL_WKTMR) { in mec_hal_wdt_init()
64 if (flags & MEC5_WDT_INIT_STALL_JTAG) { in mec_hal_wdt_init()
67 if (flags & MEC5_WDT_INIT_GEN_INTR) { in mec_hal_wdt_init()
Dmec_kbc_api.h77 int mec_hal_kbc_init(struct mec_kbc_regs *base, uint32_t flags);
82 int mec_hal_kbc_activate(struct mec_kbc_regs *base, uint8_t enable, uint8_t flags);
84 int mec_hal_kbc_girq_en(struct mec_kbc_regs *base, uint32_t flags);
85 int mec_hal_kbc_girq_dis(struct mec_kbc_regs *base, uint32_t flags);
86 int mec_hal_kbc_girq_clr(struct mec_kbc_regs *base, uint32_t flags);
Dmec_pwm.c151 uint32_t perc, pulc, ps1, cnt_on, cnt_off, cfg, fin, fpwm, flags; in prog_pwm_fd() local
153 flags = 0u; in prog_pwm_fd()
167 flags |= MEC_BIT(0); in prog_pwm_fd()
187 if (flags & MEC_BIT(0)) { in prog_pwm_fd()
281 uint32_t pulse_cycles, uint32_t flags) in mec_hal_pwm_init() argument
293 if (flags & MEC5_PWM_CFG_RESET) { in mec_hal_pwm_init()
297 if (flags & MEC5_PWM_CFG_INVERT) { in mec_hal_pwm_init()
306 if (flags & MEC5_PWM_CFG_ENABLE) { in mec_hal_pwm_init()
Dmec_espi_vw.h193 uint8_t widx, uint8_t val, uint32_t flags);
200 uint8_t val, uint8_t msk, uint32_t flags);
222 struct mec_espi_vw_config *cfg, uint32_t flags);
259 uint32_t flags);
261 uint32_t flags);
266 uint32_t flags);
268 uint32_t flags);
274 uint8_t src_id, uint8_t val, uint32_t flags);
287 uint8_t groupval, uint8_t groupmsk, uint32_t flags);
Dmec_peci.c59 int mec_hal_peci_init(struct mec_peci_regs *regs, struct mec_peci_config *cfg, uint32_t flags) in mec_hal_peci_init() argument
74 if (flags & MEC_PECI_CFG_RESET) { in mec_hal_peci_init()
81 if (flags & MEC_PECI_CFG_CLK_DIV) { in mec_hal_peci_init()
85 if (flags & MEC_PECI_CFG_OBT) { in mec_hal_peci_init()
90 if (flags & MEC_PECI_CFG_REQ_TIMER) { in mec_hal_peci_init()
95 if (flags & MEC_PECI_CFG_DIS_BIT_TIME_CLAMP) { in mec_hal_peci_init()
101 if (flags & MEC_PECI_CFG_INTR_EN) { in mec_hal_peci_init()
106 if (flags & MEC_PECI_CFG_ENABLE) { in mec_hal_peci_init()
Dmec_espi_vw.c450 struct mec_espi_vw_config *cfg, uint32_t flags) in mec_hal_espi_vwg_ct_config() argument
456 if (!flags) { /* do not modify anything */ in mec_hal_espi_vwg_ct_config()
463 if (flags & MEC_BIT(MEC_ESPI_VWG_CFG_HI_POS)) { in mec_hal_espi_vwg_ct_config()
469 if (flags & MEC_BIT(MEC_ESPI_VWG_CFG_RST_SRC_POS)) { in mec_hal_espi_vwg_ct_config()
476 if (flags & MEC_BIT(MEC_ESPI_VWG_CFG_SRC0_RST_VAL_POS + i)) { in mec_hal_espi_vwg_ct_config()
482 if (flags & MEC_BIT(MEC_ESPI_VWG_CFG_SRC0_IRQ_POS + i)) { in mec_hal_espi_vwg_ct_config()
739 struct mec_espi_vw_config *cfg, uint32_t flags) in mec_hal_espi_vwg_tc_config() argument
747 if (flags & MEC_BIT(MEC_ESPI_VWG_CFG_HI_POS)) { in mec_hal_espi_vwg_tc_config()
753 if (flags & MEC_BIT(MEC_ESPI_VWG_CFG_RST_SRC_POS)) { in mec_hal_espi_vwg_tc_config()
760 if (flags & MEC_BIT(MEC_ESPI_VWG_CFG_SRC0_RST_VAL_POS + i)) { in mec_hal_espi_vwg_tc_config()
[all …]
Dmec_adc_api.h77 uint8_t flags; member
89 int mec_hal_adc_girq_ctrl(struct mec_adc_regs *regs, uint32_t flags, uint8_t enable);
90 int mec_hal_adc_girq_status_clr(struct mec_adc_regs *regs, uint32_t flags);
108 int mec_hal_adc_status_clear(struct mec_adc_regs *regs, uint32_t flags);
Dmec_espi_taf.h57 uint8_t flags; member
85 uint16_t flags; member
203 uint8_t flags; /* bit[0]==1 is lock the region */ member
215 void mec_hal_espi_taf_girq_ctrl(uint8_t enable, uint32_t flags);
216 void mec_hal_espi_taf_girq_status_clr(uint32_t flags);
Dmec_acpi_ec_api.h52 int mec_hal_acpi_ec_init(struct mec_acpi_ec_regs *regs, uint32_t flags);
74 int mec_hal_acpi_ec_girq_en(struct mec_acpi_ec_regs *regs, uint32_t flags);
75 int mec_hal_acpi_ec_girq_dis(struct mec_acpi_ec_regs *regs, uint32_t flags);
76 int mec_hal_acpi_ec_girq_clr(struct mec_acpi_ec_regs *regs, uint32_t flags);
Dmec_bclink.c53 int mec_hal_bcl_init(struct mec_bcl_regs *base, uint32_t flags) in mec_hal_bcl_init() argument
68 base->CLKSEL = (flags & MEC_BCL_CFG_FREQ_DIV_MSK) >> MEC_BCL_CFG_FREQ_DIV_POS; in mec_hal_bcl_init()
295 int mec_hal_bcl_start(struct mec_bcl_regs *regs, uint8_t target_reg, uint8_t wrdata, uint32_t flags) in mec_hal_bcl_start() argument
312 if (flags & MEC_BCL_START_FLAG_BERR_IEN) { in mec_hal_bcl_start()
319 if (flags & MEC_BCL_START_FLAG_READ) { in mec_hal_bcl_start()
329 if (flags & MEC_BCL_START_FLAG_BCLR_IEN) { in mec_hal_bcl_start()
Dmec_qspi.c913 static int qspi_gen_ts_clocks(struct mec_qspi_regs *base, uint32_t nclocks, uint32_t flags) in qspi_gen_ts_clocks() argument
924 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_CLOSE_POS)) { in qspi_gen_ts_clocks()
929 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_IEN_POS)) { in qspi_gen_ts_clocks()
936 if (flags & MEC_QSPI_XFR_FLAG_START_POS) { in qspi_gen_ts_clocks()
953 uint8_t *rxb, size_t lenb, uint32_t flags) in mec_hal_qspi_ldma() argument
969 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_CLR_FIFOS_POS)) { in mec_hal_qspi_ldma()
981 return qspi_gen_ts_clocks(base, lenb, flags); in mec_hal_qspi_ldma()
1013 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_CLOSE_POS)) { in mec_hal_qspi_ldma()
1026 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_IEN_POS)) { in mec_hal_qspi_ldma()
1033 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_START_POS)) { in mec_hal_qspi_ldma()
[all …]
Dmec_ps2.c103 int mec_hal_ps2_init(struct mec_ps2_regs *regs, uint32_t flags) in mec_hal_ps2_init() argument
114 if (flags & MEC_PS2_FLAGS_RESET) { in mec_hal_ps2_init()
124 temp = ((flags & MEC_PS2_FLAGS_PARITY_MSK) >> MEC_PS2_FLAGS_PARITY_POS); in mec_hal_ps2_init()
127 temp = ((flags & MEC_PS2_FLAGS_STOP_BITS_MSK) >> MEC_PS2_FLAGS_STOP_BITS_POS); in mec_hal_ps2_init()
130 if (flags & MEC_PS2_FLAGS_ENABLE) { in mec_hal_ps2_init()
136 if (flags & MEC_PS2_FLAGS_INTR_EN) { in mec_hal_ps2_init()
Dmec_i2c.c366 int mec_hal_i2c_smb_girq_ctrl(struct mec_i2c_smb_ctx *ctx, int flags) in mec_hal_i2c_smb_girq_ctrl() argument
372 if (flags & MEC_I2C_SMB_GIRQ_DIS) { in mec_hal_i2c_smb_girq_ctrl()
376 if (flags & MEC_I2C_SMB_GIRQ_CLR_STS) { in mec_hal_i2c_smb_girq_ctrl()
380 if (flags & MEC_I2C_SMB_GIRQ_EN) { in mec_hal_i2c_smb_girq_ctrl()
708 int mec_hal_i2c_smb_start_gen(struct mec_i2c_smb_ctx *ctx, uint8_t target_addr, int flags) in mec_hal_i2c_smb_start_gen() argument
719 if (flags & MEC_I2C_SMB_BYTE_ENI) { in mec_hal_i2c_smb_start_gen()
857 uint32_t flags) in mec_hal_i2c_nl_cm_cfg_start() argument
885 if (flags & MEC_I2C_NL_FLAG_START) { in mec_hal_i2c_nl_cm_cfg_start()
889 if (flags & MEC_I2C_NL_FLAG_RPT_START) { in mec_hal_i2c_nl_cm_cfg_start()
893 if (flags & MEC_I2C_NL_FLAG_STOP) { in mec_hal_i2c_nl_cm_cfg_start()
[all …]
Dmec_btimer_api.h46 uint32_t count, uint32_t flags);
50 int mec_hal_btimer_reset(struct mec_btmr_regs *regs, uint32_t flags);
64 uint32_t flags);
Dmec_espi_fc.c96 void mec_hal_espi_fc_op_start(struct mec_espi_io_regs *iobase, uint32_t flags) in mec_hal_espi_fc_op_start() argument
100 if (flags & MEC_BIT(MEC_ESPI_FC_XFR_FLAG_START_IEN_POS)) { in mec_hal_espi_fc_op_start()
268 uint32_t flags) in mec_hal_espi_fc_xfr_start() argument
313 if (flags & MEC_BIT(MEC_ESPI_FC_XFR_FLAG_START_IEN_POS)) { in mec_hal_espi_fc_xfr_start()
Dmec_qspi_api.h138 uint8_t flags; member
249 uint32_t flags);
257 uint8_t* rxb, size_t lenb, uint32_t flags);
296 uint32_t mec_hal_qspi_descrs_cfg1(struct mec_qspi_context *ctx, uint32_t nbytes, uint32_t flags);
318 uint32_t flags);
/hal_microchip-latest/mpfs/drivers/mss/mss_mmc/
Dmss_mmc_if.c220 uint32_t flags; in cif_send_cq_direct_command() local
236 flags = (uint32_t)(CQ_DESC_VALID | CQ_DESC_END | CQ_DESC_ACT_TASK | CQ_DESC_INT); in cif_send_cq_direct_command()
239 flags |= ((cmd_type & 0x3FU) << SHIFT_16BIT); in cif_send_cq_direct_command()
244 flags |= (uint32_t)CQ_DESC_DCMD_RESP_TYPE_NO_RESP; in cif_send_cq_direct_command()
249 flags |= (uint32_t)CQ_DESC_DCMD_RESP_TYPE_R1_R4_R5; in cif_send_cq_direct_command()
252 flags |= (uint32_t)CQ_DESC_DCMD_RESP_TYPE_R1B; in cif_send_cq_direct_command()
259 flags |= (uint32_t)CQ_DESC_DCMD_CMD_TIMING; in cif_send_cq_direct_command()
261 dcmdTaskDesc[0] = flags; in cif_send_cq_direct_command()

123