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Searched refs:expert_mode_en (Results 1 – 2 of 2) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr.c915 CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000002U; in ddr_setup()
990 CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en =\ in ddr_setup()
1134 CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000001U; in ddr_setup()
1353 … CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000003U; //ENABLE DLY Control & PLL Control in ddr_setup()
1564 …CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00000000U; //DISABLE DLY Control & PLL Control in ddr_setup()
1637 CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0xffU; in ddr_setup()
1643 CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x00U; in ddr_setup()
2320 CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x1U; in ddr_setup()
2325 CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x8U; in ddr_setup()
3273 CFG_DDR_SGMII_PHY->expert_mode_en.expert_mode_en = 0x21U; in load_dq()
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Dmss_ddr_sgmii_phy_defs.h3734 __IO uint32_t expert_mode_en; member
4642 …__IO CFG_DDR_SGMII_PHY_expert_mode_en_TypeDef expert_mode_en; … member