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Searched refs:csr_custom (Results 1 – 2 of 2) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr.c4735 DDRCFG->csr_custom.PHY_RESET_CONTROL.PHY_RESET_CONTROL =\ in init_ddrc()
4737 DDRCFG->csr_custom.PHY_RESET_CONTROL.PHY_RESET_CONTROL =\ in init_ddrc()
4739 DDRCFG->csr_custom.PHY_PC_RANK.PHY_PC_RANK = LIBERO_SETTING_PHY_PC_RANK; in init_ddrc()
4740 DDRCFG->csr_custom.PHY_RANKS_TO_TRAIN.PHY_RANKS_TO_TRAIN =\ in init_ddrc()
4742 DDRCFG->csr_custom.PHY_WRITE_REQUEST.PHY_WRITE_REQUEST =\ in init_ddrc()
4744 DDRCFG->csr_custom.PHY_READ_REQUEST.PHY_READ_REQUEST =\ in init_ddrc()
4746 DDRCFG->csr_custom.PHY_WRITE_LEVEL_DELAY.PHY_WRITE_LEVEL_DELAY =\ in init_ddrc()
4748 DDRCFG->csr_custom.PHY_GATE_TRAIN_DELAY.PHY_GATE_TRAIN_DELAY =\ in init_ddrc()
4750 DDRCFG->csr_custom.PHY_EYE_TRAIN_DELAY.PHY_EYE_TRAIN_DELAY =\ in init_ddrc()
4752 DDRCFG->csr_custom.PHY_EYE_PAT.PHY_EYE_PAT = LIBERO_SETTING_PHY_EYE_PAT; in init_ddrc()
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Dmss_ddr_sgmii_regs.h4388 __IO DDR_CSR_APB_csr_custom_TypeDef csr_custom; /*!< Offset: 0x3c000 */ member