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Searched refs:bclk_phase (Results 1 – 1 of 1) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr.c1053 uint32_t bclk_phase, bclk90_phase,refclk_phase; in ddr_setup() local
1068 bclk_phase = ( i & 0x07UL ) << 8U; in ddr_setup()
1073 MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase); in ddr_setup()
1074 MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | bclk_phase | bclk90_phase); in ddr_setup()
1075 MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase); in ddr_setup()
1117 bclk_phase = ((bclk_answer+SW_TRAING_BCLK_SCLK_OFFSET) & 0x07UL ) << 8U; in ddr_setup()
1119 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase); in ddr_setup()
1120 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | bclk_phase | bclk90_phase); in ddr_setup()
1121 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase); in ddr_setup()
1385 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); in ddr_setup()
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