Searched refs:__IOM (Results 1 – 25 of 104) sorted by relevance
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549 __IOM uint32_t CTRL_0000; /*!< (@ 0x0000) GPIO_0000 Control */551 __IOM uint32_t CTRL_0002; /*!< (@ 0x0008) GPIO_0002 Control */552 __IOM uint32_t CTRL_0003; /*!< (@ 0x000c) GPIO_0003 Control */553 __IOM uint32_t CTRL_0004; /*!< (@ 0x0010) GPIO_0004 Control */555 __IOM uint32_t CTRL_0007; /*!< (@ 0x001c) GPIO_0007 Control */556 __IOM uint32_t CTRL_0010; /*!< (@ 0x0020) GPIO_0010 Control */557 __IOM uint32_t CTRL_0011;558 __IOM uint32_t CTRL_0012;559 __IOM uint32_t CTRL_0013;560 __IOM uint32_t CTRL_0014; /*!< (@ 0x0030) GPIO_0014 Control */[all …]
162 __IOM uint32_t BM_STS; /*! (@ 0x0000) Bus Master Status */163 __IOM uint32_t BM_IEN; /*! (@ 0x0004) Bus Master interrupt enable */164 __IOM uint32_t BM_CFG; /*! (@ 0x0008) Bus Master configuration */166 __IOM uint32_t BM1_CTRL; /*! (@ 0x0010) Bus Master 1 control */167 __IOM uint32_t BM1_HOST_ADDR_LSW; /*! (@ 0x0014) Bus Master 1 host address bits[31:0] */168 __IOM uint32_t BM1_HOST_ADDR_MSW; /*! (@ 0x0018) Bus Master 1 host address bits[63:32] */169 __IOM uint32_t BM1_EC_ADDR_LSW; /*! (@ 0x001c) Bus Master 1 EC address bits[31:0] */170 __IOM uint32_t BM1_EC_ADDR_MSW; /*! (@ 0x0020) Bus Master 1 EC address bits[63:32] */171 __IOM uint32_t BM2_CTRL; /*! (@ 0x0024) Bus Master 2 control */172 __IOM uint32_t BM2_HOST_ADDR_LSW; /*! (@ 0x0028) Bus Master 2 host address bits[31:0] */[all …]
303 __IOM uint32_t VW_EN_STS;305 __IOM uint8_t CAP_ID;306 __IOM uint8_t GLB_CAP0;307 __IOM uint8_t GLB_CAP1;308 __IOM uint8_t PC_CAP;309 __IOM uint8_t VW_CAP;310 __IOM uint8_t OOB_CAP;311 __IOM uint8_t FC_CAP;312 __IOM uint8_t PC_RDY;313 __IOM uint8_t OOB_RDY;[all …]
172 __IOM uint8_t RSVD1[4];173 __IOM uint32_t AHB_ERR_ADDR; /*!< (@ 0x0004) ECS AHB Error Address */174 __IOM uint32_t TEST08;175 __IOM uint32_t TEST0C;176 __IOM uint32_t TEST10;177 __IOM uint32_t AHB_ERR_CTRL; /*!< (@ 0x0014) ECS AHB Error Control */178 __IOM uint32_t INTR_CTRL; /*!< (@ 0x0018) ECS Interupt Control */179 __IOM uint32_t ETM_CTRL; /*!< (@ 0x001c) ECS ETM Trace Control */180 __IOM uint32_t DEBUG_CTRL; /*!< (@ 0x0020) ECS Debug Control */181 __IOM uint32_t OTP_LOCK; /*!< (@ 0x0024) ECS OTP Lock Enable */[all …]
155 __IOM uint8_t OS_H2E_MBOX; /*!< (@ 0x0000) OS space Host to EC mailbox register */156 __IOM uint8_t OS_E2H_MBOX; /*!< (@ 0x0001) OS space EC to Host mailbox register */157 __IOM uint8_t OS_EC_ADDR_LSB; /*!< (@ 0x0002) OS space EC memory address LSB register */158 __IOM uint8_t OS_EC_ADDR_MSB; /*!< (@ 0x0003) OS space EC memory address LSB register */159 __IOM uint32_t OS_EC_DATA; /*!< (@ 0x0004) OS space EC Data register */160 __IOM uint8_t OS_INT_SRC_LSB; /*!< (@ 0x0008) OS space Interrupt Source LSB register */161 __IOM uint8_t OS_INT_SRC_MSB; /*!< (@ 0x0009) OS space Interrupt Source MSB register */162 __IOM uint8_t OS_INT_MASK_LSB; /*!< (@ 0x000a) OS space Interrupt Mask LSB register */163 __IOM uint8_t OS_INT_MASK_MSB; /*!< (@ 0x000b) OS space Interrupt Mask MSB register */164 __IOM uint32_t OS_APP_ID; /*!< (@ 0x000c) OS space Application ID register */[all …]
167 __IOM uint32_t CNT; /*!< (@ 0x00000000) BTMR Count */168 __IOM uint32_t PRLD; /*!< (@ 0x00000004) BTMR Preload */169 __IOM uint8_t STS; /*!< (@ 0x00000008) BTMR Status */171 __IOM uint8_t IEN; /*!< (@ 0x0000000c) BTMR Interrupt Enable */173 __IOM uint32_t CTRL; /*!< (@ 0x00000010) BTMR Control */234 __IOM uint16_t PRLD; /*!< (@ 0x00000000) HTMR Preload */236 __IOM uint16_t CTRL; /*!< (@ 0x00000004) HTMR Control */315 __IOM uint32_t CTRL; /*!< (@ 0x00000000) CCT Control */316 __IOM uint32_t CAP0_CTRL; /*!< (@ 0x00000004) CCT Capture 0 Control */317 __IOM uint32_t CAP1_CTRL; /*!< (@ 0x00000008) CCT Capture 1 Control */[all …]
141 __IOM uint8_t SECONDS; /*! (@ 0x0000) RTC seconds */142 __IOM uint8_t SEC_ALARM; /*! (@ 0x0001) RTC seconds alarm */143 __IOM uint8_t MINUTES; /*! (@ 0x0002) RTC minutes */144 __IOM uint8_t MIN_ALARM; /*! (@ 0x0003) RTC minutes alarm */145 __IOM uint8_t HOURS; /*! (@ 0x0004) RTC hours */146 __IOM uint8_t HOURS_ALARM; /*! (@ 0x0005) RTC hours alarm */147 __IOM uint8_t DAY_OF_WEEK; /*! (@ 0x0006) RTC day of week */148 __IOM uint8_t DAY_OF_MONTH; /*! (@ 0x0007) RTC day of month */149 __IOM uint8_t MONTH; /*! (@ 0x0008) RTC month */150 __IOM uint8_t YEAR; /*! (@ 0x0009) RTC year */[all …]
133 __IOM uint32_t OS_DATA; /*!< (@ 0x0000) OS Data */134 __IOM uint8_t OS_CMD_STS; /*!< (@ 0x0004) OS Command(WO), Status(RO) */135 __IOM uint8_t OS_BYTE_CTRL; /*!< (@ 0x0005) OS Byte Control */137 __IOM uint32_t EC2OS_DATA; /*!< (@ 0x0100) EC to OS Data */138 __IOM uint8_t EC_STS; /*!< (@ 0x0104) EC Status */139 __IOM uint8_t EC_BYTE_CTRL; /*!< (@ 0x0105) EC Byte Control */141 __IOM uint32_t OS2EC_DATA; /*!< (@ 0x0108) OS to EC Data */235 __IOM uint8_t RT_STS1; /*!< (@ 0x0000) */236 __IOM uint8_t RT_STS2; /*!< (@ 0x0001) */237 __IOM uint8_t RT_EN1; /*!< (@ 0x0002) */[all …]
94 __IOM uint8_t OS_IDX; /*!< (@ 0x0000) OS Index */95 __IOM uint8_t OS_DATA; /*!< (@ 0x0001) OS Data */97 __IOM uint32_t HOST_TO_EC; /*!< (@ 0x0100) Host to EC */98 __IOM uint32_t EC_TO_HOST; /*!< (@ 0x0104) EC to Host */99 __IOM uint32_t SMI_SRC; /*!< (@ 0x0108) SMI Source */100 __IOM uint32_t SMI_MASK; /*!< (@ 0x010c) SMI Mask */101 __IOM uint32_t MBX_0_3; /*!< (@ 0x0110) Mailboxes 0 - 3 */102 __IOM uint32_t MBX_4_7; /*!< (@ 0x0114) Mailboxes 4 - 7 */103 __IOM uint32_t MBX_8_11; /*!< (@ 0x0118) Mailboxes 8 - 11 */104 __IOM uint32_t MBX_12_15; /*!< (@ 0x011c) Mailboxes 12 - 15 */[all …]
188 __IOM uint32_t CONTROL; /*!< (@ 0x0000) ADC Control */189 __IOM uint32_t DELAY; /*!< (@ 0x0004) ADC Delay */190 __IOM uint32_t STATUS; /*!< (@ 0x0008) ADC Status */191 __IOM uint32_t SINGLE; /*!< (@ 0x000C) ADC Single */192 __IOM uint32_t REPEAT; /*!< (@ 0x0010) ADC Repeat */193 __IOM uint32_t RDCH0; /*!< (@ 0x0014) ADC Chan0 Reading */194 __IOM uint32_t RDCH1; /*!< (@ 0x0018) ADC Chan1 Reading */195 __IOM uint32_t RDCH2; /*!< (@ 0x001C) ADC Chan2 Reading */196 __IOM uint32_t RDCH3; /*!< (@ 0x0020) ADC Chan3 Reading */197 __IOM uint32_t RDCH4; /*!< (@ 0x0024) ADC Chan4 Reading */[all …]
17 …__IOM uint32_t DEV_CTRL; /*!< (@ 0x00000000) Target device control register …18 …__IOM uint32_t DEV_ADDR; /*!< (@ 0x00000004) Target device address register …20 …__IOM uint32_t CMD; /*!< (@ 0x0000000C) Command register …21 …__IOM uint32_t RESP; /*!< (@ 0x00000010) Response register …27 …__IOM uint32_t IBI_QUE_STS; /*!< (@ 0x00000018) IBI Queue status register …28 …__IOM uint32_t QUE_THLD_CTRL; /*!< (@ 0x0000001C) Queue threshold control register…29 …__IOM uint32_t DB_THLD_CTRL; /*!< (@ 0x00000020) Data buffer threshold control re…30 …__IOM uint32_t IBI_QUE_CTRL; /*!< (@ 0x00000024) IBI Queue control register …32 …__IOM uint32_t RST_CTRL; /*!< (@ 0x00000034) Reset control register …33 …__IOM uint32_t TGT_EVT_STS; /*!< (@ 0x00000038) Target event status register …[all …]
17 …__IOM uint32_t DEV_CTRL; /*!< (@ 0x00000000) Target device control register …18 …__IOM uint32_t DEV_ADDR; /*!< (@ 0x00000004) Target device address register …20 …__IOM uint32_t CMD; /*!< (@ 0x0000000C) Command register …21 …__IOM uint32_t RESP; /*!< (@ 0x00000010) Response register …27 …__IOM uint32_t IBI_QUE_STS; /*!< (@ 0x00000018) IBI Queue status register …28 …__IOM uint32_t QUE_THLD_CTRL; /*!< (@ 0x0000001C) Queue threshold control register…29 …__IOM uint32_t DB_THLD_CTRL; /*!< (@ 0x00000020) Data buffer threshold control re…30 …__IOM uint32_t IBI_QUE_CTRL; /*!< (@ 0x00000024) IBI Queue control register …32 …__IOM uint32_t RST_CTRL; /*!< (@ 0x00000034) Reset control register …34 …__IOM uint32_t INTR_STS; /*!< (@ 0x0000003C) Interrupt status register …[all …]
17 …__IOM uint32_t START; /*!< (@ 0x00000000) TAF Flash Protection Region n st…18 …__IOM uint32_t LIMIT; /*!< (@ 0x00000004) TAF Flash Protection Region n li…19 …__IOM uint32_t WRBM; /*!< (@ 0x00000008) TAF Flash Protection Region writ…21 …__IOM uint32_t RDBM; /*!< (@ 0x0000000C) TAF Flash Protection Region read…35 …__IOM uint32_t COMM_MODE; /*!< (@ 0x000002B8) eSPI TAF Communication Mode regi…44 …__IOM uint32_t ECP_CMD; /*!< (@ 0x00000018) eSPI TAF EC Portal Command regis…45 …__IOM uint32_t ECP_FADDR; /*!< (@ 0x0000001C) eSPI TAF EC Portal Flash Address…46 …__IOM uint32_t ECP_START; /*!< (@ 0x00000020) eSPI TAF EC Portal Start registe…47 …__IOM uint32_t ECP_BADDR; /*!< (@ 0x00000024) eSPI TAF EC Portal Buffer Addres…49 …__IOM uint32_t ECP_STS; /*!< (@ 0x00000028) eSPI TAF EC Portal Status regist…[all …]
17 …__IOM uint32_t START; /*!< (@ 0x00000000) TAF Flash Protection Region n st…18 …__IOM uint32_t LIMIT; /*!< (@ 0x00000004) TAF Flash Protection Region n li…19 …__IOM uint32_t WRBM; /*!< (@ 0x00000008) TAF Flash Protection Region writ…21 …__IOM uint32_t RDBM; /*!< (@ 0x0000000C) TAF Flash Protection Region read…36 …__IOM uint32_t COMM_MODE; /*!< (@ 0x000002B8) eSPI TAF Communication Mode regi…45 …__IOM uint32_t ECP_CMD; /*!< (@ 0x00000018) eSPI TAF EC Portal Command regis…46 …__IOM uint32_t ECP_FADDR; /*!< (@ 0x0000001C) eSPI TAF EC Portal Flash Address…47 …__IOM uint32_t ECP_START; /*!< (@ 0x00000020) eSPI TAF EC Portal Start registe…48 …__IOM uint32_t ECP_BADDR; /*!< (@ 0x00000024) eSPI TAF EC Portal Buffer Addres…50 …__IOM uint32_t ECP_STS; /*!< (@ 0x00000028) eSPI TAF EC Portal Status regist…[all …]
19 …__IOM uint32_t AERRA; /*!< (@ 0x00000004) ECS AHB Error Address capture …21 …__IOM uint32_t OSCID; /*!< (@ 0x00000010) ECS Oscillator ID …22 …__IOM uint32_t AERRC; /*!< (@ 0x00000014) ECS AHB Error Address capture co…23 …__IOM uint32_t INTR_CTRL; /*!< (@ 0x00000018) ECS interrupt control …24 …__IOM uint32_t ETM_CTRL; /*!< (@ 0x0000001C) ECS ETM trace enable …25 …__IOM uint32_t DBG_CTRL; /*!< (@ 0x00000020) ECS Debug enable …26 …__IOM uint32_t SECLK; /*!< (@ 0x00000024) ECS security lock …27 …__IOM uint32_t WDTEVC; /*!< (@ 0x00000028) ECS WDT event count …29 …__IOM uint32_t PECI_CTRL; /*!< (@ 0x00000040) ECS PECI control …31 …__IOM uint32_t VCIFWO; /*!< (@ 0x00000050) ECS VCI firmware override …[all …]
18 …__IOM uint8_t RT_H2EMB; /*!< (@ 0x00000000) EMI Runtime: Host to EC mailbox …19 …__IOM uint8_t RT_E2HMB; /*!< (@ 0x00000001) EMI Runtime: EC to Host mailbox …20 …__IOM uint16_t RT_RGO; /*!< (@ 0x00000002) EMI Runtime: region and offset …21 …__IOM uint32_t RT_DATA; /*!< (@ 0x00000004) EMI Runtime: Data. Access size s…23 …__IOM uint16_t RT_ISRC; /*!< (@ 0x00000008) EMI Runtime: interrupt source bi…24 …__IOM uint16_t RT_IMASK; /*!< (@ 0x0000000A) EMI Runtime: interrupt source ma…25 …__IOM uint8_t RT_AID; /*!< (@ 0x0000000C) EMI Runtime: application ID …28 …__IOM uint8_t RT_ASAID; /*!< (@ 0x00000010) EMI Runtime: application ID assi…32 …__IOM uint8_t H2EMB; /*!< (@ 0x00000100) EMI EC-only: Host to EC mailbox …33 …__IOM uint8_t E2HMB; /*!< (@ 0x00000101) EMI EC-only: EC to Host mailbox …[all …]
18 …__IOM uint8_t RTIDX; /*!< (@ 0x00000000) eSPI IO Runtime Host Index regis…19 …__IOM uint8_t RTDAT; /*!< (@ 0x00000001) eSPI IO Runtime Host Data regist…24 …__IOM uint32_t PCSTS; /*!< (@ 0x00000114) eSPI IO PC Status register …25 …__IOM uint32_t PCIEN; /*!< (@ 0x00000118) eSPI IO PC interrupt enable regi…27 …__IOM uint32_t PCBINH[2]; /*!< (@ 0x00000120) eSPI IO PC BAR inhibit registers…29 …__IOM uint32_t PCBINIT; /*!< (@ 0x00000128) eSPI IO PC BAR init register …30 …__IOM uint32_t PCECIRQ; /*!< (@ 0x0000012C) eSPI IO PC EC IRQ register …31 …__IOM uint32_t PCCKNP; /*!< (@ 0x00000130) eSPI IO PC Clock NP register …35 …__IOM uint32_t PCLTRSTS; /*!< (@ 0x00000220) eSPI IO PC LTR Status register …36 …__IOM uint32_t PCLTREN; /*!< (@ 0x00000224) eSPI IO PC LTR Enable register …[all …]
20 …__IOM uint32_t REVISION; /*!< (@ 0x00000008) USB revision register …22 …__IOM uint32_t OTG_INTR_STS; /*!< (@ 0x00000010) OTG interrupt status register …23 …__IOM uint32_t OTG_INTR_CTRL; /*!< (@ 0x00000014) OTG interrupt control register …24 …__IOM uint32_t OTG_STS; /*!< (@ 0x00000018) OTG status register …25 …__IOM uint32_t OTG_CTRL; /*!< (@ 0x0000001C) OTG control register …27 …__IOM uint32_t CTRL_INTR_STS; /*!< (@ 0x00000080) Controller interrupt status regi…28 …__IOM uint32_t CTRL_INTR_EN; /*!< (@ 0x00000084) Controller interrupt enable regi…29 …__IOM uint32_t ERR_STAT; /*!< (@ 0x00000088) Controller interrupt error statu…30 …__IOM uint32_t ERR_STAT_EN; /*!< (@ 0x0000008C) Controller interrupt error enabl…31 …__IOM uint32_t USB_STS; /*!< (@ 0x00000090) USB transaction status register …[all …]
18 …__IOM uint8_t SECV; /*!< (@ 0x00000000) RTC seconds value …19 …__IOM uint8_t SECA; /*!< (@ 0x00000001) RTC seconds alarm …20 …__IOM uint8_t MINV; /*!< (@ 0x00000002) RTC minutes value …21 …__IOM uint8_t MINA; /*!< (@ 0x00000003) RTC minutes alarm …22 …__IOM uint8_t HRSV; /*!< (@ 0x00000004) RTC hours value and AM/PM indica…23 …__IOM uint8_t HRSA; /*!< (@ 0x00000005) RTC hours alarm …24 …__IOM uint8_t DOWV; /*!< (@ 0x00000006) RTC day of week value …25 …__IOM uint8_t DOMV; /*!< (@ 0x00000007) RTC day of month value …26 …__IOM uint8_t MONV; /*!< (@ 0x00000008) RTC month value …27 …__IOM uint8_t YEARV; /*!< (@ 0x00000009) RTC Year value …[all …]
18 …__IOM uint32_t SSC; /*!< (@ 0x00000000) PCR system sleep control …19 …__IOM uint32_t PCC; /*!< (@ 0x00000004) PCR processor clock control(divi…20 …__IOM uint32_t SCC; /*!< (@ 0x00000008) PCR slow clock control(divider) …21 …__IOM uint32_t OID; /*!< (@ 0x0000000C) PCR Oscillator ID and PLL lock i…22 …__IOM uint32_t PRS; /*!< (@ 0x00000010) PCR Power Reset Status …23 …__IOM uint32_t PRC; /*!< (@ 0x00000014) PCR Power Reset Control …25 …__IOM uint32_t TURBO_CLK; /*!< (@ 0x0000001C) PCR Turbo clock control …27 …__IOM uint32_t PP_LOCK; /*!< (@ 0x00000024) Peripheral Privilege Lock. Locks…30 …__IOM uint32_t SLP_EN[5]; /*!< (@ 0x00000030) The Sleep Enable Register contai…33 …__IOM uint32_t CLK_REQ[5]; /*!< (@ 0x00000050) The Clock Required Register cont…[all …]
30 …__IOM uint16_t VASZ; /*!< (@ 0x00000000) 16-bit register with valid(enabl…32 …__IOM uint16_t EC_SRAM_ADDR_15_0; /*!< (@ 0x00000002) EC SRAM region base address[15:0…33 …__IOM uint16_t EC_SRAM_ADDR_31_16; /*!< (@ 0x00000004) EC SRAM region base address[31:1…42 …__IOM uint16_t VALID; /*!< (@ 0x00000000) eSPI Memory Host memory valid en…43 …__IOM uint16_t HOST_MEM_ADDR_B15_0; /*!< (@ 0x00000002) Host memory address bits[15:0] …44 …__IOM uint16_t HOST_MEM_ADDR_B31_16; /*!< (@ 0x00000004) Host memory address bits[31:16] …45 …__IOM uint16_t RSVD_H3; /*!< (@ 0x00000006) Bits[63:48] reserved …46 …__IOM uint16_t RSVD_H4; /*!< (@ 0x00000008) Bits[79:64] reserved …56 …__IOM uint16_t HOST_ADDR_15_0; /*!< (@ 0x00000002) Host address[15:0] for accessing…58 …__IOM uint16_t HOST_ADDR_31_16; /*!< (@ 0x00000004) Host address[31:16] for access t…[all …]
29 …__IOM uint16_t VASZ; /*!< (@ 0x00000000) 16-bit register with valid(enabl…31 …__IOM uint16_t EC_SRAM_ADDR_15_0; /*!< (@ 0x00000002) EC SRAM region base address[15:0…32 …__IOM uint16_t EC_SRAM_ADDR_31_16; /*!< (@ 0x00000004) EC SRAM region base address[31:1…41 …__IOM uint16_t VALID; /*!< (@ 0x00000000) eSPI Memory Host memory valid en…42 …__IOM uint16_t HOST_MEM_ADDR_B15_0; /*!< (@ 0x00000002) Host memory address bits[15:0] …43 …__IOM uint16_t HOST_MEM_ADDR_B31_16; /*!< (@ 0x00000004) Host memory address bits[31:16] …44 …__IOM uint16_t RSVD_H3; /*!< (@ 0x00000006) Bits[63:48] reserved …45 …__IOM uint16_t RSVD_H4; /*!< (@ 0x00000008) Bits[79:64] reserved …55 …__IOM uint16_t HOST_ADDR_15_0; /*!< (@ 0x00000002) Host address[15:0] for accessing…57 …__IOM uint16_t HOST_ADDR_31_16; /*!< (@ 0x00000004) Host address[31:16] for access t…[all …]
18 …__IOM uint32_t SSC; /*!< (@ 0x00000000) PCR system sleep control …19 …__IOM uint32_t PCC; /*!< (@ 0x00000004) PCR processor clock control(divi…20 …__IOM uint32_t SCC; /*!< (@ 0x00000008) PCR slow clock control(divider) …21 …__IOM uint32_t OID; /*!< (@ 0x0000000C) PCR Oscillator ID and PLL lock i…22 …__IOM uint32_t PRS; /*!< (@ 0x00000010) PCR Power Reset Status …23 …__IOM uint32_t PRC; /*!< (@ 0x00000014) PCR Power Reset Control …25 …__IOM uint32_t TURBO_CLK; /*!< (@ 0x0000001C) PCR Turbo clock control …27 …__IOM uint32_t SLP_EN[5]; /*!< (@ 0x00000030) The Sleep Enable Register contai…30 …__IOM uint32_t CLK_REQ[5]; /*!< (@ 0x00000050) The Clock Required Register cont…33 …__IOM uint32_t RST_EN[5]; /*!< (@ 0x00000070) The Reset Register contains bit …[all …]
