1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_QSPI_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_QSPI_COMPONENT_FIXUP_H_ 9 10 /* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint32_t :22; /*!< bit: 2..23 Reserved */ 17 uint32_t LASTXFER:1; /*!< bit: 24 Last Transfer */ 18 uint32_t :7; /*!< bit: 25..31 Reserved */ 19 } bit; /*!< Structure used for bit access */ 20 uint32_t reg; /*!< Type used for register access */ 21 } QSPI_CTRLA_Type; 22 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 23 24 /* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */ 25 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 26 typedef union { 27 struct { 28 uint32_t MODE:1; /*!< bit: 0 Serial Memory Mode */ 29 uint32_t LOOPEN:1; /*!< bit: 1 Local Loopback Enable */ 30 uint32_t WDRBT:1; /*!< bit: 2 Wait Data Read Before Transfer */ 31 uint32_t SMEMREG:1; /*!< bit: 3 Serial Memory reg */ 32 uint32_t CSMODE:2; /*!< bit: 4.. 5 Chip Select Mode */ 33 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 34 uint32_t DATALEN:4; /*!< bit: 8..11 Data Length */ 35 uint32_t :4; /*!< bit: 12..15 Reserved */ 36 uint32_t DLYBCT:8; /*!< bit: 16..23 Delay Between Consecutive Transfers */ 37 uint32_t DLYCS:8; /*!< bit: 24..31 Minimum Inactive CS Delay */ 38 } bit; /*!< Structure used for bit access */ 39 uint32_t reg; /*!< Type used for register access */ 40 } QSPI_CTRLB_Type; 41 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 42 43 /* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */ 44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 45 typedef union { 46 struct { 47 uint32_t CPOL:1; /*!< bit: 0 Clock Polarity */ 48 uint32_t CPHA:1; /*!< bit: 1 Clock Phase */ 49 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 50 uint32_t BAUD:8; /*!< bit: 8..15 Serial Clock Baud Rate */ 51 uint32_t DLYBS:8; /*!< bit: 16..23 Delay Before SCK */ 52 uint32_t :8; /*!< bit: 24..31 Reserved */ 53 } bit; /*!< Structure used for bit access */ 54 uint32_t reg; /*!< Type used for register access */ 55 } QSPI_BAUD_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 /* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) ( R/ 32) Receive Data -------- */ 59 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 60 typedef union { 61 struct { 62 uint32_t DATA:16; /*!< bit: 0..15 Receive Data */ 63 uint32_t :16; /*!< bit: 16..31 Reserved */ 64 } bit; /*!< Structure used for bit access */ 65 uint32_t reg; /*!< Type used for register access */ 66 } QSPI_RXDATA_Type; 67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 /* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */ 70 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 71 typedef union { 72 struct { 73 uint32_t DATA:16; /*!< bit: 0..15 Transmit Data */ 74 uint32_t :16; /*!< bit: 16..31 Reserved */ 75 } bit; /*!< Structure used for bit access */ 76 uint32_t reg; /*!< Type used for register access */ 77 } QSPI_TXDATA_Type; 78 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 80 /* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */ 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 82 typedef union { 83 struct { 84 uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Disable */ 85 uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Disable */ 86 uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Disable */ 87 uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Disable */ 88 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 89 uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Disable */ 90 uint32_t :1; /*!< bit: 9 Reserved */ 91 uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Disable */ 92 uint32_t :21; /*!< bit: 11..31 Reserved */ 93 } bit; /*!< Structure used for bit access */ 94 uint32_t reg; /*!< Type used for register access */ 95 } QSPI_INTENCLR_Type; 96 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 97 /* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */ 98 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 99 typedef union { 100 struct { 101 uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Enable */ 102 uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Enable */ 103 uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Enable */ 104 uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Enable */ 105 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 106 uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Enable */ 107 uint32_t :1; /*!< bit: 9 Reserved */ 108 uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Enable */ 109 uint32_t :21; /*!< bit: 11..31 Reserved */ 110 } bit; /*!< Structure used for bit access */ 111 uint32_t reg; /*!< Type used for register access */ 112 } QSPI_INTENSET_Type; 113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 114 115 /* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */ 116 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 117 typedef union { // __I to avoid read-modify-write on write-to-clear register 118 struct { 119 __I uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full */ 120 __I uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty */ 121 __I uint32_t TXC:1; /*!< bit: 2 Transmission Complete */ 122 __I uint32_t ERROR:1; /*!< bit: 3 Overrun Error */ 123 __I uint32_t :4; /*!< bit: 4.. 7 Reserved */ 124 __I uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise */ 125 __I uint32_t :1; /*!< bit: 9 Reserved */ 126 __I uint32_t INSTREND:1; /*!< bit: 10 Instruction End */ 127 __I uint32_t :21; /*!< bit: 11..31 Reserved */ 128 } bit; /*!< Structure used for bit access */ 129 uint32_t reg; /*!< Type used for register access */ 130 } QSPI_INTFLAG_Type; 131 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 132 133 /* -------- QSPI_STATUS : (QSPI Offset: 0x20) ( R/ 32) Status Register -------- */ 134 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 135 typedef union { 136 struct { 137 uint32_t :1; /*!< bit: 0 Reserved */ 138 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 139 uint32_t :7; /*!< bit: 2.. 8 Reserved */ 140 uint32_t CSSTATUS:1; /*!< bit: 9 Chip Select */ 141 uint32_t :22; /*!< bit: 10..31 Reserved */ 142 } bit; /*!< Structure used for bit access */ 143 uint32_t reg; /*!< Type used for register access */ 144 } QSPI_STATUS_Type; 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 146 147 /* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */ 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 149 typedef union { 150 struct { 151 uint32_t ADDR:32; /*!< bit: 0..31 Instruction Address */ 152 } bit; /*!< Structure used for bit access */ 153 uint32_t reg; /*!< Type used for register access */ 154 } QSPI_INSTRADDR_Type; 155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 156 157 /* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */ 158 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 159 typedef union { 160 struct { 161 uint32_t INSTR:8; /*!< bit: 0.. 7 Instruction Code */ 162 uint32_t :8; /*!< bit: 8..15 Reserved */ 163 uint32_t OPTCODE:8; /*!< bit: 16..23 Option Code */ 164 uint32_t :8; /*!< bit: 24..31 Reserved */ 165 } bit; /*!< Structure used for bit access */ 166 uint32_t reg; /*!< Type used for register access */ 167 } QSPI_INSTRCTRL_Type; 168 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 169 170 /* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */ 171 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 172 typedef union { 173 struct { 174 uint32_t WIDTH:3; /*!< bit: 0.. 2 Instruction Code, Address, Option Code and Data Width */ 175 uint32_t :1; /*!< bit: 3 Reserved */ 176 uint32_t INSTREN:1; /*!< bit: 4 Instruction Enable */ 177 uint32_t ADDREN:1; /*!< bit: 5 Address Enable */ 178 uint32_t OPTCODEEN:1; /*!< bit: 6 Option Enable */ 179 uint32_t DATAEN:1; /*!< bit: 7 Data Enable */ 180 uint32_t OPTCODELEN:2; /*!< bit: 8.. 9 Option Code Length */ 181 uint32_t ADDRLEN:1; /*!< bit: 10 Address Length */ 182 uint32_t :1; /*!< bit: 11 Reserved */ 183 uint32_t TFRTYPE:2; /*!< bit: 12..13 Data Transfer Type */ 184 uint32_t CRMODE:1; /*!< bit: 14 Continuous Read Mode */ 185 uint32_t DDREN:1; /*!< bit: 15 Double Data Rate Enable */ 186 uint32_t DUMMYLEN:5; /*!< bit: 16..20 Dummy Cycles Length */ 187 uint32_t :11; /*!< bit: 21..31 Reserved */ 188 } bit; /*!< Structure used for bit access */ 189 uint32_t reg; /*!< Type used for register access */ 190 } QSPI_INSTRFRAME_Type; 191 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 192 /* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */ 193 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 194 typedef union { 195 struct { 196 uint32_t ENABLE:1; /*!< bit: 0 Scrambling/Unscrambling Enable */ 197 uint32_t RANDOMDIS:1; /*!< bit: 1 Scrambling/Unscrambling Random Value Disable */ 198 uint32_t :30; /*!< bit: 2..31 Reserved */ 199 } bit; /*!< Structure used for bit access */ 200 uint32_t reg; /*!< Type used for register access */ 201 } QSPI_SCRAMBCTRL_Type; 202 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 203 204 /* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 struct { 208 uint32_t KEY:32; /*!< bit: 0..31 Scrambling User Key */ 209 } bit; /*!< Structure used for bit access */ 210 uint32_t reg; /*!< Type used for register access */ 211 } QSPI_SCRAMBKEY_Type; 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 213 214 /** \brief QSPI APB hardware registers */ 215 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 216 typedef struct { 217 __IO QSPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 218 __IO QSPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ 219 __IO QSPI_BAUD_Type BAUD; /**< \brief Offset: 0x08 (R/W 32) Baud Rate */ 220 __I QSPI_RXDATA_Type RXDATA; /**< \brief Offset: 0x0C (R/ 32) Receive Data */ 221 __O QSPI_TXDATA_Type TXDATA; /**< \brief Offset: 0x10 ( /W 32) Transmit Data */ 222 __IO QSPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Clear */ 223 __IO QSPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x18 (R/W 32) Interrupt Enable Set */ 224 __IO QSPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */ 225 __I QSPI_STATUS_Type STATUS; /**< \brief Offset: 0x20 (R/ 32) Status Register */ 226 RoReg8 Reserved1[0xC]; 227 __IO QSPI_INSTRADDR_Type INSTRADDR; /**< \brief Offset: 0x30 (R/W 32) Instruction Address */ 228 __IO QSPI_INSTRCTRL_Type INSTRCTRL; /**< \brief Offset: 0x34 (R/W 32) Instruction Code */ 229 __IO QSPI_INSTRFRAME_Type INSTRFRAME; /**< \brief Offset: 0x38 (R/W 32) Instruction Frame */ 230 RoReg8 Reserved2[0x4]; 231 __IO QSPI_SCRAMBCTRL_Type SCRAMBCTRL; /**< \brief Offset: 0x40 (R/W 32) Scrambling Mode */ 232 __O QSPI_SCRAMBKEY_Type SCRAMBKEY; /**< \brief Offset: 0x44 ( /W 32) Scrambling Key */ 233 } Qspi; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 #endif /* _MICROCHIP_PIC32CXSG_QSPI_COMPONENT_FIXUP_H_ */ 237
