1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_SUPC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_SUPC_COMPONENT_FIXUP_H_ 9 10 /* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ 15 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ 16 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ 17 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 18 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ 19 uint32_t :1; /*!< bit: 9 Reserved */ 20 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ 21 uint32_t :21; /*!< bit: 11..31 Reserved */ 22 } bit; /*!< Structure used for bit access */ 23 uint32_t reg; /*!< Type used for register access */ 24 } SUPC_INTENCLR_Type; 25 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 26 27 /* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 28 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 29 typedef union { 30 struct { 31 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ 32 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ 33 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ 34 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 35 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ 36 uint32_t :1; /*!< bit: 9 Reserved */ 37 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ 38 uint32_t :21; /*!< bit: 11..31 Reserved */ 39 } bit; /*!< Structure used for bit access */ 40 uint32_t reg; /*!< Type used for register access */ 41 } SUPC_INTENSET_Type; 42 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 43 44 /* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 45 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 46 typedef union { // __I to avoid read-modify-write on write-to-clear register 47 struct { 48 __I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ 49 __I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ 50 __I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ 51 __I uint32_t :5; /*!< bit: 3.. 7 Reserved */ 52 __I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ 53 __I uint32_t :1; /*!< bit: 9 Reserved */ 54 __I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ 55 __I uint32_t :21; /*!< bit: 11..31 Reserved */ 56 } bit; /*!< Structure used for bit access */ 57 uint32_t reg; /*!< Type used for register access */ 58 } SUPC_INTFLAG_Type; 59 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 /* -------- SUPC_STATUS : (SUPC Offset: 0x0C) ( R/ 32) Power and Clocks Status -------- */ 62 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 63 typedef union { 64 struct { 65 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ 66 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ 67 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ 68 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 69 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ 70 uint32_t :1; /*!< bit: 9 Reserved */ 71 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ 72 uint32_t :21; /*!< bit: 11..31 Reserved */ 73 } bit; /*!< Structure used for bit access */ 74 uint32_t reg; /*!< Type used for register access */ 75 } SUPC_STATUS_Type; 76 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 77 78 /* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */ 79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 80 typedef union { 81 struct { 82 uint32_t :1; /*!< bit: 0 Reserved */ 83 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 84 uint32_t ACTION:2; /*!< bit: 2.. 3 Action when Threshold Crossed */ 85 uint32_t STDBYCFG:1; /*!< bit: 4 Configuration in Standby mode */ 86 uint32_t RUNSTDBY:1; /*!< bit: 5 Run in Standby mode */ 87 uint32_t RUNHIB:1; /*!< bit: 6 Run in Hibernate mode */ 88 uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */ 89 uint32_t HYST:4; /*!< bit: 8..11 Hysteresis value */ 90 uint32_t PSEL:3; /*!< bit: 12..14 Prescaler Select */ 91 uint32_t :1; /*!< bit: 15 Reserved */ 92 uint32_t LEVEL:8; /*!< bit: 16..23 Threshold Level for VDD */ 93 uint32_t VBATLEVEL:8; /*!< bit: 24..31 Threshold Level in battery backup sleep mode for VBAT */ 94 } bit; /*!< Structure used for bit access */ 95 uint32_t reg; /*!< Type used for register access */ 96 } SUPC_BOD33_Type; 97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 /* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ 100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 101 typedef union { 102 struct { 103 uint32_t :1; /*!< bit: 0 Reserved */ 104 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 105 uint32_t SEL:1; /*!< bit: 2 Voltage Regulator Selection */ 106 uint32_t :4; /*!< bit: 3.. 6 Reserved */ 107 uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */ 108 uint32_t :8; /*!< bit: 8..15 Reserved */ 109 uint32_t VSEN:1; /*!< bit: 16 Voltage Scaling Enable */ 110 uint32_t :7; /*!< bit: 17..23 Reserved */ 111 uint32_t VSPER:3; /*!< bit: 24..26 Voltage Scaling Period */ 112 uint32_t :5; /*!< bit: 27..31 Reserved */ 113 } bit; /*!< Structure used for bit access */ 114 uint32_t reg; /*!< Type used for register access */ 115 } SUPC_VREG_Type; 116 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 117 118 /* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */ 119 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 120 typedef union { 121 struct { 122 uint32_t :1; /*!< bit: 0 Reserved */ 123 uint32_t :1; /*!< bit: 1 Reserved */ 124 uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */ 125 uint32_t :1; /*!< bit: 3 Reserved */ 126 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 127 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 128 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */ 129 uint32_t :8; /*!< bit: 8..15 Reserved */ 130 uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */ 131 uint32_t :12; /*!< bit: 20..31 Reserved */ 132 } bit; /*!< Structure used for bit access */ 133 uint32_t reg; /*!< Type used for register access */ 134 } SUPC_VREF_Type; 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 /* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */ 138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 139 typedef union { 140 struct { 141 uint32_t CONF:1; /*!< bit: 0 Battery Backup Configuration */ 142 uint32_t :1; /*!< bit: 1 Reserved */ 143 uint32_t WAKEEN:1; /*!< bit: 2 Wake Enable */ 144 uint32_t :29; /*!< bit: 3..31 Reserved */ 145 } bit; /*!< Structure used for bit access */ 146 uint32_t reg; /*!< Type used for register access */ 147 } SUPC_BBPS_Type; 148 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 149 150 /* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */ 151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 152 typedef union { 153 struct { 154 uint32_t EN:2; /*!< bit: 0.. 1 Enable Output */ 155 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 156 uint32_t CLR:2; /*!< bit: 8.. 9 Clear Output */ 157 uint32_t :6; /*!< bit: 10..15 Reserved */ 158 uint32_t SET:2; /*!< bit: 16..17 Set Output */ 159 uint32_t :6; /*!< bit: 18..23 Reserved */ 160 uint32_t RTCTGL:2; /*!< bit: 24..25 RTC Toggle Output */ 161 uint32_t :6; /*!< bit: 26..31 Reserved */ 162 } bit; /*!< Structure used for bit access */ 163 uint32_t reg; /*!< Type used for register access */ 164 } SUPC_BKOUT_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 /* -------- SUPC_BKIN : (SUPC Offset: 0x28) ( R/ 32) Backup Input Control -------- */ 168 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 169 typedef union { 170 struct { 171 uint32_t BKIN:8; /*!< bit: 0.. 7 Backup Input Value */ 172 uint32_t :24; /*!< bit: 8..31 Reserved */ 173 } bit; /*!< Structure used for bit access */ 174 uint32_t reg; /*!< Type used for register access */ 175 } SUPC_BKIN_Type; 176 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 177 178 /** \brief SUPC hardware registers */ 179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 180 typedef struct { 181 __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 182 __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 183 __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 184 __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 185 __IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */ 186 RoReg8 Reserved1[0x4]; 187 __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */ 188 __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */ 189 __IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */ 190 __IO SUPC_BKOUT_Type BKOUT; /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */ 191 __I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control */ 192 } Supc; 193 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 194 195 #endif /* _MICROCHIP_PIC32CXSG_SUPC_COMPONENT_FIXUP_H_ */ 196
