1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_EVSYS_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_EVSYS_COMPONENT_FIXUP_H_ 9 10 /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x00) (R/W 32) Channel n Control -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */ 15 uint32_t :1; /*!< bit: 7 Reserved */ 16 uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */ 17 uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */ 18 uint32_t :2; /*!< bit: 12..13 Reserved */ 19 uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */ 20 uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */ 21 uint32_t :16; /*!< bit: 16..31 Reserved */ 22 } bit; /*!< Structure used for bit access */ 23 uint32_t reg; /*!< Type used for register access */ 24 } EVSYS_CHANNEL_Type; 25 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 26 27 /* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x04) (R/W 8) Channel n Interrupt Enable Clear -------- */ 28 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 29 typedef union { 30 struct { 31 uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Disable */ 32 uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Disable */ 33 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 34 } bit; /*!< Structure used for bit access */ 35 uint8_t reg; /*!< Type used for register access */ 36 } EVSYS_CHINTENCLR_Type; 37 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 38 39 /* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x05) (R/W 8) Channel n Interrupt Enable Set -------- */ 40 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 41 typedef union { 42 struct { 43 uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Enable */ 44 uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Enable */ 45 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 46 } bit; /*!< Structure used for bit access */ 47 uint8_t reg; /*!< Type used for register access */ 48 } EVSYS_CHINTENSET_Type; 49 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 50 51 /* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x06) (R/W 8) Channel n Interrupt Flag Status and Clear -------- */ 52 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 53 typedef union { // __I to avoid read-modify-write on write-to-clear register 54 struct { 55 __I uint8_t OVR:1; /*!< bit: 0 Channel Overrun */ 56 __I uint8_t EVD:1; /*!< bit: 1 Channel Event Detected */ 57 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 58 } bit; /*!< Structure used for bit access */ 59 uint8_t reg; /*!< Type used for register access */ 60 } EVSYS_CHINTFLAG_Type; 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x07) ( R/ 8) Channel n Status -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint8_t RDYUSR:1; /*!< bit: 0 Ready User */ 68 uint8_t BUSYCH:1; /*!< bit: 1 Busy Channel */ 69 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 70 } bit; /*!< Structure used for bit access */ 71 uint8_t reg; /*!< Type used for register access */ 72 } EVSYS_CHSTATUS_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 /* -------- EVSYS_CTRLA : (EVSYS Offset: 0x00) (R/W 8) Control -------- */ 76 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 77 typedef union { 78 struct { 79 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 80 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 81 } bit; /*!< Structure used for bit access */ 82 uint8_t reg; /*!< Type used for register access */ 83 } EVSYS_CTRLA_Type; 84 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 85 86 /* -------- EVSYS_SWEVT : (EVSYS Offset: 0x04) ( /W 32) Software Event -------- */ 87 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 88 typedef union { 89 struct { 90 uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */ 91 uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */ 92 uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */ 93 uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */ 94 uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */ 95 uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */ 96 uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */ 97 uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */ 98 uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */ 99 uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */ 100 uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */ 101 uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */ 102 uint32_t CHANNEL12:1; /*!< bit: 12 Channel 12 Software Selection */ 103 uint32_t CHANNEL13:1; /*!< bit: 13 Channel 13 Software Selection */ 104 uint32_t CHANNEL14:1; /*!< bit: 14 Channel 14 Software Selection */ 105 uint32_t CHANNEL15:1; /*!< bit: 15 Channel 15 Software Selection */ 106 uint32_t CHANNEL16:1; /*!< bit: 16 Channel 16 Software Selection */ 107 uint32_t CHANNEL17:1; /*!< bit: 17 Channel 17 Software Selection */ 108 uint32_t CHANNEL18:1; /*!< bit: 18 Channel 18 Software Selection */ 109 uint32_t CHANNEL19:1; /*!< bit: 19 Channel 19 Software Selection */ 110 uint32_t CHANNEL20:1; /*!< bit: 20 Channel 20 Software Selection */ 111 uint32_t CHANNEL21:1; /*!< bit: 21 Channel 21 Software Selection */ 112 uint32_t CHANNEL22:1; /*!< bit: 22 Channel 22 Software Selection */ 113 uint32_t CHANNEL23:1; /*!< bit: 23 Channel 23 Software Selection */ 114 uint32_t CHANNEL24:1; /*!< bit: 24 Channel 24 Software Selection */ 115 uint32_t CHANNEL25:1; /*!< bit: 25 Channel 25 Software Selection */ 116 uint32_t CHANNEL26:1; /*!< bit: 26 Channel 26 Software Selection */ 117 uint32_t CHANNEL27:1; /*!< bit: 27 Channel 27 Software Selection */ 118 uint32_t CHANNEL28:1; /*!< bit: 28 Channel 28 Software Selection */ 119 uint32_t CHANNEL29:1; /*!< bit: 29 Channel 29 Software Selection */ 120 uint32_t CHANNEL30:1; /*!< bit: 30 Channel 30 Software Selection */ 121 uint32_t CHANNEL31:1; /*!< bit: 31 Channel 31 Software Selection */ 122 } bit; /*!< Structure used for bit access */ 123 struct { 124 uint32_t CHANNEL:32; /*!< bit: 0..31 Channel x Software Selection */ 125 } vec; /*!< Structure used for vec access */ 126 uint32_t reg; /*!< Type used for register access */ 127 } EVSYS_SWEVT_Type; 128 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 129 130 /* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x08) (R/W 8) Priority Control -------- */ 131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 132 typedef union { 133 struct { 134 uint8_t PRI:4; /*!< bit: 0.. 3 Channel Priority Number */ 135 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 136 uint8_t RREN:1; /*!< bit: 7 Round-Robin Scheduling Enable */ 137 } bit; /*!< Structure used for bit access */ 138 uint8_t reg; /*!< Type used for register access */ 139 } EVSYS_PRICTRL_Type; 140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 141 142 /* -------- EVSYS_INTPEND : (EVSYS Offset: 0x10) (R/W 16) Channel Pending Interrupt -------- */ 143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 144 typedef union { 145 struct { 146 uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ 147 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 148 uint16_t OVR:1; /*!< bit: 8 Channel Overrun */ 149 uint16_t EVD:1; /*!< bit: 9 Channel Event Detected */ 150 uint16_t :4; /*!< bit: 10..13 Reserved */ 151 uint16_t READY:1; /*!< bit: 14 Ready */ 152 uint16_t BUSY:1; /*!< bit: 15 Busy */ 153 } bit; /*!< Structure used for bit access */ 154 uint16_t reg; /*!< Type used for register access */ 155 } EVSYS_INTPEND_Type; 156 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 157 158 /* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x14) ( R/ 32) Interrupt Status -------- */ 159 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 160 typedef union { 161 struct { 162 uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ 163 uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ 164 uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ 165 uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ 166 uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ 167 uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ 168 uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ 169 uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ 170 uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ 171 uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ 172 uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ 173 uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ 174 uint32_t :20; /*!< bit: 12..31 Reserved */ 175 } bit; /*!< Structure used for bit access */ 176 struct { 177 uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ 178 uint32_t :20; /*!< bit: 12..31 Reserved */ 179 } vec; /*!< Structure used for vec access */ 180 uint32_t reg; /*!< Type used for register access */ 181 } EVSYS_INTSTATUS_Type; 182 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 183 184 /* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x18) ( R/ 32) Busy Channels -------- */ 185 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 186 typedef union { 187 struct { 188 uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ 189 uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ 190 uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ 191 uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ 192 uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ 193 uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ 194 uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ 195 uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ 196 uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ 197 uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ 198 uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ 199 uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ 200 uint32_t :20; /*!< bit: 12..31 Reserved */ 201 } bit; /*!< Structure used for bit access */ 202 struct { 203 uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ 204 uint32_t :20; /*!< bit: 12..31 Reserved */ 205 } vec; /*!< Structure used for vec access */ 206 uint32_t reg; /*!< Type used for register access */ 207 } EVSYS_BUSYCH_Type; 208 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 209 210 /* -------- EVSYS_READYUSR : (EVSYS Offset: 0x1C) ( R/ 32) Ready Users -------- */ 211 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 212 typedef union { 213 struct { 214 uint32_t READYUSR0:1; /*!< bit: 0 Ready User for Channel 0 */ 215 uint32_t READYUSR1:1; /*!< bit: 1 Ready User for Channel 1 */ 216 uint32_t READYUSR2:1; /*!< bit: 2 Ready User for Channel 2 */ 217 uint32_t READYUSR3:1; /*!< bit: 3 Ready User for Channel 3 */ 218 uint32_t READYUSR4:1; /*!< bit: 4 Ready User for Channel 4 */ 219 uint32_t READYUSR5:1; /*!< bit: 5 Ready User for Channel 5 */ 220 uint32_t READYUSR6:1; /*!< bit: 6 Ready User for Channel 6 */ 221 uint32_t READYUSR7:1; /*!< bit: 7 Ready User for Channel 7 */ 222 uint32_t READYUSR8:1; /*!< bit: 8 Ready User for Channel 8 */ 223 uint32_t READYUSR9:1; /*!< bit: 9 Ready User for Channel 9 */ 224 uint32_t READYUSR10:1; /*!< bit: 10 Ready User for Channel 10 */ 225 uint32_t READYUSR11:1; /*!< bit: 11 Ready User for Channel 11 */ 226 uint32_t :20; /*!< bit: 12..31 Reserved */ 227 } bit; /*!< Structure used for bit access */ 228 struct { 229 uint32_t READYUSR:12; /*!< bit: 0..11 Ready User for Channel x */ 230 uint32_t :20; /*!< bit: 12..31 Reserved */ 231 } vec; /*!< Structure used for vec access */ 232 uint32_t reg; /*!< Type used for register access */ 233 } EVSYS_READYUSR_Type; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 /* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */ 237 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 238 typedef union { 239 struct { 240 uint32_t CHANNEL:6; /*!< bit: 0.. 5 Channel Event Selection */ 241 uint32_t :26; /*!< bit: 6..31 Reserved */ 242 } bit; /*!< Structure used for bit access */ 243 uint32_t reg; /*!< Type used for register access */ 244 } EVSYS_USER_Type; 245 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 246 247 /** \brief EvsysChannel hardware registers */ 248 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 249 typedef struct { 250 __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x000 (R/W 32) Channel n Control */ 251 __IO EVSYS_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x004 (R/W 8) Channel n Interrupt Enable Clear */ 252 __IO EVSYS_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x005 (R/W 8) Channel n Interrupt Enable Set */ 253 __IO EVSYS_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x006 (R/W 8) Channel n Interrupt Flag Status and Clear */ 254 __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x007 (R/ 8) Channel n Status */ 255 } EvsysChannel; 256 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 257 258 /** \brief EVSYS hardware registers */ 259 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 260 typedef struct { 261 __IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control */ 262 RoReg8 Reserved1[0x3]; 263 __O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x004 ( /W 32) Software Event */ 264 __IO EVSYS_PRICTRL_Type PRICTRL; /**< \brief Offset: 0x008 (R/W 8) Priority Control */ 265 RoReg8 Reserved2[0x7]; 266 __IO EVSYS_INTPEND_Type INTPEND; /**< \brief Offset: 0x010 (R/W 16) Channel Pending Interrupt */ 267 RoReg8 Reserved3[0x2]; 268 __I EVSYS_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x014 (R/ 32) Interrupt Status */ 269 __I EVSYS_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x018 (R/ 32) Busy Channels */ 270 __I EVSYS_READYUSR_Type READYUSR; /**< \brief Offset: 0x01C (R/ 32) Ready Users */ 271 EvsysChannel Channel[EVSYS_CHANNEL_NUMBER]; /**< \brief Offset: 0x020 EvsysChannel groups [CHANNELS] */ 272 __IO EVSYS_USER_Type USER[67]; /**< \brief Offset: 0x120 (R/W 32) User Multiplexer n */ 273 } Evsys; 274 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 275 276 #endif /* _MICROCHIP_PIC32CXSG_EVSYS_COMPONENT_FIXUP_H_ */ 277
