1 /*
2  * Copyright (c) 2024 Microchip
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _MICROCHIP_PIC32CXSG_GMAC_COMPONENT_FIXUP_H_
8 #define _MICROCHIP_PIC32CXSG_GMAC_COMPONENT_FIXUP_H_
9 
10 /* -------- GMAC_SAB : (GMAC Offset: 0x00) (R/W 32) Specific Address Bottom [31:0] Register -------- */
11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
12 typedef union {
13   struct {
14     uint32_t ADDR:32;          /*!< bit:  0..31  Specific Address 1                 */
15   } bit;                       /*!< Structure used for bit  access                  */
16   uint32_t reg;                /*!< Type      used for register access              */
17 } GMAC_SAB_Type;
18 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
19 
20 /* -------- GMAC_SAT : (GMAC Offset: 0x04) (R/W 32) Specific Address Top [47:32] Register -------- */
21 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
22 typedef union {
23   struct {
24     uint32_t ADDR:16;          /*!< bit:  0..15  Specific Address 1                 */
25     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
26   } bit;                       /*!< Structure used for bit  access                  */
27   uint32_t reg;                /*!< Type      used for register access              */
28 } GMAC_SAT_Type;
29 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
30 
31 /* -------- GMAC_NCR : (GMAC Offset: 0x00) (R/W 32) Network Control Register -------- */
32 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
33 typedef union {
34   struct {
35     uint32_t :1;               /*!< bit:      0  Reserved                           */
36     uint32_t LBL:1;            /*!< bit:      1  Loop Back Local                    */
37     uint32_t RXEN:1;           /*!< bit:      2  Receive Enable                     */
38     uint32_t TXEN:1;           /*!< bit:      3  Transmit Enable                    */
39     uint32_t MPE:1;            /*!< bit:      4  Management Port Enable             */
40     uint32_t CLRSTAT:1;        /*!< bit:      5  Clear Statistics Registers         */
41     uint32_t INCSTAT:1;        /*!< bit:      6  Increment Statistics Registers     */
42     uint32_t WESTAT:1;         /*!< bit:      7  Write Enable for Statistics Registers */
43     uint32_t BP:1;             /*!< bit:      8  Back pressure                      */
44     uint32_t TSTART:1;         /*!< bit:      9  Start Transmission                 */
45     uint32_t THALT:1;          /*!< bit:     10  Transmit Halt                      */
46     uint32_t TXPF:1;           /*!< bit:     11  Transmit Pause Frame               */
47     uint32_t TXZQPF:1;         /*!< bit:     12  Transmit Zero Quantum Pause Frame  */
48     uint32_t :2;               /*!< bit: 13..14  Reserved                           */
49     uint32_t SRTSM:1;          /*!< bit:     15  Store Receive Time Stamp to Memory */
50     uint32_t ENPBPR:1;         /*!< bit:     16  Enable PFC Priority-based Pause Reception */
51     uint32_t TXPBPF:1;         /*!< bit:     17  Transmit PFC Priority-based Pause Frame */
52     uint32_t FNP:1;            /*!< bit:     18  Flush Next Packet                  */
53     uint32_t LPI:1;            /*!< bit:     19  Low Power Idle Enable              */
54     uint32_t :12;              /*!< bit: 20..31  Reserved                           */
55   } bit;                       /*!< Structure used for bit  access                  */
56   uint32_t reg;                /*!< Type      used for register access              */
57 } GMAC_NCR_Type;
58 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
59 
60 /* -------- GMAC_NCFGR : (GMAC Offset: 0x04) (R/W 32) Network Configuration Register -------- */
61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
62 typedef union {
63   struct {
64     uint32_t SPD:1;            /*!< bit:      0  Speed                              */
65     uint32_t FD:1;             /*!< bit:      1  Full Duplex                        */
66     uint32_t DNVLAN:1;         /*!< bit:      2  Discard Non-VLAN FRAMES            */
67     uint32_t JFRAME:1;         /*!< bit:      3  Jumbo Frame Size                   */
68     uint32_t CAF:1;            /*!< bit:      4  Copy All Frames                    */
69     uint32_t NBC:1;            /*!< bit:      5  No Broadcast                       */
70     uint32_t MTIHEN:1;         /*!< bit:      6  Multicast Hash Enable              */
71     uint32_t UNIHEN:1;         /*!< bit:      7  Unicast Hash Enable                */
72     uint32_t MAXFS:1;          /*!< bit:      8  1536 Maximum Frame Size            */
73     uint32_t :3;               /*!< bit:  9..11  Reserved                           */
74     uint32_t RTY:1;            /*!< bit:     12  Retry Test                         */
75     uint32_t PEN:1;            /*!< bit:     13  Pause Enable                       */
76     uint32_t RXBUFO:2;         /*!< bit: 14..15  Receive Buffer Offset              */
77     uint32_t LFERD:1;          /*!< bit:     16  Length Field Error Frame Discard   */
78     uint32_t RFCS:1;           /*!< bit:     17  Remove FCS                         */
79     uint32_t CLK:3;            /*!< bit: 18..20  MDC CLock Division                 */
80     uint32_t DBW:2;            /*!< bit: 21..22  Data Bus Width                     */
81     uint32_t DCPF:1;           /*!< bit:     23  Disable Copy of Pause Frames       */
82     uint32_t RXCOEN:1;         /*!< bit:     24  Receive Checksum Offload Enable    */
83     uint32_t EFRHD:1;          /*!< bit:     25  Enable Frames Received in Half Duplex */
84     uint32_t IRXFCS:1;         /*!< bit:     26  Ignore RX FCS                      */
85     uint32_t :1;               /*!< bit:     27  Reserved                           */
86     uint32_t IPGSEN:1;         /*!< bit:     28  IP Stretch Enable                  */
87     uint32_t RXBP:1;           /*!< bit:     29  Receive Bad Preamble               */
88     uint32_t IRXER:1;          /*!< bit:     30  Ignore IPG GRXER                   */
89     uint32_t :1;               /*!< bit:     31  Reserved                           */
90   } bit;                       /*!< Structure used for bit  access                  */
91   uint32_t reg;                /*!< Type      used for register access              */
92 } GMAC_NCFGR_Type;
93 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
94 /* -------- GMAC_NSR : (GMAC Offset: 0x08) ( R/ 32) Network Status Register -------- */
95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
96 typedef union {
97   struct {
98     uint32_t :1;               /*!< bit:      0  Reserved                           */
99     uint32_t MDIO:1;           /*!< bit:      1  MDIO Input Status                  */
100     uint32_t IDLE:1;           /*!< bit:      2  PHY Management Logic Idle          */
101     uint32_t :29;              /*!< bit:  3..31  Reserved                           */
102   } bit;                       /*!< Structure used for bit  access                  */
103   uint32_t reg;                /*!< Type      used for register access              */
104 } GMAC_NSR_Type;
105 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
106 
107 /* -------- GMAC_UR : (GMAC Offset: 0x0C) (R/W 32) User Register -------- */
108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
109 typedef union {
110   struct {
111     uint32_t MII:1;            /*!< bit:      0  MII Mode                           */
112     uint32_t :31;              /*!< bit:  1..31  Reserved                           */
113   } bit;                       /*!< Structure used for bit  access                  */
114   uint32_t reg;                /*!< Type      used for register access              */
115 } GMAC_UR_Type;
116 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
117 
118 /* -------- GMAC_DCFGR : (GMAC Offset: 0x10) (R/W 32) DMA Configuration Register -------- */
119 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
120 typedef union {
121   struct {
122     uint32_t FBLDO:5;          /*!< bit:  0.. 4  Fixed Burst Length for DMA Data Operations: */
123     uint32_t :1;               /*!< bit:      5  Reserved                           */
124     uint32_t ESMA:1;           /*!< bit:      6  Endian Swap Mode Enable for Management Descriptor Accesses */
125     uint32_t ESPA:1;           /*!< bit:      7  Endian Swap Mode Enable for Packet Data Accesses */
126     uint32_t RXBMS:2;          /*!< bit:  8.. 9  Receiver Packet Buffer Memory Size Select */
127     uint32_t TXPBMS:1;         /*!< bit:     10  Transmitter Packet Buffer Memory Size Select */
128     uint32_t TXCOEN:1;         /*!< bit:     11  Transmitter Checksum Generation Offload Enable */
129     uint32_t :4;               /*!< bit: 12..15  Reserved                           */
130     uint32_t DRBS:8;           /*!< bit: 16..23  DMA Receive Buffer Size            */
131     uint32_t DDRP:1;           /*!< bit:     24  DMA Discard Receive Packets        */
132     uint32_t :7;               /*!< bit: 25..31  Reserved                           */
133   } bit;                       /*!< Structure used for bit  access                  */
134   uint32_t reg;                /*!< Type      used for register access              */
135 } GMAC_DCFGR_Type;
136 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
137 
138 /* -------- GMAC_TSR : (GMAC Offset: 0x14) (R/W 32) Transmit Status Register -------- */
139 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
140 typedef union {
141   struct {
142     uint32_t UBR:1;            /*!< bit:      0  Used Bit Read                      */
143     uint32_t COL:1;            /*!< bit:      1  Collision Occurred                 */
144     uint32_t RLE:1;            /*!< bit:      2  Retry Limit Exceeded               */
145     uint32_t TXGO:1;           /*!< bit:      3  Transmit Go                        */
146     uint32_t TFC:1;            /*!< bit:      4  Transmit Frame Corruption Due to AHB Error */
147     uint32_t TXCOMP:1;         /*!< bit:      5  Transmit Complete                  */
148     uint32_t UND:1;            /*!< bit:      6  Transmit Underrun                  */
149     uint32_t :1;               /*!< bit:      7  Reserved                           */
150     uint32_t HRESP:1;          /*!< bit:      8  HRESP Not OK                       */
151     uint32_t :23;              /*!< bit:  9..31  Reserved                           */
152   } bit;                       /*!< Structure used for bit  access                  */
153   uint32_t reg;                /*!< Type      used for register access              */
154 } GMAC_TSR_Type;
155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
156 
157 /* -------- GMAC_RBQB : (GMAC Offset: 0x18) (R/W 32) Receive Buffer Queue Base Address -------- */
158 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
159 typedef union {
160   struct {
161     uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
162     uint32_t ADDR:30;          /*!< bit:  2..31  Receive Buffer Queue Base Address  */
163   } bit;                       /*!< Structure used for bit  access                  */
164   uint32_t reg;                /*!< Type      used for register access              */
165 } GMAC_RBQB_Type;
166 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
167 
168 /* -------- GMAC_TBQB : (GMAC Offset: 0x1C) (R/W 32) Transmit Buffer Queue Base Address -------- */
169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
170 typedef union {
171   struct {
172     uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
173     uint32_t ADDR:30;          /*!< bit:  2..31  Transmit Buffer Queue Base Address */
174   } bit;                       /*!< Structure used for bit  access                  */
175   uint32_t reg;                /*!< Type      used for register access              */
176 } GMAC_TBQB_Type;
177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
178 
179 /* -------- GMAC_RSR : (GMAC Offset: 0x20) (R/W 32) Receive Status Register -------- */
180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
181 typedef union {
182   struct {
183     uint32_t BNA:1;            /*!< bit:      0  Buffer Not Available               */
184     uint32_t REC:1;            /*!< bit:      1  Frame Received                     */
185     uint32_t RXOVR:1;          /*!< bit:      2  Receive Overrun                    */
186     uint32_t HNO:1;            /*!< bit:      3  HRESP Not OK                       */
187     uint32_t :28;              /*!< bit:  4..31  Reserved                           */
188   } bit;                       /*!< Structure used for bit  access                  */
189   uint32_t reg;                /*!< Type      used for register access              */
190 } GMAC_RSR_Type;
191 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
192 
193 /* -------- GMAC_ISR : (GMAC Offset: 0x24) (R/W 32) Interrupt Status Register -------- */
194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
195 typedef union {
196   struct {
197     uint32_t MFS:1;            /*!< bit:      0  Management Frame Sent              */
198     uint32_t RCOMP:1;          /*!< bit:      1  Receive Complete                   */
199     uint32_t RXUBR:1;          /*!< bit:      2  RX Used Bit Read                   */
200     uint32_t TXUBR:1;          /*!< bit:      3  TX Used Bit Read                   */
201     uint32_t TUR:1;            /*!< bit:      4  Transmit Underrun                  */
202     uint32_t RLEX:1;           /*!< bit:      5  Retry Limit Exceeded               */
203     uint32_t TFC:1;            /*!< bit:      6  Transmit Frame Corruption Due to AHB Error */
204     uint32_t TCOMP:1;          /*!< bit:      7  Transmit Complete                  */
205     uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
206     uint32_t ROVR:1;           /*!< bit:     10  Receive Overrun                    */
207     uint32_t HRESP:1;          /*!< bit:     11  HRESP Not OK                       */
208     uint32_t PFNZ:1;           /*!< bit:     12  Pause Frame with Non-zero Pause Quantum Received */
209     uint32_t PTZ:1;            /*!< bit:     13  Pause Time Zero                    */
210     uint32_t PFTR:1;           /*!< bit:     14  Pause Frame Transmitted            */
211     uint32_t :3;               /*!< bit: 15..17  Reserved                           */
212     uint32_t DRQFR:1;          /*!< bit:     18  PTP Delay Request Frame Received   */
213     uint32_t SFR:1;            /*!< bit:     19  PTP Sync Frame Received            */
214     uint32_t DRQFT:1;          /*!< bit:     20  PTP Delay Request Frame Transmitted */
215     uint32_t SFT:1;            /*!< bit:     21  PTP Sync Frame Transmitted         */
216     uint32_t PDRQFR:1;         /*!< bit:     22  PDelay Request Frame Received      */
217     uint32_t PDRSFR:1;         /*!< bit:     23  PDelay Response Frame Received     */
218     uint32_t PDRQFT:1;         /*!< bit:     24  PDelay Request Frame Transmitted   */
219     uint32_t PDRSFT:1;         /*!< bit:     25  PDelay Response Frame Transmitted  */
220     uint32_t SRI:1;            /*!< bit:     26  TSU Seconds Register Increment     */
221     uint32_t :1;               /*!< bit:     27  Reserved                           */
222     uint32_t WOL:1;            /*!< bit:     28  Wake On LAN                        */
223     uint32_t TSUCMP:1;         /*!< bit:     29  Tsu timer comparison               */
224     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
225   } bit;                       /*!< Structure used for bit  access                  */
226   uint32_t reg;                /*!< Type      used for register access              */
227 } GMAC_ISR_Type;
228 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
229 /* -------- GMAC_IER : (GMAC Offset: 0x28) ( /W 32) Interrupt Enable Register -------- */
230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
231 typedef union {
232   struct {
233     uint32_t MFS:1;            /*!< bit:      0  Management Frame Sent              */
234     uint32_t RCOMP:1;          /*!< bit:      1  Receive Complete                   */
235     uint32_t RXUBR:1;          /*!< bit:      2  RX Used Bit Read                   */
236     uint32_t TXUBR:1;          /*!< bit:      3  TX Used Bit Read                   */
237     uint32_t TUR:1;            /*!< bit:      4  Transmit Underrun                  */
238     uint32_t RLEX:1;           /*!< bit:      5  Retry Limit Exceeded or Late Collision */
239     uint32_t TFC:1;            /*!< bit:      6  Transmit Frame Corruption Due to AHB Error */
240     uint32_t TCOMP:1;          /*!< bit:      7  Transmit Complete                  */
241     uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
242     uint32_t ROVR:1;           /*!< bit:     10  Receive Overrun                    */
243     uint32_t HRESP:1;          /*!< bit:     11  HRESP Not OK                       */
244     uint32_t PFNZ:1;           /*!< bit:     12  Pause Frame with Non-zero Pause Quantum Received */
245     uint32_t PTZ:1;            /*!< bit:     13  Pause Time Zero                    */
246     uint32_t PFTR:1;           /*!< bit:     14  Pause Frame Transmitted            */
247     uint32_t EXINT:1;          /*!< bit:     15  External Interrupt                 */
248     uint32_t :2;               /*!< bit: 16..17  Reserved                           */
249     uint32_t DRQFR:1;          /*!< bit:     18  PTP Delay Request Frame Received   */
250     uint32_t SFR:1;            /*!< bit:     19  PTP Sync Frame Received            */
251     uint32_t DRQFT:1;          /*!< bit:     20  PTP Delay Request Frame Transmitted */
252     uint32_t SFT:1;            /*!< bit:     21  PTP Sync Frame Transmitted         */
253     uint32_t PDRQFR:1;         /*!< bit:     22  PDelay Request Frame Received      */
254     uint32_t PDRSFR:1;         /*!< bit:     23  PDelay Response Frame Received     */
255     uint32_t PDRQFT:1;         /*!< bit:     24  PDelay Request Frame Transmitted   */
256     uint32_t PDRSFT:1;         /*!< bit:     25  PDelay Response Frame Transmitted  */
257     uint32_t SRI:1;            /*!< bit:     26  TSU Seconds Register Increment     */
258     uint32_t :1;               /*!< bit:     27  Reserved                           */
259     uint32_t WOL:1;            /*!< bit:     28  Wake On LAN                        */
260     uint32_t TSUCMP:1;         /*!< bit:     29  Tsu timer comparison               */
261     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
262   } bit;                       /*!< Structure used for bit  access                  */
263   uint32_t reg;                /*!< Type      used for register access              */
264 } GMAC_IER_Type;
265 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
266 /* -------- GMAC_IDR : (GMAC Offset: 0x2C) ( /W 32) Interrupt Disable Register -------- */
267 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
268 typedef union {
269   struct {
270     uint32_t MFS:1;            /*!< bit:      0  Management Frame Sent              */
271     uint32_t RCOMP:1;          /*!< bit:      1  Receive Complete                   */
272     uint32_t RXUBR:1;          /*!< bit:      2  RX Used Bit Read                   */
273     uint32_t TXUBR:1;          /*!< bit:      3  TX Used Bit Read                   */
274     uint32_t TUR:1;            /*!< bit:      4  Transmit Underrun                  */
275     uint32_t RLEX:1;           /*!< bit:      5  Retry Limit Exceeded or Late Collision */
276     uint32_t TFC:1;            /*!< bit:      6  Transmit Frame Corruption Due to AHB Error */
277     uint32_t TCOMP:1;          /*!< bit:      7  Transmit Complete                  */
278     uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
279     uint32_t ROVR:1;           /*!< bit:     10  Receive Overrun                    */
280     uint32_t HRESP:1;          /*!< bit:     11  HRESP Not OK                       */
281     uint32_t PFNZ:1;           /*!< bit:     12  Pause Frame with Non-zero Pause Quantum Received */
282     uint32_t PTZ:1;            /*!< bit:     13  Pause Time Zero                    */
283     uint32_t PFTR:1;           /*!< bit:     14  Pause Frame Transmitted            */
284     uint32_t EXINT:1;          /*!< bit:     15  External Interrupt                 */
285     uint32_t :2;               /*!< bit: 16..17  Reserved                           */
286     uint32_t DRQFR:1;          /*!< bit:     18  PTP Delay Request Frame Received   */
287     uint32_t SFR:1;            /*!< bit:     19  PTP Sync Frame Received            */
288     uint32_t DRQFT:1;          /*!< bit:     20  PTP Delay Request Frame Transmitted */
289     uint32_t SFT:1;            /*!< bit:     21  PTP Sync Frame Transmitted         */
290     uint32_t PDRQFR:1;         /*!< bit:     22  PDelay Request Frame Received      */
291     uint32_t PDRSFR:1;         /*!< bit:     23  PDelay Response Frame Received     */
292     uint32_t PDRQFT:1;         /*!< bit:     24  PDelay Request Frame Transmitted   */
293     uint32_t PDRSFT:1;         /*!< bit:     25  PDelay Response Frame Transmitted  */
294     uint32_t SRI:1;            /*!< bit:     26  TSU Seconds Register Increment     */
295     uint32_t :1;               /*!< bit:     27  Reserved                           */
296     uint32_t WOL:1;            /*!< bit:     28  Wake On LAN                        */
297     uint32_t TSUCMP:1;         /*!< bit:     29  Tsu timer comparison               */
298     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
299   } bit;                       /*!< Structure used for bit  access                  */
300   uint32_t reg;                /*!< Type      used for register access              */
301 } GMAC_IDR_Type;
302 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
303 
304 /* -------- GMAC_IMR : (GMAC Offset: 0x30) ( R/ 32) Interrupt Mask Register -------- */
305 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
306 typedef union {
307   struct {
308     uint32_t MFS:1;            /*!< bit:      0  Management Frame Sent              */
309     uint32_t RCOMP:1;          /*!< bit:      1  Receive Complete                   */
310     uint32_t RXUBR:1;          /*!< bit:      2  RX Used Bit Read                   */
311     uint32_t TXUBR:1;          /*!< bit:      3  TX Used Bit Read                   */
312     uint32_t TUR:1;            /*!< bit:      4  Transmit Underrun                  */
313     uint32_t RLEX:1;           /*!< bit:      5  Retry Limit Exceeded               */
314     uint32_t TFC:1;            /*!< bit:      6  Transmit Frame Corruption Due to AHB Error */
315     uint32_t TCOMP:1;          /*!< bit:      7  Transmit Complete                  */
316     uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
317     uint32_t ROVR:1;           /*!< bit:     10  Receive Overrun                    */
318     uint32_t HRESP:1;          /*!< bit:     11  HRESP Not OK                       */
319     uint32_t PFNZ:1;           /*!< bit:     12  Pause Frame with Non-zero Pause Quantum Received */
320     uint32_t PTZ:1;            /*!< bit:     13  Pause Time Zero                    */
321     uint32_t PFTR:1;           /*!< bit:     14  Pause Frame Transmitted            */
322     uint32_t EXINT:1;          /*!< bit:     15  External Interrupt                 */
323     uint32_t :2;               /*!< bit: 16..17  Reserved                           */
324     uint32_t DRQFR:1;          /*!< bit:     18  PTP Delay Request Frame Received   */
325     uint32_t SFR:1;            /*!< bit:     19  PTP Sync Frame Received            */
326     uint32_t DRQFT:1;          /*!< bit:     20  PTP Delay Request Frame Transmitted */
327     uint32_t SFT:1;            /*!< bit:     21  PTP Sync Frame Transmitted         */
328     uint32_t PDRQFR:1;         /*!< bit:     22  PDelay Request Frame Received      */
329     uint32_t PDRSFR:1;         /*!< bit:     23  PDelay Response Frame Received     */
330     uint32_t PDRQFT:1;         /*!< bit:     24  PDelay Request Frame Transmitted   */
331     uint32_t PDRSFT:1;         /*!< bit:     25  PDelay Response Frame Transmitted  */
332     uint32_t SRI:1;            /*!< bit:     26  TSU Seconds Register Increment     */
333     uint32_t :1;               /*!< bit:     27  Reserved                           */
334     uint32_t WOL:1;            /*!< bit:     28  Wake On Lan                        */
335     uint32_t TSUCMP:1;         /*!< bit:     29  Tsu timer comparison               */
336     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
337   } bit;                       /*!< Structure used for bit  access                  */
338   uint32_t reg;                /*!< Type      used for register access              */
339 } GMAC_IMR_Type;
340 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
341 
342 /* -------- GMAC_MAN : (GMAC Offset: 0x34) (R/W 32) PHY Maintenance Register -------- */
343 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
344 typedef union {
345   struct {
346     uint32_t DATA:16;          /*!< bit:  0..15  PHY Data                           */
347     uint32_t WTN:2;            /*!< bit: 16..17  Write Ten                          */
348     uint32_t REGA:5;           /*!< bit: 18..22  Register Address                   */
349     uint32_t PHYA:5;           /*!< bit: 23..27  PHY Address                        */
350     uint32_t OP:2;             /*!< bit: 28..29  Operation                          */
351     uint32_t CLTTO:1;          /*!< bit:     30  Clause 22 Operation                */
352     uint32_t WZO:1;            /*!< bit:     31  Write ZERO                         */
353   } bit;                       /*!< Structure used for bit  access                  */
354   uint32_t reg;                /*!< Type      used for register access              */
355 } GMAC_MAN_Type;
356 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
357 
358 /* -------- GMAC_RPQ : (GMAC Offset: 0x38) ( R/ 32) Received Pause Quantum Register -------- */
359 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
360 typedef union {
361   struct {
362     uint32_t RPQ:16;           /*!< bit:  0..15  Received Pause Quantum             */
363     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
364   } bit;                       /*!< Structure used for bit  access                  */
365   uint32_t reg;                /*!< Type      used for register access              */
366 } GMAC_RPQ_Type;
367 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
368 
369 /* -------- GMAC_TPQ : (GMAC Offset: 0x3C) (R/W 32) Transmit Pause Quantum Register -------- */
370 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
371 typedef union {
372   struct {
373     uint32_t TPQ:16;           /*!< bit:  0..15  Transmit Pause Quantum             */
374     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
375   } bit;                       /*!< Structure used for bit  access                  */
376   uint32_t reg;                /*!< Type      used for register access              */
377 } GMAC_TPQ_Type;
378 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
379 
380 /* -------- GMAC_TPSF : (GMAC Offset: 0x40) (R/W 32) TX partial store and forward Register -------- */
381 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
382 typedef union {
383   struct {
384     uint32_t TPB1ADR:10;       /*!< bit:  0.. 9  TX packet buffer address           */
385     uint32_t :21;              /*!< bit: 10..30  Reserved                           */
386     uint32_t ENTXP:1;          /*!< bit:     31  Enable TX partial store and forward operation */
387   } bit;                       /*!< Structure used for bit  access                  */
388   uint32_t reg;                /*!< Type      used for register access              */
389 } GMAC_TPSF_Type;
390 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
391 
392 /* -------- GMAC_RPSF : (GMAC Offset: 0x44) (R/W 32) RX partial store and forward Register -------- */
393 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
394 typedef union {
395   struct {
396     uint32_t RPB1ADR:10;       /*!< bit:  0.. 9  RX packet buffer address           */
397     uint32_t :21;              /*!< bit: 10..30  Reserved                           */
398     uint32_t ENRXP:1;          /*!< bit:     31  Enable RX partial store and forward operation */
399   } bit;                       /*!< Structure used for bit  access                  */
400   uint32_t reg;                /*!< Type      used for register access              */
401 } GMAC_RPSF_Type;
402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
403 
404 /* -------- GMAC_RJFML : (GMAC Offset: 0x48) (R/W 32) RX Jumbo Frame Max Length Register -------- */
405 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
406 typedef union {
407   struct {
408     uint32_t FML:14;           /*!< bit:  0..13  Frame Max Length                   */
409     uint32_t :18;              /*!< bit: 14..31  Reserved                           */
410   } bit;                       /*!< Structure used for bit  access                  */
411   uint32_t reg;                /*!< Type      used for register access              */
412 } GMAC_RJFML_Type;
413 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
414 
415 /* -------- GMAC_HRB : (GMAC Offset: 0x80) (R/W 32) Hash Register Bottom [31:0] -------- */
416 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
417 typedef union {
418   struct {
419     uint32_t ADDR:32;          /*!< bit:  0..31  Hash Address                       */
420   } bit;                       /*!< Structure used for bit  access                  */
421   uint32_t reg;                /*!< Type      used for register access              */
422 } GMAC_HRB_Type;
423 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
424 
425 /* -------- GMAC_HRT : (GMAC Offset: 0x84) (R/W 32) Hash Register Top [63:32] -------- */
426 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
427 typedef union {
428   struct {
429     uint32_t ADDR:32;          /*!< bit:  0..31  Hash Address                       */
430   } bit;                       /*!< Structure used for bit  access                  */
431   uint32_t reg;                /*!< Type      used for register access              */
432 } GMAC_HRT_Type;
433 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
434 
435 /* -------- GMAC_TIDM : (GMAC Offset: 0xA8) (R/W 32) Type ID Match n Register -------- */
436 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
437 typedef union {
438   struct {
439     uint32_t TID:16;           /*!< bit:  0..15  Type ID Match 1                    */
440     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
441   } bit;                       /*!< Structure used for bit  access                  */
442   uint32_t reg;                /*!< Type      used for register access              */
443 } GMAC_TIDM_Type;
444 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
445 
446 /* -------- GMAC_WOL : (GMAC Offset: 0xB8) (R/W 32) Wake on LAN -------- */
447 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
448 typedef union {
449   struct {
450     uint32_t IP:16;            /*!< bit:  0..15  IP address                         */
451     uint32_t MAG:1;            /*!< bit:     16  Event enable                       */
452     uint32_t ARP:1;            /*!< bit:     17  LAN ARP req                        */
453     uint32_t SA1:1;            /*!< bit:     18  WOL specific address reg 1         */
454     uint32_t MTI:1;            /*!< bit:     19  WOL LAN multicast                  */
455     uint32_t :12;              /*!< bit: 20..31  Reserved                           */
456   } bit;                       /*!< Structure used for bit  access                  */
457   uint32_t reg;                /*!< Type      used for register access              */
458 } GMAC_WOL_Type;
459 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
460 
461 /* -------- GMAC_IPGS : (GMAC Offset: 0xBC) (R/W 32) IPG Stretch Register -------- */
462 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
463 typedef union {
464   struct {
465     uint32_t FL:16;            /*!< bit:  0..15  Frame Length                       */
466     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
467   } bit;                       /*!< Structure used for bit  access                  */
468   uint32_t reg;                /*!< Type      used for register access              */
469 } GMAC_IPGS_Type;
470 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
471 
472 /* -------- GMAC_SVLAN : (GMAC Offset: 0xC0) (R/W 32) Stacked VLAN Register -------- */
473 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
474 typedef union {
475   struct {
476     uint32_t VLAN_TYPE:16;     /*!< bit:  0..15  User Defined VLAN_TYPE Field       */
477     uint32_t :15;              /*!< bit: 16..30  Reserved                           */
478     uint32_t ESVLAN:1;         /*!< bit:     31  Enable Stacked VLAN Processing Mode */
479   } bit;                       /*!< Structure used for bit  access                  */
480   uint32_t reg;                /*!< Type      used for register access              */
481 } GMAC_SVLAN_Type;
482 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
483 
484 /* -------- GMAC_TPFCP : (GMAC Offset: 0xC4) (R/W 32) Transmit PFC Pause Register -------- */
485 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
486 typedef union {
487   struct {
488     uint32_t PEV:8;            /*!< bit:  0.. 7  Priority Enable Vector             */
489     uint32_t PQ:8;             /*!< bit:  8..15  Pause Quantum                      */
490     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
491   } bit;                       /*!< Structure used for bit  access                  */
492   uint32_t reg;                /*!< Type      used for register access              */
493 } GMAC_TPFCP_Type;
494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
495 
496 /* -------- GMAC_SAMB1 : (GMAC Offset: 0xC8) (R/W 32) Specific Address 1 Mask Bottom [31:0] Register -------- */
497 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
498 typedef union {
499   struct {
500     uint32_t ADDR:32;          /*!< bit:  0..31  Specific Address 1 Mask            */
501   } bit;                       /*!< Structure used for bit  access                  */
502   uint32_t reg;                /*!< Type      used for register access              */
503 } GMAC_SAMB1_Type;
504 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
505 
506 /* -------- GMAC_SAMT1 : (GMAC Offset: 0xCC) (R/W 32) Specific Address 1 Mask Top [47:32] Register -------- */
507 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
508 typedef union {
509   struct {
510     uint32_t ADDR:16;          /*!< bit:  0..15  Specific Address 1 Mask            */
511     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
512   } bit;                       /*!< Structure used for bit  access                  */
513   uint32_t reg;                /*!< Type      used for register access              */
514 } GMAC_SAMT1_Type;
515 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
516 
517 /* -------- GMAC_NSC : (GMAC Offset: 0xDC) (R/W 32) Tsu timer comparison nanoseconds Register -------- */
518 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
519 typedef union {
520   struct {
521     uint32_t NANOSEC:21;       /*!< bit:  0..20  1588 Timer Nanosecond comparison value */
522     uint32_t :11;              /*!< bit: 21..31  Reserved                           */
523   } bit;                       /*!< Structure used for bit  access                  */
524   uint32_t reg;                /*!< Type      used for register access              */
525 } GMAC_NSC_Type;
526 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
527 
528 /* -------- GMAC_SCL : (GMAC Offset: 0xE0) (R/W 32) Tsu timer second comparison Register -------- */
529 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
530 typedef union {
531   struct {
532     uint32_t SEC:32;           /*!< bit:  0..31  1588 Timer Second comparison value */
533   } bit;                       /*!< Structure used for bit  access                  */
534   uint32_t reg;                /*!< Type      used for register access              */
535 } GMAC_SCL_Type;
536 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
537 
538 /* -------- GMAC_SCH : (GMAC Offset: 0xE4) (R/W 32) Tsu timer second comparison Register -------- */
539 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
540 typedef union {
541   struct {
542     uint32_t SEC:16;           /*!< bit:  0..15  1588 Timer Second comparison value */
543     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
544   } bit;                       /*!< Structure used for bit  access                  */
545   uint32_t reg;                /*!< Type      used for register access              */
546 } GMAC_SCH_Type;
547 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
548 
549 /* -------- GMAC_EFTSH : (GMAC Offset: 0xE8) ( R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */
550 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
551 typedef union {
552   struct {
553     uint32_t RUD:16;           /*!< bit:  0..15  Register Update                    */
554     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
555   } bit;                       /*!< Structure used for bit  access                  */
556   uint32_t reg;                /*!< Type      used for register access              */
557 } GMAC_EFTSH_Type;
558 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
559 
560 /* -------- GMAC_EFRSH : (GMAC Offset: 0xEC) ( R/ 32) PTP Event Frame Received Seconds High Register -------- */
561 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
562 typedef union {
563   struct {
564     uint32_t RUD:16;           /*!< bit:  0..15  Register Update                    */
565     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
566   } bit;                       /*!< Structure used for bit  access                  */
567   uint32_t reg;                /*!< Type      used for register access              */
568 } GMAC_EFRSH_Type;
569 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
570 
571 /* -------- GMAC_PEFTSH : (GMAC Offset: 0xF0) ( R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */
572 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
573 typedef union {
574   struct {
575     uint32_t RUD:16;           /*!< bit:  0..15  Register Update                    */
576     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
577   } bit;                       /*!< Structure used for bit  access                  */
578   uint32_t reg;                /*!< Type      used for register access              */
579 } GMAC_PEFTSH_Type;
580 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
581 
582 /* -------- GMAC_PEFRSH : (GMAC Offset: 0xF4) ( R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */
583 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
584 typedef union {
585   struct {
586     uint32_t RUD:16;           /*!< bit:  0..15  Register Update                    */
587     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
588   } bit;                       /*!< Structure used for bit  access                  */
589   uint32_t reg;                /*!< Type      used for register access              */
590 } GMAC_PEFRSH_Type;
591 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
592 
593 /* -------- GMAC_OTLO : (GMAC Offset: 0x100) ( R/ 32) Octets Transmitted [31:0] Register -------- */
594 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
595 typedef union {
596   struct {
597     uint32_t TXO:32;           /*!< bit:  0..31  Transmitted Octets                 */
598   } bit;                       /*!< Structure used for bit  access                  */
599   uint32_t reg;                /*!< Type      used for register access              */
600 } GMAC_OTLO_Type;
601 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
602 
603 /* -------- GMAC_OTHI : (GMAC Offset: 0x104) ( R/ 32) Octets Transmitted [47:32] Register -------- */
604 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
605 typedef union {
606   struct {
607     uint32_t TXO:16;           /*!< bit:  0..15  Transmitted Octets                 */
608     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
609   } bit;                       /*!< Structure used for bit  access                  */
610   uint32_t reg;                /*!< Type      used for register access              */
611 } GMAC_OTHI_Type;
612 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
613 
614 /* -------- GMAC_FT : (GMAC Offset: 0x108) ( R/ 32) Frames Transmitted Register -------- */
615 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
616 typedef union {
617   struct {
618     uint32_t FTX:32;           /*!< bit:  0..31  Frames Transmitted without Error   */
619   } bit;                       /*!< Structure used for bit  access                  */
620   uint32_t reg;                /*!< Type      used for register access              */
621 } GMAC_FT_Type;
622 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
623 
624 /* -------- GMAC_BCFT : (GMAC Offset: 0x10C) ( R/ 32) Broadcast Frames Transmitted Register -------- */
625 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
626 typedef union {
627   struct {
628     uint32_t BFTX:32;          /*!< bit:  0..31  Broadcast Frames Transmitted without Error */
629   } bit;                       /*!< Structure used for bit  access                  */
630   uint32_t reg;                /*!< Type      used for register access              */
631 } GMAC_BCFT_Type;
632 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
633 
634 /* -------- GMAC_MFT : (GMAC Offset: 0x110) ( R/ 32) Multicast Frames Transmitted Register -------- */
635 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
636 typedef union {
637   struct {
638     uint32_t MFTX:32;          /*!< bit:  0..31  Multicast Frames Transmitted without Error */
639   } bit;                       /*!< Structure used for bit  access                  */
640   uint32_t reg;                /*!< Type      used for register access              */
641 } GMAC_MFT_Type;
642 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
643 
644 /* -------- GMAC_PFT : (GMAC Offset: 0x114) ( R/ 32) Pause Frames Transmitted Register -------- */
645 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
646 typedef union {
647   struct {
648     uint32_t PFTX:16;          /*!< bit:  0..15  Pause Frames Transmitted Register  */
649     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
650   } bit;                       /*!< Structure used for bit  access                  */
651   uint32_t reg;                /*!< Type      used for register access              */
652 } GMAC_PFT_Type;
653 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
654 
655 /* -------- GMAC_BFT64 : (GMAC Offset: 0x118) ( R/ 32) 64 Byte Frames Transmitted Register -------- */
656 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
657 typedef union {
658   struct {
659     uint32_t NFTX:32;          /*!< bit:  0..31  64 Byte Frames Transmitted without Error */
660   } bit;                       /*!< Structure used for bit  access                  */
661   uint32_t reg;                /*!< Type      used for register access              */
662 } GMAC_BFT64_Type;
663 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
664 
665 /* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) ( R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */
666 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
667 typedef union {
668   struct {
669     uint32_t NFTX:32;          /*!< bit:  0..31  65 to 127 Byte Frames Transmitted without Error */
670   } bit;                       /*!< Structure used for bit  access                  */
671   uint32_t reg;                /*!< Type      used for register access              */
672 } GMAC_TBFT127_Type;
673 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
674 
675 /* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) ( R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */
676 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
677 typedef union {
678   struct {
679     uint32_t NFTX:32;          /*!< bit:  0..31  128 to 255 Byte Frames Transmitted without Error */
680   } bit;                       /*!< Structure used for bit  access                  */
681   uint32_t reg;                /*!< Type      used for register access              */
682 } GMAC_TBFT255_Type;
683 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
684 
685 /* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) ( R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */
686 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
687 typedef union {
688   struct {
689     uint32_t NFTX:32;          /*!< bit:  0..31  256 to 511 Byte Frames Transmitted without Error */
690   } bit;                       /*!< Structure used for bit  access                  */
691   uint32_t reg;                /*!< Type      used for register access              */
692 } GMAC_TBFT511_Type;
693 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
694 
695 /* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) ( R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */
696 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
697 typedef union {
698   struct {
699     uint32_t NFTX:32;          /*!< bit:  0..31  512 to 1023 Byte Frames Transmitted without Error */
700   } bit;                       /*!< Structure used for bit  access                  */
701   uint32_t reg;                /*!< Type      used for register access              */
702 } GMAC_TBFT1023_Type;
703 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
704 
705 /* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) ( R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */
706 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
707 typedef union {
708   struct {
709     uint32_t NFTX:32;          /*!< bit:  0..31  1024 to 1518 Byte Frames Transmitted without Error */
710   } bit;                       /*!< Structure used for bit  access                  */
711   uint32_t reg;                /*!< Type      used for register access              */
712 } GMAC_TBFT1518_Type;
713 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
714 
715 /* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) ( R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */
716 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
717 typedef union {
718   struct {
719     uint32_t NFTX:32;          /*!< bit:  0..31  Greater than 1518 Byte Frames Transmitted without Error */
720   } bit;                       /*!< Structure used for bit  access                  */
721   uint32_t reg;                /*!< Type      used for register access              */
722 } GMAC_GTBFT1518_Type;
723 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
724 
725 /* -------- GMAC_TUR : (GMAC Offset: 0x134) ( R/ 32) Transmit Underruns Register -------- */
726 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
727 typedef union {
728   struct {
729     uint32_t TXUNR:10;         /*!< bit:  0.. 9  Transmit Underruns                 */
730     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
731   } bit;                       /*!< Structure used for bit  access                  */
732   uint32_t reg;                /*!< Type      used for register access              */
733 } GMAC_TUR_Type;
734 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
735 
736 /* -------- GMAC_SCF : (GMAC Offset: 0x138) ( R/ 32) Single Collision Frames Register -------- */
737 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
738 typedef union {
739   struct {
740     uint32_t SCOL:18;          /*!< bit:  0..17  Single Collision                   */
741     uint32_t :14;              /*!< bit: 18..31  Reserved                           */
742   } bit;                       /*!< Structure used for bit  access                  */
743   uint32_t reg;                /*!< Type      used for register access              */
744 } GMAC_SCF_Type;
745 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
746 
747 /* -------- GMAC_MCF : (GMAC Offset: 0x13C) ( R/ 32) Multiple Collision Frames Register -------- */
748 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
749 typedef union {
750   struct {
751     uint32_t MCOL:18;          /*!< bit:  0..17  Multiple Collision                 */
752     uint32_t :14;              /*!< bit: 18..31  Reserved                           */
753   } bit;                       /*!< Structure used for bit  access                  */
754   uint32_t reg;                /*!< Type      used for register access              */
755 } GMAC_MCF_Type;
756 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
757 
758 /* -------- GMAC_EC : (GMAC Offset: 0x140) ( R/ 32) Excessive Collisions Register -------- */
759 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
760 typedef union {
761   struct {
762     uint32_t XCOL:10;          /*!< bit:  0.. 9  Excessive Collisions               */
763     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
764   } bit;                       /*!< Structure used for bit  access                  */
765   uint32_t reg;                /*!< Type      used for register access              */
766 } GMAC_EC_Type;
767 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
768 
769 /* -------- GMAC_LC : (GMAC Offset: 0x144) ( R/ 32) Late Collisions Register -------- */
770 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
771 typedef union {
772   struct {
773     uint32_t LCOL:10;          /*!< bit:  0.. 9  Late Collisions                    */
774     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
775   } bit;                       /*!< Structure used for bit  access                  */
776   uint32_t reg;                /*!< Type      used for register access              */
777 } GMAC_LC_Type;
778 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
779 
780 /* -------- GMAC_DTF : (GMAC Offset: 0x148) ( R/ 32) Deferred Transmission Frames Register -------- */
781 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
782 typedef union {
783   struct {
784     uint32_t DEFT:18;          /*!< bit:  0..17  Deferred Transmission              */
785     uint32_t :14;              /*!< bit: 18..31  Reserved                           */
786   } bit;                       /*!< Structure used for bit  access                  */
787   uint32_t reg;                /*!< Type      used for register access              */
788 } GMAC_DTF_Type;
789 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
790 
791 /* -------- GMAC_CSE : (GMAC Offset: 0x14C) ( R/ 32) Carrier Sense Errors Register -------- */
792 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
793 typedef union {
794   struct {
795     uint32_t CSR:10;           /*!< bit:  0.. 9  Carrier Sense Error                */
796     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
797   } bit;                       /*!< Structure used for bit  access                  */
798   uint32_t reg;                /*!< Type      used for register access              */
799 } GMAC_CSE_Type;
800 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
801 
802 /* -------- GMAC_ORLO : (GMAC Offset: 0x150) ( R/ 32) Octets Received [31:0] Received -------- */
803 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
804 typedef union {
805   struct {
806     uint32_t RXO:32;           /*!< bit:  0..31  Received Octets                    */
807   } bit;                       /*!< Structure used for bit  access                  */
808   uint32_t reg;                /*!< Type      used for register access              */
809 } GMAC_ORLO_Type;
810 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
811 
812 /* -------- GMAC_ORHI : (GMAC Offset: 0x154) ( R/ 32) Octets Received [47:32] Received -------- */
813 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
814 typedef union {
815   struct {
816     uint32_t RXO:16;           /*!< bit:  0..15  Received Octets                    */
817     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
818   } bit;                       /*!< Structure used for bit  access                  */
819   uint32_t reg;                /*!< Type      used for register access              */
820 } GMAC_ORHI_Type;
821 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
822 
823 /* -------- GMAC_FR : (GMAC Offset: 0x158) ( R/ 32) Frames Received Register -------- */
824 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
825 typedef union {
826   struct {
827     uint32_t FRX:32;           /*!< bit:  0..31  Frames Received without Error      */
828   } bit;                       /*!< Structure used for bit  access                  */
829   uint32_t reg;                /*!< Type      used for register access              */
830 } GMAC_FR_Type;
831 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
832 
833 /* -------- GMAC_BCFR : (GMAC Offset: 0x15C) ( R/ 32) Broadcast Frames Received Register -------- */
834 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
835 typedef union {
836   struct {
837     uint32_t BFRX:32;          /*!< bit:  0..31  Broadcast Frames Received without Error */
838   } bit;                       /*!< Structure used for bit  access                  */
839   uint32_t reg;                /*!< Type      used for register access              */
840 } GMAC_BCFR_Type;
841 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
842 
843 /* -------- GMAC_MFR : (GMAC Offset: 0x160) ( R/ 32) Multicast Frames Received Register -------- */
844 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
845 typedef union {
846   struct {
847     uint32_t MFRX:32;          /*!< bit:  0..31  Multicast Frames Received without Error */
848   } bit;                       /*!< Structure used for bit  access                  */
849   uint32_t reg;                /*!< Type      used for register access              */
850 } GMAC_MFR_Type;
851 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
852 
853 /* -------- GMAC_PFR : (GMAC Offset: 0x164) ( R/ 32) Pause Frames Received Register -------- */
854 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
855 typedef union {
856   struct {
857     uint32_t PFRX:16;          /*!< bit:  0..15  Pause Frames Received Register     */
858     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
859   } bit;                       /*!< Structure used for bit  access                  */
860   uint32_t reg;                /*!< Type      used for register access              */
861 } GMAC_PFR_Type;
862 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
863 
864 /* -------- GMAC_BFR64 : (GMAC Offset: 0x168) ( R/ 32) 64 Byte Frames Received Register -------- */
865 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
866 typedef union {
867   struct {
868     uint32_t NFRX:32;          /*!< bit:  0..31  64 Byte Frames Received without Error */
869   } bit;                       /*!< Structure used for bit  access                  */
870   uint32_t reg;                /*!< Type      used for register access              */
871 } GMAC_BFR64_Type;
872 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
873 
874 /* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) ( R/ 32) 65 to 127 Byte Frames Received Register -------- */
875 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
876 typedef union {
877   struct {
878     uint32_t NFRX:32;          /*!< bit:  0..31  65 to 127 Byte Frames Received without Error */
879   } bit;                       /*!< Structure used for bit  access                  */
880   uint32_t reg;                /*!< Type      used for register access              */
881 } GMAC_TBFR127_Type;
882 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
883 
884 /* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) ( R/ 32) 128 to 255 Byte Frames Received Register -------- */
885 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
886 typedef union {
887   struct {
888     uint32_t NFRX:32;          /*!< bit:  0..31  128 to 255 Byte Frames Received without Error */
889   } bit;                       /*!< Structure used for bit  access                  */
890   uint32_t reg;                /*!< Type      used for register access              */
891 } GMAC_TBFR255_Type;
892 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
893 
894 /* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) ( R/ 32) 256 to 511Byte Frames Received Register -------- */
895 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
896 typedef union {
897   struct {
898     uint32_t NFRX:32;          /*!< bit:  0..31  256 to 511 Byte Frames Received without Error */
899   } bit;                       /*!< Structure used for bit  access                  */
900   uint32_t reg;                /*!< Type      used for register access              */
901 } GMAC_TBFR511_Type;
902 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
903 
904 /* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) ( R/ 32) 512 to 1023 Byte Frames Received Register -------- */
905 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
906 typedef union {
907   struct {
908     uint32_t NFRX:32;          /*!< bit:  0..31  512 to 1023 Byte Frames Received without Error */
909   } bit;                       /*!< Structure used for bit  access                  */
910   uint32_t reg;                /*!< Type      used for register access              */
911 } GMAC_TBFR1023_Type;
912 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
913 
914 /* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) ( R/ 32) 1024 to 1518 Byte Frames Received Register -------- */
915 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
916 typedef union {
917   struct {
918     uint32_t NFRX:32;          /*!< bit:  0..31  1024 to 1518 Byte Frames Received without Error */
919   } bit;                       /*!< Structure used for bit  access                  */
920   uint32_t reg;                /*!< Type      used for register access              */
921 } GMAC_TBFR1518_Type;
922 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
923 
924 /* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) ( R/ 32) 1519 to Maximum Byte Frames Received Register -------- */
925 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
926 typedef union {
927   struct {
928     uint32_t NFRX:32;          /*!< bit:  0..31  1519 to Maximum Byte Frames Received without Error */
929   } bit;                       /*!< Structure used for bit  access                  */
930   uint32_t reg;                /*!< Type      used for register access              */
931 } GMAC_TMXBFR_Type;
932 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
933 
934 /* -------- GMAC_UFR : (GMAC Offset: 0x184) ( R/ 32) Undersize Frames Received Register -------- */
935 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
936 typedef union {
937   struct {
938     uint32_t UFRX:10;          /*!< bit:  0.. 9  Undersize Frames Received          */
939     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
940   } bit;                       /*!< Structure used for bit  access                  */
941   uint32_t reg;                /*!< Type      used for register access              */
942 } GMAC_UFR_Type;
943 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
944 
945 /* -------- GMAC_OFR : (GMAC Offset: 0x188) ( R/ 32) Oversize Frames Received Register -------- */
946 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
947 typedef union {
948   struct {
949     uint32_t OFRX:10;          /*!< bit:  0.. 9  Oversized Frames Received          */
950     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
951   } bit;                       /*!< Structure used for bit  access                  */
952   uint32_t reg;                /*!< Type      used for register access              */
953 } GMAC_OFR_Type;
954 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
955 
956 /* -------- GMAC_JR : (GMAC Offset: 0x18C) ( R/ 32) Jabbers Received Register -------- */
957 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
958 typedef union {
959   struct {
960     uint32_t JRX:10;           /*!< bit:  0.. 9  Jabbers Received                   */
961     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
962   } bit;                       /*!< Structure used for bit  access                  */
963   uint32_t reg;                /*!< Type      used for register access              */
964 } GMAC_JR_Type;
965 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
966 
967 /* -------- GMAC_FCSE : (GMAC Offset: 0x190) ( R/ 32) Frame Check Sequence Errors Register -------- */
968 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
969 typedef union {
970   struct {
971     uint32_t FCKR:10;          /*!< bit:  0.. 9  Frame Check Sequence Errors        */
972     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
973   } bit;                       /*!< Structure used for bit  access                  */
974   uint32_t reg;                /*!< Type      used for register access              */
975 } GMAC_FCSE_Type;
976 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
977 
978 /* -------- GMAC_LFFE : (GMAC Offset: 0x194) ( R/ 32) Length Field Frame Errors Register -------- */
979 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
980 typedef union {
981   struct {
982     uint32_t LFER:10;          /*!< bit:  0.. 9  Length Field Frame Errors          */
983     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
984   } bit;                       /*!< Structure used for bit  access                  */
985   uint32_t reg;                /*!< Type      used for register access              */
986 } GMAC_LFFE_Type;
987 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
988 
989 /* -------- GMAC_RSE : (GMAC Offset: 0x198) ( R/ 32) Receive Symbol Errors Register -------- */
990 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
991 typedef union {
992   struct {
993     uint32_t RXSE:10;          /*!< bit:  0.. 9  Receive Symbol Errors              */
994     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
995   } bit;                       /*!< Structure used for bit  access                  */
996   uint32_t reg;                /*!< Type      used for register access              */
997 } GMAC_RSE_Type;
998 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
999 
1000 /* -------- GMAC_AE : (GMAC Offset: 0x19C) ( R/ 32) Alignment Errors Register -------- */
1001 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1002 typedef union {
1003   struct {
1004     uint32_t AER:10;           /*!< bit:  0.. 9  Alignment Errors                   */
1005     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
1006   } bit;                       /*!< Structure used for bit  access                  */
1007   uint32_t reg;                /*!< Type      used for register access              */
1008 } GMAC_AE_Type;
1009 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1010 
1011 /* -------- GMAC_RRE : (GMAC Offset: 0x1A0) ( R/ 32) Receive Resource Errors Register -------- */
1012 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1013 typedef union {
1014   struct {
1015     uint32_t RXRER:18;         /*!< bit:  0..17  Receive Resource Errors            */
1016     uint32_t :14;              /*!< bit: 18..31  Reserved                           */
1017   } bit;                       /*!< Structure used for bit  access                  */
1018   uint32_t reg;                /*!< Type      used for register access              */
1019 } GMAC_RRE_Type;
1020 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1021 
1022 /* -------- GMAC_ROE : (GMAC Offset: 0x1A4) ( R/ 32) Receive Overrun Register -------- */
1023 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1024 typedef union {
1025   struct {
1026     uint32_t RXOVR:10;         /*!< bit:  0.. 9  Receive Overruns                   */
1027     uint32_t :22;              /*!< bit: 10..31  Reserved                           */
1028   } bit;                       /*!< Structure used for bit  access                  */
1029   uint32_t reg;                /*!< Type      used for register access              */
1030 } GMAC_ROE_Type;
1031 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1032 
1033 /* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) ( R/ 32) IP Header Checksum Errors Register -------- */
1034 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1035 typedef union {
1036   struct {
1037     uint32_t HCKER:8;          /*!< bit:  0.. 7  IP Header Checksum Errors          */
1038     uint32_t :24;              /*!< bit:  8..31  Reserved                           */
1039   } bit;                       /*!< Structure used for bit  access                  */
1040   uint32_t reg;                /*!< Type      used for register access              */
1041 } GMAC_IHCE_Type;
1042 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1043 
1044 /* -------- GMAC_TCE : (GMAC Offset: 0x1AC) ( R/ 32) TCP Checksum Errors Register -------- */
1045 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1046 typedef union {
1047   struct {
1048     uint32_t TCKER:8;          /*!< bit:  0.. 7  TCP Checksum Errors                */
1049     uint32_t :24;              /*!< bit:  8..31  Reserved                           */
1050   } bit;                       /*!< Structure used for bit  access                  */
1051   uint32_t reg;                /*!< Type      used for register access              */
1052 } GMAC_TCE_Type;
1053 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1054 
1055 /* -------- GMAC_UCE : (GMAC Offset: 0x1B0) ( R/ 32) UDP Checksum Errors Register -------- */
1056 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1057 typedef union {
1058   struct {
1059     uint32_t UCKER:8;          /*!< bit:  0.. 7  UDP Checksum Errors                */
1060     uint32_t :24;              /*!< bit:  8..31  Reserved                           */
1061   } bit;                       /*!< Structure used for bit  access                  */
1062   uint32_t reg;                /*!< Type      used for register access              */
1063 } GMAC_UCE_Type;
1064 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1065 
1066 /* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register -------- */
1067 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1068 typedef union {
1069   struct {
1070     uint32_t LSBTIR:16;        /*!< bit:  0..15  Lower Significant Bits of Timer Increment */
1071     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
1072   } bit;                       /*!< Structure used for bit  access                  */
1073   uint32_t reg;                /*!< Type      used for register access              */
1074 } GMAC_TISUBN_Type;
1075 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1076 
1077 /* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High [15:0] Register -------- */
1078 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1079 typedef union {
1080   struct {
1081     uint32_t TCS:16;           /*!< bit:  0..15  Timer Count in Seconds             */
1082     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
1083   } bit;                       /*!< Structure used for bit  access                  */
1084   uint32_t reg;                /*!< Type      used for register access              */
1085 } GMAC_TSH_Type;
1086 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1087 
1088 /* -------- GMAC_TSSSL : (GMAC Offset: 0x1C8) (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register -------- */
1089 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1090 typedef union {
1091   struct {
1092     uint32_t VTS:32;           /*!< bit:  0..31  Value of Timer Seconds Register Capture */
1093   } bit;                       /*!< Structure used for bit  access                  */
1094   uint32_t reg;                /*!< Type      used for register access              */
1095 } GMAC_TSSSL_Type;
1096 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1097 
1098 /* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register -------- */
1099 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1100 typedef union {
1101   struct {
1102     uint32_t VTN:30;           /*!< bit:  0..29  Value Timer Nanoseconds Register Capture */
1103     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
1104   } bit;                       /*!< Structure used for bit  access                  */
1105   uint32_t reg;                /*!< Type      used for register access              */
1106 } GMAC_TSSN_Type;
1107 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1108 
1109 /* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds [31:0] Register -------- */
1110 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1111 typedef union {
1112   struct {
1113     uint32_t TCS:32;           /*!< bit:  0..31  Timer Count in Seconds             */
1114   } bit;                       /*!< Structure used for bit  access                  */
1115   uint32_t reg;                /*!< Type      used for register access              */
1116 } GMAC_TSL_Type;
1117 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1118 
1119 /* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */
1120 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1121 typedef union {
1122   struct {
1123     uint32_t TNS:30;           /*!< bit:  0..29  Timer Count in Nanoseconds         */
1124     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
1125   } bit;                       /*!< Structure used for bit  access                  */
1126   uint32_t reg;                /*!< Type      used for register access              */
1127 } GMAC_TN_Type;
1128 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1129 
1130 /* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */
1131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1132 typedef union {
1133   struct {
1134     uint32_t ITDT:30;          /*!< bit:  0..29  Increment/Decrement                */
1135     uint32_t :1;               /*!< bit:     30  Reserved                           */
1136     uint32_t ADJ:1;            /*!< bit:     31  Adjust 1588 Timer                  */
1137   } bit;                       /*!< Structure used for bit  access                  */
1138   uint32_t reg;                /*!< Type      used for register access              */
1139 } GMAC_TA_Type;
1140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1141 
1142 /* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */
1143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1144 typedef union {
1145   struct {
1146     uint32_t CNS:8;            /*!< bit:  0.. 7  Count Nanoseconds                  */
1147     uint32_t ACNS:8;           /*!< bit:  8..15  Alternative Count Nanoseconds      */
1148     uint32_t NIT:8;            /*!< bit: 16..23  Number of Increments               */
1149     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
1150   } bit;                       /*!< Structure used for bit  access                  */
1151   uint32_t reg;                /*!< Type      used for register access              */
1152 } GMAC_TI_Type;
1153 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1154 
1155 /* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) ( R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */
1156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1157 typedef union {
1158   struct {
1159     uint32_t RUD:32;           /*!< bit:  0..31  Register Update                    */
1160   } bit;                       /*!< Structure used for bit  access                  */
1161   uint32_t reg;                /*!< Type      used for register access              */
1162 } GMAC_EFTSL_Type;
1163 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1164 
1165 /* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) ( R/ 32) PTP Event Frame Transmitted Nanoseconds -------- */
1166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1167 typedef union {
1168   struct {
1169     uint32_t RUD:30;           /*!< bit:  0..29  Register Update                    */
1170     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
1171   } bit;                       /*!< Structure used for bit  access                  */
1172   uint32_t reg;                /*!< Type      used for register access              */
1173 } GMAC_EFTN_Type;
1174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1175 
1176 /* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) ( R/ 32) PTP Event Frame Received Seconds Low Register -------- */
1177 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1178 typedef union {
1179   struct {
1180     uint32_t RUD:32;           /*!< bit:  0..31  Register Update                    */
1181   } bit;                       /*!< Structure used for bit  access                  */
1182   uint32_t reg;                /*!< Type      used for register access              */
1183 } GMAC_EFRSL_Type;
1184 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1185 
1186 /* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) ( R/ 32) PTP Event Frame Received Nanoseconds -------- */
1187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1188 typedef union {
1189   struct {
1190     uint32_t RUD:30;           /*!< bit:  0..29  Register Update                    */
1191     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
1192   } bit;                       /*!< Structure used for bit  access                  */
1193   uint32_t reg;                /*!< Type      used for register access              */
1194 } GMAC_EFRN_Type;
1195 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1196 
1197 /* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) ( R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */
1198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1199 typedef union {
1200   struct {
1201     uint32_t RUD:32;           /*!< bit:  0..31  Register Update                    */
1202   } bit;                       /*!< Structure used for bit  access                  */
1203   uint32_t reg;                /*!< Type      used for register access              */
1204 } GMAC_PEFTSL_Type;
1205 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1206 
1207 /* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) ( R/ 32) PTP Peer Event Frame Transmitted Nanoseconds -------- */
1208 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1209 typedef union {
1210   struct {
1211     uint32_t RUD:30;           /*!< bit:  0..29  Register Update                    */
1212     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
1213   } bit;                       /*!< Structure used for bit  access                  */
1214   uint32_t reg;                /*!< Type      used for register access              */
1215 } GMAC_PEFTN_Type;
1216 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1217 
1218 /* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) ( R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */
1219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1220 typedef union {
1221   struct {
1222     uint32_t RUD:32;           /*!< bit:  0..31  Register Update                    */
1223   } bit;                       /*!< Structure used for bit  access                  */
1224   uint32_t reg;                /*!< Type      used for register access              */
1225 } GMAC_PEFRSL_Type;
1226 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1227 
1228 /* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) ( R/ 32) PTP Peer Event Frame Received Nanoseconds -------- */
1229 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1230 typedef union {
1231   struct {
1232     uint32_t RUD:30;           /*!< bit:  0..29  Register Update                    */
1233     uint32_t :2;               /*!< bit: 30..31  Reserved                           */
1234   } bit;                       /*!< Structure used for bit  access                  */
1235   uint32_t reg;                /*!< Type      used for register access              */
1236 } GMAC_PEFRN_Type;
1237 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1238 
1239 /* -------- GMAC_RLPITR : (GMAC Offset: 0x270) ( R/ 32) Receive LPI transition Register -------- */
1240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1241 typedef union {
1242   struct {
1243     uint32_t RLPITR:16;        /*!< bit:  0..15  Count number of times transition from rx normal idle to low power idle */
1244     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
1245   } bit;                       /*!< Structure used for bit  access                  */
1246   uint32_t reg;                /*!< Type      used for register access              */
1247 } GMAC_RLPITR_Type;
1248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1249 
1250 /* -------- GMAC_RLPITI : (GMAC Offset: 0x274) ( R/ 32) Receive LPI Time Register -------- */
1251 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1252 typedef union {
1253   struct {
1254     uint32_t RLPITI:24;        /*!< bit:  0..23  Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode */
1255     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
1256   } bit;                       /*!< Structure used for bit  access                  */
1257   uint32_t reg;                /*!< Type      used for register access              */
1258 } GMAC_RLPITI_Type;
1259 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1260 
1261 /* -------- GMAC_TLPITR : (GMAC Offset: 0x278) ( R/ 32) Receive LPI transition Register -------- */
1262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1263 typedef union {
1264   struct {
1265     uint32_t TLPITR:16;        /*!< bit:  0..15  Count number of times enable LPI tx bit 20 goes from low to high */
1266     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
1267   } bit;                       /*!< Structure used for bit  access                  */
1268   uint32_t reg;                /*!< Type      used for register access              */
1269 } GMAC_TLPITR_Type;
1270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1271 
1272 /* -------- GMAC_TLPITI : (GMAC Offset: 0x27C) ( R/ 32) Receive LPI Time Register -------- */
1273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1274 typedef union {
1275   struct {
1276     uint32_t TLPITI:24;        /*!< bit:  0..23  Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode */
1277     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
1278   } bit;                       /*!< Structure used for bit  access                  */
1279   uint32_t reg;                /*!< Type      used for register access              */
1280 } GMAC_TLPITI_Type;
1281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1282 
1283 /** \brief GmacSa hardware registers */
1284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1285 typedef struct {
1286   __IO GMAC_SAB_Type             SAB;         /**< \brief Offset: 0x000 (R/W 32) Specific Address Bottom [31:0] Register */
1287   __IO GMAC_SAT_Type             SAT;         /**< \brief Offset: 0x004 (R/W 32) Specific Address Top [47:32] Register */
1288 } GmacSa;
1289 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1290 
1291 /** \brief GMAC hardware registers */
1292 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1293 typedef struct {
1294   __IO GMAC_NCR_Type             NCR;         /**< \brief Offset: 0x000 (R/W 32) Network Control Register */
1295   __IO GMAC_NCFGR_Type           NCFGR;       /**< \brief Offset: 0x004 (R/W 32) Network Configuration Register */
1296   __I  GMAC_NSR_Type             NSR;         /**< \brief Offset: 0x008 (R/  32) Network Status Register */
1297   __IO GMAC_UR_Type              UR;          /**< \brief Offset: 0x00C (R/W 32) User Register */
1298   __IO GMAC_DCFGR_Type           DCFGR;       /**< \brief Offset: 0x010 (R/W 32) DMA Configuration Register */
1299   __IO GMAC_TSR_Type             TSR;         /**< \brief Offset: 0x014 (R/W 32) Transmit Status Register */
1300   __IO GMAC_RBQB_Type            RBQB;        /**< \brief Offset: 0x018 (R/W 32) Receive Buffer Queue Base Address */
1301   __IO GMAC_TBQB_Type            TBQB;        /**< \brief Offset: 0x01C (R/W 32) Transmit Buffer Queue Base Address */
1302   __IO GMAC_RSR_Type             RSR;         /**< \brief Offset: 0x020 (R/W 32) Receive Status Register */
1303   __IO GMAC_ISR_Type             ISR;         /**< \brief Offset: 0x024 (R/W 32) Interrupt Status Register */
1304   __O  GMAC_IER_Type             IER;         /**< \brief Offset: 0x028 ( /W 32) Interrupt Enable Register */
1305   __O  GMAC_IDR_Type             IDR;         /**< \brief Offset: 0x02C ( /W 32) Interrupt Disable Register */
1306   __I  GMAC_IMR_Type             IMR;         /**< \brief Offset: 0x030 (R/  32) Interrupt Mask Register */
1307   __IO GMAC_MAN_Type             MAN;         /**< \brief Offset: 0x034 (R/W 32) PHY Maintenance Register */
1308   __I  GMAC_RPQ_Type             RPQ;         /**< \brief Offset: 0x038 (R/  32) Received Pause Quantum Register */
1309   __IO GMAC_TPQ_Type             TPQ;         /**< \brief Offset: 0x03C (R/W 32) Transmit Pause Quantum Register */
1310   __IO GMAC_TPSF_Type            TPSF;        /**< \brief Offset: 0x040 (R/W 32) TX partial store and forward Register */
1311   __IO GMAC_RPSF_Type            RPSF;        /**< \brief Offset: 0x044 (R/W 32) RX partial store and forward Register */
1312   __IO GMAC_RJFML_Type           RJFML;       /**< \brief Offset: 0x048 (R/W 32) RX Jumbo Frame Max Length Register */
1313        RoReg8                    Reserved1[0x34];
1314   __IO GMAC_HRB_Type             HRB;         /**< \brief Offset: 0x080 (R/W 32) Hash Register Bottom [31:0] */
1315   __IO GMAC_HRT_Type             HRT;         /**< \brief Offset: 0x084 (R/W 32) Hash Register Top [63:32] */
1316        GmacSa                    Sa[4];       /**< \brief Offset: 0x088 GmacSa groups */
1317   __IO GMAC_TIDM_Type            TIDM[4];     /**< \brief Offset: 0x0A8 (R/W 32) Type ID Match Register */
1318   __IO GMAC_WOL_Type             WOL;         /**< \brief Offset: 0x0B8 (R/W 32) Wake on LAN */
1319   __IO GMAC_IPGS_Type            IPGS;        /**< \brief Offset: 0x0BC (R/W 32) IPG Stretch Register */
1320   __IO GMAC_SVLAN_Type           SVLAN;       /**< \brief Offset: 0x0C0 (R/W 32) Stacked VLAN Register */
1321   __IO GMAC_TPFCP_Type           TPFCP;       /**< \brief Offset: 0x0C4 (R/W 32) Transmit PFC Pause Register */
1322   __IO GMAC_SAMB1_Type           SAMB1;       /**< \brief Offset: 0x0C8 (R/W 32) Specific Address 1 Mask Bottom [31:0] Register */
1323   __IO GMAC_SAMT1_Type           SAMT1;       /**< \brief Offset: 0x0CC (R/W 32) Specific Address 1 Mask Top [47:32] Register */
1324        RoReg8                    Reserved2[0xC];
1325   __IO GMAC_NSC_Type             NSC;         /**< \brief Offset: 0x0DC (R/W 32) Tsu timer comparison nanoseconds Register */
1326   __IO GMAC_SCL_Type             SCL;         /**< \brief Offset: 0x0E0 (R/W 32) Tsu timer second comparison Register */
1327   __IO GMAC_SCH_Type             SCH;         /**< \brief Offset: 0x0E4 (R/W 32) Tsu timer second comparison Register */
1328   __I  GMAC_EFTSH_Type           EFTSH;       /**< \brief Offset: 0x0E8 (R/  32) PTP Event Frame Transmitted Seconds High Register */
1329   __I  GMAC_EFRSH_Type           EFRSH;       /**< \brief Offset: 0x0EC (R/  32) PTP Event Frame Received Seconds High Register */
1330   __I  GMAC_PEFTSH_Type          PEFTSH;      /**< \brief Offset: 0x0F0 (R/  32) PTP Peer Event Frame Transmitted Seconds High Register */
1331   __I  GMAC_PEFRSH_Type          PEFRSH;      /**< \brief Offset: 0x0F4 (R/  32) PTP Peer Event Frame Received Seconds High Register */
1332        RoReg8                    Reserved3[0x8];
1333   __I  GMAC_OTLO_Type            OTLO;        /**< \brief Offset: 0x100 (R/  32) Octets Transmitted [31:0] Register */
1334   __I  GMAC_OTHI_Type            OTHI;        /**< \brief Offset: 0x104 (R/  32) Octets Transmitted [47:32] Register */
1335   __I  GMAC_FT_Type              FT;          /**< \brief Offset: 0x108 (R/  32) Frames Transmitted Register */
1336   __I  GMAC_BCFT_Type            BCFT;        /**< \brief Offset: 0x10C (R/  32) Broadcast Frames Transmitted Register */
1337   __I  GMAC_MFT_Type             MFT;         /**< \brief Offset: 0x110 (R/  32) Multicast Frames Transmitted Register */
1338   __I  GMAC_PFT_Type             PFT;         /**< \brief Offset: 0x114 (R/  32) Pause Frames Transmitted Register */
1339   __I  GMAC_BFT64_Type           BFT64;       /**< \brief Offset: 0x118 (R/  32) 64 Byte Frames Transmitted Register */
1340   __I  GMAC_TBFT127_Type         TBFT127;     /**< \brief Offset: 0x11C (R/  32) 65 to 127 Byte Frames Transmitted Register */
1341   __I  GMAC_TBFT255_Type         TBFT255;     /**< \brief Offset: 0x120 (R/  32) 128 to 255 Byte Frames Transmitted Register */
1342   __I  GMAC_TBFT511_Type         TBFT511;     /**< \brief Offset: 0x124 (R/  32) 256 to 511 Byte Frames Transmitted Register */
1343   __I  GMAC_TBFT1023_Type        TBFT1023;    /**< \brief Offset: 0x128 (R/  32) 512 to 1023 Byte Frames Transmitted Register */
1344   __I  GMAC_TBFT1518_Type        TBFT1518;    /**< \brief Offset: 0x12C (R/  32) 1024 to 1518 Byte Frames Transmitted Register */
1345   __I  GMAC_GTBFT1518_Type       GTBFT1518;   /**< \brief Offset: 0x130 (R/  32) Greater Than 1518 Byte Frames Transmitted Register */
1346   __I  GMAC_TUR_Type             TUR;         /**< \brief Offset: 0x134 (R/  32) Transmit Underruns Register */
1347   __I  GMAC_SCF_Type             SCF;         /**< \brief Offset: 0x138 (R/  32) Single Collision Frames Register */
1348   __I  GMAC_MCF_Type             MCF;         /**< \brief Offset: 0x13C (R/  32) Multiple Collision Frames Register */
1349   __I  GMAC_EC_Type              EC;          /**< \brief Offset: 0x140 (R/  32) Excessive Collisions Register */
1350   __I  GMAC_LC_Type              LC;          /**< \brief Offset: 0x144 (R/  32) Late Collisions Register */
1351   __I  GMAC_DTF_Type             DTF;         /**< \brief Offset: 0x148 (R/  32) Deferred Transmission Frames Register */
1352   __I  GMAC_CSE_Type             CSE;         /**< \brief Offset: 0x14C (R/  32) Carrier Sense Errors Register */
1353   __I  GMAC_ORLO_Type            ORLO;        /**< \brief Offset: 0x150 (R/  32) Octets Received [31:0] Received */
1354   __I  GMAC_ORHI_Type            ORHI;        /**< \brief Offset: 0x154 (R/  32) Octets Received [47:32] Received */
1355   __I  GMAC_FR_Type              FR;          /**< \brief Offset: 0x158 (R/  32) Frames Received Register */
1356   __I  GMAC_BCFR_Type            BCFR;        /**< \brief Offset: 0x15C (R/  32) Broadcast Frames Received Register */
1357   __I  GMAC_MFR_Type             MFR;         /**< \brief Offset: 0x160 (R/  32) Multicast Frames Received Register */
1358   __I  GMAC_PFR_Type             PFR;         /**< \brief Offset: 0x164 (R/  32) Pause Frames Received Register */
1359   __I  GMAC_BFR64_Type           BFR64;       /**< \brief Offset: 0x168 (R/  32) 64 Byte Frames Received Register */
1360   __I  GMAC_TBFR127_Type         TBFR127;     /**< \brief Offset: 0x16C (R/  32) 65 to 127 Byte Frames Received Register */
1361   __I  GMAC_TBFR255_Type         TBFR255;     /**< \brief Offset: 0x170 (R/  32) 128 to 255 Byte Frames Received Register */
1362   __I  GMAC_TBFR511_Type         TBFR511;     /**< \brief Offset: 0x174 (R/  32) 256 to 511Byte Frames Received Register */
1363   __I  GMAC_TBFR1023_Type        TBFR1023;    /**< \brief Offset: 0x178 (R/  32) 512 to 1023 Byte Frames Received Register */
1364   __I  GMAC_TBFR1518_Type        TBFR1518;    /**< \brief Offset: 0x17C (R/  32) 1024 to 1518 Byte Frames Received Register */
1365   __I  GMAC_TMXBFR_Type          TMXBFR;      /**< \brief Offset: 0x180 (R/  32) 1519 to Maximum Byte Frames Received Register */
1366   __I  GMAC_UFR_Type             UFR;         /**< \brief Offset: 0x184 (R/  32) Undersize Frames Received Register */
1367   __I  GMAC_OFR_Type             OFR;         /**< \brief Offset: 0x188 (R/  32) Oversize Frames Received Register */
1368   __I  GMAC_JR_Type              JR;          /**< \brief Offset: 0x18C (R/  32) Jabbers Received Register */
1369   __I  GMAC_FCSE_Type            FCSE;        /**< \brief Offset: 0x190 (R/  32) Frame Check Sequence Errors Register */
1370   __I  GMAC_LFFE_Type            LFFE;        /**< \brief Offset: 0x194 (R/  32) Length Field Frame Errors Register */
1371   __I  GMAC_RSE_Type             RSE;         /**< \brief Offset: 0x198 (R/  32) Receive Symbol Errors Register */
1372   __I  GMAC_AE_Type              AE;          /**< \brief Offset: 0x19C (R/  32) Alignment Errors Register */
1373   __I  GMAC_RRE_Type             RRE;         /**< \brief Offset: 0x1A0 (R/  32) Receive Resource Errors Register */
1374   __I  GMAC_ROE_Type             ROE;         /**< \brief Offset: 0x1A4 (R/  32) Receive Overrun Register */
1375   __I  GMAC_IHCE_Type            IHCE;        /**< \brief Offset: 0x1A8 (R/  32) IP Header Checksum Errors Register */
1376   __I  GMAC_TCE_Type             TCE;         /**< \brief Offset: 0x1AC (R/  32) TCP Checksum Errors Register */
1377   __I  GMAC_UCE_Type             UCE;         /**< \brief Offset: 0x1B0 (R/  32) UDP Checksum Errors Register */
1378        RoReg8                    Reserved4[0x8];
1379   __IO GMAC_TISUBN_Type          TISUBN;      /**< \brief Offset: 0x1BC (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */
1380   __IO GMAC_TSH_Type             TSH;         /**< \brief Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High [15:0] Register */
1381        RoReg8                    Reserved5[0x4];
1382   __IO GMAC_TSSSL_Type           TSSSL;       /**< \brief Offset: 0x1C8 (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register */
1383   __IO GMAC_TSSN_Type            TSSN;        /**< \brief Offset: 0x1CC (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register */
1384   __IO GMAC_TSL_Type             TSL;         /**< \brief Offset: 0x1D0 (R/W 32) 1588 Timer Seconds [31:0] Register */
1385   __IO GMAC_TN_Type              TN;          /**< \brief Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */
1386   __O  GMAC_TA_Type              TA;          /**< \brief Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */
1387   __IO GMAC_TI_Type              TI;          /**< \brief Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */
1388   __I  GMAC_EFTSL_Type           EFTSL;       /**< \brief Offset: 0x1E0 (R/  32) PTP Event Frame Transmitted Seconds Low Register */
1389   __I  GMAC_EFTN_Type            EFTN;        /**< \brief Offset: 0x1E4 (R/  32) PTP Event Frame Transmitted Nanoseconds */
1390   __I  GMAC_EFRSL_Type           EFRSL;       /**< \brief Offset: 0x1E8 (R/  32) PTP Event Frame Received Seconds Low Register */
1391   __I  GMAC_EFRN_Type            EFRN;        /**< \brief Offset: 0x1EC (R/  32) PTP Event Frame Received Nanoseconds */
1392   __I  GMAC_PEFTSL_Type          PEFTSL;      /**< \brief Offset: 0x1F0 (R/  32) PTP Peer Event Frame Transmitted Seconds Low Register */
1393   __I  GMAC_PEFTN_Type           PEFTN;       /**< \brief Offset: 0x1F4 (R/  32) PTP Peer Event Frame Transmitted Nanoseconds */
1394   __I  GMAC_PEFRSL_Type          PEFRSL;      /**< \brief Offset: 0x1F8 (R/  32) PTP Peer Event Frame Received Seconds Low Register */
1395   __I  GMAC_PEFRN_Type           PEFRN;       /**< \brief Offset: 0x1FC (R/  32) PTP Peer Event Frame Received Nanoseconds */
1396        RoReg8                    Reserved6[0x70];
1397   __I  GMAC_RLPITR_Type          RLPITR;      /**< \brief Offset: 0x270 (R/  32) Receive LPI transition Register */
1398   __I  GMAC_RLPITI_Type          RLPITI;      /**< \brief Offset: 0x274 (R/  32) Receive LPI Time Register */
1399   __I  GMAC_TLPITR_Type          TLPITR;      /**< \brief Offset: 0x278 (R/  32) Receive LPI transition Register */
1400   __I  GMAC_TLPITI_Type          TLPITI;      /**< \brief Offset: 0x27C (R/  32) Receive LPI Time Register */
1401 } Gmac;
1402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1403 
1404 #endif /* _MICROCHIP_PIC32CXSG_GMAC_COMPONENT_FIXUP_H_ */
1405