1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_DMAC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_DMAC_COMPONENT_FIXUP_H_ 9 10 /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ 15 uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */ 16 uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ 17 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 18 uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ 19 uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ 20 uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ 21 uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ 22 uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ 23 } bit; /*!< Structure used for bit access */ 24 uint16_t reg; /*!< Type used for register access */ 25 } DMAC_BTCTRL_Type; 26 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 27 28 /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ 29 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 30 typedef union { 31 struct { 32 uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ 33 } bit; /*!< Structure used for bit access */ 34 uint16_t reg; /*!< Type used for register access */ 35 } DMAC_BTCNT_Type; 36 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 37 38 /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */ 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 typedef union { 41 struct { 42 uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ 43 } bit; /*!< Structure used for bit access */ 44 uint32_t reg; /*!< Type used for register access */ 45 } DMAC_SRCADDR_Type; 46 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 47 48 /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */ 49 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 typedef union { 51 struct { // CRC mode 52 uint32_t CHKINIT:32; /*!< bit: 0..31 CRC Checksum Initial Value */ 53 } CRC; /*!< Structure used for CRC */ 54 struct { 55 uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ 56 } bit; /*!< Structure used for bit access */ 57 uint32_t reg; /*!< Type used for register access */ 58 } DMAC_DSTADDR_Type; 59 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ 62 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 63 typedef union { 64 struct { 65 uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ 66 } bit; /*!< Structure used for bit access */ 67 uint32_t reg; /*!< Type used for register access */ 68 } DMAC_DESCADDR_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x00) (R/W 32) Channel n Control A -------- */ 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 typedef union { 74 struct { 75 uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */ 76 uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */ 77 uint32_t :4; /*!< bit: 2.. 5 Reserved */ 78 uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */ 79 uint32_t :1; /*!< bit: 7 Reserved */ 80 uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */ 81 uint32_t :5; /*!< bit: 15..19 Reserved */ 82 uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */ 83 uint32_t :2; /*!< bit: 22..23 Reserved */ 84 uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */ 85 uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */ 86 uint32_t :2; /*!< bit: 30..31 Reserved */ 87 } bit; /*!< Structure used for bit access */ 88 uint32_t reg; /*!< Type used for register access */ 89 } DMAC_CHCTRLA_Type; 90 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x04) (R/W 8) Channel n Control B -------- */ 93 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 94 typedef union { 95 struct { 96 uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */ 97 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 98 } bit; /*!< Structure used for bit access */ 99 uint8_t reg; /*!< Type used for register access */ 100 } DMAC_CHCTRLB_Type; 101 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 102 103 /* -------- DMAC_CHPRILVL : (DMAC Offset: 0x05) (R/W 8) Channel n Priority Level -------- */ 104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 105 typedef union { 106 struct { 107 uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */ 108 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 109 } bit; /*!< Structure used for bit access */ 110 uint8_t reg; /*!< Type used for register access */ 111 } DMAC_CHPRILVL_Type; 112 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 113 114 /* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x06) (R/W 8) Channel n Event Control -------- */ 115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 116 typedef union { 117 struct { 118 uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */ 119 uint8_t :1; /*!< bit: 3 Reserved */ 120 uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */ 121 uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */ 122 uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */ 123 } bit; /*!< Structure used for bit access */ 124 uint8_t reg; /*!< Type used for register access */ 125 } DMAC_CHEVCTRL_Type; 126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 127 128 /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x0C) (R/W 8) Channel n Interrupt Enable Clear -------- */ 129 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 130 typedef union { 131 struct { 132 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ 133 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ 134 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ 135 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 136 } bit; /*!< Structure used for bit access */ 137 uint8_t reg; /*!< Type used for register access */ 138 } DMAC_CHINTENCLR_Type; 139 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x0D) (R/W 8) Channel n Interrupt Enable Set -------- */ 142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 143 typedef union { 144 struct { 145 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ 146 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ 147 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ 148 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 149 } bit; /*!< Structure used for bit access */ 150 uint8_t reg; /*!< Type used for register access */ 151 } DMAC_CHINTENSET_Type; 152 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 153 154 /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x0E) (R/W 8) Channel n Interrupt Flag Status and Clear -------- */ 155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 156 typedef union { // __I to avoid read-modify-write on write-to-clear register 157 struct { 158 __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ 159 __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ 160 __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ 161 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ 162 } bit; /*!< Structure used for bit access */ 163 uint8_t reg; /*!< Type used for register access */ 164 } DMAC_CHINTFLAG_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x0F) (R/W 8) Channel n Status -------- */ 168 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 169 typedef union { 170 struct { 171 uint8_t PEND:1; /*!< bit: 0 Channel Pending */ 172 uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ 173 uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ 174 uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */ 175 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 176 } bit; /*!< Structure used for bit access */ 177 uint8_t reg; /*!< Type used for register access */ 178 } DMAC_CHSTATUS_Type; 179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 180 181 /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ 182 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 183 typedef union { 184 struct { 185 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 186 uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ 187 uint16_t :6; /*!< bit: 2.. 7 Reserved */ 188 uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ 189 uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ 190 uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ 191 uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ 192 uint16_t :4; /*!< bit: 12..15 Reserved */ 193 } bit; /*!< Structure used for bit access */ 194 struct { 195 uint16_t :8; /*!< bit: 0.. 7 Reserved */ 196 uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ 197 uint16_t :4; /*!< bit: 12..15 Reserved */ 198 } vec; /*!< Structure used for vec access */ 199 uint16_t reg; /*!< Type used for register access */ 200 } DMAC_CTRL_Type; 201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 202 203 /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ 204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 205 typedef union { 206 struct { 207 uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ 208 uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ 209 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 210 uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ 211 uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */ 212 } bit; /*!< Structure used for bit access */ 213 uint16_t reg; /*!< Type used for register access */ 214 } DMAC_CRCCTRL_Type; 215 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 216 217 /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ 218 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 219 typedef union { 220 struct { 221 uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ 222 } bit; /*!< Structure used for bit access */ 223 uint32_t reg; /*!< Type used for register access */ 224 } DMAC_CRCDATAIN_Type; 225 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 226 227 /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ 228 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 229 typedef union { 230 struct { 231 uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ 232 } bit; /*!< Structure used for bit access */ 233 uint32_t reg; /*!< Type used for register access */ 234 } DMAC_CRCCHKSUM_Type; 235 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 236 237 /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ 238 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 239 typedef union { 240 struct { 241 uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ 242 uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ 243 uint8_t CRCERR:1; /*!< bit: 2 CRC Error */ 244 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 245 } bit; /*!< Structure used for bit access */ 246 uint8_t reg; /*!< Type used for register access */ 247 } DMAC_CRCSTATUS_Type; 248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 249 250 /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ 251 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 252 typedef union { 253 struct { 254 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 255 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 256 } bit; /*!< Structure used for bit access */ 257 uint8_t reg; /*!< Type used for register access */ 258 } DMAC_DBGCTRL_Type; 259 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 260 261 /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 263 typedef union { 264 struct { 265 uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ 266 uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ 267 uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ 268 uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ 269 uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ 270 uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ 271 uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ 272 uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ 273 uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ 274 uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ 275 uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ 276 uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ 277 uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ 278 uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ 279 uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ 280 uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ 281 uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */ 282 uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */ 283 uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */ 284 uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */ 285 uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */ 286 uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */ 287 uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */ 288 uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */ 289 uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */ 290 uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */ 291 uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */ 292 uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */ 293 uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */ 294 uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */ 295 uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */ 296 uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */ 297 } bit; /*!< Structure used for bit access */ 298 struct { 299 uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */ 300 } vec; /*!< Structure used for vec access */ 301 uint32_t reg; /*!< Type used for register access */ 302 } DMAC_SWTRIGCTRL_Type; 303 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 304 305 /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ 306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 307 typedef union { 308 struct { 309 uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */ 310 uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */ 311 uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ 312 uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */ 313 uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */ 314 uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ 315 uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */ 316 uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */ 317 uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ 318 uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */ 319 uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */ 320 uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ 321 } bit; /*!< Structure used for bit access */ 322 uint32_t reg; /*!< Type used for register access */ 323 } DMAC_PRICTRL0_Type; 324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 325 326 /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ 327 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 328 typedef union { 329 struct { 330 uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */ 331 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 332 uint16_t TERR:1; /*!< bit: 8 Transfer Error */ 333 uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ 334 uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ 335 uint16_t :1; /*!< bit: 11 Reserved */ 336 uint16_t CRCERR:1; /*!< bit: 12 CRC Error */ 337 uint16_t FERR:1; /*!< bit: 13 Fetch Error */ 338 uint16_t BUSY:1; /*!< bit: 14 Busy */ 339 uint16_t PEND:1; /*!< bit: 15 Pending */ 340 } bit; /*!< Structure used for bit access */ 341 uint16_t reg; /*!< Type used for register access */ 342 } DMAC_INTPEND_Type; 343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 344 345 /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) ( R/ 32) Interrupt Status -------- */ 346 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 347 typedef union { 348 struct { 349 uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ 350 uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ 351 uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ 352 uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ 353 uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ 354 uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ 355 uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ 356 uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ 357 uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ 358 uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ 359 uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ 360 uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ 361 uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ 362 uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ 363 uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ 364 uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ 365 uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */ 366 uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */ 367 uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */ 368 uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */ 369 uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */ 370 uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */ 371 uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */ 372 uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */ 373 uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */ 374 uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */ 375 uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */ 376 uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */ 377 uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */ 378 uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */ 379 uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */ 380 uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */ 381 } bit; /*!< Structure used for bit access */ 382 struct { 383 uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */ 384 } vec; /*!< Structure used for vec access */ 385 uint32_t reg; /*!< Type used for register access */ 386 } DMAC_INTSTATUS_Type; 387 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 388 389 /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) ( R/ 32) Busy Channels -------- */ 390 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 391 typedef union { 392 struct { 393 uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ 394 uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ 395 uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ 396 uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ 397 uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ 398 uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ 399 uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ 400 uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ 401 uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ 402 uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ 403 uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ 404 uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ 405 uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ 406 uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ 407 uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ 408 uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ 409 uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */ 410 uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */ 411 uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */ 412 uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */ 413 uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */ 414 uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */ 415 uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */ 416 uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */ 417 uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */ 418 uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */ 419 uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */ 420 uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */ 421 uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */ 422 uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */ 423 uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */ 424 uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */ 425 } bit; /*!< Structure used for bit access */ 426 struct { 427 uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */ 428 } vec; /*!< Structure used for vec access */ 429 uint32_t reg; /*!< Type used for register access */ 430 } DMAC_BUSYCH_Type; 431 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 432 433 /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) ( R/ 32) Pending Channels -------- */ 434 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 435 typedef union { 436 struct { 437 uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ 438 uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ 439 uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ 440 uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ 441 uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ 442 uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ 443 uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ 444 uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ 445 uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ 446 uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ 447 uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ 448 uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ 449 uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ 450 uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ 451 uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ 452 uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ 453 uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */ 454 uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */ 455 uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */ 456 uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */ 457 uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */ 458 uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */ 459 uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */ 460 uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */ 461 uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */ 462 uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */ 463 uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */ 464 uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */ 465 uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */ 466 uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */ 467 uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */ 468 uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */ 469 } bit; /*!< Structure used for bit access */ 470 struct { 471 uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */ 472 } vec; /*!< Structure used for vec access */ 473 uint32_t reg; /*!< Type used for register access */ 474 } DMAC_PENDCH_Type; 475 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 476 477 /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) ( R/ 32) Active Channel and Levels -------- */ 478 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 479 typedef union { 480 struct { 481 uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ 482 uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ 483 uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ 484 uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ 485 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 486 uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ 487 uint32_t :2; /*!< bit: 13..14 Reserved */ 488 uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ 489 uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ 490 } bit; /*!< Structure used for bit access */ 491 struct { 492 uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ 493 uint32_t :28; /*!< bit: 4..31 Reserved */ 494 } vec; /*!< Structure used for vec access */ 495 uint32_t reg; /*!< Type used for register access */ 496 } DMAC_ACTIVE_Type; 497 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 498 499 /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ 500 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 501 typedef union { 502 struct { 503 uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ 504 } bit; /*!< Structure used for bit access */ 505 uint32_t reg; /*!< Type used for register access */ 506 } DMAC_BASEADDR_Type; 507 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 508 509 /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ 510 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 511 typedef union { 512 struct { 513 uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ 514 } bit; /*!< Structure used for bit access */ 515 uint32_t reg; /*!< Type used for register access */ 516 } DMAC_WRBADDR_Type; 517 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 518 519 /** \brief DMAC Descriptor SRAM registers */ 520 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 521 typedef struct { 522 __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ 523 __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ 524 __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ 525 __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ 526 __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ 527 } DmacDescriptor 528 #ifdef __GNUC__ 529 __attribute__ ((aligned (8))) 530 #endif 531 ; 532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 533 534 /** \brief DmacChannel hardware registers */ 535 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 536 typedef struct { 537 __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x00 (R/W 32) Channel n Control A */ 538 __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x04 (R/W 8) Channel n Control B */ 539 __IO DMAC_CHPRILVL_Type CHPRILVL; /**< \brief Offset: 0x05 (R/W 8) Channel n Priority Level */ 540 __IO DMAC_CHEVCTRL_Type CHEVCTRL; /**< \brief Offset: 0x06 (R/W 8) Channel n Event Control */ 541 RoReg8 Reserved1[0x5]; 542 __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x0C (R/W 8) Channel n Interrupt Enable Clear */ 543 __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x0D (R/W 8) Channel n Interrupt Enable Set */ 544 __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x0E (R/W 8) Channel n Interrupt Flag Status and Clear */ 545 __IO DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0F (R/W 8) Channel n Status */ 546 } DmacChannel; 547 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 548 549 /** \brief DMAC APB hardware registers */ 550 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 551 typedef struct { 552 __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ 553 __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ 554 __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ 555 __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ 556 __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ 557 __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ 558 RoReg8 Reserved1[0x2]; 559 __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ 560 __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ 561 RoReg8 Reserved2[0x8]; 562 __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ 563 RoReg8 Reserved3[0x2]; 564 __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ 565 __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ 566 __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ 567 __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ 568 __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ 569 __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ 570 RoReg8 Reserved4[0x4]; 571 DmacChannel Channel[DMAC_CHANNEL_NUMBER]; /**< \brief Offset: 0x40 DmacChannel groups [CH_NUM] */ 572 } Dmac; 573 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 574 575 #endif /* _MICROCHIP_PIC32CXSG_DMAC_COMPONENT_FIXUP_H_ */ 576