1  /*******************************************************************************
2  * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * Register bit offsets and masks definitions for PolarFire SoC MSS Timer
7  */
8 
9 #ifndef MSS_TIMER_REGS_H_
10 #define MSS_TIMER_REGS_H_
11 
12 #ifdef __cplusplus
13 extern "C" {
14 #endif
15 /*----------------------------------------------------------------------------*/
16 /*--------------------------MPFS MSS Timer register map-----------------------*/
17 /*----------------------------------------------------------------------------*/
18 typedef struct
19 {
20     /* Timer 1 register declaration */
21     const volatile  uint32_t TIM1_VAL;
22     volatile uint32_t TIM1_LOADVAL;
23     volatile uint32_t TIM1_BGLOADVAL;
24     volatile uint32_t TIM1_CTRL;
25     volatile uint32_t TIM1_RIS;
26     const volatile  uint32_t TIM1_MIS;
27 
28     /* Timer 2 register declaration */
29     const volatile  uint32_t TIM2_VAL;
30     volatile uint32_t TIM2_LOADVAL;
31     volatile uint32_t TIM2_BGLOADVAL;
32     volatile uint32_t TIM2_CTRL;
33     volatile uint32_t TIM2_RIS;
34     const volatile  uint32_t TIM2_MIS;
35 
36     /* Timer 64 register declaration */
37     const volatile  uint32_t TIM64_VAL_U;
38     const volatile  uint32_t TIM64_VAL_L;
39     volatile uint32_t TIM64_LOADVAL_U;
40     volatile uint32_t TIM64_LOADVAL_L;
41     volatile uint32_t TIM64_BGLOADVAL_U;
42     volatile uint32_t TIM64_BGLOADVAL_L;
43     volatile uint32_t TIM64_CTRL;
44     volatile uint32_t TIM64_RIS;
45     const volatile  uint32_t TIM64_MIS;
46     volatile uint32_t TIM64_MODE;
47 } TIMER_TypeDef;
48 
49 /******************************************************************************/
50 /*                         Peripheral memory map                              */
51 /******************************************************************************/
52 #define TIMER_LO_BASE         0x20125000
53 #define TIMER_HI_BASE         0x28125000
54 
55 
56 #ifdef __cplusplus
57 }
58 #endif
59 
60 #endif  /* MSS_TIMER_REGS_H_ */
61