1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_RTC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_RTC_COMPONENT_FIXUP_H_ 9 10 /* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 17 uint16_t :3; /*!< bit: 4.. 6 Reserved */ 18 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ 19 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 20 uint16_t :1; /*!< bit: 12 Reserved */ 21 uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */ 22 uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */ 23 uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */ 24 } bit; /*!< Structure used for bit access */ 25 uint16_t reg; /*!< Type used for register access */ 26 } RTC_MODE0_CTRLA_Type; 27 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 28 29 /* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 Control A -------- */ 30 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 31 typedef union { 32 struct { 33 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 34 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 35 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 36 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 37 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 38 uint16_t :1; /*!< bit: 12 Reserved */ 39 uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */ 40 uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */ 41 uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */ 42 } bit; /*!< Structure used for bit access */ 43 uint16_t reg; /*!< Type used for register access */ 44 } RTC_MODE1_CTRLA_Type; 45 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 46 47 /* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 Control A -------- */ 48 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 typedef union { 50 struct { 51 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 52 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 53 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 54 uint16_t :2; /*!< bit: 4.. 5 Reserved */ 55 uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ 56 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ 57 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 58 uint16_t :1; /*!< bit: 12 Reserved */ 59 uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */ 60 uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */ 61 uint16_t CLOCKSYNC:1; /*!< bit: 15 Clock Read Synchronization Enable */ 62 } bit; /*!< Structure used for bit access */ 63 uint16_t reg; /*!< Type used for register access */ 64 } RTC_MODE2_CTRLA_Type; 65 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 /* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 Control B -------- */ 68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 69 typedef union { 70 struct { 71 uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */ 72 uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */ 73 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 74 uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */ 75 uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */ 76 uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */ 77 uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */ 78 uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */ 79 uint16_t :1; /*!< bit: 11 Reserved */ 80 uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */ 81 uint16_t :1; /*!< bit: 15 Reserved */ 82 } bit; /*!< Structure used for bit access */ 83 uint16_t reg; /*!< Type used for register access */ 84 } RTC_MODE0_CTRLB_Type; 85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 87 /* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 Control B -------- */ 88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 89 typedef union { 90 struct { 91 uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */ 92 uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */ 93 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 94 uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */ 95 uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */ 96 uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */ 97 uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */ 98 uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */ 99 uint16_t :1; /*!< bit: 11 Reserved */ 100 uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */ 101 uint16_t :1; /*!< bit: 15 Reserved */ 102 } bit; /*!< Structure used for bit access */ 103 uint16_t reg; /*!< Type used for register access */ 104 } RTC_MODE1_CTRLB_Type; 105 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 106 107 /* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 Control B -------- */ 108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 109 typedef union { 110 struct { 111 uint16_t GP0EN:1; /*!< bit: 0 General Purpose 0 Enable */ 112 uint16_t GP2EN:1; /*!< bit: 1 General Purpose 2 Enable */ 113 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 114 uint16_t DEBMAJ:1; /*!< bit: 4 Debouncer Majority Enable */ 115 uint16_t DEBASYNC:1; /*!< bit: 5 Debouncer Asynchronous Enable */ 116 uint16_t RTCOUT:1; /*!< bit: 6 RTC Output Enable */ 117 uint16_t DMAEN:1; /*!< bit: 7 DMA Enable */ 118 uint16_t DEBF:3; /*!< bit: 8..10 Debounce Freqnuency */ 119 uint16_t :1; /*!< bit: 11 Reserved */ 120 uint16_t ACTF:3; /*!< bit: 12..14 Active Layer Freqnuency */ 121 uint16_t :1; /*!< bit: 15 Reserved */ 122 } bit; /*!< Structure used for bit access */ 123 uint16_t reg; /*!< Type used for register access */ 124 } RTC_MODE2_CTRLB_Type; 125 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 126 127 /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 Event Control -------- */ 128 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 129 typedef union { 130 struct { 131 uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 132 uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 133 uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 134 uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 135 uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 136 uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 137 uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 138 uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 139 uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ 140 uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ 141 uint32_t :4; /*!< bit: 10..13 Reserved */ 142 uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */ 143 uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 144 uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */ 145 uint32_t :15; /*!< bit: 17..31 Reserved */ 146 } bit; /*!< Structure used for bit access */ 147 struct { 148 uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 149 uint32_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ 150 uint32_t :22; /*!< bit: 10..31 Reserved */ 151 } vec; /*!< Structure used for vec access */ 152 uint32_t reg; /*!< Type used for register access */ 153 } RTC_MODE0_EVCTRL_Type; 154 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 155 156 /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 Event Control -------- */ 157 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 158 typedef union { 159 struct { 160 uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 161 uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 162 uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 163 uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 164 uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 165 uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 166 uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 167 uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 168 uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ 169 uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ 170 uint32_t CMPEO2:1; /*!< bit: 10 Compare 2 Event Output Enable */ 171 uint32_t CMPEO3:1; /*!< bit: 11 Compare 3 Event Output Enable */ 172 uint32_t :2; /*!< bit: 12..13 Reserved */ 173 uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */ 174 uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 175 uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */ 176 uint32_t :15; /*!< bit: 17..31 Reserved */ 177 } bit; /*!< Structure used for bit access */ 178 struct { 179 uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 180 uint32_t CMPEO:4; /*!< bit: 8..11 Compare x Event Output Enable */ 181 uint32_t :20; /*!< bit: 12..31 Reserved */ 182 } vec; /*!< Structure used for vec access */ 183 uint32_t reg; /*!< Type used for register access */ 184 } RTC_MODE1_EVCTRL_Type; 185 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 186 187 /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 Event Control -------- */ 188 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 189 typedef union { 190 struct { 191 uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 192 uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 193 uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 194 uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 195 uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 196 uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 197 uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 198 uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 199 uint32_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ 200 uint32_t ALARMEO1:1; /*!< bit: 9 Alarm 1 Event Output Enable */ 201 uint32_t :4; /*!< bit: 10..13 Reserved */ 202 uint32_t TAMPEREO:1; /*!< bit: 14 Tamper Event Output Enable */ 203 uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 204 uint32_t TAMPEVEI:1; /*!< bit: 16 Tamper Event Input Enable */ 205 uint32_t :15; /*!< bit: 17..31 Reserved */ 206 } bit; /*!< Structure used for bit access */ 207 struct { 208 uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 209 uint32_t ALARMEO:2; /*!< bit: 8.. 9 Alarm x Event Output Enable */ 210 uint32_t :22; /*!< bit: 10..31 Reserved */ 211 } vec; /*!< Structure used for vec access */ 212 uint32_t reg; /*!< Type used for register access */ 213 } RTC_MODE2_EVCTRL_Type; 214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 215 216 /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 Interrupt Enable Clear -------- */ 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 218 typedef union { 219 struct { 220 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 221 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 222 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 223 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 224 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 225 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 226 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 227 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 228 uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ 229 uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ 230 uint16_t :4; /*!< bit: 10..13 Reserved */ 231 uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */ 232 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 233 } bit; /*!< Structure used for bit access */ 234 struct { 235 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 236 uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */ 237 uint16_t :6; /*!< bit: 10..15 Reserved */ 238 } vec; /*!< Structure used for vec access */ 239 uint16_t reg; /*!< Type used for register access */ 240 } RTC_MODE0_INTENCLR_Type; 241 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 242 243 /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 Interrupt Enable Clear -------- */ 244 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 245 typedef union { 246 struct { 247 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 248 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 249 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 250 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 251 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 252 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 253 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 254 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 255 uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ 256 uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ 257 uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */ 258 uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */ 259 uint16_t :2; /*!< bit: 12..13 Reserved */ 260 uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */ 261 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 262 } bit; /*!< Structure used for bit access */ 263 struct { 264 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 265 uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */ 266 uint16_t :4; /*!< bit: 12..15 Reserved */ 267 } vec; /*!< Structure used for vec access */ 268 uint16_t reg; /*!< Type used for register access */ 269 } RTC_MODE1_INTENCLR_Type; 270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 271 272 /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 Interrupt Enable Clear -------- */ 273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 274 typedef union { 275 struct { 276 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 277 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 278 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 279 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 280 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 281 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 282 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 283 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 284 uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */ 285 uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */ 286 uint16_t :4; /*!< bit: 10..13 Reserved */ 287 uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */ 288 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 289 } bit; /*!< Structure used for bit access */ 290 struct { 291 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 292 uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */ 293 uint16_t :6; /*!< bit: 10..15 Reserved */ 294 } vec; /*!< Structure used for vec access */ 295 uint16_t reg; /*!< Type used for register access */ 296 } RTC_MODE2_INTENCLR_Type; 297 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 298 299 /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 Interrupt Enable Set -------- */ 300 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 301 typedef union { 302 struct { 303 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 304 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 305 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 306 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 307 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 308 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 309 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 310 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 311 uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ 312 uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ 313 uint16_t :4; /*!< bit: 10..13 Reserved */ 314 uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */ 315 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 316 } bit; /*!< Structure used for bit access */ 317 struct { 318 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 319 uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */ 320 uint16_t :6; /*!< bit: 10..15 Reserved */ 321 } vec; /*!< Structure used for vec access */ 322 uint16_t reg; /*!< Type used for register access */ 323 } RTC_MODE0_INTENSET_Type; 324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 325 326 /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 Interrupt Enable Set -------- */ 327 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 328 typedef union { 329 struct { 330 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 331 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 332 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 333 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 334 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 335 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 336 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 337 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 338 uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ 339 uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ 340 uint16_t CMP2:1; /*!< bit: 10 Compare 2 Interrupt Enable */ 341 uint16_t CMP3:1; /*!< bit: 11 Compare 3 Interrupt Enable */ 342 uint16_t :2; /*!< bit: 12..13 Reserved */ 343 uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */ 344 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 345 } bit; /*!< Structure used for bit access */ 346 struct { 347 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 348 uint16_t CMP:4; /*!< bit: 8..11 Compare x Interrupt Enable */ 349 uint16_t :4; /*!< bit: 12..15 Reserved */ 350 } vec; /*!< Structure used for vec access */ 351 uint16_t reg; /*!< Type used for register access */ 352 } RTC_MODE1_INTENSET_Type; 353 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 354 355 /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 Interrupt Enable Set -------- */ 356 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 357 typedef union { 358 struct { 359 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Enable */ 360 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Enable */ 361 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Enable */ 362 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Enable */ 363 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Enable */ 364 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Enable */ 365 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Enable */ 366 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Enable */ 367 uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */ 368 uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 Interrupt Enable */ 369 uint16_t :4; /*!< bit: 10..13 Reserved */ 370 uint16_t TAMPER:1; /*!< bit: 14 Tamper Enable */ 371 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 372 } bit; /*!< Structure used for bit access */ 373 struct { 374 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Enable */ 375 uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x Interrupt Enable */ 376 uint16_t :6; /*!< bit: 10..15 Reserved */ 377 } vec; /*!< Structure used for vec access */ 378 uint16_t reg; /*!< Type used for register access */ 379 } RTC_MODE2_INTENSET_Type; 380 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 381 382 /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 Interrupt Flag Status and Clear -------- */ 383 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 384 typedef union { // __I to avoid read-modify-write on write-to-clear register 385 struct { 386 __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ 387 __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ 388 __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ 389 __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ 390 __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ 391 __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ 392 __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ 393 __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ 394 __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */ 395 __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */ 396 __I uint16_t :4; /*!< bit: 10..13 Reserved */ 397 __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */ 398 __I uint16_t OVF:1; /*!< bit: 15 Overflow */ 399 } bit; /*!< Structure used for bit access */ 400 struct { 401 __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ 402 __I uint16_t CMP:2; /*!< bit: 8.. 9 Compare x */ 403 __I uint16_t :6; /*!< bit: 10..15 Reserved */ 404 } vec; /*!< Structure used for vec access */ 405 uint16_t reg; /*!< Type used for register access */ 406 } RTC_MODE0_INTFLAG_Type; 407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 408 409 /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 Interrupt Flag Status and Clear -------- */ 410 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 411 typedef union { // __I to avoid read-modify-write on write-to-clear register 412 struct { 413 __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ 414 __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ 415 __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ 416 __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ 417 __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ 418 __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ 419 __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ 420 __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ 421 __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */ 422 __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */ 423 __I uint16_t CMP2:1; /*!< bit: 10 Compare 2 */ 424 __I uint16_t CMP3:1; /*!< bit: 11 Compare 3 */ 425 __I uint16_t :2; /*!< bit: 12..13 Reserved */ 426 __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */ 427 __I uint16_t OVF:1; /*!< bit: 15 Overflow */ 428 } bit; /*!< Structure used for bit access */ 429 struct { 430 __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ 431 __I uint16_t CMP:4; /*!< bit: 8..11 Compare x */ 432 __I uint16_t :4; /*!< bit: 12..15 Reserved */ 433 } vec; /*!< Structure used for vec access */ 434 uint16_t reg; /*!< Type used for register access */ 435 } RTC_MODE1_INTFLAG_Type; 436 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 437 438 /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 Interrupt Flag Status and Clear -------- */ 439 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 440 typedef union { // __I to avoid read-modify-write on write-to-clear register 441 struct { 442 __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ 443 __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ 444 __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ 445 __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ 446 __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ 447 __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ 448 __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ 449 __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ 450 __I uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 451 __I uint16_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 452 __I uint16_t :4; /*!< bit: 10..13 Reserved */ 453 __I uint16_t TAMPER:1; /*!< bit: 14 Tamper */ 454 __I uint16_t OVF:1; /*!< bit: 15 Overflow */ 455 } bit; /*!< Structure used for bit access */ 456 struct { 457 __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ 458 __I uint16_t ALARM:2; /*!< bit: 8.. 9 Alarm x */ 459 __I uint16_t :6; /*!< bit: 10..15 Reserved */ 460 } vec; /*!< Structure used for vec access */ 461 uint16_t reg; /*!< Type used for register access */ 462 } RTC_MODE2_INTFLAG_Type; 463 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 464 465 /* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */ 466 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 467 typedef union { 468 struct { 469 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ 470 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 471 } bit; /*!< Structure used for bit access */ 472 uint8_t reg; /*!< Type used for register access */ 473 } RTC_DBGCTRL_Type; 474 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 475 476 /* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) ( R/ 32) MODE0 Synchronization Busy Status -------- */ 477 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 478 typedef union { 479 struct { 480 uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */ 481 uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ 482 uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ 483 uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */ 484 uint32_t :1; /*!< bit: 4 Reserved */ 485 uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */ 486 uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */ 487 uint32_t :8; /*!< bit: 7..14 Reserved */ 488 uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */ 489 uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */ 490 uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */ 491 uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */ 492 uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */ 493 uint32_t :12; /*!< bit: 20..31 Reserved */ 494 } bit; /*!< Structure used for bit access */ 495 struct { 496 uint32_t :5; /*!< bit: 0.. 4 Reserved */ 497 uint32_t COMP:2; /*!< bit: 5.. 6 COMP x Register Busy */ 498 uint32_t :9; /*!< bit: 7..15 Reserved */ 499 uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */ 500 uint32_t :12; /*!< bit: 20..31 Reserved */ 501 } vec; /*!< Structure used for vec access */ 502 uint32_t reg; /*!< Type used for register access */ 503 } RTC_MODE0_SYNCBUSY_Type; 504 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 505 /* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) ( R/ 32) MODE1 Synchronization Busy Status -------- */ 506 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 507 typedef union { 508 struct { 509 uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */ 510 uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ 511 uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ 512 uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */ 513 uint32_t PER:1; /*!< bit: 4 PER Register Busy */ 514 uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */ 515 uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */ 516 uint32_t COMP2:1; /*!< bit: 7 COMP 2 Register Busy */ 517 uint32_t COMP3:1; /*!< bit: 8 COMP 3 Register Busy */ 518 uint32_t :6; /*!< bit: 9..14 Reserved */ 519 uint32_t COUNTSYNC:1; /*!< bit: 15 Count Synchronization Enable Bit Busy */ 520 uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */ 521 uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */ 522 uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */ 523 uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */ 524 uint32_t :12; /*!< bit: 20..31 Reserved */ 525 } bit; /*!< Structure used for bit access */ 526 struct { 527 uint32_t :5; /*!< bit: 0.. 4 Reserved */ 528 uint32_t COMP:4; /*!< bit: 5.. 8 COMP x Register Busy */ 529 uint32_t :7; /*!< bit: 9..15 Reserved */ 530 uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */ 531 uint32_t :12; /*!< bit: 20..31 Reserved */ 532 } vec; /*!< Structure used for vec access */ 533 uint32_t reg; /*!< Type used for register access */ 534 } RTC_MODE1_SYNCBUSY_Type; 535 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 536 537 /* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) ( R/ 32) MODE2 Synchronization Busy Status -------- */ 538 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 539 typedef union { 540 struct { 541 uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */ 542 uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ 543 uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ 544 uint32_t CLOCK:1; /*!< bit: 3 CLOCK Register Busy */ 545 uint32_t :1; /*!< bit: 4 Reserved */ 546 uint32_t ALARM0:1; /*!< bit: 5 ALARM 0 Register Busy */ 547 uint32_t ALARM1:1; /*!< bit: 6 ALARM 1 Register Busy */ 548 uint32_t :4; /*!< bit: 7..10 Reserved */ 549 uint32_t MASK0:1; /*!< bit: 11 MASK 0 Register Busy */ 550 uint32_t MASK1:1; /*!< bit: 12 MASK 1 Register Busy */ 551 uint32_t :2; /*!< bit: 13..14 Reserved */ 552 uint32_t CLOCKSYNC:1; /*!< bit: 15 Clock Synchronization Enable Bit Busy */ 553 uint32_t GP0:1; /*!< bit: 16 General Purpose 0 Register Busy */ 554 uint32_t GP1:1; /*!< bit: 17 General Purpose 1 Register Busy */ 555 uint32_t GP2:1; /*!< bit: 18 General Purpose 2 Register Busy */ 556 uint32_t GP3:1; /*!< bit: 19 General Purpose 3 Register Busy */ 557 uint32_t :12; /*!< bit: 20..31 Reserved */ 558 } bit; /*!< Structure used for bit access */ 559 struct { 560 uint32_t :5; /*!< bit: 0.. 4 Reserved */ 561 uint32_t ALARM:2; /*!< bit: 5.. 6 ALARM x Register Busy */ 562 uint32_t :4; /*!< bit: 7..10 Reserved */ 563 uint32_t MASK:2; /*!< bit: 11..12 MASK x Register Busy */ 564 uint32_t :3; /*!< bit: 13..15 Reserved */ 565 uint32_t GP:4; /*!< bit: 16..19 General Purpose x Register Busy */ 566 uint32_t :12; /*!< bit: 20..31 Reserved */ 567 } vec; /*!< Structure used for vec access */ 568 uint32_t reg; /*!< Type used for register access */ 569 } RTC_MODE2_SYNCBUSY_Type; 570 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 571 572 /* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */ 573 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 574 typedef union { 575 struct { 576 uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ 577 uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ 578 } bit; /*!< Structure used for bit access */ 579 uint8_t reg; /*!< Type used for register access */ 580 } RTC_FREQCORR_Type; 581 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 582 583 /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 Counter Value -------- */ 584 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 585 typedef union { 586 struct { 587 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ 588 } bit; /*!< Structure used for bit access */ 589 uint32_t reg; /*!< Type used for register access */ 590 } RTC_MODE0_COUNT_Type; 591 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 592 593 /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 Counter Value -------- */ 594 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 595 typedef union { 596 struct { 597 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ 598 } bit; /*!< Structure used for bit access */ 599 uint16_t reg; /*!< Type used for register access */ 600 } RTC_MODE1_COUNT_Type; 601 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 602 603 /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 Clock Value -------- */ 604 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 605 typedef union { 606 struct { 607 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ 608 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ 609 uint32_t HOUR:5; /*!< bit: 12..16 Hour */ 610 uint32_t DAY:5; /*!< bit: 17..21 Day */ 611 uint32_t MONTH:4; /*!< bit: 22..25 Month */ 612 uint32_t YEAR:6; /*!< bit: 26..31 Year */ 613 } bit; /*!< Structure used for bit access */ 614 uint32_t reg; /*!< Type used for register access */ 615 } RTC_MODE2_CLOCK_Type; 616 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 617 618 /* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 Counter Period -------- */ 619 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 620 typedef union { 621 struct { 622 uint16_t PER:16; /*!< bit: 0..15 Counter Period */ 623 } bit; /*!< Structure used for bit access */ 624 uint16_t reg; /*!< Type used for register access */ 625 } RTC_MODE1_PER_Type; 626 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 627 628 /* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 Compare n Value -------- */ 629 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 630 typedef union { 631 struct { 632 uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ 633 } bit; /*!< Structure used for bit access */ 634 uint32_t reg; /*!< Type used for register access */ 635 } RTC_MODE0_COMP_Type; 636 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 637 638 /* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 Compare n Value -------- */ 639 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 640 typedef union { 641 struct { 642 uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ 643 } bit; /*!< Structure used for bit access */ 644 uint16_t reg; /*!< Type used for register access */ 645 } RTC_MODE1_COMP_Type; 646 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 647 648 /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ 649 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 650 typedef union { 651 struct { 652 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ 653 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ 654 uint32_t HOUR:5; /*!< bit: 12..16 Hour */ 655 uint32_t DAY:5; /*!< bit: 17..21 Day */ 656 uint32_t MONTH:4; /*!< bit: 22..25 Month */ 657 uint32_t YEAR:6; /*!< bit: 26..31 Year */ 658 } bit; /*!< Structure used for bit access */ 659 uint32_t reg; /*!< Type used for register access */ 660 } RTC_MODE2_ALARM_Type; 661 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 662 663 #define RTC_MODE2_ALARM_OFFSET 0x20 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */ 664 #define RTC_MODE2_ALARM_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */ 665 666 #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */ 667 #define RTC_MODE2_ALARM_SECOND_Msk (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos) 668 #define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)) 669 #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */ 670 #define RTC_MODE2_ALARM_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos) 671 #define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)) 672 #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */ 673 #define RTC_MODE2_ALARM_HOUR_Msk (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos) 674 #define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)) 675 #define RTC_MODE2_ALARM_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_ALARM) Morning hour */ 676 #define RTC_MODE2_ALARM_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_ALARM) Afternoon hour */ 677 #define RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos) 678 #define RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos) 679 #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */ 680 #define RTC_MODE2_ALARM_DAY_Msk (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos) 681 #define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)) 682 #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */ 683 #define RTC_MODE2_ALARM_MONTH_Msk (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos) 684 #define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)) 685 #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */ 686 #define RTC_MODE2_ALARM_YEAR_Msk (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos) 687 #define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)) 688 #define RTC_MODE2_ALARM_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */ 689 690 /* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ 691 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 692 typedef union { 693 struct { 694 uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ 695 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 696 } bit; /*!< Structure used for bit access */ 697 uint8_t reg; /*!< Type used for register access */ 698 } RTC_MODE2_MASK_Type; 699 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 700 701 #define RTC_MODE2_MASK_OFFSET 0x24 /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */ 702 #define RTC_MODE2_MASK_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */ 703 704 #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */ 705 #define RTC_MODE2_MASK_SEL_Msk (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos) 706 #define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)) 707 #define RTC_MODE2_MASK_SEL_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_MASK) Alarm Disabled */ 708 #define RTC_MODE2_MASK_SEL_SS_Val _U_(0x1) /**< \brief (RTC_MODE2_MASK) Match seconds only */ 709 #define RTC_MODE2_MASK_SEL_MMSS_Val _U_(0x2) /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */ 710 #define RTC_MODE2_MASK_SEL_HHMMSS_Val _U_(0x3) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */ 711 #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */ 712 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */ 713 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */ 714 #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) 715 #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) 716 #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) 717 #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 718 #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 719 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 720 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 721 #define RTC_MODE2_MASK_MASK _U_(0x07) /**< \brief (RTC_MODE2_MASK) MASK Register */ 722 723 /* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */ 724 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 725 typedef union { 726 struct { 727 uint32_t GP:32; /*!< bit: 0..31 General Purpose */ 728 } bit; /*!< Structure used for bit access */ 729 uint32_t reg; /*!< Type used for register access */ 730 } RTC_GP_Type; 731 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 732 733 /* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */ 734 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 735 typedef union { 736 struct { 737 uint32_t IN0ACT:2; /*!< bit: 0.. 1 Tamper Input 0 Action */ 738 uint32_t IN1ACT:2; /*!< bit: 2.. 3 Tamper Input 1 Action */ 739 uint32_t IN2ACT:2; /*!< bit: 4.. 5 Tamper Input 2 Action */ 740 uint32_t IN3ACT:2; /*!< bit: 6.. 7 Tamper Input 3 Action */ 741 uint32_t IN4ACT:2; /*!< bit: 8.. 9 Tamper Input 4 Action */ 742 uint32_t :6; /*!< bit: 10..15 Reserved */ 743 uint32_t TAMLVL0:1; /*!< bit: 16 Tamper Level Select 0 */ 744 uint32_t TAMLVL1:1; /*!< bit: 17 Tamper Level Select 1 */ 745 uint32_t TAMLVL2:1; /*!< bit: 18 Tamper Level Select 2 */ 746 uint32_t TAMLVL3:1; /*!< bit: 19 Tamper Level Select 3 */ 747 uint32_t TAMLVL4:1; /*!< bit: 20 Tamper Level Select 4 */ 748 uint32_t :3; /*!< bit: 21..23 Reserved */ 749 uint32_t DEBNC0:1; /*!< bit: 24 Debouncer Enable 0 */ 750 uint32_t DEBNC1:1; /*!< bit: 25 Debouncer Enable 1 */ 751 uint32_t DEBNC2:1; /*!< bit: 26 Debouncer Enable 2 */ 752 uint32_t DEBNC3:1; /*!< bit: 27 Debouncer Enable 3 */ 753 uint32_t DEBNC4:1; /*!< bit: 28 Debouncer Enable 4 */ 754 uint32_t :3; /*!< bit: 29..31 Reserved */ 755 } bit; /*!< Structure used for bit access */ 756 struct { 757 uint32_t :16; /*!< bit: 0..15 Reserved */ 758 uint32_t TAMLVL:5; /*!< bit: 16..20 Tamper Level Select x */ 759 uint32_t :3; /*!< bit: 21..23 Reserved */ 760 uint32_t DEBNC:5; /*!< bit: 24..28 Debouncer Enable x */ 761 uint32_t :3; /*!< bit: 29..31 Reserved */ 762 } vec; /*!< Structure used for vec access */ 763 uint32_t reg; /*!< Type used for register access */ 764 } RTC_TAMPCTRL_Type; 765 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 766 767 /* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) ( R/ 32) MODE0 Timestamp -------- */ 768 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 769 typedef union { 770 struct { 771 uint32_t COUNT:32; /*!< bit: 0..31 Count Timestamp Value */ 772 } bit; /*!< Structure used for bit access */ 773 uint32_t reg; /*!< Type used for register access */ 774 } RTC_MODE0_TIMESTAMP_Type; 775 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 776 777 /* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) ( R/ 32) MODE1 Timestamp -------- */ 778 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 779 typedef union { 780 struct { 781 uint32_t COUNT:16; /*!< bit: 0..15 Count Timestamp Value */ 782 uint32_t :16; /*!< bit: 16..31 Reserved */ 783 } bit; /*!< Structure used for bit access */ 784 uint32_t reg; /*!< Type used for register access */ 785 } RTC_MODE1_TIMESTAMP_Type; 786 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 787 788 /* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) ( R/ 32) MODE2 Timestamp -------- */ 789 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 790 typedef union { 791 struct { 792 uint32_t SECOND:6; /*!< bit: 0.. 5 Second Timestamp Value */ 793 uint32_t MINUTE:6; /*!< bit: 6..11 Minute Timestamp Value */ 794 uint32_t HOUR:5; /*!< bit: 12..16 Hour Timestamp Value */ 795 uint32_t DAY:5; /*!< bit: 17..21 Day Timestamp Value */ 796 uint32_t MONTH:4; /*!< bit: 22..25 Month Timestamp Value */ 797 uint32_t YEAR:6; /*!< bit: 26..31 Year Timestamp Value */ 798 } bit; /*!< Structure used for bit access */ 799 uint32_t reg; /*!< Type used for register access */ 800 } RTC_MODE2_TIMESTAMP_Type; 801 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 802 803 /* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */ 804 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 805 typedef union { 806 struct { 807 uint32_t TAMPID0:1; /*!< bit: 0 Tamper Input 0 Detected */ 808 uint32_t TAMPID1:1; /*!< bit: 1 Tamper Input 1 Detected */ 809 uint32_t TAMPID2:1; /*!< bit: 2 Tamper Input 2 Detected */ 810 uint32_t TAMPID3:1; /*!< bit: 3 Tamper Input 3 Detected */ 811 uint32_t TAMPID4:1; /*!< bit: 4 Tamper Input 4 Detected */ 812 uint32_t :26; /*!< bit: 5..30 Reserved */ 813 uint32_t TAMPEVT:1; /*!< bit: 31 Tamper Event Detected */ 814 } bit; /*!< Structure used for bit access */ 815 struct { 816 uint32_t TAMPID:5; /*!< bit: 0.. 4 Tamper Input x Detected */ 817 uint32_t :27; /*!< bit: 5..31 Reserved */ 818 } vec; /*!< Structure used for vec access */ 819 uint32_t reg; /*!< Type used for register access */ 820 } RTC_TAMPID_Type; 821 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 822 823 /* -------- RTC_BKUP : (RTC Offset: 0x80) (R/W 32) Backup -------- */ 824 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 825 typedef union { 826 struct { 827 uint32_t BKUP:32; /*!< bit: 0..31 Backup */ 828 } bit; /*!< Structure used for bit access */ 829 uint32_t reg; /*!< Type used for register access */ 830 } RTC_BKUP_Type; 831 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 832 833 /** \brief RtcMode2Alarm hardware registers */ 834 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 835 typedef struct { 836 __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ 837 __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ 838 RoReg8 Reserved1[0x3]; 839 } RtcMode2Alarm; 840 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 841 842 /** \brief RTC_MODE0 hardware registers */ 843 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 844 typedef struct { /* 32-bit Counter with Single 32-bit Compare */ 845 __IO RTC_MODE0_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */ 846 __IO RTC_MODE0_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE0 Control B */ 847 __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */ 848 __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */ 849 __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */ 850 __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */ 851 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ 852 RoReg8 Reserved1[0x1]; 853 __I RTC_MODE0_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE0 Synchronization Busy Status */ 854 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ 855 RoReg8 Reserved2[0x3]; 856 __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */ 857 RoReg8 Reserved3[0x4]; 858 __IO RTC_MODE0_COMP_Type COMP[2]; /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */ 859 RoReg8 Reserved4[0x18]; 860 __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ 861 RoReg8 Reserved5[0x10]; 862 __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */ 863 __I RTC_MODE0_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE0 Timestamp */ 864 __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */ 865 RoReg8 Reserved6[0x14]; 866 __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */ 867 } RtcMode0; 868 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 869 870 /** \brief RTC_MODE1 hardware registers */ 871 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 872 typedef struct { /* 16-bit Counter with Two 16-bit Compares */ 873 __IO RTC_MODE1_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */ 874 __IO RTC_MODE1_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE1 Control B */ 875 __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */ 876 __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */ 877 __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */ 878 __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */ 879 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ 880 RoReg8 Reserved1[0x1]; 881 __I RTC_MODE1_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status */ 882 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ 883 RoReg8 Reserved2[0x3]; 884 __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */ 885 RoReg8 Reserved3[0x2]; 886 __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */ 887 RoReg8 Reserved4[0x2]; 888 __IO RTC_MODE1_COMP_Type COMP[4]; /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */ 889 RoReg8 Reserved5[0x18]; 890 __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ 891 RoReg8 Reserved6[0x10]; 892 __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */ 893 __I RTC_MODE1_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE1 Timestamp */ 894 __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */ 895 RoReg8 Reserved7[0x14]; 896 __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */ 897 } RtcMode1; 898 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 899 900 /** \brief RTC_MODE2 hardware registers */ 901 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 902 typedef struct { /* Clock/Calendar with Alarm */ 903 __IO RTC_MODE2_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */ 904 __IO RTC_MODE2_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE2 Control B */ 905 __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */ 906 __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */ 907 __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */ 908 __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */ 909 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ 910 RoReg8 Reserved1[0x1]; 911 __I RTC_MODE2_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE2 Synchronization Busy Status */ 912 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ 913 RoReg8 Reserved2[0x3]; 914 __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */ 915 RoReg8 Reserved3[0x4]; 916 RtcMode2Alarm Mode2Alarm[2]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [NUM_OF_ALARMS] */ 917 RoReg8 Reserved4[0x10]; 918 __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ 919 RoReg8 Reserved5[0x10]; 920 __IO RTC_TAMPCTRL_Type TAMPCTRL; /**< \brief Offset: 0x60 (R/W 32) Tamper Control */ 921 __I RTC_MODE2_TIMESTAMP_Type TIMESTAMP; /**< \brief Offset: 0x64 (R/ 32) MODE2 Timestamp */ 922 __IO RTC_TAMPID_Type TAMPID; /**< \brief Offset: 0x68 (R/W 32) Tamper ID */ 923 RoReg8 Reserved6[0x14]; 924 __IO RTC_BKUP_Type BKUP[8]; /**< \brief Offset: 0x80 (R/W 32) Backup */ 925 } RtcMode2; 926 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 927 928 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 929 typedef union { 930 RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ 931 RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ 932 RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ 933 } Rtc; 934 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 935 936 #endif /* _MICROCHIP_PIC32CXSG_RTC_COMPONENT_FIXUP_H_ */ 937
