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Searched refs:SW_TRAING_BCLK_SCLK_OFFSET (Results 1 – 2 of 2) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr.h449 #if !defined (SW_TRAING_BCLK_SCLK_OFFSET)
450 #define SW_TRAING_BCLK_SCLK_OFFSET 0x00000000UL macro
Dmss_ddr.c1117 bclk_phase = ((bclk_answer+SW_TRAING_BCLK_SCLK_OFFSET) & 0x07UL ) << 8U; in ddr_setup()
1118 … bclk90_phase=((bclk_answer+SW_TRAING_BCLK_SCLK_OFFSET+2U) & 0x07UL ) << 11U; in ddr_setup()