1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_USB_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_USB_COMPONENT_FIXUP_H_ 9 10 /* -------- USB_DEVICE_ADDR : (USB Offset: 0x00) (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ 15 } bit; /*!< Structure used for bit access */ 16 uint32_t reg; /*!< Type used for register access */ 17 } USB_DEVICE_ADDR_Type; 18 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 19 20 /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x04) (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ 21 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 22 typedef union { 23 struct { 24 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ 25 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ 26 uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ 27 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ 28 } bit; /*!< Structure used for bit access */ 29 uint32_t reg; /*!< Type used for register access */ 30 } USB_DEVICE_PCKSIZE_Type; 31 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 32 33 /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x08) (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ 34 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 typedef union { 36 struct { 37 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ 38 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ 39 uint16_t :1; /*!< bit: 15 Reserved */ 40 } bit; /*!< Structure used for bit access */ 41 uint16_t reg; /*!< Type used for register access */ 42 } USB_DEVICE_EXTREG_Type; 43 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 44 45 /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x0A) (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ 46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 47 typedef union { 48 struct { 49 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ 50 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ 51 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 52 } bit; /*!< Structure used for bit access */ 53 uint8_t reg; /*!< Type used for register access */ 54 } USB_DEVICE_STATUS_BK_Type; 55 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 56 57 /* -------- USB_HOST_ADDR : (USB Offset: 0x00) (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ 58 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 59 typedef union { 60 struct { 61 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ 62 } bit; /*!< Structure used for bit access */ 63 uint32_t reg; /*!< Type used for register access */ 64 } USB_HOST_ADDR_Type; 65 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x04) (R/W 32) HOST_DESC_BANK Host Bank, Packet Size -------- */ 68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 69 typedef union { 70 struct { 71 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ 72 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ 73 uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ 74 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ 75 } bit; /*!< Structure used for bit access */ 76 uint32_t reg; /*!< Type used for register access */ 77 } USB_HOST_PCKSIZE_Type; 78 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 80 /* -------- USB_HOST_EXTREG : (USB Offset: 0x08) (R/W 16) HOST_DESC_BANK Host Bank, Extended -------- */ 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 82 typedef union { 83 struct { 84 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ 85 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ 86 uint16_t :1; /*!< bit: 15 Reserved */ 87 } bit; /*!< Structure used for bit access */ 88 uint16_t reg; /*!< Type used for register access */ 89 } USB_HOST_EXTREG_Type; 90 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x0A) (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank -------- */ 93 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 94 typedef union { 95 struct { 96 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ 97 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ 98 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 99 } bit; /*!< Structure used for bit access */ 100 uint8_t reg; /*!< Type used for register access */ 101 } USB_HOST_STATUS_BK_Type; 102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x0C) (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ 105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 106 typedef union { 107 struct { 108 uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ 109 uint16_t :1; /*!< bit: 7 Reserved */ 110 uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ 111 uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ 112 } bit; /*!< Structure used for bit access */ 113 uint16_t reg; /*!< Type used for register access */ 114 } USB_HOST_CTRL_PIPE_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x0E) (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ 118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 119 typedef union { 120 struct { 121 uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ 122 uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ 123 uint16_t PIDER:1; /*!< bit: 2 PID Error */ 124 uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ 125 uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ 126 uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ 127 uint16_t :8; /*!< bit: 8..15 Reserved */ 128 } bit; /*!< Structure used for bit access */ 129 uint16_t reg; /*!< Type used for register access */ 130 } USB_HOST_STATUS_PIPE_Type; 131 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 132 133 /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x00) (R/W 8) DEVICE_ENDPOINT End Point Configuration -------- */ 134 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 135 typedef union { 136 struct { 137 uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ 138 uint8_t :1; /*!< bit: 3 Reserved */ 139 uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ 140 uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ 141 } bit; /*!< Structure used for bit access */ 142 uint8_t reg; /*!< Type used for register access */ 143 } USB_DEVICE_EPCFG_Type; 144 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 145 146 /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x04) ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 148 typedef union { 149 struct { 150 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ 151 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ 152 uint8_t CURBK:1; /*!< bit: 2 Current Bank Clear */ 153 uint8_t :1; /*!< bit: 3 Reserved */ 154 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ 155 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ 156 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ 157 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ 158 } bit; /*!< Structure used for bit access */ 159 struct { 160 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 161 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ 162 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 163 } vec; /*!< Structure used for vec access */ 164 uint8_t reg; /*!< Type used for register access */ 165 } USB_DEVICE_EPSTATUSCLR_Type; 166 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 167 168 /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x05) ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set -------- */ 169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 170 typedef union { 171 struct { 172 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ 173 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ 174 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ 175 uint8_t :1; /*!< bit: 3 Reserved */ 176 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ 177 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ 178 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ 179 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ 180 } bit; /*!< Structure used for bit access */ 181 struct { 182 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 183 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ 184 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 185 } vec; /*!< Structure used for vec access */ 186 uint8_t reg; /*!< Type used for register access */ 187 } USB_DEVICE_EPSTATUSSET_Type; 188 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 189 190 /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x06) ( R/ 8) DEVICE_ENDPOINT End Point Pipe Status -------- */ 191 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 192 typedef union { 193 struct { 194 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ 195 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ 196 uint8_t CURBK:1; /*!< bit: 2 Current Bank */ 197 uint8_t :1; /*!< bit: 3 Reserved */ 198 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ 199 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ 200 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ 201 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ 202 } bit; /*!< Structure used for bit access */ 203 struct { 204 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 205 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ 206 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 207 } vec; /*!< Structure used for vec access */ 208 uint8_t reg; /*!< Type used for register access */ 209 } USB_DEVICE_EPSTATUS_Type; 210 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 211 212 /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x07) (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag -------- */ 213 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 214 typedef union { // __I to avoid read-modify-write on write-to-clear register 215 struct { 216 __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ 217 __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ 218 __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ 219 __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ 220 __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ 221 __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ 222 __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ 223 __I uint8_t :1; /*!< bit: 7 Reserved */ 224 } bit; /*!< Structure used for bit access */ 225 struct { 226 __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ 227 __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ 228 __I uint8_t :1; /*!< bit: 4 Reserved */ 229 __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ 230 __I uint8_t :1; /*!< bit: 7 Reserved */ 231 } vec; /*!< Structure used for vec access */ 232 uint8_t reg; /*!< Type used for register access */ 233 } USB_DEVICE_EPINTFLAG_Type; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x08) (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ 237 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 238 typedef union { 239 struct { 240 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ 241 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ 242 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ 243 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ 244 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ 245 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ 246 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ 247 uint8_t :1; /*!< bit: 7 Reserved */ 248 } bit; /*!< Structure used for bit access */ 249 struct { 250 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ 251 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ 252 uint8_t :1; /*!< bit: 4 Reserved */ 253 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ 254 uint8_t :1; /*!< bit: 7 Reserved */ 255 } vec; /*!< Structure used for vec access */ 256 uint8_t reg; /*!< Type used for register access */ 257 } USB_DEVICE_EPINTENCLR_Type; 258 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 259 260 /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x09) (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ 261 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 262 typedef union { 263 struct { 264 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ 265 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ 266 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ 267 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ 268 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ 269 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ 270 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ 271 uint8_t :1; /*!< bit: 7 Reserved */ 272 } bit; /*!< Structure used for bit access */ 273 struct { 274 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ 275 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ 276 uint8_t :1; /*!< bit: 4 Reserved */ 277 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ 278 uint8_t :1; /*!< bit: 7 Reserved */ 279 } vec; /*!< Structure used for vec access */ 280 uint8_t reg; /*!< Type used for register access */ 281 } USB_DEVICE_EPINTENSET_Type; 282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 283 284 /* -------- USB_HOST_PCFG : (USB Offset: 0x00) (R/W 8) HOST_PIPE End Point Configuration -------- */ 285 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 286 typedef union { 287 struct { 288 uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ 289 uint8_t BK:1; /*!< bit: 2 Pipe Bank */ 290 uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ 291 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 292 } bit; /*!< Structure used for bit access */ 293 uint8_t reg; /*!< Type used for register access */ 294 } USB_HOST_PCFG_Type; 295 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 296 297 /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x03) (R/W 8) HOST_PIPE Bus Access Period of Pipe -------- */ 298 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 299 typedef union { 300 struct { 301 uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ 302 } bit; /*!< Structure used for bit access */ 303 uint8_t reg; /*!< Type used for register access */ 304 } USB_HOST_BINTERVAL_Type; 305 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 306 307 /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x04) ( /W 8) HOST_PIPE End Point Pipe Status Clear -------- */ 308 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 309 typedef union { 310 struct { 311 uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ 312 uint8_t :1; /*!< bit: 1 Reserved */ 313 uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ 314 uint8_t :1; /*!< bit: 3 Reserved */ 315 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ 316 uint8_t :1; /*!< bit: 5 Reserved */ 317 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ 318 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ 319 } bit; /*!< Structure used for bit access */ 320 uint8_t reg; /*!< Type used for register access */ 321 } USB_HOST_PSTATUSCLR_Type; 322 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 323 324 /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x05) ( /W 8) HOST_PIPE End Point Pipe Status Set -------- */ 325 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 326 typedef union { 327 struct { 328 uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ 329 uint8_t :1; /*!< bit: 1 Reserved */ 330 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ 331 uint8_t :1; /*!< bit: 3 Reserved */ 332 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ 333 uint8_t :1; /*!< bit: 5 Reserved */ 334 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ 335 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ 336 } bit; /*!< Structure used for bit access */ 337 uint8_t reg; /*!< Type used for register access */ 338 } USB_HOST_PSTATUSSET_Type; 339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 340 /* -------- USB_HOST_PSTATUS : (USB Offset: 0x06) ( R/ 8) HOST_PIPE End Point Pipe Status -------- */ 341 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 342 typedef union { 343 struct { 344 uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ 345 uint8_t :1; /*!< bit: 1 Reserved */ 346 uint8_t CURBK:1; /*!< bit: 2 Current Bank */ 347 uint8_t :1; /*!< bit: 3 Reserved */ 348 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ 349 uint8_t :1; /*!< bit: 5 Reserved */ 350 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ 351 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ 352 } bit; /*!< Structure used for bit access */ 353 uint8_t reg; /*!< Type used for register access */ 354 } USB_HOST_PSTATUS_Type; 355 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 356 357 /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x07) (R/W 8) HOST_PIPE Pipe Interrupt Flag -------- */ 358 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 359 typedef union { // __I to avoid read-modify-write on write-to-clear register 360 struct { 361 __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ 362 __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ 363 __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ 364 __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ 365 __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ 366 __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ 367 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 368 } bit; /*!< Structure used for bit access */ 369 struct { 370 __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ 371 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 372 } vec; /*!< Structure used for vec access */ 373 uint8_t reg; /*!< Type used for register access */ 374 } USB_HOST_PINTFLAG_Type; 375 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 376 377 /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x08) (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear -------- */ 378 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 379 typedef union { 380 struct { 381 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ 382 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ 383 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ 384 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ 385 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ 386 uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ 387 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 388 } bit; /*!< Structure used for bit access */ 389 struct { 390 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ 391 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 392 } vec; /*!< Structure used for vec access */ 393 uint8_t reg; /*!< Type used for register access */ 394 } USB_HOST_PINTENCLR_Type; 395 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 396 397 /* -------- USB_HOST_PINTENSET : (USB Offset: 0x09) (R/W 8) HOST_PIPE Pipe Interrupt Flag Set -------- */ 398 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 399 typedef union { 400 struct { 401 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ 402 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ 403 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ 404 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ 405 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ 406 uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ 407 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 408 } bit; /*!< Structure used for bit access */ 409 struct { 410 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ 411 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 412 } vec; /*!< Structure used for vec access */ 413 uint8_t reg; /*!< Type used for register access */ 414 } USB_HOST_PINTENSET_Type; 415 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 416 417 /* -------- USB_CTRLA : (USB Offset: 0x00) (R/W 8) Control A -------- */ 418 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 419 typedef union { 420 struct { 421 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 422 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 423 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ 424 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 425 uint8_t MODE:1; /*!< bit: 7 Operating Mode */ 426 } bit; /*!< Structure used for bit access */ 427 uint8_t reg; /*!< Type used for register access */ 428 } USB_CTRLA_Type; 429 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 430 431 /* -------- USB_SYNCBUSY : (USB Offset: 0x02) ( R/ 8) Synchronization Busy -------- */ 432 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 433 typedef union { 434 struct { 435 uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 436 uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ 437 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 438 } bit; /*!< Structure used for bit access */ 439 uint8_t reg; /*!< Type used for register access */ 440 } USB_SYNCBUSY_Type; 441 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 442 443 /* -------- USB_QOSCTRL : (USB Offset: 0x03) (R/W 8) USB Quality Of Service -------- */ 444 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 445 typedef union { 446 struct { 447 uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ 448 uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ 449 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 450 } bit; /*!< Structure used for bit access */ 451 uint8_t reg; /*!< Type used for register access */ 452 } USB_QOSCTRL_Type; 453 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 454 455 /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x08) (R/W 16) DEVICE Control B -------- */ 456 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 457 typedef union { 458 struct { 459 uint16_t DETACH:1; /*!< bit: 0 Detach */ 460 uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ 461 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ 462 uint16_t NREPLY:1; /*!< bit: 4 No Reply */ 463 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ 464 uint16_t TSTK:1; /*!< bit: 6 Test mode K */ 465 uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ 466 uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ 467 uint16_t GNAK:1; /*!< bit: 9 Global NAK */ 468 uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ 469 uint16_t :4; /*!< bit: 12..15 Reserved */ 470 } bit; /*!< Structure used for bit access */ 471 uint16_t reg; /*!< Type used for register access */ 472 } USB_DEVICE_CTRLB_Type; 473 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 474 475 /* -------- USB_HOST_CTRLB : (USB Offset: 0x08) (R/W 16) HOST Control B -------- */ 476 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 477 typedef union { 478 struct { 479 uint16_t :1; /*!< bit: 0 Reserved */ 480 uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ 481 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ 482 uint16_t AUTORESUME:1; /*!< bit: 4 Auto Resume Enable */ 483 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ 484 uint16_t TSTK:1; /*!< bit: 6 Test mode K */ 485 uint16_t :1; /*!< bit: 7 Reserved */ 486 uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ 487 uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ 488 uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ 489 uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ 490 uint16_t :4; /*!< bit: 12..15 Reserved */ 491 } bit; /*!< Structure used for bit access */ 492 uint16_t reg; /*!< Type used for register access */ 493 } USB_HOST_CTRLB_Type; 494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 495 496 /* -------- USB_DEVICE_DADD : (USB Offset: 0x0A) (R/W 8) DEVICE Device Address -------- */ 497 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 498 typedef union { 499 struct { 500 uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ 501 uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ 502 } bit; /*!< Structure used for bit access */ 503 uint8_t reg; /*!< Type used for register access */ 504 } USB_DEVICE_DADD_Type; 505 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 506 507 /* -------- USB_HOST_HSOFC : (USB Offset: 0x0A) (R/W 8) HOST Host Start Of Frame Control -------- */ 508 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 509 typedef union { 510 struct { 511 uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ 512 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 513 uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ 514 } bit; /*!< Structure used for bit access */ 515 uint8_t reg; /*!< Type used for register access */ 516 } USB_HOST_HSOFC_Type; 517 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 518 519 /* -------- USB_DEVICE_STATUS : (USB Offset: 0x0C) ( R/ 8) DEVICE Status -------- */ 520 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 521 typedef union { 522 struct { 523 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 524 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ 525 uint8_t :2; /*!< bit: 4.. 5 Reserved */ 526 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ 527 } bit; /*!< Structure used for bit access */ 528 uint8_t reg; /*!< Type used for register access */ 529 } USB_DEVICE_STATUS_Type; 530 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 531 532 /* -------- USB_HOST_STATUS : (USB Offset: 0x0C) (R/W 8) HOST Status -------- */ 533 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 534 typedef union { 535 struct { 536 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 537 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ 538 uint8_t :2; /*!< bit: 4.. 5 Reserved */ 539 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ 540 } bit; /*!< Structure used for bit access */ 541 uint8_t reg; /*!< Type used for register access */ 542 } USB_HOST_STATUS_Type; 543 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 544 545 /* -------- USB_FSMSTATUS : (USB Offset: 0x0D) ( R/ 8) Finite State Machine Status -------- */ 546 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 547 typedef union { 548 struct { 549 uint8_t FSMSTATE:7; /*!< bit: 0.. 6 Fine State Machine Status */ 550 uint8_t :1; /*!< bit: 7 Reserved */ 551 } bit; /*!< Structure used for bit access */ 552 uint8_t reg; /*!< Type used for register access */ 553 } USB_FSMSTATUS_Type; 554 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 555 556 /* -------- USB_DEVICE_FNUM : (USB Offset: 0x10) ( R/ 16) DEVICE Device Frame Number -------- */ 557 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 558 typedef union { 559 struct { 560 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ 561 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ 562 uint16_t :1; /*!< bit: 14 Reserved */ 563 uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ 564 } bit; /*!< Structure used for bit access */ 565 uint16_t reg; /*!< Type used for register access */ 566 } USB_DEVICE_FNUM_Type; 567 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 568 569 /* -------- USB_HOST_FNUM : (USB Offset: 0x10) (R/W 16) HOST Host Frame Number -------- */ 570 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 571 typedef union { 572 struct { 573 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ 574 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ 575 uint16_t :2; /*!< bit: 14..15 Reserved */ 576 } bit; /*!< Structure used for bit access */ 577 uint16_t reg; /*!< Type used for register access */ 578 } USB_HOST_FNUM_Type; 579 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 580 581 /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x12) ( R/ 8) HOST Host Frame Length -------- */ 582 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 583 typedef union { 584 struct { 585 uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ 586 } bit; /*!< Structure used for bit access */ 587 uint8_t reg; /*!< Type used for register access */ 588 } USB_HOST_FLENHIGH_Type; 589 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 590 591 /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x14) (R/W 16) DEVICE Device Interrupt Enable Clear -------- */ 592 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 593 typedef union { 594 struct { 595 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ 596 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ 597 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ 598 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ 599 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ 600 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ 601 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ 602 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ 603 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ 604 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ 605 uint16_t :6; /*!< bit: 10..15 Reserved */ 606 } bit; /*!< Structure used for bit access */ 607 uint16_t reg; /*!< Type used for register access */ 608 } USB_DEVICE_INTENCLR_Type; 609 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 610 611 /* -------- USB_HOST_INTENCLR : (USB Offset: 0x14) (R/W 16) HOST Host Interrupt Enable Clear -------- */ 612 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 613 typedef union { 614 struct { 615 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 616 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ 617 uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ 618 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ 619 uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ 620 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ 621 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ 622 uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ 623 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ 624 uint16_t :6; /*!< bit: 10..15 Reserved */ 625 } bit; /*!< Structure used for bit access */ 626 uint16_t reg; /*!< Type used for register access */ 627 } USB_HOST_INTENCLR_Type; 628 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 629 630 /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x18) (R/W 16) DEVICE Device Interrupt Enable Set -------- */ 631 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 632 typedef union { 633 struct { 634 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ 635 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ 636 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ 637 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ 638 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ 639 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ 640 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ 641 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ 642 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ 643 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ 644 uint16_t :6; /*!< bit: 10..15 Reserved */ 645 } bit; /*!< Structure used for bit access */ 646 uint16_t reg; /*!< Type used for register access */ 647 } USB_DEVICE_INTENSET_Type; 648 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 649 650 /* -------- USB_HOST_INTENSET : (USB Offset: 0x18) (R/W 16) HOST Host Interrupt Enable Set -------- */ 651 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 652 typedef union { 653 struct { 654 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 655 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ 656 uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ 657 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ 658 uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ 659 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ 660 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ 661 uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ 662 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ 663 uint16_t :6; /*!< bit: 10..15 Reserved */ 664 } bit; /*!< Structure used for bit access */ 665 uint16_t reg; /*!< Type used for register access */ 666 } USB_HOST_INTENSET_Type; 667 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 668 669 /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x1C) (R/W 16) DEVICE Device Interrupt Flag -------- */ 670 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 671 typedef union { // __I to avoid read-modify-write on write-to-clear register 672 struct { 673 __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ 674 __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ 675 __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ 676 __I uint16_t EORST:1; /*!< bit: 3 End of Reset */ 677 __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ 678 __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ 679 __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ 680 __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ 681 __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ 682 __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ 683 __I uint16_t :6; /*!< bit: 10..15 Reserved */ 684 } bit; /*!< Structure used for bit access */ 685 uint16_t reg; /*!< Type used for register access */ 686 } USB_DEVICE_INTFLAG_Type; 687 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 688 689 /* -------- USB_HOST_INTFLAG : (USB Offset: 0x1C) (R/W 16) HOST Host Interrupt Flag -------- */ 690 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 691 typedef union { // __I to avoid read-modify-write on write-to-clear register 692 struct { 693 __I uint16_t :2; /*!< bit: 0.. 1 Reserved */ 694 __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ 695 __I uint16_t RST:1; /*!< bit: 3 Bus Reset */ 696 __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ 697 __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */ 698 __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ 699 __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ 700 __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */ 701 __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ 702 __I uint16_t :6; /*!< bit: 10..15 Reserved */ 703 } bit; /*!< Structure used for bit access */ 704 uint16_t reg; /*!< Type used for register access */ 705 } USB_HOST_INTFLAG_Type; 706 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 707 708 /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x20) ( R/ 16) DEVICE End Point Interrupt Summary -------- */ 709 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 710 typedef union { 711 struct { 712 uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ 713 uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ 714 uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ 715 uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ 716 uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ 717 uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ 718 uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ 719 uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ 720 uint16_t :8; /*!< bit: 8..15 Reserved */ 721 } bit; /*!< Structure used for bit access */ 722 struct { 723 uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ 724 uint16_t :8; /*!< bit: 8..15 Reserved */ 725 } vec; /*!< Structure used for vec access */ 726 uint16_t reg; /*!< Type used for register access */ 727 } USB_DEVICE_EPINTSMRY_Type; 728 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 729 730 /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x20) ( R/ 16) HOST Pipe Interrupt Summary -------- */ 731 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 732 typedef union { 733 struct { 734 uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ 735 uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ 736 uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ 737 uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ 738 uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ 739 uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ 740 uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ 741 uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ 742 uint16_t :8; /*!< bit: 8..15 Reserved */ 743 } bit; /*!< Structure used for bit access */ 744 struct { 745 uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ 746 uint16_t :8; /*!< bit: 8..15 Reserved */ 747 } vec; /*!< Structure used for vec access */ 748 uint16_t reg; /*!< Type used for register access */ 749 } USB_HOST_PINTSMRY_Type; 750 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 751 752 /* -------- USB_DESCADD : (USB Offset: 0x24) (R/W 32) Descriptor Address -------- */ 753 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 754 typedef union { 755 struct { 756 uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ 757 } bit; /*!< Structure used for bit access */ 758 uint32_t reg; /*!< Type used for register access */ 759 } USB_DESCADD_Type; 760 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 761 762 /* -------- USB_PADCAL : (USB Offset: 0x28) (R/W 16) USB PAD Calibration -------- */ 763 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 764 typedef union { 765 struct { 766 uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ 767 uint16_t :1; /*!< bit: 5 Reserved */ 768 uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ 769 uint16_t :1; /*!< bit: 11 Reserved */ 770 uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ 771 uint16_t :1; /*!< bit: 15 Reserved */ 772 } bit; /*!< Structure used for bit access */ 773 uint16_t reg; /*!< Type used for register access */ 774 } USB_PADCAL_Type; 775 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 776 777 /** \brief UsbDeviceDescBank SRAM registers */ 778 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 779 typedef struct { 780 __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ 781 __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ 782 __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ 783 __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ 784 RoReg8 Reserved1[0x5]; 785 } UsbDeviceDescBank; 786 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 787 788 /** \brief UsbHostDescBank SRAM registers */ 789 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 790 typedef struct { 791 __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ 792 __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ 793 __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ 794 __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ 795 RoReg8 Reserved1[0x1]; 796 __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ 797 __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ 798 } UsbHostDescBank; 799 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 800 801 /** \brief UsbDeviceEndpoint hardware registers */ 802 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 803 typedef struct { 804 __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ 805 RoReg8 Reserved1[0x3]; 806 __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ 807 __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ 808 __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ 809 __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ 810 __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ 811 __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ 812 RoReg8 Reserved2[0x16]; 813 } UsbDeviceEndpoint; 814 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 815 816 /** \brief UsbHostPipe hardware registers */ 817 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 818 typedef struct { 819 __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ 820 RoReg8 Reserved1[0x2]; 821 __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ 822 __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ 823 __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ 824 __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ 825 __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ 826 __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ 827 __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ 828 RoReg8 Reserved2[0x16]; 829 } UsbHostPipe; 830 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 831 832 /** \brief USB_DEVICE APB hardware registers */ 833 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 834 typedef struct { /* USB is Device */ 835 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ 836 RoReg8 Reserved1[0x1]; 837 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ 838 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ 839 RoReg8 Reserved2[0x4]; 840 __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ 841 __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ 842 RoReg8 Reserved3[0x1]; 843 __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ 844 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ 845 RoReg8 Reserved4[0x2]; 846 __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ 847 RoReg8 Reserved5[0x2]; 848 __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ 849 RoReg8 Reserved6[0x2]; 850 __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ 851 RoReg8 Reserved7[0x2]; 852 __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ 853 RoReg8 Reserved8[0x2]; 854 __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ 855 RoReg8 Reserved9[0x2]; 856 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ 857 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ 858 RoReg8 Reserved10[0xD6]; 859 UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ 860 } UsbDevice; 861 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 862 863 /** \brief USB_HOST hardware registers */ 864 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 865 typedef struct { /* USB is Host */ 866 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ 867 RoReg8 Reserved1[0x1]; 868 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ 869 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ 870 RoReg8 Reserved2[0x4]; 871 __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ 872 __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ 873 RoReg8 Reserved3[0x1]; 874 __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ 875 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ 876 RoReg8 Reserved4[0x2]; 877 __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ 878 __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ 879 RoReg8 Reserved5[0x1]; 880 __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ 881 RoReg8 Reserved6[0x2]; 882 __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ 883 RoReg8 Reserved7[0x2]; 884 __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ 885 RoReg8 Reserved8[0x2]; 886 __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ 887 RoReg8 Reserved9[0x2]; 888 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ 889 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ 890 RoReg8 Reserved10[0xD6]; 891 UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [PIPE_NUM*HOST_IMPLEMENTED] */ 892 } UsbHost; 893 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 894 895 /** \brief USB_DEVICE Descriptor SRAM registers */ 896 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 897 typedef struct { /* USB is Device */ 898 UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ 899 } UsbDeviceDescriptor; 900 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 901 902 /** \brief USB_HOST Descriptor SRAM registers */ 903 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 904 typedef struct { /* USB is Host */ 905 UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ 906 } UsbHostDescriptor; 907 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 908 909 #define SECTION_USB_DESCRIPTOR 910 911 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 912 typedef union { 913 UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ 914 UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ 915 } Usb; 916 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 917 918 #endif /* _MICROCHIP_PIC32CXSG_USB_COMPONENT_FIXUP_H_ */ 919
