1 /*******************************************************************************
2 * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Register definitions of the PolarFire SoC MSS eMMC SD.
7 *
8 */
9
10 #ifndef __MSS_MMC_REGS_H_
11 #define __MSS_MMC_REGS_H_
12
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
16
17 /* PolarFire SoC MSS eMMC/SD/SDIO Host Controller register set */
18 typedef struct {
19 volatile uint32_t HRS00;
20 volatile uint32_t HRS01;
21 volatile uint32_t HRS02;
22 volatile uint32_t HRS03;
23 volatile uint32_t HRS04;
24 volatile uint32_t HRS05;
25 volatile uint32_t HRS06;
26 volatile uint32_t HRS07;
27 volatile uint32_t RESERVED0[22u];
28 volatile uint32_t HRS30;
29 volatile uint32_t HRS31;
30 volatile uint32_t HRS32;
31 volatile uint32_t HRS33;
32 volatile uint32_t HRS34;
33 volatile uint32_t HRS35;
34 volatile uint32_t HRS36;
35 volatile uint32_t HRS37;
36 volatile uint32_t HRS38;
37 volatile uint32_t RESERVED1[20u];
38 volatile uint32_t HRS59;
39 volatile uint32_t RESERVED2[3u];
40 volatile uint32_t CRS63;
41 volatile uint32_t RESERVED3[64u];
42 volatile uint32_t SRS00;
43 volatile uint32_t SRS01;
44 volatile uint32_t SRS02;
45 volatile uint32_t SRS03;
46 volatile uint32_t SRS04;
47 volatile uint32_t SRS05;
48 volatile uint32_t SRS06;
49 volatile uint32_t SRS07;
50 volatile uint32_t SRS08;
51 volatile uint32_t SRS09;
52 volatile uint32_t SRS10;
53 volatile uint32_t SRS11;
54 volatile uint32_t SRS12;
55 volatile uint32_t SRS13;
56 volatile uint32_t SRS14;
57 volatile uint32_t SRS15;
58 volatile uint32_t SRS16;
59 volatile uint32_t SRS17;
60 volatile uint32_t SRS18;
61 volatile uint32_t SRS19;
62 volatile uint32_t SRS20;
63 volatile uint32_t SRS21;
64 volatile uint32_t SRS22;
65 volatile uint32_t SRS23;
66 volatile uint32_t SRS24;
67 volatile uint32_t SRS25;
68 volatile uint32_t SRS26;
69 volatile uint32_t SRS27;
70 volatile uint32_t RESERVED4[100u];
71 volatile uint32_t CQRS00;
72 volatile uint32_t CQRS01;
73 volatile uint32_t CQRS02;
74 volatile uint32_t CQRS03;
75 volatile uint32_t CQRS04;
76 volatile uint32_t CQRS05;
77 volatile uint32_t CQRS06;
78 volatile uint32_t CQRS07;
79 volatile uint32_t CQRS08;
80 volatile uint32_t CQRS09;
81 volatile uint32_t CQRS10;
82 volatile uint32_t CQRS11;
83 volatile uint32_t CQRS12;
84 volatile uint32_t CQRS13;
85 volatile uint32_t CQRS14;
86 volatile uint32_t RESERVED5;
87 volatile uint32_t CQRS16;
88 volatile uint32_t CQRS17;
89 volatile uint32_t CQRS18;
90 volatile uint32_t RESERVED6;
91 volatile uint32_t CQRS20;
92 volatile uint32_t CQRS21;
93 volatile uint32_t CQRS22;
94 volatile uint32_t CQRS23;
95 }MMC_TypeDef;
96
97 #define MMC_BASE 0x20008000u
98 #define MMC ((MMC_TypeDef *) MMC_BASE)
99
100 /*-----------------------------------------------------------------------------
101 @name (HRS6) - masks and macros
102 ------------------------------------------------------------------------------
103 */
104 #define HRS6_EMMC_MODE_MASK 0x00000007u
105 #define HRS6_EMMC_MODE_SDCARD (0x0u << 0)
106 #define HRS6_EMMC_MODE_SDR (0x2u << 0)
107 #define HRS6_EMMC_MODE_DDR (0x3u << 0)
108 #define HRS6_EMMC_MODE_HS200 (0x4u << 0)
109 #define HRS6_EMMC_MODE_HS400 (0x5u << 0)
110 #define HRS6_EMMC_MODE_HS400_ES (0x6u << 0)
111 #define HRS6_EMMC_MODE_LEGACY (0x7u << 0)
112 #define HRS6_EMMC_TUNE_VALUE_MASK 0x00003F00u
113 #define HRS6_EMMC_TUNE_REQUEST 0x00008000u
114
115 /*-----------------------------------------------------------------------------
116 @name Block count and size register (SRS01) - masks
117 ------------------------------------------------------------------------------
118 */
119 /* Block count for current transfer mask */
120 #define SRS1_BLOCK_COUNT 0xFFFF0000u
121 /* DMA buffer size 4kB */
122 #define SRS1_DMA_BUFF_SIZE_4KB 0x00000000u
123 /* DMA buffer size 8kB */
124 #define SRS1_DMA_BUFF_SIZE_8KB 0x00001000u
125 /* DMA buffer size 16kB */
126 #define SRS1_DMA_BUFF_SIZE_16KB 0x00002000u
127 /* DMA buffer size 32kB */
128 #define SRS1_DMA_BUFF_SIZE_32KB 0x00003000u
129 /* DMA buffer size 64kB */
130 #define SRS1_DMA_BUFF_SIZE_64KB 0x00004000u
131 /* DMA buffer size 128kB */
132 #define SRS1_DMA_BUFF_SIZE_128KB 0x00005000u
133 /* DMA buffer size 265kB */
134 #define SRS1_DMA_BUFF_SIZE_256KB 0x00006000u
135 /* DMA buffer size 512kB */
136 #define SRS1_DMA_BUFF_SIZE_512KB 0x00007000u
137 /* DMA buffer size mask */
138 #define SRS1_DMA_BUFF_SIZE_MASK 0x00007000u
139 /* Transfer block size mask */
140 #define SRS1_BLOCK_SIZE 0x00000FFFu
141
142 /*-----------------------------------------------------------------------------
143 @name Transfer mode and command information register (SRS3) - masks
144 ------------------------------------------------------------------------------
145 */
146 /* command type */
147 /* Abort CMD12, CMD52 for writing "I/O Abort" in CCCR */
148 #define SRS3_ABORT_CMD (0x3u << 22)
149 /* Resume CMD52 for writing "Function Select" in CCCR */
150 #define SRS3_RESUME_CMD (0x2u << 22)
151 /*Suspend CMD52 for writing "Bus Suspend" in CCCR */
152 #define SRS3_SUSPEND_CMD (0x1u << 22)
153 /* data is present and will be transferred using the DAT line */
154 #define SRS3_DATA_PRESENT 0x00200000u
155 /* index check enable */
156 #define SRS3_INDEX_CHECK_EN 0x00100000u
157 /* response CRC check enable */
158 #define SRS3_CRC_CHECK_EN 0x00080000u
159 /* response type */
160 /* response type - no response */
161 #define SRS3_NO_RESPONSE (0x0u << 16)
162 /* response type - response length 136 */
163 #define SRS3_RESP_LENGTH_136 (0x1u << 16)
164 /* response type - response length 48 */
165 #define SRS3_RESP_LENGTH_48 (0x2u << 16)
166 /* response type - response length 48 and check Busy after response */
167 #define SRS3_RESP_LENGTH_48B (0x3u << 16)
168 /* RID - Response Interrupt Disable
169 When set to 1, the Command Complete Interrupt (SRS12.CC)
170 will be disabled */
171 #define SRS3_RESP_INTER_DISABLE 0x00000100u
172 /* RECE - Response Error Check Enable.
173 When set 1, the host will look after R1/R5 responses. */
174 #define SRS3_RESP_ERR_CHECK_EN 0x00000080u
175 /* Response type
176 Response type R1 for the response content checker */
177 #define SRS3_RESPONSE_CHECK_TYPE_R1 (0x0u << 6)
178 /* Response type R5 for the response content checker */
179 #define SRS3_RESPONSE_CHECK_TYPE_R5 (0x1u << 6)
180 /* multi block DAT line data transfers */
181 #define SRS3_MULTI_BLOCK_SEL 0x00000020u
182 /* Data Transfer Direction Select */
183 /* data transfer direction - write */
184 #define SRS3_TRANS_DIRECT_WRITE (0x0u << 4)
185 /* data transfer direction - read */
186 #define SRS3_TRANS_DIRECT_READ (0x1u << 4)
187 /* Auto CMD Enable */
188 /* Auto CMD23 enable */
189 #define SRS3_AUTOCMD23_ENABLE (0x2u << 2)
190 /* Auto CMD12 enable */
191 #define SRS3_AUTOCMD12_ENABLE (0x1u << 2)
192 /* Block count enable */
193 #define SRS3_BLOCK_COUNT_ENABLE 0x00000002u
194 /* DMA enable */
195 #define SRS3_DMA_ENABLE 0x00000001u
196
197 /*-----------------------------------------------------------------------------
198 @name Present state register masks (SRS9) - masks
199 ------------------------------------------------------------------------------
200 */
201 /* U2DET - STB.L Detection (UHS-II only)
202 * Field used when UHS-II interface is enabled (U2IE=1)
203 * and SD clock is supplied (SDCE=1) */
204 #define SRS9_STBL_DETECTION 0x80000000u
205 /* U2SYN Lane Synchronization (UHS-II only)
206 * After STB.L Detection set 1,
207 * this bit is set when SYN LLS is received on D1 lan*/
208 #define SRS9_LANE_SYNCHRONIZATION 0x40000000u
209 /* U2DOR - In Dormant State (UHS-II only) */
210 #define SRS9_IN_DORMANT_STATE 0x20000000u
211 /* CMD line signal level */
212 #define SRS9_CMD_SIGNAL_LEVEL 0x01000000u
213 /* DAT[3:0] Line Signal Level */
214 /* DAT3 signal level */
215 #define SRS9_DAT3_SIGNAL_LEVEL (0x1u << 23)
216 /* DAT2 signal level */
217 #define SRS9_DAT2_SIGNAL_LEVEL (0x1u << 22)
218 /* DAT1 signal level */
219 #define SRS9_DAT1_SIGNAL_LEVEL (0x1u << 21)
220 /* DAT0 signal level */
221 #define SRS9_DAT0_SIGNAL_LEVEL (0x1u << 20)
222 /* Write protect switch pin level */
223 #define SRS9_WP_SWITCH_LEVEL 0x00080000u
224 /* Card detect pin level */
225 #define SRS9_CARD_DETECT_LEVEL 0x00040000u
226 /* Card state stable */
227 #define SRS9_CARD_STATE_STABLE 0x00020000u
228 /* Card inserted */
229 #define SRS9_CARD_INSERTED 0x00010000u
230 /* Buffer read enable */
231 #define SRS9_BUFF_READ_EN 0x00000800u
232 /* Buffer write enable */
233 #define SRS9_BUFF_WRITE_EN 0x00000400u
234 /* Read transfer active */
235 #define SRS9_READ_TRANS_ACTIVE 0x00000200u
236 /* Write transfer active */
237 #define SRS9_WRITE_TRANS_ACTIVE 0x00000100u
238 /* DAT[7:4] Line Signal Level */
239 /* DAT7 Line Signal Level l (SD Mode only) */
240 #define SRS9_WRITE_DAT7_PIN_LEVEL (0x1u << 7)
241 /* DAT6 Line Signal Level l (SD Mode only) */
242 #define SRS9_WRITE_DAT6_PIN_LEVEL (0x1u << 6)
243 /* DAT5 Line Signal Level l (SD Mode only) */
244 #define SRS9_WRITE_DAT5_PIN_LEVEL (0x1u << 5)
245 /* DAT4 Line Signal Level l (SD Mode only) */
246 #define SRS9_WRITE_DAT4_PIN_LEVEL (0x1u << 4)
247 /* The signal will be used by the SD driver to rerun the
248 DAT line active */
249 #define SRS9_DAT_LINE_ACTIVE 0x00000004u
250 /* Command Inhibit (DAT) */
251 #define SRS9_CMD_INHIBIT_DAT 0x00000002u
252 /* Command Inhibit (CMD) */
253 #define SRS9_CMD_INHIBIT_CMD 0x00000001u
254
255
256 /*-----------------------------------------------------------------------------
257 @name SRS10
258 ------------------------------------------------------------------------------
259 */
260 /* SD Bus Voltage Select */
261 /* SD bus voltage - 3.3V */
262 #define SRS10_SET_3_3V_BUS_VOLTAGE (0x7u << 9)
263 /* SD bus voltage - 3.0V */
264 #define SRS10_SET_3_0V_BUS_VOLTAGE (0x6u << 9)
265 /* SD bus voltage - 1.8V */
266 #define SRS10_SET_1_8V_BUS_VOLTAGE (0x5u << 9)
267 /* SD bus voltage mask */
268 #define SRS10_BUS_VOLTAGE_MASK (0x7u << 9)
269 /* SD bus power. The SD device is powered. */
270 #define SRS10_SD_BUS_POWER 0x00000100u
271 /* select SDMA mode */
272 #define SRS10_DMA_SELECT_SDMA (0x0u << 3)
273 /* select ADMA1 mode */
274 #define SRS10_DMA_SELECT_ADMA1 (0x1u << 3)
275 /* select ADMA2 mode */
276 #define SRS10_DMA_SELECT_ADMA2 (0x2u << 3)
277 /* DMA mode selection mask */
278 #define SRS10_DMA_SELECT_MASK (0x3u << 3)
279 /* Set 4 bit data transfer width */
280 #define SRS10_DATA_WIDTH_4BIT 0x00000002u
281 /* Extended Data Transfer Width */
282 #define SRS10_EXTENDED_DATA_TRANSFER_WIDTH 0x00000020u
283 /* High speed enable. */
284 #define SRS10_HIGH_SPEED_ENABLE 0x00000004u
285 /* Turning on the LED.*/
286 #define SRS10_TURN_ON_LED 0x00000001u
287 /*-----------------------------------------------------------------------------
288 @name SRS11
289 ------------------------------------------------------------------------------
290 */
291 /* Data timeout mask */
292 #define SRS11_TIMEOUT_MASK (0xFu << 16)
293 /* SD clock enable */
294 #define SRS11_SD_CLOCK_ENABLE 0x00000004u
295 /* SDCLK Frequency mask */
296 #define SRS11_SEL_FREQ_BASE_MASK (0x0000FF00u | 0x000000C0u)
297 /*The SDCLK Frequency Divider method can be selected by this field */
298 #define SRS11_CLOCK_GENERATOR_SELECT (0x1u << 5)
299 /* Internal clock stable */
300 #define SRS11_INT_CLOCK_STABLE 0x00000002u
301 /* internal clock enable */
302 #define SRS11_INT_CLOCK_ENABLE 0x00000001u
303
304 /*-----------------------------------------------------------------------------
305 @name Interrupt status register (SRS12) - masks
306 ------------------------------------------------------------------------------
307 */
308 /* ERSP - Response Error (SD Mode only) */
309 #define SRS12_RESPONSE_ERROR 0x08000000u
310 /* Tuning error */
311 /*#define SRS12_TUNING_ERROR 0x04000000u*/
312 /* ADMA error */
313 #define SRS12_ADMA_ERROR 0x02000000u
314 /* Auto CMD (CMD12 or CMD23) error */
315 #define SRS12_AUTO_CMD_ERROR 0x01000000u
316 /* Current limit error host controller is not supplying power to SD card
317 due some failure. */
318 #define SRS12_CURRENT_LIMIT_ERROR 0x00800000u
319 /* Data end bit error */
320 #define SRS12_DATA_END_BIT_ERROR 0x00400000u
321 /* Data CRC error */
322 #define SRS12_DATA_CRC_ERROR 0x00200000u
323 /* Data timeout error */
324 #define SRS12_DATA_TIMEOUT_ERROR 0x00100000u
325 /* Command index error. Index error occurs in the command response. */
326 #define SRS12_COMMAND_INDEX_ERROR 0x00080000u
327 /* Command end bit error */
328 #define SRS12_COMMAND_END_BIT_ERROR 0x00040000u
329 /* Command CRC error */
330 #define SRS12_COMMAND_CRC_ERROR 0x00020000u
331 /* Command timeout error */
332 #define SRS12_COMMAND_TIMEOUT_ERROR 0x00010000u
333 /* Error interrupt */
334 #define SRS12_ERROR_INTERRUPT 0x00008000u
335 /* Command Queuing - interrupt */
336 #define SRS12_CMD_QUEUING_INT 0x00004000u
337 /* Re-Tuning Event */
338 /*#define SRS12_RETUNING_EVENT 0x00001000u
339 /* Interrupt on line C */
340 #define SRS12_INTERRUPT_ON_LINE_C 0x00000800u
341 /* Interrupt on line B */
342 #define SRS12_INTERRUPT_ON_LINE_B 0x00000400u
343 /* Interrupt on line A */
344 #define SRS12_INTERRUPT_ON_LINE_A 0x00000200u*/
345 /* Card interrupt */
346 #define SRS12_CARD_INTERRUPT 0x00000100u
347 /* Card removal */
348 #define SRS12_CARD_REMOVAL 0x00000080u
349 /* Card insertion */
350 #define SRS12_CARD_INSERTION 0x00000040u
351 /* Buffer read ready. Host is ready to read the buffer. */
352 #define SRS12_BUFFER_READ_READY 0x00000020u
353 /* Buffer write ready. Host is ready for writing data to the buffer.*/
354 #define SRS12_BUFFER_WRITE_READY 0x00000010u
355 /* DMA interrupt */
356 #define SRS12_DMA_INTERRUPT 0x00000008u
357 /* Block gap event */
358 #define SRS12_BLOCK_GAP_EVENT 0x00000004u
359 /* Transfer complete */
360 #define SRS12_TRANSFER_COMPLETE 0x00000002u
361 /* Command complete */
362 #define SRS12_COMMAND_COMPLETE 0x00000001u
363 /* normal interrupt status mask */
364 #define SRS12_NORMAL_STAUS_MASK (0xFFFFu)
365 #define SRS12_ERROR_STATUS_MASK (0xFFFF8000u)
366 #define SRS12_ERROR_CMD_LINE (SRS12_COMMAND_TIMEOUT_ERROR \
367 | SRS12_COMMAND_CRC_ERROR \
368 | SRS12_COMMAND_END_BIT_ERROR \
369 | SRS12_COMMAND_INDEX_ERROR)
370
371 /*-----------------------------------------------------------------------------
372 @name Interrupt status enable register (SRS13) - masks
373 ------------------------------------------------------------------------------
374 */
375 /** ERSP_SE - Response Error Status Enable */
376 #define SRS13_RESPONSE_ERROR_STAT_EN 0x08000000u
377 /* Tuning error status enable */
378 #define SRS13_TUNING_ERROR_STAT_EN (0x1u << 26)
379 /* ADMA error status enable */
380 #define SRS13_ADMA_ERROR_STAT_EN 0x02000000u
381 /* Auto CMD12 error status enable */
382 #define SRS13_AUTO_CMD12_ERR_STAT_EN 0x01000000u
383 /* Current limit error status enable */
384 #define SRS13_CURRENT_LIMIT_ERR_STAT_EN 0x00800000u
385 /* Data end bit error status enable */
386 #define SRS13_DATA_END_BIT_ERR_STAT_EN 0x00400000u
387 /* Data CRC error status enable */
388 #define SRS13_DATA_CRC_ERR_STAT_EN 0x00200000u
389 /* Data timeout error status enable */
390 #define SRS13_DATA_TIMEOUT_ERR_STAT_EN 0x00100000u
391 /* Command index error status enable */
392 #define SRS13_COMMAND_INDEX_ERR_STAT_EN 0x00080000u
393 /* Command end bit error status enable */
394 #define SRS13_COMMAND_END_BIT_ERR_STAT_EN 0x00040000u
395 /* Command CRC error status enable */
396 #define SRS13_COMMAND_CRC_ERR_STAT_EN 0x00020000u
397 /* Command timeout error status enable */
398 #define SRS13_COMMAND_TIMEOUT_ERR_STAT_EN 0x00010000u
399 /* Command Queuing Status Enable */
400 #define SRS13_CMD_QUEUING_STAT_EN 0x00004000u
401 /* Re-Tuning Event status enable */
402 #define SRS13_RETUNING_EVENT_STAT_EN (0x1u << 12)
403 /*Interrupt on line C status enable */
404 #define SRS13_INTERRUPT_ON_LINE_C_STAT_EN (0x1u << 11)
405 /* Interrupt on line B status enable */
406 #define SRS13_INTERRUPT_ON_LINE_B_STAT_EN (0x1u << 10)
407 /* Interrupt on line A status enable */
408 #define SRS13_INTERRUPT_ON_LINE_A_STAT_EN (0x1u << 9)
409 /* Card interrupt status enable */
410 #define SRS13_CARD_INTERRUPT_STAT_EN 0x00000100u
411 /* Card removal status enable */
412 #define SRS13_CARD_REMOVAL_STAT_EN 0x00000080u
413 /* Card insertion status enable */
414 #define SRS13_CARD_INERTION_STAT_EN 0x00000040u
415 /* Buffer read ready status enable */
416 #define SRS13_BUF_READ_READY_STAT_EN 0x00000020u
417 /* Buffer write ready status enable */
418 #define SRS13_BUF_WRITE_READY_STAT_EN 0x00000010u
419 /* DMA interrupt status enable */
420 #define SRS13_DMA_INTERRUPT_STAT_EN 0x00000008u
421 /* Block gap event status enable */
422 #define SRS13_BLOCK_GAP_EVENT_STAT_EN 0x00000004u
423 /* Transfer complete status enable */
424 #define SRS13_TRANSFER_COMPLETE_STAT_EN 0x00000002u
425 /* Command complete status enable */
426 #define SRS13_COMMAND_COMPLETE_STAT_EN 0x00000001u
427
428 /*-----------------------------------------------------------------------------
429 @name Interrupt signal enable register (SRS14) - masks
430 ------------------------------------------------------------------------------
431 */
432 /* Response error interrupt signdla enable */
433 #define SRS14_RESPONSE_ERROR_SIG_EN 0x08000000u
434 /* Tuning error signal enable */
435 #define SRS14_TUNING_ERROR_SIG_EN 0x04000000u
436 /* ADMA error signal enable */
437 #define SRS14_ADMA_ERROR_SIG_EN 0x02000000u
438 /* Auto CMD12 error signal enable */
439 #define SRS14_AUTO_CMD12_ERR_SIG_EN 0x01000000u
440 /* Current limit error signal enable */
441 #define SRS14_CURRENT_LIMIT_ERR_SIG_EN 0x00800000u
442 /* Data end bit error signal enable */
443 #define SRS14_DATA_END_BIT_ERR_SIG_EN 0x00400000u
444 /* Data CRC error signal enable */
445 #define SRS14_DATA_CRC_ERR_SIG_EN 0x00200000u
446 /* Data timeout error signal enable */
447 #define SRS14_DATA_TIMEOUT_ERR_SIG_EN 0x00100000u
448 /* Command index error signal enable */
449 #define SRS14_COMMAND_INDEX_ERR_SIG_EN 0x00080000u
450 /* Command end bit error signal enable */
451 #define SRS14_COMMAND_END_BIT_ERR_SIG_EN 0x00040000u
452 /* Command CRC error signal enable */
453 #define SRS14_COMMAND_CRC_ERR_SIG_EN 0x00020000u
454 /* Command timeout error signal enable */
455 #define SRS14_COMMAND_TIMEOUT_ERR_SIG_EN 0x00010000u
456 /* Command Queuing - interrupt enable */
457 #define SRS14_CMD_QUEUING_SIG_EN 0x00004000u
458 /* SD4HC__SRS__SRS14__RSVD_0_MASK 0x00003E00u */
459 /* Re-Tuning Event signal enable */
460 #define SRS14_RETUNING_EVENT_SIG_EN (0x1u << 12)
461 /*Interrupt on line C signal enable */
462 #define SRS14_INTERRUPT_ON_LINE_C_SIG_EN (0x1u << 11)
463 /* Interrupt on line B signal enable */
464 #define SRS14_INTERRUPT_ON_LINE_B_SIG_EN (0x1u << 10)
465 /* Interrupt on line A signal enable */
466 #define SRS14_INTERRUPT_ON_LINE_A_SIG_EN (0x1u << 9)
467 /* Card interrupt signal enable */
468 #define SRS14_CARD_INTERRUPT_SIG_EN 0x00000100u
469 /* Card removal signal enable */
470 #define SRS14_CARD_REMOVAL_SIG_EN 0x00000080u
471 /* Card insertion signal enable */
472 #define SRS14_CARD_INERTION_SIG_EN 0x00000040u
473 /* Buffer read ready signal enable */
474 #define SRS14_BUFFER_READ_READY_SIG_EN 0x00000020u
475 /* Buffer write ready signal enable */
476 #define SRS14_BUFFER_WRITE_READY_SIG_EN 0x00000010u
477 /* DMA interrupt signal enable */
478 #define SRS14_DMA_INTERRUPT_SIG_EN 0x00000008u
479 /* Block gap event signal enable */
480 #define SRS14_BLOCK_GAP_EVENT_SIG_EN 0x00000004u
481 /* Transfer complete signal enable */
482 #define SRS14_TRANSFER_COMPLETE_SIG_EN 0x00000002u
483 /* Command complete signal enable */
484 #define SRS14_COMMAND_COMPLETE_SIG_EN 0x00000001u
485
486 /*-----------------------------------------------------------------------------
487 @name AutoCMD12 Error Status Register/Host Control Register (SRR15) - masks
488 ------------------------------------------------------------------------------
489 */
490 /* Preset Value Enable */
491 #define SRS15_PRESET_VALUE_ENABLE 0x80000000u
492 /* Asynchronous Interrupt Enable */
493 #define SRS15_ASYNCHRONOUS_INT_EN (0x1u << 30)
494 /* 64-bit Addressing Specifies the addressing mode for DMA ending. */
495 #define SRS15_64_BIT_ADDRESSING 0x20000000u
496 /* Host Version 4.00 Enable
497 * Selects backward (SD Host 3.00 Version) compatibility mode
498 * or SD Host 4.00 Version mode
499 */
500 #define SRS15_HOST_4_ENABLE 0x10000000u
501 /* UHS-II Interface Enable */
502 #define SRS15_UHSII_ENABLE 0x01000000u
503 /* Sampling Clock Select */
504 #define SRS15_SAMPLING_CLOCK_SELECT 0x00800000u
505 /* Execute Tuning */
506 #define SRS15_EXECUTE_TUNING 0x00400000u
507
508 /* Driver Strength Select mask */
509 #define SRS15_DRIVER_TYPE_MASK (0x3u << 20)
510 /* Driver Strength Select type D */
511 #define SRS15_DRIVER_TYPE_D (0x3u << 20)
512 /* Driver Strength Select type C */
513 #define SRS15_DRIVER_TYPE_C (0x2u << 20)
514 /* Driver Strength Select type A */
515 #define SRS15_DRIVER_TYPE_A (0x1u << 20)
516 /* Driver Strength Select type B */
517 #define SRS15_DRIVER_TYPE_B (0x0u << 20)
518 /* This bit is to switch I/O signaling voltage level on */
519 /* the SD interface between 3.3V and 1.8V */
520 #define SRS15_18V_ENABLE 0x00080000u
521 /* UHS mode select mask */
522 #define SRS15_UHS_MODE_MASK (0x7u << 16)
523 /* UHS-II mode select */
524 #define SRS15_UHS_MODE_UHSII (0x7u << 16)
525 /* DDR50 mode select */
526 #define SRS15_UHS_MODE_DDR50 (0x4u << 16)
527 /* SDR104 mode select */
528 #define SRS15_UHS_MODE_SDR104 (0x3u << 16)
529 /* SDR50 mode select */
530 #define SRS15_UHS_MODE_SDR50 (0x2u << 16)
531 /* SDR25 mode select */
532 #define SRS15_UHS_MODE_SDR25 (0x1u << 16)
533 /* SDR12 mode select */
534 #define SRS15_UHS_MODE_SDR12 (0x0u << 16)
535 /* Command not issued bu auto CMD12 error */
536 #define SRS15_CMD_NOT_ISSUED_ERR 0x00000080u
537 /* Auto CMD12 index error */
538 #define SRS15_AUTO_CMD12_INDEX_ERR 0x00000010u
539 /* Auto CMD12 end bit error */
540 #define SRS15_AUTO_CMD12_END_BIT_ERR 0x00000008u
541 /* Auto CMD12 CRC error */
542 #define SRS15_AUTO_CMD12_CRC_ERR 0x00000004u
543 /* Auto CMD12 timeout error */
544 #define SRS15_AUTO_CMD12_TIMEOUT_ERR 0x00000002u
545 /* Autp CMD12 not executed */
546 #define SRS15_AUTO_CMD12_NOT_EXECUTED 0x00000001u
547
548 /*-----------------------------------------------------------------------------
549 @name SRS16
550 ------------------------------------------------------------------------------
551 */
552 #define SRS16_64BIT_SUPPORT 0x10000000u
553 /* 512 is the maximum block size that can be written */
554 /* to the buffer in the Host Controller. */
555 #define SRS16_MAX_BLOCK_LENGTH_512 (0x0u << 16)
556 /* 1024 is the maximum block size that can be written */
557 /* to the buffer in the Host Controller. */
558 #define SRS16_MAX_BLOCK_LENGTH_1024 (0x1u << 16)
559 /* 2048 is the maximum block size that can be written to*/
560 /* the buffer in the Host Controller. */
561 #define SRS16_MAX_BLOCK_LENGTH_2048 (0x2u << 16)
562 /* timeout unit clock is MHz*/
563 #define SRS16_TIMEOUT_CLOCK_UNIT_MHZ 0x00000080u
564 /* 64-bit System Bus Support */
565 #define SRS16_64BIT_SUPPORT 0x10000000u
566 /* Voltage 1.8V is supported */
567 #define SRS16_VOLTAGE_1_8V_SUPPORT 0x04000000u
568 /* Voltage 3.0V is supported */
569 #define SRS16_VOLTAGE_3_0V_SUPPORT 0x02000000u
570 /* Voltage 3.3V is supported */
571 #define SRS16_VOLTAGE_3_3V_SUPPORT 0x01000000u
572
573 #define SRS13_STATUS_EN (SRS13_TUNING_ERROR_STAT_EN \
574 | SRS13_ADMA_ERROR_STAT_EN \
575 | SRS13_AUTO_CMD12_ERR_STAT_EN \
576 | SRS13_CURRENT_LIMIT_ERR_STAT_EN \
577 | SRS13_DATA_END_BIT_ERR_STAT_EN \
578 | SRS13_DATA_CRC_ERR_STAT_EN \
579 | SRS13_DATA_TIMEOUT_ERR_STAT_EN \
580 | SRS13_COMMAND_INDEX_ERR_STAT_EN \
581 | SRS13_COMMAND_END_BIT_ERR_STAT_EN \
582 | SRS13_COMMAND_CRC_ERR_STAT_EN \
583 | SRS13_COMMAND_TIMEOUT_ERR_STAT_EN \
584 | SRS13_RETUNING_EVENT_STAT_EN \
585 | SRS13_INTERRUPT_ON_LINE_A_STAT_EN \
586 | SRS13_INTERRUPT_ON_LINE_B_STAT_EN \
587 | SRS13_INTERRUPT_ON_LINE_C_STAT_EN \
588 | SRS13_CARD_REMOVAL_STAT_EN \
589 | SRS13_CARD_INERTION_STAT_EN \
590 | SRS13_BUF_READ_READY_STAT_EN \
591 | SRS13_BUF_WRITE_READY_STAT_EN \
592 | SRS13_DMA_INTERRUPT_STAT_EN \
593 | SRS13_BLOCK_GAP_EVENT_STAT_EN \
594 | SRS13_TRANSFER_COMPLETE_STAT_EN \
595 | SRS13_COMMAND_COMPLETE_STAT_EN \
596 | SRS13_RESPONSE_ERROR_STAT_EN \
597 | SRS13_CMD_QUEUING_STAT_EN)
598
599 /*-----------------------------------------------------------------------------
600 @name Capabilities Register #2 Fields (SRS17) - masks
601 ------------------------------------------------------------------------------
602 */
603 /* VDD2 Supported */
604 #define SRS17_VDD2_ENABLED 0x10000000u
605 /* Macro gets value of clock multiplier */
SRS17_GET_CLOCK_MULTIPLIER(const uint32_t val)606 static inline uint32_t SRS17_GET_CLOCK_MULTIPLIER(const uint32_t val)
607 {
608 return ((val & 0x00FF0000u) >> 16u);
609 }
610 /* Re-Tuning Modes SD4HC__SRS__SRS17__RTNGM_MASK */
611 /* Re-Tuning Modes - mode 3 */
612 #define SRS17_RETUNING_MODE_3 (0x2u << 14)
613 /* Re-Tuning Modes - mode 2 */
614 #define SRS17_RETUNING_MODE_2 (0x1u << 14)
615 /* Re-Tuning Modes - mode 1 */
616 #define SRS17_RETUNING_MODE_1 (0x0u << 14)
617 /* tuning operation is necessary in SDR50 mode */
618 #define SRS17_USE_TUNING_SDR50 0x00002000u
619 /* It gest value of timer Count for Re-Tuning, */
SRS17_GET_RETUNING_TIMER_COUNT(const uint32_t val)620 static inline uint32_t SRS17_GET_RETUNING_TIMER_COUNT(const uint32_t val)
621 {
622 /* (1 << (((val >> 8) & 0xF) - 1)) */
623 uint32_t result = 0x80000000u; /* 1 << -1 */
624
625 uint32_t shift = ((val & 0x00000F00u) >> 8u);
626 if (shift > 0u) {
627 shift -= 1u;
628 result = (((uint32_t)1u) << shift);
629 }
630 return (result);
631 }
632 /* 1.8V Line Driver Type D Supported */
633 #define SRS17_1_8V_DRIVER_TYPE_D_SUPPORTED 0x00000040u
634 /* 1.8V Line Driver Type C Supported */
635 #define SRS17_1_8V_DRIVER_TYPE_C_SUPPORTED 0x00000020u
636 /* 1.8V Line Driver Type A Supported */
637 #define SRS17_1_8V_DRIVER_TYPE_A_SUPPORTED 0x00000010u
638 /* UHS-II Supported */
639 #define SRS17_UHSII_SUPPORTED 0x00000008u
640 /* DDR50 Supported */
641 #define SRS17_DDR50_SUPPORTED 0x00000004u
642 /* SDR104 Supported */
643 #define SRS17_SDR104_SUPPORTED 0x00000002u
644 /* SDR50 Supported */
645 #define SRS17_SDR50_SUPPORTED 0x00000001u
646
647 /*-----------------------------------------------------------------------------
648 @name PHY settings register (HRS4) - masks and macros
649 ------------------------------------------------------------------------------
650 */
651 /* PHY request acknowledge */
652 #define HRS_PHY_ACKNOWLEDGE_REQUEST 0x04000000u
653 /* make read request */
654 #define HRS_PHY_READ_REQUEST 0x02000000u
655 /* make write request */
656 #define HRS_PHY_WRITE_REQUEST 0x01000000u
657
658 /*-----------------------------------------------------------------------------
659 @name PHY Delay Value Registers addressing
660 ------------------------------------------------------------------------------
661 */
662 /* PHY register addresses using */
663 #define UIS_ADDR_HIGH_SPEED 0x00u
664 #define UIS_ADDR_DEFAULT_SPEED 0x01u
665 #define UIS_ADDR_UHSI_SDR12 0x02u
666 #define UIS_ADDR_UHSI_SDR25 0x03u
667 #define UIS_ADDR_UHSI_SDR50 0x04u
668 #define UIS_ADDR_UHSI_DDR50 0x05u
669 #define UIS_ADDR_MMC_LEGACY 0x06u
670 #define UIS_ADDR_MMC_SDR 0x07u
671 #define UIS_ADDR_MMC_DDR 0x08u
672 #define UIS_ADDR_SDCLK 0x0Bu
673 #define UIS_ADDR_HS_SDCLK 0x0Cu
674 #define UIS_ADDR_DAT_STROBE 0x0Du
675
676 /*---------------------------------------------------------------------------
677 @name OCR register bits definitions of SD memory cards
678 ----------------------------------------------------------------------------
679 */
680 #define SDCARD_REG_OCR_2_7_2_8 (1u << 15)
681 #define SDCARD_REG_OCR_2_8_2_9 (1u << 16)
682 #define SDCARD_REG_OCR_2_9_3_0 (1u << 17)
683 #define SDCARD_REG_OCR_3_0_3_1 (1u << 18)
684 #define SDCARD_REG_OCR_3_1_3_2 (1u << 19)
685 #define SDCARD_REG_OCR_3_2_3_3 (1u << 20)
686 #define SDCARD_REG_OCR_3_3_3_4 (1u << 21)
687 #define SDCARD_REG_OCR_3_4_3_5 (1u << 22)
688 #define SDCARD_REG_OCR_3_5_3_6 (1u << 23)
689 /* Switching to 1.8V request */
690 #define SDCARD_REG_OCR_S18R (1u<< 24)
691 /* Switching to 1.8V accepted */
692 #define SDCARD_REG_OCR_S18A (1u << 24)
693 /* SDXC power controll (0 - power saving, 1 - maximum performance) */
694 /* (this bit is not aviable in the SDIO cards) */
695 #define SDCARD_REG_OCR_XPC (1u << 28)
696 /* card capacity status (this bit is not aviable in the SDIO cards) */
697 #define SDCARD_REG_OCR_CCS (1u << 30)
698 /* card power up busy status (this is not aviable in the SDIO cards) */
699 #define SDCARD_REG_OCR_READY (1u << 31)
700
701
702 /*---------------------------------------------------------------------------
703 @name SCR register bits defnitions and slot masks
704 ----------------------------------------------------------------------------
705 */
706
707 /* CMD20 (speed class controll) command is supported by card */
708 #define SDCARD_REG_CMD20 (1u << 0)
709 /* CMD23 (set block count) command is supported by card */
710 #define SDCARD_REG_CMD23 (1u << 1)
SDCARD_REG_GET_EXT_SECURITY(uint32_t x)711 static inline uint32_t SDCARD_REG_GET_EXT_SECURITY(uint32_t x)
712 {
713 return ((x >> 11) & 0xFU);
714 }
715
716 #define SDCARD_REG_SD_SPEC3_SUPPORT (1u << 15)
717
718 /* SD supported bus width 1 bit */
719 #define SDCARD_REG_SCR_SBW_1BIT (1u << 16)
720 /* SD supported bus width 4 bit */
721 #define SDCARD_REG_SCR_SBW_4BIT (4u << 16)
722 /* SD bus width mask */
723 #define SDCARD_REG_SCR_SBW_MASK 0x000F0000u
724 /* SD security mask */
725 #define SDCARD_REG_SCR_SEC_MASK 0x00700000u
726 /* SD security - no security */
727 #define SDCARD_REG_SCR_SEC_NO 0x00000000u
728 /* SD security version 1.01 */
729 #define SDCARD_REG_SCR_SEC_VER_101 0x00200000u
730 /* SD security version 2.00 */
731 #define SDCARD_REG_SCR_SEC_VER_200 0x00300000u
732 /* Data state after erase is 1 */
733 #define SDCARD_REG_SCR_DSAE_1 0x00800000u
734 /* Physical Layer Specification Version supported by the card mask. */
735 #define SDCARD_REG_SCR_SPEC_MAS 0x0F000000u
736 /* Physical Layer Specification Version 1.00 - 1.01 */
737 #define SDCARD_REG_SCR_SPEC_VER_100 0x00000000u
738 /* Physical Layer Specification Version 1.10 */
739 #define SDCARD_REG_SCR_SPEC_VER_110 0x01000000u
740 /* Physical Layer Specification Version 2.00 */
741 #define SDCARD_REG_SCR_SPEC_VER_200 0x02000000u
742 /* Physical Layer Specification mask */
743 #define SDCARD_REG_SCR_SPEC_VER_MASK 0x0F000000u
744 /* SCR structure mask */
745 #define SDCARD_REG_SCR_STRUCTURE_MASK 0xF0000000u
746 /* SCR version 1.0 */
747 #define SDCARD_REG_SCR_VER_10 0x00000000u
748
749 /*---------------------------------------------------------------------------
750 @name Response R4 bit definitions
751 ----------------------------------------------------------------------------
752 */
753 /* card ready bit */
754 #define SDCARD_R4_CARD_READY (1u << 31)
755 /* memory present bit */
756 #define SDCARD_R4_MEMORY_PRESENT (1u << 27)
757
758 /*---------------------------------------------------------------------------
759 @name SD card function register bits, masks and macros definitions
760 ----------------------------------------------------------------------------
761 */
762 /* Check function mode - is used to query if the card supports a specific
763 function or functions. */
764 #define SDCARD_SWITCH_FUNC_MODE_SWITCH (0x1u << 31)
765 /* Set function mode - is used to switch the functionality of the card.*/
766 #define SDCARD_SWITCH_FUNC_MODE_CHECK (0x0u << 31)
767 /* Card access mode - SDR12 default */
768 #define SDCARD_SWITCH_ACCESS_MODE_SDR12 0x0u
769 /* Card access mode - SDR25 highspeed */
770 #define SDCARD_SWITCH_ACCESS_MODE_SDR25 0x1u
771 /* Card access mode - SDR50 */
772 #define SDCARD_SWITCH_ACCESS_MODE_SDR50 0x2u
773 /* Card access mode - SDR104 */
774 #define SDCARD_SWITCH_ACCESS_MODE_SDR104 0x3u
775 /* Card access mode - DDR50 */
776 #define SDCARD_SWITCH_ACCESS_MODE_DDR50 0x4u
777
778 /* Card command system - default */
779 #define SDCARD_SWITCH_CMD_SYSTEM_DEFAULT 0x0u
780 /* Card command system - eCommerce command set */
781 #define SDCARD_SWITCH_CMD_SYSTEM_E_COMMERCE 0x1u
782 /* Card command system - OTP */
783 #define SDCARD_SWITCH_CMD_SYSTEM_OTP 0x3u
784 /* Card command system - ASSD */
785 #define SDCARD_SWITCH_CMD_SYSTEM_ASSD 0x4u
786 /* Card command system - vendor specific command set */
787 #define SDCARD_SWITCH_CMD_SYSTEM_NR_VENDOR 0xEu
788
789 /* Card driver strength - Type B default */
790 #define SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_B 0x0u
791 /* Card driver strength - Type A */
792 #define SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_A 0x1u
793 /* Card driver strength - Type C */
794 #define SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_C 0x2u
795 /* Card driver strength - Type D */
796 #define SDCARD_SWITCH_DRIVER_STRENGTH_TYPE_D 0x3u
797
798 #define SDCARD_SWITCH_GROUP_NR_1 1u
799 #define SDCARD_SWITCH_GROUP_NR_2 2u
800 #define SDCARD_SWITCH_GROUP_NR_3 3u
801 #define SDCARD_SWITCH_GROUP_NR_4 4u
802 #define SDCARD_SWITCH_GROUP_NR_5 5u
803 #define SDCARD_SWITCH_GROUP_NR_6 6u
804
805 /* macro gets one byte from dword */
806 #define GetByte(dword, byte_nr) (((dword) >> ((byte_nr) * 8u)) & 0xFFu)
807
GET_BYTE_FROM_BUFFER(const void * buffer,uintptr_t byteNr)808 static inline uint8_t GET_BYTE_FROM_BUFFER(const void* buffer, uintptr_t byteNr)
809 {
810 return ((uint8_t)GetByte((*(uint32_t*)((uintptr_t)buffer + (byteNr & ~3u))), (byteNr & 3u)));
811 }
GET_BYTE_FROM_BUFFER2(const void * buffer,uintptr_t bufferSize,uintptr_t byteNr)812 static inline uint8_t GET_BYTE_FROM_BUFFER2(const void* buffer, uintptr_t bufferSize, uintptr_t byteNr)
813 {
814 return (GET_BYTE_FROM_BUFFER(buffer, bufferSize - 1u - byteNr));
815 }
816
817 /* Macro returns 1 if given function is supported by the card */
SDCARD_SWITCH_FUNC_IS_FUNC_SUPPORTED(const uint8_t * val,uint8_t groupNum,uint8_t funcNum)818 static inline uint8_t SDCARD_SWITCH_FUNC_IS_FUNC_SUPPORTED(const uint8_t* val, uint8_t groupNum, uint8_t funcNum)
819 {
820 uint32_t supportStatus = 0u;
821
822 if (funcNum < 32u) {
823 const uintptr_t offset = (groupNum - 1u) * 2u;
824
825 supportStatus = (((uint32_t)GET_BYTE_FROM_BUFFER2(val, 64u, 50u - offset)
826 | (uint32_t)(GET_BYTE_FROM_BUFFER2(val, 64u, 51u - offset))) << 8)
827 & (uint32_t)(1u << funcNum);
828 }
829
830 return ((supportStatus != 0u) ? 1u : 0u);
831 }
832 /* Macro gets function status code from the switch function status data structure */
SDCARD_SWICH_FUNC_GET_STAT_CODE(const uint8_t * val,uint8_t groupNum)833 static inline uint8_t SDCARD_SWICH_FUNC_GET_STAT_CODE(const uint8_t* val, uint8_t groupNum)
834 {
835 uint8_t result = 0u;
836 const uint8_t shift = ((groupNum - 1u) % 2u) * 4u;
837
838 const uintptr_t offset = 47u + ((groupNum - 1u) / 2u);
839
840 result = (GET_BYTE_FROM_BUFFER2(val, 64u, offset) >> shift) & 0xFu;
841
842 return (result);
843 }
844 /* Macro gets function busy status from the switch function status data structure */
845 /* Macro returns 1 if function is busy 0 otherwise */
SDCARD_SWICH_FUNC_GET_BUSY_STAT(const uint8_t * val,uint8_t groupNum,uint8_t funcNum)846 static inline uint8_t SDCARD_SWICH_FUNC_GET_BUSY_STAT(const uint8_t* val, uint8_t groupNum, uint8_t funcNum)
847 {
848 uint32_t busyStatus = 0u;
849
850 if (funcNum < 32u) {
851 const uintptr_t offset = (groupNum - 1u) * 2u;
852
853 busyStatus = ((GET_BYTE_FROM_BUFFER2(val, 64u, 34u - offset)
854 | GET_BYTE_FROM_BUFFER2(val, 64u, 35u - offset)) << 8)
855 & (uint32_t)(1u << funcNum);
856 }
857
858 return ((busyStatus != 0u) ? 1u : 0u);
859 }
860
861 /*---------------------------------------------------------------------------
862 @name Command masks
863 ----------------------------------------------------------------------------
864 */
865 /* host hight capacity support -*/
866 #define SDCARD_ACMD41_HCS (1u << 30)
867
868 /*--------------------------------------------------------------------------*/
869
870 /*---------------------------------------------------------------------------
871 @name Response SPI R1 for SD memory cards bits defnitions
872 ----------------------------------------------------------------------------
873 */
874 /* The card is in idle state and running the initializing process. */
875 #define SDCARD_RESP_R1_IDLE 0x01u
876 /* An erase sequence was cleared before executing because an out of
877 erase sequence command was received. */
878 #define SDCARD_RESP_R1_ERASE_RESET 0x02u
879 /* An illegal command code was detected. */
880 #define SDCARD_RESP_R1_ILLEGAL_CMD_ERR 0x04u
881 /* The CRC check of the last command failed. */
882 #define SDCARD_RESP_R1_COM_CRC_ERR 0x08u
883 /* An error in the sequence of erase commands occurred. */
884 #define SDCARD_RESP_R1_ERASE_SEQUENCE_ERR 0x10u
885 /* A misaligned address that did not match the block length was used in the command.*/
886 #define SDCARD_RESP_R1_ADDRESS_ERR 0x20u
887 /* The command's argument (e.g. address, block length) was outside the allowed */
888 #define SDCARD_RESP_R1_PARAM_ERR 0x40u
889 /* All errors mask */
890 #define SDCARD_RESP_R1_ALL_ERRORS (SDCARD_RESP_R1_ILLEGAL_CMD_ERR \
891 | SDCARD_RESP_R1_COM_CRC_ERR \
892 | SDCARD_RESP_R1_ERASE_SEQUENCE_ERR \
893 | SDCARD_RESP_R1_ADDRESS_ERR \
894 | SDCARD_RESP_R1_PARAM_ERR)
895
896
897 /* No operation go to next descriptor on the list. */
898 #define ADMA2_DESCRIPTOR_TYPE_NOP (0x0u << 4)
899 /* Transfer data from the pointed page and go to next descriptor on the list.*/
900 #define ADMA2_DESCRIPTOR_TYPE_TRAN (0x2u << 4)
901 /* Go to the next descriptor list */
902 #define ADMA2_DESCRIPTOR_TYPE_LINK (0x3u << 4)
903 /* the ADMA interrupt is generated */
904 /* when the ADMA1 engine finishes processing the descriptor. */
905 #define ADMA2_DESCRIPTOR_INT (0x1u << 2)
906 /* it signals termination of the transfer */
907 /* and generates Transfer Complete Interrupt */
908 /* when this transfer is completed */
909 #define ADMA2_DESCRIPTOR_END (0x1u << 1)
910 /* it indicates the valid descriptor on a list */
911 #define ADMA2_DESCRIPTOR_VAL (0x1u << 0)
912
913 /*-----------------------------------------------------------------------------
914 Command Queuing Configuration (CQRS02)- masks
915 ------------------------------------------------------------------------------
916 */
917 /* Direct Command (DCMD) Enable */
918 #define CQRS02_DIRECT_CMD_ENABLE 0x00001000u
919 /* Task Descriptor Size 128 bits */
920 #define CQRS02_TASK_DESCRIPTOR_SIZE_128 (1u << 8)
921 /* Task Descriptor Size 64 bits */
922 #define CQRS02_TASK_DESCRIPTOR_SIZE_64 (0u << 8)
923 /* Task Descriptor Size mask */
924 #define CQRS02_TASK_DESCRIPTOR_SIZE_MASK 0x00000100u
925 /* Command Queuing Enable */
926 #define CQRS02_COMMAND_QUEUING_ENABLE 0x00000001u
927
928 /*-----------------------------------------------------------------------------
929 Command Queuing Interrupt Status (CQRS04)- masks
930 ------------------------------------------------------------------------------
931 */
932 /* Task cleared interrupt */
933 #define CQRS04_TASK_CLEARED_INT 0x00000008u
934 /* Response Error Detected Interrupt */
935 #define CQRS04_RESP_ERR_INT 0x00000004u
936 /* Task Complete Interrupt */
937 #define CQRS04_TASK_COMPLETE_INT 0x00000002u
938 /* Halt Complete Interrupt */
939 #define CQRS04_HALT_COMPLETE_INT 0x00000001u
940
941 /*-----------------------------------------------------------------------------
942 Command Queuing Interrupt Status Enable (CQRS05)- masks
943 ------------------------------------------------------------------------------
944 */
945 /* Task cleared status enable */
946 #define CQRS05_TASK_CLEARED_STAT_EN 0x00000008u
947 /* Response Error Detected status enable */
948 #define CQRS05_RESP_ERR_STAT_EN 0x00000004u
949 /* Task Complete status enable */
950 #define CQRS05_TASK_COMPLETE_STAT_EN 0x00000002u
951 /* Halt Complete status enable */
952 #define CQRS05_HALT_COMPLETE_STAT_EN 0x00000001u
953
954 /*-----------------------------------------------------------------------------
955 Command Queuing Interrupt Signal Enable (CQRS06)- masks
956 ------------------------------------------------------------------------------
957 */
958 /* Task cleared interrupt signal enable */
959 #define CQRS06_TASK_CLEARED_INT_SIG_EN 0x00000008u
960 /* Response Error Detected Interrupt signal enable */
961 #define CQRS06_RESP_ERR_INT_SIG_EN 0x00000004u
962 /* Task Complete Interrupt signal enable */
963 #define CQRS06_TASK_COMPLETE_INT_SIG_EN 0x00000002u
964 /* Halt Complete Interrupt signal enable */
965 #define CQRS06_HALT_COMPLETE_INT_SIG_EN 0x00000001u
966
967 /*-----------------------------------------------------------------------------
968 Command Queuing Interrupt Coalescing (CQRS07)- masks and macros
969 ------------------------------------------------------------------------------
970 */
971 #define CQRS07_INT_COAL_ENABLE 0x80000000u
972 /* Interrupt Coalescing Status Bit */
973 #define CQRS07_INT_COAL_STATUS_BIT 0x00100000u
974 /* Counter and Timer Reset(ICCTR) */
975 #define CQRS07_INT_COAL_COUNTER_TIMER_RESET 0x00010000u
976 /* Interrupt Coalescing Counter Threshold Write Enable */
977 #define CQRS07_INT_COAL_COUNT_THRESHOLD_WE 0x00008000u
978
979 /* task management argument - discard task */
980 #define CQ_TASK_MGMT_ARG_TM_DISCARD_TASK 1u
981 /* task management argument - discard queue */
982 #define CQ_TASK_MGMT_ARG_TM_DISCARD_QUEUE 2u
983
984 /* number of supported tasks */
985 #define CQ_HOST_NUMBER_OF_TASKS 32u
986 /* direct command task ID */
987 #define CQ_DCMD_TASK_ID 31u
988
989 /*-----------------------------------------------------------------------------
990 @name Task Descriptor Fields
991 ------------------------------------------------------------------------------
992 */
993 /* The descriptor is valid */
994 #define CQ_DESC_VALID (1u << 0)
995 /* it is the last descriptor */
996 #define CQ_DESC_END (1u << 1)
997 /* Hardware shall generate an interrupt upon the task's completion */
998 #define CQ_DESC_INT (1u << 2)
999 /* Descriptor type - Task descriptor */
1000 #define CQ_DESC_ACT_TASK (5u << 3)
1001 /* Descriptor type - Data Transfer descriptor */
1002 #define CQ_DESC_ACT_TRAN (4u << 3)
1003 /* Descriptor type - Link descriptor */
1004 #define CQ_DESC_ACT_LINK (6u << 3)
1005 /* Descriptor type - No operation*/
1006 #define CQ_DESC_ACT_NOP (0u << 3)
1007 /* enable force programming */
1008 #define CQ_DESC_FORCE_PROG (6u << 1)
1009 /* set context ID */
CQ_DESC_SET_CONTEXT_ID(uint16_t id)1010 static inline uint16_t CQ_DESC_SET_CONTEXT_ID(uint16_t id)
1011 {
1012 return ((id & 0xFU) << 7);
1013 }
1014 #define CQ_DESC_TAG_REQUEST (1u << 11)
1015 /* Data read direction */
1016 #define CQ_DESC_DATA_DIR_READ (1u << 12)
1017 #define CQ_DESC_DATA_DIR_WRITE (0u << 12)
1018 /* High priority task */
1019 #define CQ_DESC_PRIORITY_HIGH (1u << 13)
1020 #define CQ_DESC_QUEUE_BARRIER (1u << 14)
1021 #define CQ_DESC_RELIABLE_WRITE (1u << 15)
1022 /* set data block count to transfer */
CQ_DESC_SET_BLOCK_COUNT(uint32_t count)1023 static inline uint32_t CQ_DESC_SET_BLOCK_COUNT(uint32_t count)
1024 {
1025 return ((count & 0xFFFFu) << 16);
1026 }
1027 /* Length of data buffer in bytes. A value of 0000 means 64 KB */
CQ_DESC_SET_DATA_LEN(uint32_t len)1028 static inline uint32_t CQ_DESC_SET_DATA_LEN(uint32_t len)
1029 {
1030 return ((len & 0xFFFFu) << 16);
1031 }
1032
CQ_DESC_DCMD_SET_CMD_INDEX(uint32_t idx)1033 static inline uint32_t CQ_DESC_DCMD_SET_CMD_INDEX(uint32_t idx)
1034 {
1035 return ((idx & 0x3Fu) << 16);
1036 }
1037 /* Command may be sent to device during data activity or busy time */
1038 #define CQ_DESC_DCMD_CMD_TIMING (1u << 22)
1039 /* expected reponse on direct command - R1 or R4 or R5*/
1040 #define CQ_DESC_DCMD_RESP_TYPE_R1_R4_R5 (2u << 23)
1041 /* expected reponse on direct command - R1B */
1042 #define CQ_DESC_DCMD_RESP_TYPE_R1B (3u << 23)
1043 /* no expected reponse on direct command */
1044 #define CQ_DESC_DCMD_RESP_TYPE_NO_RESP (0u << 23)
1045
1046
1047 /*-----------------------------------------------------------------------------
1048 @name CCCR transfer direction definitions
1049 ------------------------------------------------------------------------------
1050 */
1051 /* Read data from CCCR register */
1052 #define SDIOHOST_CCCR_READ 0u
1053 /* Write data to CCCR register */
1054 #define SDIOHOST_CCCR_WRITE 1u
1055
1056 /*---------------------------------------------------------------------------
1057 @name Bus interface control register bit definitions
1058 ----------------------------------------------------------------------------
1059 */
1060 /* Data 4 bit bus width */
1061 #define SDCARD_BIS_BUS_WIDTH_4BIT 0x02u
1062 /* Data 1 bit bus width */
1063 #define SDCARD_BIS_BUS_WIDTH_1BIT 0x00u
1064 /* Connect[0]/Disconnect[1] the 10K-90K ohm pull-up resistor on CD/DAT[3] */
1065 /* (pin 1) of card. */
1066 #define SDCARD_BIS_CD_DISABLE 0x80u
1067 /* Support contiunous SPI interrupt (irrespective of the state the CS line) */
1068 #define SDCARD_BIS_SCSI 0x40u
1069 /* Enable contiunous SPI interrupt (irrespective of the state the CS line) */
1070 #define SDCARD_BIS_ECSI 0x20u
1071
1072 /*---------------------------------------------------------------------------
1073 @name Card capability register bit definitions
1074 ----------------------------------------------------------------------------
1075 */
1076 /* Card supports direct commands during data trnsfer. (only in SD mode) */
1077 #define SDCARD_CCR_SDC 0x01u
1078 /* Card supports multiblock */
1079 #define SDCARD_CCR_SMB 0x02u
1080 /* Card supports read wait */
1081 #define SDCARD_CCR_SRW 0x04u
1082 /* Card supports Suspend/Resume */
1083 #define SDCARD_CCR_SBS 0x08u
1084 /* Card supports interrupt between blocks of data in 4-bit SD mode. */
1085 #define SDCARD_CCR_S4MI 0x10u
1086 /* Enable interrupt between blocks of data in 4-bit SD mode. */
1087 #define SDCARD_CCR_E4MI 0x20u
1088 /* Card is a low-speed card */
1089 #define SDCARD_CCR_LSC 0x40u
1090 /* 4 bit support for Low-Speed cards */
1091 #define SDCARD_CCR_4BLS 0x80u
1092
1093 /*---------------------------------------------------------------------------
1094 @name Bus speed register bit definitions
1095 ----------------------------------------------------------------------------
1096 */
1097 /* Support high speed. */
1098 #define SDIO_CCCR_13_SHS 0x01u
1099 /* Enable high speed. */
1100 #define SDIO_CCCR_13_EHS 0x02u
1101
1102 #define SDIO_CCCR_13_BSS_MASK (0x7u << 1)
1103 #define SDIO_CCCR_13_BSS_SDR12 (0x0u << 1)
1104 #define SDIO_CCCR_13_BSS_SDR25 (0x1u << 1)
1105 #define SDIO_CCCR_13_BSS_SDR50 (0x2u << 1)
1106 #define SDIO_CCCR_13_BSS_SDR104 (0x3u << 1)
1107 #define SDIO_CCCR_13_BSS_DDR50 (0x4u << 1)
1108
1109 /*---------------------------------------------------------------------------
1110 @name USH-I suport bits register 0x14
1111 ----------------------------------------------------------------------------
1112 */
1113 #define SDIO_CCCR_14_SSDR50 (0x1u << 0)
1114 #define SDIO_CCCR_14_SSDR104 (0x1u << 1)
1115 #define SDIO_CCCR_14_SDDR50 (0x1u << 2)
1116
1117 /*---------------------------------------------------------------------------
1118 @name Card status bits and masks definitions for cards (SD SDIO MMC)
1119 ----------------------------------------------------------------------------
1120 */
1121 /* Error authentication process */
1122 #define CARD_SATUS_AKE_SEQ_ERROR (0x1u << 3)
1123 /* The card will expect ACMD, or an indication that the command has been
1124 interpreted as ACMD */
1125 #define CARD_SATUS_APP_CMD (0x1u << 5)
1126 /* Card didn't switch to the expected mode as requested by the SWITCH command */
1127 #define CARD_STATUS_SWITCH_ERROR (0x1u << 7)
1128 /* Corresponds to buffer empty signaling on the bus - buffer is ready */
1129 #define CARD_STATUS_READY_FOR_DATA (0x1u << 8)
1130 /* The state of the card when receiving the command. Below are definded all 9 satuses.*/
1131 #define CARD_STATUS_CS_MASK (0xFu << 9)
1132 /* Current status card is in Idle State */
1133 #define CARD_STATUS_CS_IDLE (0x0u << 9)
1134 /* Current status card is in Ready State */
1135 #define CARD_STATUS_CS_READY (0x1u << 9)
1136 /* Current status card is Identification State */
1137 #define CARD_STATUS_CS_IDENT (0x2u << 9)
1138 /* Current status card is in Stand-by State */
1139 #define CARD_STATUS_CS_STBY (0x3u << 9)
1140 /* Current status card is in Transfer State */
1141 #define CARD_STATUS_CS_TRAN (0x4u << 9)
1142 /* Current status card is in Sending-data State */
1143 #define CARD_STATUS_CS_DATA (0x5u << 9)
1144 /* Current status card is in Receive-data State */
1145 #define CARD_STATUS_CS_RCV (0x6u << 9)
1146 /* Current status card is in Programming State */
1147 #define CARD_STATUS_CS_PRG (0x7u << 9)
1148 /* Current status card is in Disconnect State */
1149 #define CARD_STATUS_CS_DIS (0x8u << 9)
1150 /* An erase sequence was cleared before executing because an out of erase
1151 sequence command was received */
1152 #define CARD_STATUS_ERASE_RESET (0x1u << 13)
1153 /* The command has been executed without using the internal ECC. */
1154 #define CARD_STATUS_CARD_ECC_DISABLED (0x1u << 14)
1155 /* Problem with erase part of memory because it is protected */
1156 #define CARD_STATUS_WP_ERASE_SKIP (0x1u << 15)
1157 /* Can be either one of the following errors: */
1158 /* - The read only section of the CSD does not match the card content. */
1159 /* - An attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made.*/
1160 #define CARD_STATUS_CSD_OVERWRITE (0x1u << 16)
1161 /* The card could not sustain data programming in stream write mode */
1162 #define CARD_STATUS_OVERRUN (0x1u << 17)
1163 /* The card could not sustain data transfer in stream read mode */
1164 #define CARD_STATUS_UNDERRUN (0x1u << 18)
1165 /* A general or an unknown error occurred during the operation. */
1166 #define CARD_STATUS_ERROR (0x1u << 19)
1167 /* Internal card controller error */
1168 #define CARD_STATUS_CC_ERROR (0x1u << 20)
1169 /* Card internal ECC was applied but failure failed to correct the data.*/
1170 #define CARD_STATUS_CARD_ECC_FAILED (0x1u << 21)
1171 /* Command not legal for the card state */
1172 #define CARD_STATUS_ILLEGAL_COMMAND (0x1u << 22)
1173 /* The CRC check of the previous error command failed. */
1174 #define CARD_STATUS_COM_CRC_ERROR (0x1u << 23)
1175 /* Set when a sequence or password error has been detected in lock/unlock card command.*/
1176 #define CARD_STATUS_LOCK_UNLOCK_FAILED (0x1u << 24)
1177 /* When set, signals that the card is card locked by the host */
1178 #define CARD_STATUS_CARD_IS_LOCKED (0x1u << 25)
1179 /* Set when the host attempts to write to a protected block or
1180 to the temporary or permanent write protected card. */
1181 #define CARD_STATUS_WP_VIOLATION (0x1u << 26)
1182 /* An invalid selection of write-blocks for erase occurred.*/
1183 #define CARD_STATUS_ERASE_PARAM (0x1u << 27)
1184 /* An error in the sequence of erase error commands occurred.*/
1185 #define CARD_STATUS_ERASE_SEQ_ERROR (0x1u << 28)
1186 /* The transferred block length is not allowed for this card, or the number*/
1187 /* of transferred bytes does not match the block length.*/
1188 #define CARD_STATUS_BLOCK_LEN_ERROR (0x1u << 29)
1189 /* A misaligned address which did not match the block length was used in the command.*/
1190 #define CARD_STATUS_ADDRESS_ERROR (0x1u << 30)
1191 /* The command's argument was out of the allowed range for this card.*/
1192 #define CARD_STATUS_OUT_OF_RANGE (0x1u << 31)
1193
1194 /* All errors mask definition */
1195 #define CARD_STATUS_ALL_ERRORS_MASK ( CARD_STATUS_OUT_OF_RANGE \
1196 | CARD_STATUS_ADDRESS_ERROR \
1197 | CARD_STATUS_BLOCK_LEN_ERROR \
1198 | CARD_STATUS_ERASE_SEQ_ERROR \
1199 | CARD_STATUS_ERASE_PARAM \
1200 | CARD_STATUS_WP_VIOLATION \
1201 | CARD_STATUS_LOCK_UNLOCK_FAILED \
1202 | CARD_STATUS_COM_CRC_ERROR \
1203 | CARD_STATUS_ILLEGAL_COMMAND \
1204 | CARD_STATUS_CARD_ECC_FAILED \
1205 | CARD_STATUS_CC_ERROR \
1206 | CARD_STATUS_ERROR \
1207 | CARD_STATUS_UNDERRUN \
1208 | CARD_STATUS_OVERRUN \
1209 | CARD_STATUS_WP_ERASE_SKIP \
1210 | CARD_STATUS_SWITCH_ERROR \
1211 | CARD_SATUS_AKE_SEQ_ERROR )
1212
1213
1214 /****************************************************************************/
1215 #ifdef __cplusplus
1216 }
1217 #endif
1218
1219 #endif /* __MSS_MMC_REGS_H_ */
1220
