1 /*
2  * Copyright (c) 2024 Microchip
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _MICROCHIP_PIC32CXSG_SERCOM_COMPONENT_FIXUP_H_
8 #define _MICROCHIP_PIC32CXSG_SERCOM_COMPONENT_FIXUP_H_
9 
10 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM Control A -------- */
11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
12 typedef union {
13   struct {
14     uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
15     uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
16     uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
17     uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
18     uint32_t RUNSTDBY:1;       /*!< bit:      7  Run in Standby                     */
19     uint32_t :8;               /*!< bit:  8..15  Reserved                           */
20     uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
21     uint32_t :3;               /*!< bit: 17..19  Reserved                           */
22     uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
23     uint32_t MEXTTOEN:1;       /*!< bit:     22  Master SCL Low Extend Timeout      */
24     uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
25     uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
26     uint32_t :1;               /*!< bit:     26  Reserved                           */
27     uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
28     uint32_t INACTOUT:2;       /*!< bit: 28..29  Inactive Time-Out                  */
29     uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
30     uint32_t :1;               /*!< bit:     31  Reserved                           */
31   } bit;                       /*!< Structure used for bit  access                  */
32   uint32_t reg;                /*!< Type      used for register access              */
33 } SERCOM_I2CM_CTRLA_Type;
34 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
35 
36 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS Control A -------- */
37 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
38 typedef union {
39   struct {
40     uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
41     uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
42     uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
43     uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
44     uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
45     uint32_t :8;               /*!< bit:  8..15  Reserved                           */
46     uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
47     uint32_t :3;               /*!< bit: 17..19  Reserved                           */
48     uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
49     uint32_t :1;               /*!< bit:     22  Reserved                           */
50     uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
51     uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
52     uint32_t :1;               /*!< bit:     26  Reserved                           */
53     uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
54     uint32_t :2;               /*!< bit: 28..29  Reserved                           */
55     uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
56     uint32_t :1;               /*!< bit:     31  Reserved                           */
57   } bit;                       /*!< Structure used for bit  access                  */
58   uint32_t reg;                /*!< Type      used for register access              */
59 } SERCOM_I2CS_CTRLA_Type;
60 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
61 
62 /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
64 typedef union {
65   struct {
66     uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
67     uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
68     uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
69     uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
70     uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
71     uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
72     uint32_t :7;               /*!< bit:  9..15  Reserved                           */
73     uint32_t DOPO:2;           /*!< bit: 16..17  Data Out Pinout                    */
74     uint32_t :2;               /*!< bit: 18..19  Reserved                           */
75     uint32_t DIPO:2;           /*!< bit: 20..21  Data In Pinout                     */
76     uint32_t :2;               /*!< bit: 22..23  Reserved                           */
77     uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
78     uint32_t CPHA:1;           /*!< bit:     28  Clock Phase                        */
79     uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
80     uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
81     uint32_t :1;               /*!< bit:     31  Reserved                           */
82   } bit;                       /*!< Structure used for bit  access                  */
83   uint32_t reg;                /*!< Type      used for register access              */
84 } SERCOM_SPI_CTRLA_Type;
85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
86 
87 #define SERCOM_SPI_CTRLA_OFFSET     0x00         /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
88 #define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
89 
90 #define SERCOM_SPI_CTRLA_SWRST_Pos  0            /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
91 #define SERCOM_SPI_CTRLA_SWRST      (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos)
92 #define SERCOM_SPI_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_CTRLA) Enable */
93 #define SERCOM_SPI_CTRLA_ENABLE     (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos)
94 #define SERCOM_SPI_CTRLA_MODE_Pos   2            /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
95 #define SERCOM_SPI_CTRLA_MODE_Msk   (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos)
96 #define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
97 #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
98 #define SERCOM_SPI_CTRLA_RUNSTDBY   (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
99 #define SERCOM_SPI_CTRLA_IBON_Pos   8            /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
100 #define SERCOM_SPI_CTRLA_IBON       (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos)
101 #define SERCOM_SPI_CTRLA_DOPO_Pos   16           /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
102 #define SERCOM_SPI_CTRLA_DOPO_Msk   (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos)
103 #define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
104 #define SERCOM_SPI_CTRLA_DIPO_Pos   20           /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
105 #define SERCOM_SPI_CTRLA_DIPO_Msk   (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos)
106 #define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
107 #define SERCOM_SPI_CTRLA_FORM_Pos   24           /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
108 #define SERCOM_SPI_CTRLA_FORM_Msk   (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos)
109 #define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
110 #define SERCOM_SPI_CTRLA_CPHA_Pos   28           /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
111 #define SERCOM_SPI_CTRLA_CPHA       (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos)
112 #define SERCOM_SPI_CTRLA_CPOL_Pos   29           /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
113 #define SERCOM_SPI_CTRLA_CPOL       (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos)
114 #define SERCOM_SPI_CTRLA_DORD_Pos   30           /**< \brief (SERCOM_SPI_CTRLA) Data Order */
115 #define SERCOM_SPI_CTRLA_DORD       (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos)
116 #define SERCOM_SPI_CTRLA_MASK       _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
117 
118 /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
119 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
120 typedef union {
121   struct {
122     uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
123     uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
124     uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
125     uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
126     uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
127     uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
128     uint32_t TXINV:1;          /*!< bit:      9  Transmit Data Invert               */
129     uint32_t RXINV:1;          /*!< bit:     10  Receive Data Invert                */
130     uint32_t :2;               /*!< bit: 11..12  Reserved                           */
131     uint32_t SAMPR:3;          /*!< bit: 13..15  Sample                             */
132     uint32_t TXPO:2;           /*!< bit: 16..17  Transmit Data Pinout               */
133     uint32_t :2;               /*!< bit: 18..19  Reserved                           */
134     uint32_t RXPO:2;           /*!< bit: 20..21  Receive Data Pinout                */
135     uint32_t SAMPA:2;          /*!< bit: 22..23  Sample Adjustment                  */
136     uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
137     uint32_t CMODE:1;          /*!< bit:     28  Communication Mode                 */
138     uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
139     uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
140     uint32_t :1;               /*!< bit:     31  Reserved                           */
141   } bit;                       /*!< Structure used for bit  access                  */
142   uint32_t reg;                /*!< Type      used for register access              */
143 } SERCOM_USART_CTRLA_Type;
144 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
145 
146 #define SERCOM_USART_CTRLA_OFFSET   0x00         /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
147 #define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
148 
149 #define SERCOM_USART_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_USART_CTRLA) Software Reset */
150 #define SERCOM_USART_CTRLA_SWRST    (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos)
151 #define SERCOM_USART_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_USART_CTRLA) Enable */
152 #define SERCOM_USART_CTRLA_ENABLE   (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos)
153 #define SERCOM_USART_CTRLA_MODE_Pos 2            /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
154 #define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos)
155 #define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
156 #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
157 #define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
158 #define SERCOM_USART_CTRLA_IBON_Pos 8            /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
159 #define SERCOM_USART_CTRLA_IBON     (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos)
160 #define SERCOM_USART_CTRLA_TXINV_Pos 9            /**< \brief (SERCOM_USART_CTRLA) Transmit Data Invert */
161 #define SERCOM_USART_CTRLA_TXINV    (_U_(0x1) << SERCOM_USART_CTRLA_TXINV_Pos)
162 #define SERCOM_USART_CTRLA_RXINV_Pos 10           /**< \brief (SERCOM_USART_CTRLA) Receive Data Invert */
163 #define SERCOM_USART_CTRLA_RXINV    (_U_(0x1) << SERCOM_USART_CTRLA_RXINV_Pos)
164 #define SERCOM_USART_CTRLA_SAMPR_Pos 13           /**< \brief (SERCOM_USART_CTRLA) Sample */
165 #define SERCOM_USART_CTRLA_SAMPR_Msk (_U_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos)
166 #define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
167 #define SERCOM_USART_CTRLA_TXPO_Pos 16           /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
168 #define SERCOM_USART_CTRLA_TXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos)
169 #define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
170 #define SERCOM_USART_CTRLA_RXPO_Pos 20           /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
171 #define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos)
172 #define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
173 #define SERCOM_USART_CTRLA_SAMPA_Pos 22           /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
174 #define SERCOM_USART_CTRLA_SAMPA_Msk (_U_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos)
175 #define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
176 #define SERCOM_USART_CTRLA_FORM_Pos 24           /**< \brief (SERCOM_USART_CTRLA) Frame Format */
177 #define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos)
178 #define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
179 #define SERCOM_USART_CTRLA_CMODE_Pos 28           /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
180 #define SERCOM_USART_CTRLA_CMODE    (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos)
181 #define SERCOM_USART_CTRLA_CPOL_Pos 29           /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
182 #define SERCOM_USART_CTRLA_CPOL     (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos)
183 #define SERCOM_USART_CTRLA_DORD_Pos 30           /**< \brief (SERCOM_USART_CTRLA) Data Order */
184 #define SERCOM_USART_CTRLA_DORD     (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos)
185 #define SERCOM_USART_CTRLA_MASK     _U_(0x7FF3E79F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */
186 
187 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM Control B -------- */
188 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
189 typedef union {
190   struct {
191     uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
192     uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
193     uint32_t QCEN:1;           /*!< bit:      9  Quick Command Enable               */
194     uint32_t :6;               /*!< bit: 10..15  Reserved                           */
195     uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
196     uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
197     uint32_t :13;              /*!< bit: 19..31  Reserved                           */
198   } bit;                       /*!< Structure used for bit  access                  */
199   uint32_t reg;                /*!< Type      used for register access              */
200 } SERCOM_I2CM_CTRLB_Type;
201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
202 
203 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS Control B -------- */
204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
205 typedef union {
206   struct {
207     uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
208     uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
209     uint32_t GCMD:1;           /*!< bit:      9  PMBus Group Command                */
210     uint32_t AACKEN:1;         /*!< bit:     10  Automatic Address Acknowledge      */
211     uint32_t :3;               /*!< bit: 11..13  Reserved                           */
212     uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
213     uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
214     uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
215     uint32_t :13;              /*!< bit: 19..31  Reserved                           */
216   } bit;                       /*!< Structure used for bit  access                  */
217   uint32_t reg;                /*!< Type      used for register access              */
218 } SERCOM_I2CS_CTRLB_Type;
219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
220 
221 /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
223 typedef union {
224   struct {
225     uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
226     uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
227     uint32_t PLOADEN:1;        /*!< bit:      6  Data Preload Enable                */
228     uint32_t :2;               /*!< bit:  7.. 8  Reserved                           */
229     uint32_t SSDE:1;           /*!< bit:      9  Slave Select Low Detect Enable     */
230     uint32_t :3;               /*!< bit: 10..12  Reserved                           */
231     uint32_t MSSEN:1;          /*!< bit:     13  Master Slave Select Enable         */
232     uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
233     uint32_t :1;               /*!< bit:     16  Reserved                           */
234     uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
235     uint32_t :14;              /*!< bit: 18..31  Reserved                           */
236   } bit;                       /*!< Structure used for bit  access                  */
237   uint32_t reg;                /*!< Type      used for register access              */
238 } SERCOM_SPI_CTRLB_Type;
239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
240 
241 #define SERCOM_SPI_CTRLB_OFFSET     0x04         /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
242 #define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
243 
244 #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_SPI_CTRLB) Character Size */
245 #define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos)
246 #define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
247 #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6            /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
248 #define SERCOM_SPI_CTRLB_PLOADEN    (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos)
249 #define SERCOM_SPI_CTRLB_SSDE_Pos   9            /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
250 #define SERCOM_SPI_CTRLB_SSDE       (_U_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos)
251 #define SERCOM_SPI_CTRLB_MSSEN_Pos  13           /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
252 #define SERCOM_SPI_CTRLB_MSSEN      (_U_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos)
253 #define SERCOM_SPI_CTRLB_AMODE_Pos  14           /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
254 #define SERCOM_SPI_CTRLB_AMODE_Msk  (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos)
255 #define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
256 #define SERCOM_SPI_CTRLB_RXEN_Pos   17           /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
257 #define SERCOM_SPI_CTRLB_RXEN       (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos)
258 #define SERCOM_SPI_CTRLB_MASK       _U_(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
259 
260 /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
261 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
262 typedef union {
263   struct {
264     uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
265     uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
266     uint32_t SBMODE:1;         /*!< bit:      6  Stop Bit Mode                      */
267     uint32_t :1;               /*!< bit:      7  Reserved                           */
268     uint32_t COLDEN:1;         /*!< bit:      8  Collision Detection Enable         */
269     uint32_t SFDE:1;           /*!< bit:      9  Start of Frame Detection Enable    */
270     uint32_t ENC:1;            /*!< bit:     10  Encoding Format                    */
271     uint32_t :2;               /*!< bit: 11..12  Reserved                           */
272     uint32_t PMODE:1;          /*!< bit:     13  Parity Mode                        */
273     uint32_t :2;               /*!< bit: 14..15  Reserved                           */
274     uint32_t TXEN:1;           /*!< bit:     16  Transmitter Enable                 */
275     uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
276     uint32_t :6;               /*!< bit: 18..23  Reserved                           */
277     uint32_t LINCMD:2;         /*!< bit: 24..25  LIN Command                        */
278     uint32_t :6;               /*!< bit: 26..31  Reserved                           */
279   } bit;                       /*!< Structure used for bit  access                  */
280   uint32_t reg;                /*!< Type      used for register access              */
281 } SERCOM_USART_CTRLB_Type;
282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
283 
284 #define SERCOM_USART_CTRLB_OFFSET   0x04         /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
285 #define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
286 
287 #define SERCOM_USART_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_USART_CTRLB) Character Size */
288 #define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos)
289 #define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
290 #define SERCOM_USART_CTRLB_SBMODE_Pos 6            /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
291 #define SERCOM_USART_CTRLB_SBMODE   (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos)
292 #define SERCOM_USART_CTRLB_COLDEN_Pos 8            /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
293 #define SERCOM_USART_CTRLB_COLDEN   (_U_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos)
294 #define SERCOM_USART_CTRLB_SFDE_Pos 9            /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
295 #define SERCOM_USART_CTRLB_SFDE     (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos)
296 #define SERCOM_USART_CTRLB_ENC_Pos  10           /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
297 #define SERCOM_USART_CTRLB_ENC      (_U_(0x1) << SERCOM_USART_CTRLB_ENC_Pos)
298 #define SERCOM_USART_CTRLB_PMODE_Pos 13           /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
299 #define SERCOM_USART_CTRLB_PMODE    (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos)
300 #define SERCOM_USART_CTRLB_TXEN_Pos 16           /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
301 #define SERCOM_USART_CTRLB_TXEN     (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos)
302 #define SERCOM_USART_CTRLB_RXEN_Pos 17           /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
303 #define SERCOM_USART_CTRLB_RXEN     (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos)
304 #define SERCOM_USART_CTRLB_LINCMD_Pos 24           /**< \brief (SERCOM_USART_CTRLB) LIN Command */
305 #define SERCOM_USART_CTRLB_LINCMD_Msk (_U_(0x3) << SERCOM_USART_CTRLB_LINCMD_Pos)
306 #define SERCOM_USART_CTRLB_LINCMD(value) (SERCOM_USART_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_CTRLB_LINCMD_Pos))
307 #define SERCOM_USART_CTRLB_MASK     _U_(0x03032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */
308 
309 /* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM Control C -------- */
310 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
311 typedef union {
312   struct {
313     uint32_t :24;              /*!< bit:  0..23  Reserved                           */
314     uint32_t DATA32B:1;        /*!< bit:     24  Data 32 Bit                        */
315     uint32_t :7;               /*!< bit: 25..31  Reserved                           */
316   } bit;                       /*!< Structure used for bit  access                  */
317   uint32_t reg;                /*!< Type      used for register access              */
318 } SERCOM_I2CM_CTRLC_Type;
319 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
320 
321 /* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS Control C -------- */
322 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
323 typedef union {
324   struct {
325     uint32_t SDASETUP:4;       /*!< bit:  0.. 3  SDA Setup Time                     */
326     uint32_t :20;              /*!< bit:  4..23  Reserved                           */
327     uint32_t DATA32B:1;        /*!< bit:     24  Data 32 Bit                        */
328     uint32_t :7;               /*!< bit: 25..31  Reserved                           */
329   } bit;                       /*!< Structure used for bit  access                  */
330   uint32_t reg;                /*!< Type      used for register access              */
331 } SERCOM_I2CS_CTRLC_Type;
332 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
333 
334 /* -------- SERCOM_SPI_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPI SPI Control C -------- */
335 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
336 typedef union {
337   struct {
338     uint32_t ICSPACE:6;        /*!< bit:  0.. 5  Inter-Character Spacing            */
339     uint32_t :18;              /*!< bit:  6..23  Reserved                           */
340     uint32_t DATA32B:1;        /*!< bit:     24  Data 32 Bit                        */
341     uint32_t :7;               /*!< bit: 25..31  Reserved                           */
342   } bit;                       /*!< Structure used for bit  access                  */
343   uint32_t reg;                /*!< Type      used for register access              */
344 } SERCOM_SPI_CTRLC_Type;
345 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
346 
347 #define SERCOM_SPI_CTRLC_OFFSET     0x08         /**< \brief (SERCOM_SPI_CTRLC offset) SPI Control C */
348 #define SERCOM_SPI_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLC reset_value) SPI Control C */
349 
350 #define SERCOM_SPI_CTRLC_ICSPACE_Pos 0            /**< \brief (SERCOM_SPI_CTRLC) Inter-Character Spacing */
351 #define SERCOM_SPI_CTRLC_ICSPACE_Msk (_U_(0x3F) << SERCOM_SPI_CTRLC_ICSPACE_Pos)
352 #define SERCOM_SPI_CTRLC_ICSPACE(value) (SERCOM_SPI_CTRLC_ICSPACE_Msk & ((value) << SERCOM_SPI_CTRLC_ICSPACE_Pos))
353 #define SERCOM_SPI_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_SPI_CTRLC) Data 32 Bit */
354 #define SERCOM_SPI_CTRLC_DATA32B    (_U_(0x1) << SERCOM_SPI_CTRLC_DATA32B_Pos)
355 #define SERCOM_SPI_CTRLC_MASK       _U_(0x0100003F) /**< \brief (SERCOM_SPI_CTRLC) MASK Register */
356 
357 /* -------- SERCOM_USART_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART USART Control C -------- */
358 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
359 typedef union {
360   struct {
361     uint32_t GTIME:3;          /*!< bit:  0.. 2  Guard Time                         */
362     uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
363     uint32_t BRKLEN:2;         /*!< bit:  8.. 9  LIN Master Break Length            */
364     uint32_t HDRDLY:2;         /*!< bit: 10..11  LIN Master Header Delay            */
365     uint32_t :4;               /*!< bit: 12..15  Reserved                           */
366     uint32_t INACK:1;          /*!< bit:     16  Inhibit Not Acknowledge            */
367     uint32_t DSNACK:1;         /*!< bit:     17  Disable Successive NACK            */
368     uint32_t :2;               /*!< bit: 18..19  Reserved                           */
369     uint32_t MAXITER:3;        /*!< bit: 20..22  Maximum Iterations                 */
370     uint32_t :1;               /*!< bit:     23  Reserved                           */
371     uint32_t DATA32B:2;        /*!< bit: 24..25  Data 32 Bit                        */
372     uint32_t :6;               /*!< bit: 26..31  Reserved                           */
373   } bit;                       /*!< Structure used for bit  access                  */
374   uint32_t reg;                /*!< Type      used for register access              */
375 } SERCOM_USART_CTRLC_Type;
376 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
377 
378 #define SERCOM_USART_CTRLC_OFFSET   0x08         /**< \brief (SERCOM_USART_CTRLC offset) USART Control C */
379 #define SERCOM_USART_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLC reset_value) USART Control C */
380 
381 #define SERCOM_USART_CTRLC_GTIME_Pos 0            /**< \brief (SERCOM_USART_CTRLC) Guard Time */
382 #define SERCOM_USART_CTRLC_GTIME_Msk (_U_(0x7) << SERCOM_USART_CTRLC_GTIME_Pos)
383 #define SERCOM_USART_CTRLC_GTIME(value) (SERCOM_USART_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_CTRLC_GTIME_Pos))
384 #define SERCOM_USART_CTRLC_BRKLEN_Pos 8            /**< \brief (SERCOM_USART_CTRLC) LIN Master Break Length */
385 #define SERCOM_USART_CTRLC_BRKLEN_Msk (_U_(0x3) << SERCOM_USART_CTRLC_BRKLEN_Pos)
386 #define SERCOM_USART_CTRLC_BRKLEN(value) (SERCOM_USART_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_CTRLC_BRKLEN_Pos))
387 #define SERCOM_USART_CTRLC_HDRDLY_Pos 10           /**< \brief (SERCOM_USART_CTRLC) LIN Master Header Delay */
388 #define SERCOM_USART_CTRLC_HDRDLY_Msk (_U_(0x3) << SERCOM_USART_CTRLC_HDRDLY_Pos)
389 #define SERCOM_USART_CTRLC_HDRDLY(value) (SERCOM_USART_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_CTRLC_HDRDLY_Pos))
390 #define SERCOM_USART_CTRLC_INACK_Pos 16           /**< \brief (SERCOM_USART_CTRLC) Inhibit Not Acknowledge */
391 #define SERCOM_USART_CTRLC_INACK    (_U_(0x1) << SERCOM_USART_CTRLC_INACK_Pos)
392 #define SERCOM_USART_CTRLC_DSNACK_Pos 17           /**< \brief (SERCOM_USART_CTRLC) Disable Successive NACK */
393 #define SERCOM_USART_CTRLC_DSNACK   (_U_(0x1) << SERCOM_USART_CTRLC_DSNACK_Pos)
394 #define SERCOM_USART_CTRLC_MAXITER_Pos 20           /**< \brief (SERCOM_USART_CTRLC) Maximum Iterations */
395 #define SERCOM_USART_CTRLC_MAXITER_Msk (_U_(0x7) << SERCOM_USART_CTRLC_MAXITER_Pos)
396 #define SERCOM_USART_CTRLC_MAXITER(value) (SERCOM_USART_CTRLC_MAXITER_Msk & ((value) << SERCOM_USART_CTRLC_MAXITER_Pos))
397 #define SERCOM_USART_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_USART_CTRLC) Data 32 Bit */
398 #define SERCOM_USART_CTRLC_DATA32B_Msk (_U_(0x3) << SERCOM_USART_CTRLC_DATA32B_Pos)
399 #define SERCOM_USART_CTRLC_DATA32B(value) (SERCOM_USART_CTRLC_DATA32B_Msk & ((value) << SERCOM_USART_CTRLC_DATA32B_Pos))
400 #define SERCOM_USART_CTRLC_MASK     _U_(0x03730F07) /**< \brief (SERCOM_USART_CTRLC) MASK Register */
401 
402 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM Baud Rate -------- */
403 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
404 typedef union {
405   struct {
406     uint32_t BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
407     uint32_t BAUDLOW:8;        /*!< bit:  8..15  Baud Rate Value Low                */
408     uint32_t HSBAUD:8;         /*!< bit: 16..23  High Speed Baud Rate Value         */
409     uint32_t HSBAUDLOW:8;      /*!< bit: 24..31  High Speed Baud Rate Value Low     */
410   } bit;                       /*!< Structure used for bit  access                  */
411   uint32_t reg;                /*!< Type      used for register access              */
412 } SERCOM_I2CM_BAUD_Type;
413 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
414 
415 /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W  8) SPI SPI Baud Rate -------- */
416 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
417 typedef union {
418   struct {
419     uint8_t  BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
420   } bit;                       /*!< Structure used for bit  access                  */
421   uint8_t reg;                 /*!< Type      used for register access              */
422 } SERCOM_SPI_BAUD_Type;
423 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
424 
425 #define SERCOM_SPI_BAUD_OFFSET      0x0C         /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
426 #define SERCOM_SPI_BAUD_RESETVALUE  _U_(0x00)    /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
427 
428 #define SERCOM_SPI_BAUD_BAUD_Pos    0            /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
429 #define SERCOM_SPI_BAUD_BAUD_Msk    (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos)
430 #define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
431 #define SERCOM_SPI_BAUD_MASK        _U_(0xFF)    /**< \brief (SERCOM_SPI_BAUD) MASK Register */
432 
433 /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
434 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
435 typedef union {
436   struct {
437     uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
438   } bit;                       /*!< Structure used for bit  access                  */
439   struct { // FRAC mode
440     uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
441     uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
442   } FRAC;                      /*!< Structure used for FRAC                         */
443   struct { // FRACFP mode
444     uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
445     uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
446   } FRACFP;                    /*!< Structure used for FRACFP                       */
447   struct { // USARTFP mode
448     uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
449   } USARTFP;                   /*!< Structure used for USARTFP                      */
450   uint16_t reg;                /*!< Type      used for register access              */
451 } SERCOM_USART_BAUD_Type;
452 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
453 
454 #define SERCOM_USART_BAUD_OFFSET    0x0C         /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
455 #define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
456 
457 #define SERCOM_USART_BAUD_BAUD_Pos  0            /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
458 #define SERCOM_USART_BAUD_BAUD_Msk  (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos)
459 #define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
460 #define SERCOM_USART_BAUD_MASK      _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD) MASK Register */
461 
462 // FRAC mode
463 #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
464 #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
465 #define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
466 #define SERCOM_USART_BAUD_FRAC_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
467 #define SERCOM_USART_BAUD_FRAC_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos)
468 #define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
469 #define SERCOM_USART_BAUD_FRAC_MASK _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
470 
471 // FRACFP mode
472 #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
473 #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
474 #define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
475 #define SERCOM_USART_BAUD_FRACFP_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
476 #define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos)
477 #define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
478 #define SERCOM_USART_BAUD_FRACFP_MASK _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
479 
480 // USARTFP mode
481 #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
482 #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
483 #define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
484 #define SERCOM_USART_BAUD_USARTFP_MASK _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
485 
486 /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W  8) USART USART Receive Pulse Length -------- */
487 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
488 typedef union {
489   struct {
490     uint8_t  RXPL:8;           /*!< bit:  0.. 7  Receive Pulse Length               */
491   } bit;                       /*!< Structure used for bit  access                  */
492   uint8_t reg;                 /*!< Type      used for register access              */
493 } SERCOM_USART_RXPL_Type;
494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
495 
496 #define SERCOM_USART_RXPL_OFFSET    0x0E         /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
497 #define SERCOM_USART_RXPL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
498 
499 #define SERCOM_USART_RXPL_RXPL_Pos  0            /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
500 #define SERCOM_USART_RXPL_RXPL_Msk  (_U_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos)
501 #define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
502 #define SERCOM_USART_RXPL_MASK      _U_(0xFF)    /**< \brief (SERCOM_USART_RXPL) MASK Register */
503 
504 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM Interrupt Enable Clear -------- */
505 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
506 typedef union {
507   struct {
508     uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Disable    */
509     uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Disable     */
510     uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
511     uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
512   } bit;                       /*!< Structure used for bit  access                  */
513   uint8_t reg;                 /*!< Type      used for register access              */
514 } SERCOM_I2CM_INTENCLR_Type;
515 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
516 
517 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS Interrupt Enable Clear -------- */
518 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
519 typedef union {
520   struct {
521     uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Disable    */
522     uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Disable    */
523     uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Disable             */
524     uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
525     uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
526   } bit;                       /*!< Structure used for bit  access                  */
527   uint8_t reg;                 /*!< Type      used for register access              */
528 } SERCOM_I2CS_INTENCLR_Type;
529 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
530 
531 /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) SPI SPI Interrupt Enable Clear -------- */
532 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
533 typedef union {
534   struct {
535     uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
536     uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
537     uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
538     uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Disable */
539     uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
540     uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
541   } bit;                       /*!< Structure used for bit  access                  */
542   uint8_t reg;                 /*!< Type      used for register access              */
543 } SERCOM_SPI_INTENCLR_Type;
544 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
545 
546 #define SERCOM_SPI_INTENCLR_OFFSET  0x14         /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
547 #define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
548 
549 #define SERCOM_SPI_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
550 #define SERCOM_SPI_INTENCLR_DRE     (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos)
551 #define SERCOM_SPI_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
552 #define SERCOM_SPI_INTENCLR_TXC     (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos)
553 #define SERCOM_SPI_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
554 #define SERCOM_SPI_INTENCLR_RXC     (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos)
555 #define SERCOM_SPI_INTENCLR_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
556 #define SERCOM_SPI_INTENCLR_SSL     (_U_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos)
557 #define SERCOM_SPI_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
558 #define SERCOM_SPI_INTENCLR_ERROR   (_U_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos)
559 #define SERCOM_SPI_INTENCLR_MASK    _U_(0x8F)    /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
560 
561 /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) USART USART Interrupt Enable Clear -------- */
562 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
563 typedef union {
564   struct {
565     uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
566     uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
567     uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
568     uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Disable    */
569     uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Disable */
570     uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Disable   */
571     uint8_t  :1;               /*!< bit:      6  Reserved                           */
572     uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
573   } bit;                       /*!< Structure used for bit  access                  */
574   uint8_t reg;                 /*!< Type      used for register access              */
575 } SERCOM_USART_INTENCLR_Type;
576 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
577 
578 #define SERCOM_USART_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
579 #define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
580 
581 #define SERCOM_USART_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
582 #define SERCOM_USART_INTENCLR_DRE   (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos)
583 #define SERCOM_USART_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
584 #define SERCOM_USART_INTENCLR_TXC   (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos)
585 #define SERCOM_USART_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
586 #define SERCOM_USART_INTENCLR_RXC   (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos)
587 #define SERCOM_USART_INTENCLR_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
588 #define SERCOM_USART_INTENCLR_RXS   (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos)
589 #define SERCOM_USART_INTENCLR_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
590 #define SERCOM_USART_INTENCLR_CTSIC (_U_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos)
591 #define SERCOM_USART_INTENCLR_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
592 #define SERCOM_USART_INTENCLR_RXBRK (_U_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos)
593 #define SERCOM_USART_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
594 #define SERCOM_USART_INTENCLR_ERROR (_U_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos)
595 #define SERCOM_USART_INTENCLR_MASK  _U_(0xBF)    /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
596 
597 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM Interrupt Enable Set -------- */
598 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
599 typedef union {
600   struct {
601     uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Enable     */
602     uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Enable      */
603     uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
604     uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
605   } bit;                       /*!< Structure used for bit  access                  */
606   uint8_t reg;                 /*!< Type      used for register access              */
607 } SERCOM_I2CM_INTENSET_Type;
608 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
609 
610 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS Interrupt Enable Set -------- */
611 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
612 typedef union {
613   struct {
614     uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Enable     */
615     uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Enable     */
616     uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Enable              */
617     uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
618     uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
619   } bit;                       /*!< Structure used for bit  access                  */
620   uint8_t reg;                 /*!< Type      used for register access              */
621 } SERCOM_I2CS_INTENSET_Type;
622 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
623 
624 /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W  8) SPI SPI Interrupt Enable Set -------- */
625 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
626 typedef union {
627   struct {
628     uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
629     uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
630     uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
631     uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Enable  */
632     uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
633     uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
634   } bit;                       /*!< Structure used for bit  access                  */
635   uint8_t reg;                 /*!< Type      used for register access              */
636 } SERCOM_SPI_INTENSET_Type;
637 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
638 
639 #define SERCOM_SPI_INTENSET_OFFSET  0x16         /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
640 #define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
641 
642 #define SERCOM_SPI_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
643 #define SERCOM_SPI_INTENSET_DRE     (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos)
644 #define SERCOM_SPI_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
645 #define SERCOM_SPI_INTENSET_TXC     (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos)
646 #define SERCOM_SPI_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
647 #define SERCOM_SPI_INTENSET_RXC     (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos)
648 #define SERCOM_SPI_INTENSET_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
649 #define SERCOM_SPI_INTENSET_SSL     (_U_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos)
650 #define SERCOM_SPI_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
651 #define SERCOM_SPI_INTENSET_ERROR   (_U_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos)
652 #define SERCOM_SPI_INTENSET_MASK    _U_(0x8F)    /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
653 
654 /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W  8) USART USART Interrupt Enable Set -------- */
655 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
656 typedef union {
657   struct {
658     uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
659     uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
660     uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
661     uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Enable     */
662     uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Enable */
663     uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Enable    */
664     uint8_t  :1;               /*!< bit:      6  Reserved                           */
665     uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
666   } bit;                       /*!< Structure used for bit  access                  */
667   uint8_t reg;                 /*!< Type      used for register access              */
668 } SERCOM_USART_INTENSET_Type;
669 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
670 
671 #define SERCOM_USART_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
672 #define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
673 
674 #define SERCOM_USART_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
675 #define SERCOM_USART_INTENSET_DRE   (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos)
676 #define SERCOM_USART_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
677 #define SERCOM_USART_INTENSET_TXC   (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos)
678 #define SERCOM_USART_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
679 #define SERCOM_USART_INTENSET_RXC   (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos)
680 #define SERCOM_USART_INTENSET_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
681 #define SERCOM_USART_INTENSET_RXS   (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos)
682 #define SERCOM_USART_INTENSET_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
683 #define SERCOM_USART_INTENSET_CTSIC (_U_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos)
684 #define SERCOM_USART_INTENSET_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
685 #define SERCOM_USART_INTENSET_RXBRK (_U_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos)
686 #define SERCOM_USART_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
687 #define SERCOM_USART_INTENSET_ERROR (_U_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos)
688 #define SERCOM_USART_INTENSET_MASK  _U_(0xBF)    /**< \brief (SERCOM_USART_INTENSET) MASK Register */
689 
690 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM Interrupt Flag Status and Clear -------- */
691 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
692 typedef union { // __I to avoid read-modify-write on write-to-clear register
693   struct {
694     __I uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt            */
695     __I uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt             */
696     __I uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
697     __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
698   } bit;                       /*!< Structure used for bit  access                  */
699   uint8_t reg;                 /*!< Type      used for register access              */
700 } SERCOM_I2CM_INTFLAG_Type;
701 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
702 
703 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS Interrupt Flag Status and Clear -------- */
704 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
705 typedef union { // __I to avoid read-modify-write on write-to-clear register
706   struct {
707     __I uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt            */
708     __I uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt            */
709     __I uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt                     */
710     __I uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
711     __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
712   } bit;                       /*!< Structure used for bit  access                  */
713   uint8_t reg;                 /*!< Type      used for register access              */
714 } SERCOM_I2CS_INTFLAG_Type;
715 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
716 
717 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) SPI SPI Interrupt Flag Status and Clear -------- */
718 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
719 typedef union { // __I to avoid read-modify-write on write-to-clear register
720   struct {
721     __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
722     __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
723     __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
724     __I uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Flag    */
725     __I uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
726     __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
727   } bit;                       /*!< Structure used for bit  access                  */
728   uint8_t reg;                 /*!< Type      used for register access              */
729 } SERCOM_SPI_INTFLAG_Type;
730 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
731 
732 #define SERCOM_SPI_INTFLAG_OFFSET   0x18         /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
733 #define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
734 
735 #define SERCOM_SPI_INTFLAG_DRE_Pos  0            /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
736 #define SERCOM_SPI_INTFLAG_DRE      (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos)
737 #define SERCOM_SPI_INTFLAG_TXC_Pos  1            /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
738 #define SERCOM_SPI_INTFLAG_TXC      (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos)
739 #define SERCOM_SPI_INTFLAG_RXC_Pos  2            /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
740 #define SERCOM_SPI_INTFLAG_RXC      (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos)
741 #define SERCOM_SPI_INTFLAG_SSL_Pos  3            /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
742 #define SERCOM_SPI_INTFLAG_SSL      (_U_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos)
743 #define SERCOM_SPI_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
744 #define SERCOM_SPI_INTFLAG_ERROR    (_U_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos)
745 #define SERCOM_SPI_INTFLAG_MASK     _U_(0x8F)    /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
746 
747 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) USART USART Interrupt Flag Status and Clear -------- */
748 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
749 typedef union { // __I to avoid read-modify-write on write-to-clear register
750   struct {
751     __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
752     __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
753     __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
754     __I uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt            */
755     __I uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt */
756     __I uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt           */
757     __I uint8_t  :1;               /*!< bit:      6  Reserved                           */
758     __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
759   } bit;                       /*!< Structure used for bit  access                  */
760   uint8_t reg;                 /*!< Type      used for register access              */
761 } SERCOM_USART_INTFLAG_Type;
762 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
763 
764 #define SERCOM_USART_INTFLAG_OFFSET 0x18         /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
765 #define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
766 
767 #define SERCOM_USART_INTFLAG_DRE_Pos 0            /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
768 #define SERCOM_USART_INTFLAG_DRE    (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos)
769 #define SERCOM_USART_INTFLAG_TXC_Pos 1            /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
770 #define SERCOM_USART_INTFLAG_TXC    (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos)
771 #define SERCOM_USART_INTFLAG_RXC_Pos 2            /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
772 #define SERCOM_USART_INTFLAG_RXC    (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos)
773 #define SERCOM_USART_INTFLAG_RXS_Pos 3            /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
774 #define SERCOM_USART_INTFLAG_RXS    (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos)
775 #define SERCOM_USART_INTFLAG_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
776 #define SERCOM_USART_INTFLAG_CTSIC  (_U_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos)
777 #define SERCOM_USART_INTFLAG_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
778 #define SERCOM_USART_INTFLAG_RXBRK  (_U_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos)
779 #define SERCOM_USART_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
780 #define SERCOM_USART_INTFLAG_ERROR  (_U_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos)
781 #define SERCOM_USART_INTFLAG_MASK   _U_(0xBF)    /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
782 
783 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM Status -------- */
784 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
785 typedef union {
786   struct {
787     uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
788     uint16_t ARBLOST:1;        /*!< bit:      1  Arbitration Lost                   */
789     uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
790     uint16_t :1;               /*!< bit:      3  Reserved                           */
791     uint16_t BUSSTATE:2;       /*!< bit:  4.. 5  Bus State                          */
792     uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
793     uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
794     uint16_t MEXTTOUT:1;       /*!< bit:      8  Master SCL Low Extend Timeout      */
795     uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
796     uint16_t LENERR:1;         /*!< bit:     10  Length Error                       */
797     uint16_t :5;               /*!< bit: 11..15  Reserved                           */
798   } bit;                       /*!< Structure used for bit  access                  */
799   uint16_t reg;                /*!< Type      used for register access              */
800 } SERCOM_I2CM_STATUS_Type;
801 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
802 
803 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS Status -------- */
804 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
805 typedef union {
806   struct {
807     uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
808     uint16_t COLL:1;           /*!< bit:      1  Transmit Collision                 */
809     uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
810     uint16_t DIR:1;            /*!< bit:      3  Read/Write Direction               */
811     uint16_t SR:1;             /*!< bit:      4  Repeated Start                     */
812     uint16_t :1;               /*!< bit:      5  Reserved                           */
813     uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
814     uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
815     uint16_t :1;               /*!< bit:      8  Reserved                           */
816     uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
817     uint16_t HS:1;             /*!< bit:     10  High Speed                         */
818     uint16_t LENERR:1;         /*!< bit:     11  Transaction Length Error           */
819     uint16_t :4;               /*!< bit: 12..15  Reserved                           */
820   } bit;                       /*!< Structure used for bit  access                  */
821   uint16_t reg;                /*!< Type      used for register access              */
822 } SERCOM_I2CS_STATUS_Type;
823 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
824 
825 /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
826 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
827 typedef union {
828   struct {
829     uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
830     uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
831     uint16_t :8;               /*!< bit:  3..10  Reserved                           */
832     uint16_t LENERR:1;         /*!< bit:     11  Transaction Length Error           */
833     uint16_t :4;               /*!< bit: 12..15  Reserved                           */
834   } bit;                       /*!< Structure used for bit  access                  */
835   uint16_t reg;                /*!< Type      used for register access              */
836 } SERCOM_SPI_STATUS_Type;
837 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
838 
839 #define SERCOM_SPI_STATUS_OFFSET    0x1A         /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
840 #define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
841 
842 #define SERCOM_SPI_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
843 #define SERCOM_SPI_STATUS_BUFOVF    (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos)
844 #define SERCOM_SPI_STATUS_LENERR_Pos 11           /**< \brief (SERCOM_SPI_STATUS) Transaction Length Error */
845 #define SERCOM_SPI_STATUS_LENERR    (_U_(0x1) << SERCOM_SPI_STATUS_LENERR_Pos)
846 #define SERCOM_SPI_STATUS_MASK      _U_(0x0804)  /**< \brief (SERCOM_SPI_STATUS) MASK Register */
847 
848 /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
849 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
850 typedef union {
851   struct {
852     uint16_t PERR:1;           /*!< bit:      0  Parity Error                       */
853     uint16_t FERR:1;           /*!< bit:      1  Frame Error                        */
854     uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
855     uint16_t CTS:1;            /*!< bit:      3  Clear To Send                      */
856     uint16_t ISF:1;            /*!< bit:      4  Inconsistent Sync Field            */
857     uint16_t COLL:1;           /*!< bit:      5  Collision Detected                 */
858     uint16_t TXE:1;            /*!< bit:      6  Transmitter Empty                  */
859     uint16_t ITER:1;           /*!< bit:      7  Maximum Number of Repetitions Reached */
860     uint16_t :8;               /*!< bit:  8..15  Reserved                           */
861   } bit;                       /*!< Structure used for bit  access                  */
862   uint16_t reg;                /*!< Type      used for register access              */
863 } SERCOM_USART_STATUS_Type;
864 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
865 
866 #define SERCOM_USART_STATUS_OFFSET  0x1A         /**< \brief (SERCOM_USART_STATUS offset) USART Status */
867 #define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
868 
869 #define SERCOM_USART_STATUS_PERR_Pos 0            /**< \brief (SERCOM_USART_STATUS) Parity Error */
870 #define SERCOM_USART_STATUS_PERR    (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos)
871 #define SERCOM_USART_STATUS_FERR_Pos 1            /**< \brief (SERCOM_USART_STATUS) Frame Error */
872 #define SERCOM_USART_STATUS_FERR    (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos)
873 #define SERCOM_USART_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
874 #define SERCOM_USART_STATUS_BUFOVF  (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos)
875 #define SERCOM_USART_STATUS_CTS_Pos 3            /**< \brief (SERCOM_USART_STATUS) Clear To Send */
876 #define SERCOM_USART_STATUS_CTS     (_U_(0x1) << SERCOM_USART_STATUS_CTS_Pos)
877 #define SERCOM_USART_STATUS_ISF_Pos 4            /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
878 #define SERCOM_USART_STATUS_ISF     (_U_(0x1) << SERCOM_USART_STATUS_ISF_Pos)
879 #define SERCOM_USART_STATUS_COLL_Pos 5            /**< \brief (SERCOM_USART_STATUS) Collision Detected */
880 #define SERCOM_USART_STATUS_COLL    (_U_(0x1) << SERCOM_USART_STATUS_COLL_Pos)
881 #define SERCOM_USART_STATUS_TXE_Pos 6            /**< \brief (SERCOM_USART_STATUS) Transmitter Empty */
882 #define SERCOM_USART_STATUS_TXE     (_U_(0x1) << SERCOM_USART_STATUS_TXE_Pos)
883 #define SERCOM_USART_STATUS_ITER_Pos 7            /**< \brief (SERCOM_USART_STATUS) Maximum Number of Repetitions Reached */
884 #define SERCOM_USART_STATUS_ITER    (_U_(0x1) << SERCOM_USART_STATUS_ITER_Pos)
885 #define SERCOM_USART_STATUS_MASK    _U_(0x00FF)  /**< \brief (SERCOM_USART_STATUS) MASK Register */
886 
887 /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CM Synchronization Busy -------- */
888 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
889 typedef union {
890   struct {
891     uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
892     uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
893     uint32_t SYSOP:1;          /*!< bit:      2  System Operation Synchronization Busy */
894     uint32_t :1;               /*!< bit:      3  Reserved                           */
895     uint32_t LENGTH:1;         /*!< bit:      4  Length Synchronization Busy        */
896     uint32_t :27;              /*!< bit:  5..31  Reserved                           */
897   } bit;                       /*!< Structure used for bit  access                  */
898   uint32_t reg;                /*!< Type      used for register access              */
899 } SERCOM_I2CM_SYNCBUSY_Type;
900 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
901 
902 /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CS Synchronization Busy -------- */
903 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
904 typedef union {
905   struct {
906     uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
907     uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
908     uint32_t :2;               /*!< bit:  2.. 3  Reserved                           */
909     uint32_t LENGTH:1;         /*!< bit:      4  Length Synchronization Busy        */
910     uint32_t :27;              /*!< bit:  5..31  Reserved                           */
911   } bit;                       /*!< Structure used for bit  access                  */
912   uint32_t reg;                /*!< Type      used for register access              */
913 } SERCOM_I2CS_SYNCBUSY_Type;
914 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
915 
916 /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) SPI SPI Synchronization Busy -------- */
917 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
918 typedef union {
919   struct {
920     uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
921     uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
922     uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
923     uint32_t :1;               /*!< bit:      3  Reserved                           */
924     uint32_t LENGTH:1;         /*!< bit:      4  LENGTH Synchronization Busy        */
925     uint32_t :27;              /*!< bit:  5..31  Reserved                           */
926   } bit;                       /*!< Structure used for bit  access                  */
927   uint32_t reg;                /*!< Type      used for register access              */
928 } SERCOM_SPI_SYNCBUSY_Type;
929 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
930 
931 #define SERCOM_SPI_SYNCBUSY_OFFSET  0x1C         /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
932 #define SERCOM_SPI_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
933 
934 #define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
935 #define SERCOM_SPI_SYNCBUSY_SWRST   (_U_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
936 #define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
937 #define SERCOM_SPI_SYNCBUSY_ENABLE  (_U_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
938 #define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
939 #define SERCOM_SPI_SYNCBUSY_CTRLB   (_U_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
940 #define SERCOM_SPI_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_SPI_SYNCBUSY) LENGTH Synchronization Busy */
941 #define SERCOM_SPI_SYNCBUSY_LENGTH  (_U_(0x1) << SERCOM_SPI_SYNCBUSY_LENGTH_Pos)
942 #define SERCOM_SPI_SYNCBUSY_MASK    _U_(0x00000017) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
943 
944 /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) USART USART Synchronization Busy -------- */
945 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
946 typedef union {
947   struct {
948     uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
949     uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
950     uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
951     uint32_t RXERRCNT:1;       /*!< bit:      3  RXERRCNT Synchronization Busy      */
952     uint32_t LENGTH:1;         /*!< bit:      4  LENGTH Synchronization Busy        */
953     uint32_t :27;              /*!< bit:  5..31  Reserved                           */
954   } bit;                       /*!< Structure used for bit  access                  */
955   uint32_t reg;                /*!< Type      used for register access              */
956 } SERCOM_USART_SYNCBUSY_Type;
957 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
958 
959 #define SERCOM_USART_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
960 #define SERCOM_USART_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
961 
962 #define SERCOM_USART_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
963 #define SERCOM_USART_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos)
964 #define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
965 #define SERCOM_USART_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
966 #define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
967 #define SERCOM_USART_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
968 #define SERCOM_USART_SYNCBUSY_RXERRCNT_Pos 3            /**< \brief (SERCOM_USART_SYNCBUSY) RXERRCNT Synchronization Busy */
969 #define SERCOM_USART_SYNCBUSY_RXERRCNT (_U_(0x1) << SERCOM_USART_SYNCBUSY_RXERRCNT_Pos)
970 #define SERCOM_USART_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_USART_SYNCBUSY) LENGTH Synchronization Busy */
971 #define SERCOM_USART_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_USART_SYNCBUSY_LENGTH_Pos)
972 #define SERCOM_USART_SYNCBUSY_MASK  _U_(0x0000001F) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
973 
974 /* -------- SERCOM_USART_RXERRCNT : (SERCOM Offset: 0x20) (R/   8) USART USART Receive Error Count -------- */
975 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
976 typedef union {
977   uint8_t reg;                 /*!< Type      used for register access              */
978 } SERCOM_USART_RXERRCNT_Type;
979 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
980 
981 #define SERCOM_USART_RXERRCNT_OFFSET 0x20         /**< \brief (SERCOM_USART_RXERRCNT offset) USART Receive Error Count */
982 #define SERCOM_USART_RXERRCNT_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_RXERRCNT reset_value) USART Receive Error Count */
983 #define SERCOM_USART_RXERRCNT_MASK  _U_(0xFF)    /**< \brief (SERCOM_USART_RXERRCNT) MASK Register */
984 
985 /* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS Length -------- */
986 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
987 typedef union {
988   struct {
989     uint16_t LEN:8;            /*!< bit:  0.. 7  Data Length                        */
990     uint16_t LENEN:1;          /*!< bit:      8  Data Length Enable                 */
991     uint16_t :7;               /*!< bit:  9..15  Reserved                           */
992   } bit;                       /*!< Structure used for bit  access                  */
993   uint16_t reg;                /*!< Type      used for register access              */
994 } SERCOM_I2CS_LENGTH_Type;
995 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
996 
997 /* -------- SERCOM_SPI_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPI SPI Length -------- */
998 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
999 typedef union {
1000   struct {
1001     uint16_t LEN:8;            /*!< bit:  0.. 7  Data Length                        */
1002     uint16_t LENEN:1;          /*!< bit:      8  Data Length Enable                 */
1003     uint16_t :7;               /*!< bit:  9..15  Reserved                           */
1004   } bit;                       /*!< Structure used for bit  access                  */
1005   uint16_t reg;                /*!< Type      used for register access              */
1006 } SERCOM_SPI_LENGTH_Type;
1007 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1008 
1009 #define SERCOM_SPI_LENGTH_OFFSET    0x22         /**< \brief (SERCOM_SPI_LENGTH offset) SPI Length */
1010 #define SERCOM_SPI_LENGTH_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_SPI_LENGTH reset_value) SPI Length */
1011 
1012 #define SERCOM_SPI_LENGTH_LEN_Pos   0            /**< \brief (SERCOM_SPI_LENGTH) Data Length */
1013 #define SERCOM_SPI_LENGTH_LEN_Msk   (_U_(0xFF) << SERCOM_SPI_LENGTH_LEN_Pos)
1014 #define SERCOM_SPI_LENGTH_LEN(value) (SERCOM_SPI_LENGTH_LEN_Msk & ((value) << SERCOM_SPI_LENGTH_LEN_Pos))
1015 #define SERCOM_SPI_LENGTH_LENEN_Pos 8            /**< \brief (SERCOM_SPI_LENGTH) Data Length Enable */
1016 #define SERCOM_SPI_LENGTH_LENEN     (_U_(0x1) << SERCOM_SPI_LENGTH_LENEN_Pos)
1017 #define SERCOM_SPI_LENGTH_MASK      _U_(0x01FF)  /**< \brief (SERCOM_SPI_LENGTH) MASK Register */
1018 
1019 /* -------- SERCOM_USART_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART USART Length -------- */
1020 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1021 typedef union {
1022   struct {
1023     uint16_t LEN:8;            /*!< bit:  0.. 7  Data Length                        */
1024     uint16_t LENEN:2;          /*!< bit:  8.. 9  Data Length Enable                 */
1025     uint16_t :6;               /*!< bit: 10..15  Reserved                           */
1026   } bit;                       /*!< Structure used for bit  access                  */
1027   uint16_t reg;                /*!< Type      used for register access              */
1028 } SERCOM_USART_LENGTH_Type;
1029 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1030 
1031 #define SERCOM_USART_LENGTH_OFFSET  0x22         /**< \brief (SERCOM_USART_LENGTH offset) USART Length */
1032 #define SERCOM_USART_LENGTH_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_USART_LENGTH reset_value) USART Length */
1033 
1034 #define SERCOM_USART_LENGTH_LEN_Pos 0            /**< \brief (SERCOM_USART_LENGTH) Data Length */
1035 #define SERCOM_USART_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_USART_LENGTH_LEN_Pos)
1036 #define SERCOM_USART_LENGTH_LEN(value) (SERCOM_USART_LENGTH_LEN_Msk & ((value) << SERCOM_USART_LENGTH_LEN_Pos))
1037 #define SERCOM_USART_LENGTH_LENEN_Pos 8            /**< \brief (SERCOM_USART_LENGTH) Data Length Enable */
1038 #define SERCOM_USART_LENGTH_LENEN_Msk (_U_(0x3) << SERCOM_USART_LENGTH_LENEN_Pos)
1039 #define SERCOM_USART_LENGTH_LENEN(value) (SERCOM_USART_LENGTH_LENEN_Msk & ((value) << SERCOM_USART_LENGTH_LENEN_Pos))
1040 #define SERCOM_USART_LENGTH_MASK    _U_(0x03FF)  /**< \brief (SERCOM_USART_LENGTH) MASK Register */
1041 
1042 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM Address -------- */
1043 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1044 typedef union {
1045   struct {
1046     uint32_t ADDR:11;          /*!< bit:  0..10  Address Value                      */
1047     uint32_t :2;               /*!< bit: 11..12  Reserved                           */
1048     uint32_t LENEN:1;          /*!< bit:     13  Length Enable                      */
1049     uint32_t HS:1;             /*!< bit:     14  High Speed Mode                    */
1050     uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
1051     uint32_t LEN:8;            /*!< bit: 16..23  Length                             */
1052     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
1053   } bit;                       /*!< Structure used for bit  access                  */
1054   uint32_t reg;                /*!< Type      used for register access              */
1055 } SERCOM_I2CM_ADDR_Type;
1056 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1057 
1058 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS Address -------- */
1059 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1060 typedef union {
1061   struct {
1062     uint32_t GENCEN:1;         /*!< bit:      0  General Call Address Enable        */
1063     uint32_t ADDR:10;          /*!< bit:  1..10  Address Value                      */
1064     uint32_t :4;               /*!< bit: 11..14  Reserved                           */
1065     uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
1066     uint32_t :1;               /*!< bit:     16  Reserved                           */
1067     uint32_t ADDRMASK:10;      /*!< bit: 17..26  Address Mask                       */
1068     uint32_t :5;               /*!< bit: 27..31  Reserved                           */
1069   } bit;                       /*!< Structure used for bit  access                  */
1070   uint32_t reg;                /*!< Type      used for register access              */
1071 } SERCOM_I2CS_ADDR_Type;
1072 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1073 
1074 /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
1075 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1076 typedef union {
1077   struct {
1078     uint32_t ADDR:8;           /*!< bit:  0.. 7  Address Value                      */
1079     uint32_t :8;               /*!< bit:  8..15  Reserved                           */
1080     uint32_t ADDRMASK:8;       /*!< bit: 16..23  Address Mask                       */
1081     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
1082   } bit;                       /*!< Structure used for bit  access                  */
1083   uint32_t reg;                /*!< Type      used for register access              */
1084 } SERCOM_SPI_ADDR_Type;
1085 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1086 
1087 #define SERCOM_SPI_ADDR_OFFSET      0x24         /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
1088 #define SERCOM_SPI_ADDR_RESETVALUE  _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
1089 
1090 #define SERCOM_SPI_ADDR_ADDR_Pos    0            /**< \brief (SERCOM_SPI_ADDR) Address Value */
1091 #define SERCOM_SPI_ADDR_ADDR_Msk    (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos)
1092 #define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
1093 #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16           /**< \brief (SERCOM_SPI_ADDR) Address Mask */
1094 #define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos)
1095 #define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
1096 #define SERCOM_SPI_ADDR_MASK        _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */
1097 
1098 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CM Data -------- */
1099 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1100 typedef union {
1101   struct {
1102     uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
1103   } bit;                       /*!< Structure used for bit  access                  */
1104   uint32_t reg;                /*!< Type      used for register access              */
1105 } SERCOM_I2CM_DATA_Type;
1106 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1107 
1108 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS Data -------- */
1109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1110 typedef union {
1111   struct {
1112     uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
1113   } bit;                       /*!< Structure used for bit  access                  */
1114   uint32_t reg;                /*!< Type      used for register access              */
1115 } SERCOM_I2CS_DATA_Type;
1116 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1117 
1118 /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
1119 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1120 typedef union {
1121   struct {
1122     uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
1123   } bit;                       /*!< Structure used for bit  access                  */
1124   uint32_t reg;                /*!< Type      used for register access              */
1125 } SERCOM_SPI_DATA_Type;
1126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1127 
1128 #define SERCOM_SPI_DATA_OFFSET      0x28         /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
1129 #define SERCOM_SPI_DATA_RESETVALUE  _U_(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
1130 
1131 #define SERCOM_SPI_DATA_DATA_Pos    0            /**< \brief (SERCOM_SPI_DATA) Data Value */
1132 #define SERCOM_SPI_DATA_DATA_Msk    (_U_(0xFFFFFFFF) << SERCOM_SPI_DATA_DATA_Pos)
1133 #define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
1134 #define SERCOM_SPI_DATA_MASK        _U_(0xFFFFFFFF) /**< \brief (SERCOM_SPI_DATA) MASK Register */
1135 
1136 /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 32) USART USART Data -------- */
1137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1138 typedef union {
1139   struct {
1140     uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
1141   } bit;                       /*!< Structure used for bit  access                  */
1142   uint32_t reg;                /*!< Type      used for register access              */
1143 } SERCOM_USART_DATA_Type;
1144 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1145 
1146 #define SERCOM_USART_DATA_OFFSET    0x28         /**< \brief (SERCOM_USART_DATA offset) USART Data */
1147 #define SERCOM_USART_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
1148 
1149 #define SERCOM_USART_DATA_DATA_Pos  0            /**< \brief (SERCOM_USART_DATA) Data Value */
1150 #define SERCOM_USART_DATA_DATA_Msk  (_U_(0xFFFFFFFF) << SERCOM_USART_DATA_DATA_Pos)
1151 #define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
1152 #define SERCOM_USART_DATA_MASK      _U_(0xFFFFFFFF) /**< \brief (SERCOM_USART_DATA) MASK Register */
1153 
1154 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM Debug Control -------- */
1155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1156 typedef union {
1157   struct {
1158     uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
1159     uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
1160   } bit;                       /*!< Structure used for bit  access                  */
1161   uint8_t reg;                 /*!< Type      used for register access              */
1162 } SERCOM_I2CM_DBGCTRL_Type;
1163 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1164 
1165 /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) SPI SPI Debug Control -------- */
1166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1167 typedef union {
1168   struct {
1169     uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
1170     uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
1171   } bit;                       /*!< Structure used for bit  access                  */
1172   uint8_t reg;                 /*!< Type      used for register access              */
1173 } SERCOM_SPI_DBGCTRL_Type;
1174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1175 
1176 #define SERCOM_SPI_DBGCTRL_OFFSET   0x30         /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
1177 #define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
1178 
1179 #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
1180 #define SERCOM_SPI_DBGCTRL_DBGSTOP  (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
1181 #define SERCOM_SPI_DBGCTRL_MASK     _U_(0x01)    /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
1182 
1183 /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) USART USART Debug Control -------- */
1184 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1185 typedef union {
1186   struct {
1187     uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
1188     uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
1189   } bit;                       /*!< Structure used for bit  access                  */
1190   uint8_t reg;                 /*!< Type      used for register access              */
1191 } SERCOM_USART_DBGCTRL_Type;
1192 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1193 
1194 #define SERCOM_USART_DBGCTRL_OFFSET 0x30         /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
1195 #define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
1196 
1197 #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
1198 #define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
1199 #define SERCOM_USART_DBGCTRL_MASK   _U_(0x01)    /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
1200 
1201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1202 typedef struct { /* I2C Master Mode */
1203   __IO SERCOM_I2CM_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
1204   __IO SERCOM_I2CM_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
1205   __IO SERCOM_I2CM_CTRLC_Type    CTRLC;       /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */
1206   __IO SERCOM_I2CM_BAUD_Type     BAUD;        /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
1207        RoReg8                    Reserved1[0x4];
1208   __IO SERCOM_I2CM_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
1209        RoReg8                    Reserved2[0x1];
1210   __IO SERCOM_I2CM_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
1211        RoReg8                    Reserved3[0x1];
1212   __IO SERCOM_I2CM_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
1213        RoReg8                    Reserved4[0x1];
1214   __IO SERCOM_I2CM_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
1215   __I  SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CM Synchronization Busy */
1216        RoReg8                    Reserved5[0x4];
1217   __IO SERCOM_I2CM_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
1218   __IO SERCOM_I2CM_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W 32) I2CM Data */
1219        RoReg8                    Reserved6[0x4];
1220   __IO SERCOM_I2CM_DBGCTRL_Type  DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) I2CM Debug Control */
1221 } SercomI2cm;
1222 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1223 
1224 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1225 typedef struct { /* I2C Slave Mode */
1226   __IO SERCOM_I2CS_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
1227   __IO SERCOM_I2CS_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
1228   __IO SERCOM_I2CS_CTRLC_Type    CTRLC;       /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */
1229        RoReg8                    Reserved1[0x8];
1230   __IO SERCOM_I2CS_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
1231        RoReg8                    Reserved2[0x1];
1232   __IO SERCOM_I2CS_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
1233        RoReg8                    Reserved3[0x1];
1234   __IO SERCOM_I2CS_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
1235        RoReg8                    Reserved4[0x1];
1236   __IO SERCOM_I2CS_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
1237   __I  SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CS Synchronization Busy */
1238        RoReg8                    Reserved5[0x2];
1239   __IO SERCOM_I2CS_LENGTH_Type   LENGTH;      /**< \brief Offset: 0x22 (R/W 16) I2CS Length */
1240   __IO SERCOM_I2CS_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
1241   __IO SERCOM_I2CS_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W 32) I2CS Data */
1242 } SercomI2cs;
1243 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1244 
1245 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1246 typedef struct { /* SPI Mode */
1247   __IO SERCOM_SPI_CTRLA_Type     CTRLA;       /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
1248   __IO SERCOM_SPI_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
1249   __IO SERCOM_SPI_CTRLC_Type     CTRLC;       /**< \brief Offset: 0x08 (R/W 32) SPI Control C */
1250   __IO SERCOM_SPI_BAUD_Type      BAUD;        /**< \brief Offset: 0x0C (R/W  8) SPI Baud Rate */
1251        RoReg8                    Reserved1[0x7];
1252   __IO SERCOM_SPI_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) SPI Interrupt Enable Clear */
1253        RoReg8                    Reserved2[0x1];
1254   __IO SERCOM_SPI_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x16 (R/W  8) SPI Interrupt Enable Set */
1255        RoReg8                    Reserved3[0x1];
1256   __IO SERCOM_SPI_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) SPI Interrupt Flag Status and Clear */
1257        RoReg8                    Reserved4[0x1];
1258   __IO SERCOM_SPI_STATUS_Type    STATUS;      /**< \brief Offset: 0x1A (R/W 16) SPI Status */
1259   __I  SERCOM_SPI_SYNCBUSY_Type  SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) SPI Synchronization Busy */
1260        RoReg8                    Reserved5[0x2];
1261   __IO SERCOM_SPI_LENGTH_Type    LENGTH;      /**< \brief Offset: 0x22 (R/W 16) SPI Length */
1262   __IO SERCOM_SPI_ADDR_Type      ADDR;        /**< \brief Offset: 0x24 (R/W 32) SPI Address */
1263   __IO SERCOM_SPI_DATA_Type      DATA;        /**< \brief Offset: 0x28 (R/W 32) SPI Data */
1264        RoReg8                    Reserved6[0x4];
1265   __IO SERCOM_SPI_DBGCTRL_Type   DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) SPI Debug Control */
1266 } SercomSpi;
1267 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1268 
1269 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1270 typedef struct { /* USART Mode */
1271   __IO SERCOM_USART_CTRLA_Type   CTRLA;       /**< \brief Offset: 0x00 (R/W 32) USART Control A */
1272   __IO SERCOM_USART_CTRLB_Type   CTRLB;       /**< \brief Offset: 0x04 (R/W 32) USART Control B */
1273   __IO SERCOM_USART_CTRLC_Type   CTRLC;       /**< \brief Offset: 0x08 (R/W 32) USART Control C */
1274   __IO SERCOM_USART_BAUD_Type    BAUD;        /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
1275   __IO SERCOM_USART_RXPL_Type    RXPL;        /**< \brief Offset: 0x0E (R/W  8) USART Receive Pulse Length */
1276        RoReg8                    Reserved1[0x5];
1277   __IO SERCOM_USART_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) USART Interrupt Enable Clear */
1278        RoReg8                    Reserved2[0x1];
1279   __IO SERCOM_USART_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) USART Interrupt Enable Set */
1280        RoReg8                    Reserved3[0x1];
1281   __IO SERCOM_USART_INTFLAG_Type INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) USART Interrupt Flag Status and Clear */
1282        RoReg8                    Reserved4[0x1];
1283   __IO SERCOM_USART_STATUS_Type  STATUS;      /**< \brief Offset: 0x1A (R/W 16) USART Status */
1284   __I  SERCOM_USART_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) USART Synchronization Busy */
1285   __I  SERCOM_USART_RXERRCNT_Type RXERRCNT;    /**< \brief Offset: 0x20 (R/   8) USART Receive Error Count */
1286        RoReg8                    Reserved5[0x1];
1287   __IO SERCOM_USART_LENGTH_Type  LENGTH;      /**< \brief Offset: 0x22 (R/W 16) USART Length */
1288        RoReg8                    Reserved6[0x4];
1289   __IO SERCOM_USART_DATA_Type    DATA;        /**< \brief Offset: 0x28 (R/W 32) USART Data */
1290        RoReg8                    Reserved7[0x4];
1291   __IO SERCOM_USART_DBGCTRL_Type DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) USART Debug Control */
1292 } SercomUsart;
1293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1294 
1295 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1296 typedef union {
1297        SercomI2cm                I2CM;        /**< \brief Offset: 0x00 I2C Master Mode */
1298        SercomI2cs                I2CS;        /**< \brief Offset: 0x00 I2C Slave Mode */
1299        SercomSpi                 SPI;         /**< \brief Offset: 0x00 SPI Mode */
1300        SercomUsart               USART;       /**< \brief Offset: 0x00 USART Mode */
1301 } Sercom;
1302 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1303 
1304 
1305 
1306 
1307 
1308 
1309 
1310 
1311 
1312 
1313 
1314 
1315 
1316 
1317 #endif /* _MICROCHIP_PIC32CXSG_SERCOM_COMPONENT_FIXUP_H_ */
1318