1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_CCL_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_CCL_COMPONENT_FIXUP_H_ 9 10 /* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 17 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 18 uint8_t :1; /*!< bit: 7 Reserved */ 19 } bit; /*!< Structure used for bit access */ 20 uint8_t reg; /*!< Type used for register access */ 21 } CCL_CTRL_Type; 22 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 23 24 /* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ 25 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 26 typedef union { 27 struct { 28 uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ 29 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 30 } bit; /*!< Structure used for bit access */ 31 uint8_t reg; /*!< Type used for register access */ 32 } CCL_SEQCTRL_Type; 33 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 34 35 /* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ 36 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 37 typedef union { 38 struct { 39 uint32_t :1; /*!< bit: 0 Reserved */ 40 uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ 41 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 42 uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ 43 uint32_t :1; /*!< bit: 6 Reserved */ 44 uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ 45 uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ 46 uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ 47 uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ 48 uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ 49 uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ 50 uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ 51 uint32_t :1; /*!< bit: 23 Reserved */ 52 uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ 53 } bit; /*!< Structure used for bit access */ 54 uint32_t reg; /*!< Type used for register access */ 55 } CCL_LUTCTRL_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 /** \brief CCL hardware registers */ 59 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 60 typedef struct { 61 __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ 62 RoReg8 Reserved1[0x3]; 63 __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ 64 RoReg8 Reserved2[0x2]; 65 __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ 66 } Ccl; 67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 #endif /* _MICROCHIP_PIC32CXSG_CCL_COMPONENT_FIXUP_H_ */ 70
