1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Register bit offsets and masks definitions for PolarFire SoC MSS system 7 * services 8 */ 9 #ifndef MSS_SYS_SERVICES_REGS_H_ 10 #define MSS_SYS_SERVICES_REGS_H_ 11 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 /***************SCBCTRL SERVICES_CR register*************************/ 17 18 #define SCBCTRL_SERVICESCR_REQ (0u) 19 #define SCBCTRL_SERVICESCR_REQ_MASK (1u << SCBCTRL_SERVICESCR_REQ) 20 21 #define SCBCTRL_SERVICESCR_BUSY (1u) 22 #define SCBCTRL_SERVICESCR_BUSY_MASK (1u << SCBCTRL_SERVICESCR_BUSY) 23 24 #define SCBCTRL_SERVICESCR_ABORT (2u) 25 #define SCBCTRL_SERVICESCR_ABORT_MASK (1u << SCBCTRL_SERVICESCR_ABORT) 26 27 #define SCBCTRL_SERVICESCR_NOTIFY (3u) 28 #define SCBCTRL_SERVICESCR_NOTIFY_MASK (1u << SCBCTRL_SERVICESCR_NOTIFY) 29 30 #define SCBCTRL_SERVICESCR_COMMAND (16u) 31 #define SCBCTRL_SERVICESCR_COMMAND_MASK (0xFFFFu << SCBCTRL_SERVICESCR_COMMAND) 32 33 34 /***************SCBCTRL SERVICES_SR registers*************************/ 35 36 #define SCBCTRL_SERVICESSR_REQ (0u) 37 #define SCBCTRL_SERVICESSR_REQ_MASK (1u << SCBCTRL_SERVICESSR_REQ) 38 39 #define SCBCTRL_SERVICESSR_BUSY (1u) 40 #define SCBCTRL_SERVICESSR_BUSY_MASK (1u << SCBCTRL_SERVICESSR_BUSY) 41 42 #define SCBCTRL_SERVICESSR_ABORT (2u) 43 #define SCBCTRL_SERVICESSR_ABORT_MASK (1u << SCBCTRL_SERVICESSR_ABORT) 44 45 #define SCBCTRL_SERVICESSR_NOTIFY (3u) 46 #define SCBCTRL_SERVICESSR_NOTIFY_MASK (1u << SCBCTRL_SERVICESSR_NOTIFY) 47 48 #define SCBCTRL_SERVICESSR_STATUS (16u) 49 #define SCBCTRL_SERVICESSR_STATUS_MASK (0xFFFFu << SCBCTRL_SERVICESSR_STATUS) 50 51 #ifdef __cplusplus 52 } 53 #endif 54 55 #endif /* MSS_SYS_SERVICES_REGS_H_ */ 56