1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_ADC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_ADC_COMPONENT_FIXUP_H_ 9 10 /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint16_t :1; /*!< bit: 2 Reserved */ 17 uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ 18 uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ 19 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 20 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 21 uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ 22 uint16_t :4; /*!< bit: 11..14 Reserved */ 23 uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ 24 } bit; /*!< Structure used for bit access */ 25 uint16_t reg; /*!< Type used for register access */ 26 } ADC_CTRLA_Type; 27 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 28 29 /* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ 30 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 31 typedef union { 32 struct { 33 uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ 34 uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ 35 uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ 36 uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ 37 uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ 38 uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ 39 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 40 } bit; /*!< Structure used for bit access */ 41 uint8_t reg; /*!< Type used for register access */ 42 } ADC_EVCTRL_Type; 43 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 44 45 /* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ 46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 47 typedef union { 48 struct { 49 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 50 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 51 } bit; /*!< Structure used for bit access */ 52 uint8_t reg; /*!< Type used for register access */ 53 } ADC_DBGCTRL_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 /* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ 56 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 57 typedef union { 58 struct { 59 uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ 60 uint16_t :2; /*!< bit: 5.. 6 Reserved */ 61 uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ 62 uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ 63 uint16_t :2; /*!< bit: 13..14 Reserved */ 64 uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ 65 } bit; /*!< Structure used for bit access */ 66 uint16_t reg; /*!< Type used for register access */ 67 } ADC_INPUTCTRL_Type; 68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 /* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ 71 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 72 typedef union { 73 struct { 74 uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ 75 uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ 76 uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ 77 uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ 78 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 79 uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ 80 uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ 81 uint16_t :4; /*!< bit: 12..15 Reserved */ 82 } bit; /*!< Structure used for bit access */ 83 uint16_t reg; /*!< Type used for register access */ 84 } ADC_CTRLB_Type; 85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 87 /* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ 88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 89 typedef union { 90 struct { 91 uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ 92 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 93 uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ 94 } bit; /*!< Structure used for bit access */ 95 uint8_t reg; /*!< Type used for register access */ 96 } ADC_REFCTRL_Type; 97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 /* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ 100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 101 typedef union { 102 struct { 103 uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ 104 uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ 105 uint8_t :1; /*!< bit: 7 Reserved */ 106 } bit; /*!< Structure used for bit access */ 107 uint8_t reg; /*!< Type used for register access */ 108 } ADC_AVGCTRL_Type; 109 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 111 /* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ 112 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 113 typedef union { 114 struct { 115 uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ 116 uint8_t :1; /*!< bit: 6 Reserved */ 117 uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ 118 } bit; /*!< Structure used for bit access */ 119 uint8_t reg; /*!< Type used for register access */ 120 } ADC_SAMPCTRL_Type; 121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 122 123 /* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ 124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 125 typedef union { 126 struct { 127 uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ 128 } bit; /*!< Structure used for bit access */ 129 uint16_t reg; /*!< Type used for register access */ 130 } ADC_WINLT_Type; 131 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 132 133 /* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ 134 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 135 typedef union { 136 struct { 137 uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ 138 } bit; /*!< Structure used for bit access */ 139 uint16_t reg; /*!< Type used for register access */ 140 } ADC_WINUT_Type; 141 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 142 /* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ 143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 144 typedef union { 145 struct { 146 uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ 147 uint16_t :4; /*!< bit: 12..15 Reserved */ 148 } bit; /*!< Structure used for bit access */ 149 uint16_t reg; /*!< Type used for register access */ 150 } ADC_GAINCORR_Type; 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 152 /* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef union { 155 struct { 156 uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ 157 uint16_t :4; /*!< bit: 12..15 Reserved */ 158 } bit; /*!< Structure used for bit access */ 159 uint16_t reg; /*!< Type used for register access */ 160 } ADC_OFFSETCORR_Type; 161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 162 163 /* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ 164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 165 typedef union { 166 struct { 167 uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ 168 uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ 169 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 170 } bit; /*!< Structure used for bit access */ 171 uint8_t reg; /*!< Type used for register access */ 172 } ADC_SWTRIG_Type; 173 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 174 175 /* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ 176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 177 typedef union { 178 struct { 179 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ 180 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ 181 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ 182 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 183 } bit; /*!< Structure used for bit access */ 184 uint8_t reg; /*!< Type used for register access */ 185 } ADC_INTENCLR_Type; 186 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 187 188 /* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 190 typedef union { 191 struct { 192 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ 193 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ 194 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ 195 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 196 } bit; /*!< Structure used for bit access */ 197 uint8_t reg; /*!< Type used for register access */ 198 } ADC_INTENSET_Type; 199 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 200 201 /* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ 202 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 203 typedef union { // __I to avoid read-modify-write on write-to-clear register 204 struct { 205 __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ 206 __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ 207 __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ 208 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ 209 } bit; /*!< Structure used for bit access */ 210 uint8_t reg; /*!< Type used for register access */ 211 } ADC_INTFLAG_Type; 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 213 214 /* -------- ADC_STATUS : (ADC Offset: 0x2F) ( R/ 8) Status -------- */ 215 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 216 typedef union { 217 struct { 218 uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ 219 uint8_t :1; /*!< bit: 1 Reserved */ 220 uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ 221 } bit; /*!< Structure used for bit access */ 222 uint8_t reg; /*!< Type used for register access */ 223 } ADC_STATUS_Type; 224 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 225 226 /* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) ( R/ 32) Synchronization Busy -------- */ 227 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 228 typedef union { 229 struct { 230 uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ 231 uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ 232 uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ 233 uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ 234 uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ 235 uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ 236 uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ 237 uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ 238 uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ 239 uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ 240 uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ 241 uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ 242 uint32_t :20; /*!< bit: 12..31 Reserved */ 243 } bit; /*!< Structure used for bit access */ 244 uint32_t reg; /*!< Type used for register access */ 245 } ADC_SYNCBUSY_Type; 246 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 247 248 /* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ 249 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 250 typedef union { 251 struct { 252 uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ 253 } bit; /*!< Structure used for bit access */ 254 uint32_t reg; /*!< Type used for register access */ 255 } ADC_DSEQDATA_Type; 256 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 257 258 /* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ 259 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 260 typedef union { 261 struct { 262 uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ 263 uint32_t CTRLB:1; /*!< bit: 1 Control B */ 264 uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ 265 uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ 266 uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ 267 uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ 268 uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ 269 uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ 270 uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ 271 uint32_t :22; /*!< bit: 9..30 Reserved */ 272 uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ 273 } bit; /*!< Structure used for bit access */ 274 uint32_t reg; /*!< Type used for register access */ 275 } ADC_DSEQCTRL_Type; 276 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 277 278 /* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) ( R/ 32) DMA Sequencial Status -------- */ 279 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 280 typedef union { 281 struct { 282 uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ 283 uint32_t CTRLB:1; /*!< bit: 1 Control B */ 284 uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ 285 uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ 286 uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ 287 uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ 288 uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ 289 uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ 290 uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ 291 uint32_t :22; /*!< bit: 9..30 Reserved */ 292 uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ 293 } bit; /*!< Structure used for bit access */ 294 uint32_t reg; /*!< Type used for register access */ 295 } ADC_DSEQSTAT_Type; 296 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 297 298 /* -------- ADC_RESULT : (ADC Offset: 0x40) ( R/ 16) Result Conversion Value -------- */ 299 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 300 typedef union { 301 struct { 302 uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ 303 } bit; /*!< Structure used for bit access */ 304 uint16_t reg; /*!< Type used for register access */ 305 } ADC_RESULT_Type; 306 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 307 308 /* -------- ADC_RESS : (ADC Offset: 0x44) ( R/ 16) Last Sample Result -------- */ 309 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 310 typedef union { 311 struct { 312 uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ 313 } bit; /*!< Structure used for bit access */ 314 uint16_t reg; /*!< Type used for register access */ 315 } ADC_RESS_Type; 316 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 317 318 /* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ 319 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 320 typedef union { 321 struct { 322 uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ 323 uint16_t :1; /*!< bit: 3 Reserved */ 324 uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ 325 uint16_t :1; /*!< bit: 7 Reserved */ 326 uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ 327 uint16_t :5; /*!< bit: 11..15 Reserved */ 328 } bit; /*!< Structure used for bit access */ 329 uint16_t reg; /*!< Type used for register access */ 330 } ADC_CALIB_Type; 331 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 332 333 /** \brief ADC hardware registers */ 334 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 335 typedef struct { 336 __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 337 __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ 338 __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ 339 __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ 340 __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ 341 __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ 342 RoReg8 Reserved1[0x1]; 343 __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ 344 __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ 345 __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ 346 __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ 347 __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ 348 __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ 349 __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ 350 RoReg8 Reserved2[0x17]; 351 __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ 352 __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ 353 __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ 354 __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ 355 __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ 356 __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ 357 __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ 358 __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ 359 __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ 360 RoReg8 Reserved3[0x2]; 361 __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ 362 RoReg8 Reserved4[0x2]; 363 __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ 364 } Adc; 365 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 366 367 #endif /* _MICROCHIP_PIC32CXSG_ADC_COMPONENT_FIXUP_H_ */ 368
